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⟦ae31efd54⟧ RcTekst

    Length: 83200 (0x14500)
    Types: RcTekst
    Names: »30-M320.WP«

Derivation

└─⟦b9fe312e5⟧ Bits:30008868 Diskette med 3 stk RCSL-30-M og 3 stk RCSL-31-D
    └─⟦this⟧ »30-M320.WP« 

RcTekst


╱04002d4e0a0006000000000201413140000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
                                i ↲
┆b0┆┆a1┆TABLE OF CONTENTS ┆05┆PAGE↲
↲
┆b0┆1.  INTRODUCTION┆f0┆ ...........................................   1↲
↲
┆b0┆2.  BLOCKDIAGRAMS┆f0┆ ..........................................   2↲
↲
┆b0┆3.  TIMING DIAGRAMS┆f0┆ ........................................   6↲
↲
┆b0┆4.  FUNCTIONAL DISCRIPTION┆f0┆ .................................   9↲
    4.1  Data Paths ........................................   9↲
         4.1.1  General Registers ..........................  10↲
         4.1.2  Q-Register .................................  10↲
         4.1.3  Scratchpad .................................  10↲
         4.1.4  Immediate Operand Register .................  10↲
         4.1.5  Sign Extension Module ......................  10↲
         4.1.6  Half-Word Rotate Module ....................  11↲
         4.1.7  Data In Register ...........................  11↲
         4.1.8  Interrupt Level Register ...................  11↲
         4.1.9  TCP Data Input Register ....................  11↲
         4.1.10 CPU Status Register ........................  12↲
         4.1.11 I/O Address Register .......................  12↲
         4.1.12 Data Out Register ..........................  12↲
         4.1.13 Control Output Register ....................  12↲
         4.1.14 TCP Data Out Register ......................  13↲
         4.1.15 Instruction Register .......................  13↲
         4.1.16 Micro Index Register .......................  14↲
         4.1.17 Interrupt Register .........................  14↲
         4.1.18 CPUBUS Control Register ....................  14↲
    4.2  Control Store Addressing ..........................  14↲
         4.2.1  Microinstruction Address Register ..........  15↲
         4.2.2  Subroutine Return Stack ....................  15↲
         4.2.3  Micro Jump Address Register ................  15↲
         4.2.4  Micro Index Register .......................  15↲
         4.2.5  Instruction Decoding Table .................  15↲
    4.3  Microinstructions .................................  16↲
         4.3.1  Microinstruction Fields ....................  16↲
                4.3.1.1  P Field = MIR(0) ..................  16↲
                4.3.1.2  NEXT Field = MIR(1:3) .............  17↲
                4.3.1.3  FORM Field = MIR(4:6) .............  18↲
                4.3.1.4  ALU DEST Field = MIR(7:9) .........  18↲
                4.3.1.5  ALU OP Field = MIR(10:12) .........  18↲
                4.3.1.6  ALU FUNC Field = MIR(13:15) .......  18↲
                4.3.1.7  C Field = MIR(16:17) ..............  19↲
                4.3.1.8  I/O Field = MIR(18, 19) ...........  19↲
                4.3.1.9  DEST REG Field = MIR(20:23) .......  20↲
                4.3.1.10 SOURCE REG Field = MIR(24:27) .....  20↲
                4.3.1.11 SPADDR Field = MIR(24:27) .........  21↲
                4.3.1.12 A Field = MIR(28:31) ..............  21↲
                4.3.1.13 B Field = MIR(32:35) ..............  21↲
                4.3.1.14 T Field = MIR(18) .................  21↲
                4.3.1.15 COND SEL Field = MIR(19:23) .......  21↲
                4.3.1.16 SI Field = MIR(24:25) .............  22↲
                4.3.1.17 TST Field = MIR(26:27) ............  23↲

════════════════════════════════════════════════════════════════════════
↓
                                ii↲
┆b0┆┆a1┆TABLE OF CONTENTS (continued)┆05┆PAGE↲
↲
┆b0┆┆f0┆         4.3.2  Microinstruction Formats ...................  25↲
                4.3.2.1  Format 0: Load Immediate ..........  25↲
                4.3.2.2  Format 1: Load Scratchpad .........  25↲
                4.3.2.3  Format 2: Read Scratchpad/Load ↲
                         Register ..........................  25↲
                4.3.2.4  Format 3: Read/Load Register ......  26↲
                4.3.2.5  Format 4: Shift ...................  26↲
                4.3.2.6  Format 5: Multiply ................  26↲
                4.3.2.7  Format 6: Divide ..................  26↲
                4.3.2.8  Format 7: Conditional Jump ........  27↲
↲
┆b0┆5.  LOGIC DIAGRAMS AND SIGNAL DESCRIPTION┆f0┆ ..................  28↲
↲
┆b0┆6.  PAL AND PROM DESCRIPTION ┆f0┆............................... 116↲
    6.1  PAL Description ................................... 116↲
         6.1.1  APT002 ..................................... 116↲
         6.1.2  PAT003 ..................................... 117↲
         6.1.3  PAT004 ..................................... 118↲
         6.1.4  PAT005 ..................................... 119↲
    6.2  PROM Descriptions ................................. 120↲
         6.2.1  ROB078 ..................................... 121↲
         6.2.2  ROA006 ..................................... 122↲
         6.2.3  ROA007 ..................................... 123↲

════════════════════════════════════════════════════════════════════════
↓

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↓
┆14┆┆b3┆                                ┆0b┆↲
↲
┆b0┆┆a1┆1.       INTRODUCTION↲
↲
         ┆84┆CPU 811 is a central processing unit which is used in a ↓
┆19┆┆89┆┄┄number of RC8000 processing units.↲
↲
         ┆84┆CPU 811 is a microprogrammed processor with a 36-bit ↓
┆19┆┆89┆┄┄microinstruction format and a 200 ns microinstruction ↓
┆19┆┆89┆┄┄execution time.↲
↲
         ┆84┆The 24-bit wide arithmetic section is designed around 6 ↓
┆19┆┆89┆┄┄cascaded 2901A 4-bit slice processor elements. The ↓
┆19┆┆89┆┄┄microprogram sequence control uses 3 cascaded 2911 4-↓
┆19┆┆89┆┄┄bit slice microprogram sequencers which provides a 12-↓
┆19┆┆89┆┄┄bit control store address. PROM's are used for the ↓
┆19┆┆89┆┄┄control store which has a capacity of 2048 36-bit words.↲
↲
         ┆84┆The CPU 811 is connected to memory and device ↓
┆19┆┆89┆┄┄controllers via the RC8000 System Bus. In addition it is ↓
┆19┆┆89┆┄┄provided with a 24-bit bidirectional backplane bus, the ↓
┆19┆┆89┆┄┄CPUBUS, which allows the FPU 801 floating point unit to ↓
┆19┆┆89┆┄┄be attached.↲
↲
         ┆84┆In addition to the routines for execution of the RC8000 ↓
┆19┆┆89┆┄┄instruction set the microprogram contain diagnostic ↓
┆19┆┆89┆┄┄routines for CPU and main memory, and routines for ↓
┆19┆┆89┆┄┄support of the technicians console.↲
↲
         ┆84┆It is assumed that the reader of this manual is familiar ↓
┆19┆┆89┆┄┄with RC8000 architecture, instruction format, and data ↓
┆19┆┆89┆┄┄formats. Such information may be found in:↲
↲
┆06┆RC8000 COMPUTER REFERENCE MANUAL↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.       BLOCKDIAGRAMS↲
↲
         ┆84┆This section contains block diagrams for the data paths ↓
┆19┆┆89┆┄┄of the CPU 811 and for the control store and ↓
┆19┆┆89┆┄┄microinstruction sequence control.↲

════════════════════════════════════════════════════════════════════════
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         CPU 811 CONTROL STORE AND ↲
         MICROINSTRUCTION SEQUENCE CONTROL↲
↲

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         CPU 811 DATA PATHS↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆3.       TIMING DIAGRAMS↲
↲

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════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.       FUNCTIONAL DESCRIPTION↲
↲
         ┆84┆Symbols and abbreviations used in the description are ↓
┆19┆┆89┆┄┄listed below.↲
↲
         (A)     Contents of A.↲
↲
         A(i)    Bit i in register A.↲
↲
         A(i:j)  Bits i to j including i and j in register A.↲
↲
         A(i,j)  Bits i and j in register A.↲
↲
         con     Concatenating operator.↲
↲
         ext     ┆84┆Extension operator. N ext P means P repeated N ↓
┆19┆┆91┆┄┄times.↲
↲
         +       Binary arithmetic addition.↲
↲
         -       Binary arithmetic 2's complement subtraction.↲
↲
         -,      Logical COMPLEMENT.↲
↲
         &       Logical AND.↲
↲
         !       Logical OR.↲
↲
         exor    Logical EXCLUSIVE OR.↲
↲
         ┆84┆When the logical operators are used on bit strings, the ↓
┆19┆┆89┆┄┄logical operation is performed on individual bits.↲
↲
↲
┆b0┆┆a1┆4.1      Data Paths↲
↲
         ┆84┆The principal data paths in the CPU 811 are 24-bit wide ↓
┆19┆┆89┆┄┄and is shown on the block diagram on page 3. An array of ↓
┆19┆┆89┆┄┄6 2901A 4-bit slice processing elements constitutes the ↓
┆19┆┆89┆┄┄kernel of the CPU 810 data path structure. It contains ↓
┆19┆┆89┆┄┄the General Registers (accumulators), the Q-register, ↓
┆19┆┆89┆┄┄and an arithmetic logic unit. The 2901 array receives ↓
┆19┆┆89┆┄┄data from external registers via the Source Bus (SBUS), ↓
┆19┆┆89┆┄┄which is a tri-state bus. Data to external registers is ↓
┆19┆┆89┆┄┄transferred via the Result Bus (RESBUS).↲
↲
         ┆84┆The following subsections gives a short description of ↓
┆19┆┆89┆┄┄the CPU 811 registers. The registers may be divided into ↓
┆19┆┆89┆┄┄the following groups: Registers located inside the 2901, ↓
┆19┆┆89┆┄┄external source registers connected to the SBUS, and ↓
┆19┆┆89┆┄┄external destination registers connected to the RESBUS.↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.1.1    General Registers↲
 ↲
         ┆84┆The 16 General Registers in the 2901 are located in a ↓
┆19┆┆89┆┄┄dual-port RAM. The contents of 2 General Registers may ↓
┆19┆┆89┆┄┄simultaneously be accessed via the A-port, GRA, and the ↓
┆19┆┆89┆┄┄B-port, GRB. GRA and GRB may be used as inputs to the ↓
┆19┆┆89┆┄┄ALU and GRA may be transferred directly to the RESBUS. ↓
┆19┆┆89┆┄┄The General Registers may be loaded with the output from ↓
┆19┆┆89┆┄┄the ALU. A shift network at the input to the General ↓
┆19┆┆89┆┄┄Registers may pass or shift the ALU output 1 bit ↓
┆19┆┆89┆┄┄position left or right before it is loaded.↲
↲
↲
┆b0┆┆a1┆4.1.2    Q-Register↲
↲
         ┆84┆The Q-register which is located in the 2901 may be used ↓
┆19┆┆89┆┄┄as an accumulator and as an extension to the General ↓
┆19┆┆89┆┄┄Registers in shift operations for shifting 48-bit ↓
┆19┆┆89┆┄┄operands. In the latter case Q holds the least ↓
┆19┆┆89┆┄┄significant 24-bit of the 48-bit operand. It is only ↓
┆19┆┆89┆┄┄possible to shift Q in conjunction with a General ↓
┆19┆┆89┆┄┄Register.↲
↲
↲
┆b0┆┆a1┆4.1.3    Scratchpad↲
↲
         ┆84┆The Scratchpad (SCRATCHP) is an external register file ↓
┆19┆┆89┆┄┄with 16 24-bit words. It may be used as both source and ↓
┆19┆┆89┆┄┄destination, but not in the same microinstruction. When ↓
┆19┆┆89┆┄┄it is used as source the ┆a1┆complement┆e1┆ of the data loaded ↓
┆19┆┆89┆┄┄into the addressed location is transferred to the SBUS. ↓
┆19┆┆89┆┄┄The SBUS cannot be used in microinstructions where the ↓
┆19┆┆89┆┄┄SCRATCHP is used as destination because the SCRATCHP ↓
┆19┆┆89┆┄┄transfers data to it during part of the cycle.↲
↲
↲
┆b0┆┆a1┆4.1.4    Immediate Operand Register↲
↲
         ┆84┆The Immediate Operand Register is a 24-bit source ↓
┆19┆┆89┆┄┄register. It may be loaded by means of an immediate ↓
┆19┆┆89┆┄┄operand microinstruction.↲
↲
↲
┆b0┆┆a1┆4.1.5    Sign Extension Module↲
↲
         ┆84┆The Sign Extension Module (SIGNEXT) is a combinatorial ↓
┆19┆┆89┆┄┄array which may be addressed in the same way as a 24-bit ↓
┆19┆┆89┆┄┄source register. When it is addressed the contents of ↓
┆19┆┆89┆┄┄the RESBUS is transferred to the SBUS with sign ↓
┆19┆┆89┆┄┄extension as defined below.↲
↲
         SBUS(0:23): = 12 ext RESBUS(12) con RESBUS(12:23)↲
↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.1.6    Half-Word Rotate Module↲
↲
         ┆84┆The Half-Word Rotate Module (ROTATE) is a combinatorial ↓
┆19┆┆89┆┄┄array which may be addressed as a 24-bit source ↓
┆19┆┆89┆┄┄register. When it is addressed the two half-words on the ↓
┆19┆┆89┆┄┄RESBUS are exchanged and transferred to the SBUS as ↓
┆19┆┆89┆┄┄defined below.↲
↲
         ┆84┆SBUS(0:23): = RESBUS(12:23) con RESBUS(0:11)↲
↲
↲
┆b0┆┆a1┆4.1.7    Data In Register↲
↲
         ┆84┆The Data In Register (DATAIN) is a 24-bit source ↓
┆19┆┆89┆┄┄register used as buffer register for data received via ↓
┆19┆┆89┆┄┄the System Bus in input operations initiated by the CPU. ↓
┆19┆┆89┆┄┄The contents of the register is undefined from the start ↓
┆19┆┆89┆┄┄of an input operation until termination of the ↓
┆19┆┆89┆┄┄operation. If an input operation is terminated by a NACK ↓
┆19┆┆89┆┄┄or a TIME OUT DATAIN will be loaded with the current ↓
┆19┆┆89┆┄┄data on the System Bus.↲
↲
↲
┆b0┆┆a1┆4.1.8    Interrupt Level Register↲
↲
         ┆84┆The Interrupt Level Register (INTRLEV) is an 8-bit ↓
┆19┆┆89┆┄┄source register. When the jump condition INTERRUPT = 1, ↓
┆19┆┆89┆┄┄INTRLEV contains the level of the interrupt with the ↓
┆19┆┆89┆┄┄highest priority. The contents of INTRLEV is transferred ↓
┆19┆┆89┆┄┄to the SBUS as defined below↲
↲
         SBUS(0:15) undefined↲
         SBUS(16:23): = INTRLEV(0:7)↲
↲
         ┆84┆The assignment of the interrupt levels is defined in the ↓
┆19┆┆89┆┄┄table below.↲
↲
         ┆a1┆┆b0┆LEVEL       INTERRUPT SOURCE↲
↲
         0           Unused↲
         1           TCP input ready (TCPINRDY)↲
         2           Single instruction (SINGLEINSTR)↲
         3           OCP autoload (RESTARTEN)↲
         4           Remote autoload (REMAUTOLOAD)↲
         5           0.1 ms timer (10 KHZ clock)↲
         6           Power low warning (PINT)↲
         7           Interval timer↲
         8:31        Device controllers↲
↲
↲
┆b0┆┆a1┆4.1.9    TCP Data Input Register↲
↲
         ┆84┆The TCP Data Input Register (TCPDATAIN) is an 8-bit ↓
┆19┆┆89┆┄┄source register used as buffer register for data ↓
┆19┆┆89┆┄┄received from the Technicians Console.↲
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆84┆The contents of TCPDATAIN is transferred to the SBUS as ↓
┆19┆┆89┆┄┄defined below↲
↲
         SBUS(0:15) undefined↲
         SBUS(16:23): = TCPDATAIN(0:7)↲
↲
↲
┆b0┆┆a1┆4.1.10   CPU Status Register↲
↲
         ┆84┆The CPU Status Register (CPUST) is a 6-bit destination ↓
┆19┆┆89┆┄┄register which is used to hold bits (0:5) of the CPU ↓
┆19┆┆89┆┄┄Status Word. The register is loaded from the RESBUS as ↓
┆19┆┆89┆┄┄defined below.↲
↲
         MONITOR MODE: =                RESBUS(0)↲
         ESCAPE MODE: =                 RESBUS(1)↲
         AFTER AM: =                    RESBUS(2)↲
         AFTER ESCAPE: =                RESBUS(3)↲
         INTEGER MASK: =                RESBUS(4)↲
         FLOATING POINT MASK: =         RESBUS(5)↲
↲
         ┆84┆The contents of the register is used for instruction ↓
┆19┆┆89┆┄┄decoding and as jump conditions.↲
↲
↲
┆b0┆┆a1┆4.1.11   I/O Address Register↲
↲
         ┆84┆The I/O Address Register (I/O ADDR) is a 24-bit ↓
┆19┆┆89┆┄┄destination which is used to hold the I/O address during ↓
┆19┆┆89┆┄┄data transfers on the System Bus initiated by the CPU.↲
↲
         ┆84┆Addressing of I/O ADDR has two purposes. The register is ↓
┆19┆┆89┆┄┄loaded with the contents of the SBUS and a data transfer ↓
┆19┆┆89┆┄┄on the System Bus is initiated. A separate field in the ↓
┆19┆┆89┆┄┄microinstruction controls the direction of the data ↓
┆19┆┆89┆┄┄transfer. The contents of the register must not be ↓
┆19┆┆89┆┄┄altered during an I/O operation in progress.↲
↲
↲
┆b0┆┆a1┆4.1.12   Data Out Register↲
↲
         ┆84┆The Data Out Register (DATAOUT) is a 24-bit destination ↓
┆19┆┆89┆┄┄register used as output buffer register for data to be ↓
┆19┆┆89┆┄┄transferred via the System Bus from the CPU to the ↓
┆19┆┆89┆┄┄addressed destination. Once an output operation has been ↓
┆19┆┆89┆┄┄started the contents of the register must not be altered ↓
┆19┆┆89┆┄┄before termination of the operation.↲
↲
↲
┆b0┆┆a1┆4.1.13   Control Output Register↲
↲
         ┆84┆The Control Output Register (CONTROLOUT) is an 8-bit ↓
┆19┆┆89┆┄┄destination register which is used for different control ↓
┆19┆┆89┆┄┄purposes in the CPU. The register is loaded from the ↓
┆19┆┆89┆┄┄RESBUS as defined below.↲
↲
         CONTROLOUT(0:7): = RESBUS(16:23)↲

════════════════════════════════════════════════════════════════════════
↓
         ┆84┆The contents of the register is used in the following ↓
┆19┆┆89┆┄┄way:↲
↲
         ┆b0┆┆a1┆BIT   CONTROL FUNCTION↲
↲
         0     ┆84┆CPUSYSRST. Controls the SYSTEM RESET signal on the ↓
┆19┆┆8f┆┄┄System Bus.↲
↲
         1     ┆84┆RUN. Controls the RUN lamp on the Operators ↓
┆19┆┆8f┆┄┄Control Panel (OCP).↲
↲
         2     ┆84┆AUTOLOADING. Controls the AUTOLOAD lamp on the ↓
┆19┆┆8f┆┄┄OCP.↲
↲
         3     ┆84┆SINGLEINSTR. Used for single instruction execution ↓
┆19┆┆8f┆┄┄controlled from the Technicians Console (TCP). The ↓
┆19┆┆8f┆┄┄signal generates a level 2 interrupt.↲
↲
         4     ┆84┆SETIVTIMER. The interval timer interrupt is set ↓
┆19┆┆8f┆┄┄when the signal changes from 0 to 1.↲
↲
         5     ┆84┆TCPINACK. Acknowledge signal from CPU to TCP. The ↓
┆19┆┆8f┆┄┄TCPDATAIN register is loaded with new data from ↓
┆19┆┆8f┆┄┄the TCP when TCPINACK changes from 0 to 1.↲
↲
         6     ┆84┆TCPOUTRDY. Control signal from CPU to TCP. Used to ↓
┆19┆┆8f┆┄┄indicate that data is available in the TCPDATAOUT ↓
┆19┆┆8f┆┄┄register.↲
↲
         7     ┆84┆TSTSYNC. Used by the microdiagnostic routines for ↓
┆19┆┆8f┆┄┄oscilloscope triggering in error loops.↲
↲
↲
┆b0┆┆a1┆4.1.14   TCP Data Out Register↲
↲
         ┆84┆The TCP Data Out Register (TCPDATAOUT) is an 8-bit ↓
┆19┆┆89┆┄┄destination register used as buffer register for data to ↓
┆19┆┆89┆┄┄the TCP. The register is loaded from the RESBUS as ↓
┆19┆┆89┆┄┄defined below.↲
↲
         FFIELD(0:5): =     RESBUS(0:5)↲
         WFIELD(0:1): =     RESBUS(6:7)↲
         RFIELD: =          RESBUS(8)↲
         IFIELD: =          RESBUS(9)↲
         XFIELD: =          RESBUS(10:11)↲
↲
↲
┆b0┆┆a1┆┆b0┆┆a1┆4.1.15   Instruction Register↲
↲
         ┆84┆The instruction Register (INSTRREG) is a 12-bit ↓
┆19┆┆89┆┄┄destination register. It is used to hold bits (0:11) of ↓
┆19┆┆89┆┄┄the RC8000 instruction which is being executed. The ↓
┆19┆┆89┆┄┄register is loaded from the RESBUS as defined below:↲
↲
         FFIELD(0:5): =     RESBUS(0:5)↲
         WFIELD(0:1): =     RESBUS(6:7)↲
         RFIELD: =          RESBUS(8)↲
         IFIELD: =          RESBUS(9)↲
         XFIELD: =          RESBUS(10:11)↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.1.16   Micro Index Register↲
↲
         ┆84┆The Micro Index Register (MIX) is a 12-bit destination ↓
┆19┆┆89┆┄┄register. The contents of MIX may be used as control ↓
┆19┆┆89┆┄┄store address in JUMP microinstructions. The register is ↓
┆19┆┆89┆┄┄loaded from the RESBUS as defined below.↲
↲
         MIX(0:11): = RESBUS(12:23)↲
↲
↲
┆b0┆┆a1┆4.1.17   Interrupt Register↲
↲
         ┆84┆The Interrupt Register (INTR) is a 31-bit register in ↓
┆19┆┆89┆┄┄which interrupt requests are stored. INTR may be ↓
┆19┆┆89┆┄┄addressed as a destination register for clearing of ↓
┆19┆┆89┆┄┄interrupt requests. A microinstruction addressing INTR ↓
┆19┆┆89┆┄┄will clear the request at the level indicated by ↓
┆19┆┆89┆┄┄RESBUS(18:23). Requests at the levels (1:3) cannot be ↓
┆19┆┆89┆┄┄cleared in this way.↲
↲
         ┆84┆The INTR register may be addressed via the System Bus in ↓
┆19┆┆89┆┄┄order to set an interrupt request. Data bits (18:23) on ↓
┆19┆┆89┆┄┄the System Bus determines at which level the request ↓
┆19┆┆89┆┄┄will be set. Only interrupt requests at the levels 8 to ↓
┆19┆┆89┆┄┄31 may be set from the System Bus.↲
↲
↲
┆b0┆┆a1┆4.1.18   CPUBUS Control Register↲
↲
         ┆84┆The CPUBUS Control Register (CBCR) is a 12-bit ↓
┆19┆┆89┆┄┄destination register which is used to control the 4 most ↓
┆19┆┆89┆┄┄significant bits of the 3 CPUBUS control fields: Unit ↓
┆19┆┆89┆┄┄Function, Source Address, and Destination Address. The 2 ↓
┆19┆┆89┆┄┄least significant bits of these control fields are ↓
┆19┆┆89┆┄┄controlled directly by microinstruction fields in format ↓
┆19┆┆89┆┄┄2 and 3 microinstructions.↲
↲
         ┆84┆The register is loaded from the RESBUS as defined below.↲
↲
         UNIT FUNCTION(0:3): =            RESBUS(6:9)↲
         CPUBUS SOURCE(0:3): =            RESBUS(12:15)↲
         CPUBUS DESTINATION(0:3): =       RESBUS(18:21)↲
↲
↲
┆b0┆┆a1┆4.2      Control Store Addressing↲
↲
         ┆84┆The block diagram on page 5 shows the control store and ↓
┆19┆┆89┆┄┄the associated address paths. The Control Store (CS) is ↓
┆19┆┆89┆┄┄addressed via a 12-bit tri-state bus, the Control Store ↓
┆19┆┆89┆┄┄Address Bus (CSADDR). The contents of the addressed CS ↓
┆19┆┆89┆┄┄location is loaded into the Microinstruction Register ↓
┆19┆┆89┆┄┄(MIR), which holds the microinstruction during its ↓
┆19┆┆89┆┄┄execution. The next microinstruction to be executed is ↓
┆19┆┆89┆┄┄fetched from CS during the execution of the current ↓
┆19┆┆89┆┄┄microinstruction in order to minimize microinstruction ↓
┆19┆┆89┆┄┄cycle time. The CSADDR may be selected from a number of ↓
┆19┆┆89┆┄┄sources which are described in the following ↓
┆19┆┆89┆┄┄subsections.↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.2.1    Microinstruction Address Register↲
↲
         ┆84┆The Microinstruction Address Register (MAR) is used for ↓
┆19┆┆89┆┄┄sequential addressing of control store locations. In ↓
┆19┆┆89┆┄┄each microcycle MAR is loaded with CSADDR + 1.↲
↲
↲
┆b0┆┆a1┆4.2.2    Subroutine Return Stack↲
↲
         ┆84┆The Subroutine Return Stack (STACK) is a 4-word register ↓
┆19┆┆89┆┄┄file, which operates as a push-pop stack, i.e. a last ↓
┆19┆┆89┆┄┄in/first out (LIFO) structure. The STACK is used for ↓
┆19┆┆89┆┄┄saving of subroutine return addresses and for ↓
┆19┆┆89┆┄┄microprogram loop control. Associated with the STACK is ↓
┆19┆┆89┆┄┄a stack pointer (SP), which points at the word on the ↓
┆19┆┆89┆┄┄top of the STACK. The word on the top of the stack ↓
┆19┆┆89┆┄┄STACK(SP) may be transferred to CSADDR bus.↲
↲
↲
┆b0┆┆a1┆4.2.3    Micro Jump Address Register↲
↲
         ┆84┆The Micro Jump Address Register (JUMP) may be used as ↓
┆19┆┆89┆┄┄control store address source in jump microinstructions. ↓
┆19┆┆89┆┄┄JUMP is loaded from CS in parallel with MIR and the ↓
┆19┆┆89┆┄┄contents of JUMP is identical to the contents of that ↓
┆19┆┆89┆┄┄part of MIR, which contains the jump address field.↲
↲
↲
┆b0┆┆a1┆4.2.4    Micro Index Register↲
↲
         ┆84┆The Micro Index Register (MIX) may be used as CS address ↓
┆19┆┆89┆┄┄source in jump microinstructions. MIX is loaded from the ↓
┆19┆┆89┆┄┄RESBUS and may e.g. be used for table look-up in control ↓
┆19┆┆89┆┄┄store.↲
↲
↲
┆b0┆┆a1┆4.2.5    Instruction Decoding Table↲
↲
         ┆84┆An RC8000 instruction is decoded and executed in two ↓
┆19┆┆89┆┄┄steps: Calculation of the effective address and ↓
┆19┆┆89┆┄┄execution of the function of the instruction. ↓
┆19┆┆89┆┄┄Microprogram start addresses for address calculation and ↓
┆19┆┆89┆┄┄instruction execution subroutines are stored in the ↓
┆19┆┆89┆┄┄Instruction Decoding Table (TABLE), which is a 256 words ↓
┆19┆┆89┆┄┄x 12 bits PROM. TABLE is deivided into 2 blocks, 128 ↓
┆19┆┆89┆┄┄words for address calculation entries and 128 words for ↓
┆19┆┆89┆┄┄instruction execution entries. A 2-input multiplexer ↓
┆19┆┆89┆┄┄controlled from the microinstructions selects address ↓
┆19┆┆89┆┄┄inputs to TABLE as described below.↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆ADDRESS CALCULATION DECODING↲
↲
         ┆b0┆┆a1┆ADDRESS BIT     ADDRESS SOURCE↲
↲
         0               = 0, controlled by MIR(3)↲
         1               = 0↲
         2               AFTERESC↲
         3               AFTERAM↲
         4               RFIELD↲
         5               IFIELD↲
         6               XFIELD(0)↲
         7               XFIELD(1)↲
↲
         ┆b0┆┆a1┆INSTRUCTION EXECUTION DECODING↲
↲
         ┆b0┆┆a1┆ADDRESS BIT     ADDRESS SOURCE↲
↲
         0               = 1, controlled by MIR(3)↲
         1               ESCMODE↲
         2               FFIELD(0)↲
         3                     (1)↲
         4                     (2)↲
         5                     (3)↲
         6                     (4)↲
         7                     (5)↲
↲
↲
┆b0┆┆a1┆4.3      Microinstructions↲
↲
         ┆84┆All microinstructions are 36 bits in length and the ↓
┆19┆┆89┆┄┄microinstruction repertoire comprises 8 different ↓
┆19┆┆89┆┄┄formats as shown in figure 4.1. The Microinstruction ↓
┆19┆┆89┆┄┄Register (MIR) holds the microinstruction during its ↓
┆19┆┆89┆┄┄execution. The execution time is 200 ns for all ↓
┆19┆┆89┆┄┄microinstruction formats.↲
↲
↲
┆b0┆┆a1┆4.3.1    Microinstruction Fields↲
↲
         ┆84┆A microinstruction consists of a number of fields. This ↓
┆19┆┆89┆┄┄section describes the fields, which are common to ↓
┆19┆┆89┆┄┄several microinstructions. Fields referring to a single ↓
┆19┆┆89┆┄┄format are described in connection with that format.↲
↲
↲
┆b0┆┆a1┆4.3.1.1  P Field = MIR(0)↲
↲
         ┆84┆The P field contains the parity bit for the micro-↓
┆19┆┆89┆┄┄instruction. Odd parity is used. In case of a parity ↓
┆19┆┆89┆┄┄error the processor stops immediately and the indicator ↓
┆19┆┆89┆┄┄'CONTROL STORE PARITY ERROR' on the PCBA front panel ↓
┆19┆┆89┆┄┄will be lit. MIR contains the faulty microinstruction, ↓
┆19┆┆89┆┄┄which is not executed. The CSADDR depends on the NEXT ↓
┆19┆┆89┆┄┄field of the faulty microinstruction. In order to ↓
┆19┆┆89┆┄┄proceed after control store parity error it is necessary ↓
┆19┆┆89┆┄┄to turn power off and then on again.↲
↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.3.1.2  NEXT Field = MIR(1:3)↲
↲
         ┆84┆The NEXT field defines the control store address for the ↓
┆19┆┆89┆┄┄next microinstruction to be executed as described on the ↓
┆19┆┆89┆┄┄next page.↲
↲
         ┆b0┆┆a1┆NEXT     FUNCTION↲
↲
         000      ┆84┆CSADDR: = MAR; MAR: = MAR+1↲
                  ┆84┆The next sequential microinstruction is ↓
┆19┆┆92┆┄┄executed.↲
↲
         001      ┆84┆TESTCOND = 0: CSADDR: = MAR; MAR: = MAR+1↲
                  TESTCOND = 1: CSADDR: = STACK(SP); ↲
                                MAR: = STACK(SP)+1; SP: = SP-1↲
                  ┆84┆Is used for conditional subroutine return. If ↓
┆19┆┆92┆┄┄the selected condition is false, the next ↓
┆19┆┆92┆┄┄sequential microinstruction is executed. If the ↓
┆19┆┆92┆┄┄condition is true the address on the top of the ↓
┆19┆┆92┆┄┄STACK is selected as next address.↲
↲
         010      ┆84┆CSADDR: = MAR; SP: = SP+1; STACK(SP): = MAR; ↓
┆19┆┆92┆┄┄MAR: = MAR+1↲
                  ┆84┆The next sequential microinstruction is ↓
┆19┆┆92┆┄┄executed and its address is pushed on to the ↓
┆19┆┆92┆┄┄STACK. Is used for loop set-up.↲
↲
         011      ┆84┆CSADDR: = STACK(SP); MAR: = STACK(SP)+1; ↲
                            SP: = SP-1 ↲
                  ┆84┆The address on the top of the STACK is selected ↓
┆19┆┆92┆┄┄as next address and is removed from the STACK. ↓
┆19┆┆92┆┄┄Is used for subroutine return.↲
↲
         101      TESTCOND=0: CSADDR: = STACK(SP);↲
                              MAR: = STACK(SP)+1↲
                  TESTCOND=1: CSADDR: = MAR; SP: = SP-1;↲
                              MAR: = MAR+1↲
                  ┆84┆Is used for microprogram loop control. If the ↓
┆19┆┆92┆┄┄selected condition (TESTCOND) is false top of ↓
┆19┆┆92┆┄┄STACK is selected as next microinstruction ↓
┆19┆┆92┆┄┄address and the loop is repeated. If TESTCOND ↓
┆19┆┆92┆┄┄is true the next sequential microinstruction is ↓
┆19┆┆92┆┄┄executed and top of STACK is removed (loop ↓
┆19┆┆92┆┄┄exit).↲
↲
         110      CSADDR: = TABLE(ADDR); SP: SP+1;↲
                  STACK(SP): = MAR; MAR: = TABLE(ADDR)+1↲
                  ┆84┆Is used to call subroutines for calculation of ↓
┆19┆┆92┆┄┄the effective address of an RC8000 instruction. ↓
┆19┆┆92┆┄┄See also point 4.2.5.↲
↲
         111      CSADDR: = TABLE(EXEC); SP: = SP+1;↲
                  STACK(SP): = MAR; MAR: = TABLE(EXEC)+1↲
                  ┆84┆Used to call subroutines for execution of an ↓
┆19┆┆92┆┄┄RC8000 instruction. See also point 4.2.5.↲
↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.3.1.3  FORM Field = MIR(4:6)↲
↲
         ┆84┆The FORM field defines the microinstruction format and ↓
┆19┆┆89┆┄┄thereby the usage of bits (10:35) of microinstruction. ↓
┆19┆┆89┆┄┄See figure 4.1.↲
↲
↲
┆b0┆┆a1┆4.3.1.4  ALU DEST Field = MIR(7:9)↲
↲
         ┆84┆The ALU DEST field selects destination for the ALU ↓
┆19┆┆89┆┄┄output (F) and controls the shift networks for the ↓
┆19┆┆89┆┄┄General Registers and the Q register. In addition it ↓
┆19┆┆89┆┄┄selects data source for the RESBUS.↲
↲
         ┆b0┆┆a1┆ALU DEST   FUNCTION↲
↲
         000        Q: = F; RESBUS: = F↲
         001        RESBUS: = F↲
         010        GRB: = F; RESBUS: = GRA↲
         011        GRB: = F; RESBUS: = F ↲
         100        GRB con Q: = SHIN con F con Q(0:22);↲
                    RESBUS: = F↲
         101        GRB: = SHIN con F(0:22); RESBUS: = F↲
         110        GRB con Q: = F(1:23) con Q con SHIN;↲
                    RESBUS: = F↲
         111        GRB: = F(1:23) con SHIN; RESBUS: = F↲
↲
         SHIN is shift input defined by S1 field.↲
↲
↲
┆b0┆┆a1┆4.3.1.5  ALU OP Field = MIR(10:12)↲
↲
         ┆84┆The ALU OP field selects the two operands, R and S, for ↓
┆19┆┆89┆┄┄the ALU.↲
↲
         ┆84┆┆b0┆┆a1┆ALU OP   OPERAND R   OPERAND S↲
↲
         000      GRA          Q↲
         001      GRA          GRB ↲
         010      ZERO         Q↲
         011      ZERO         GRB↲
         100      ZERO         GRA↲
         101      SBUS         GRA↲
         110      SBUS         Q↲
         111      SBUS         ZERO↲
↲
↲
┆a1┆┆b0┆4.3.1.6  ALU FUNC Field = MIR(13:15)↲
↲
         ┆84┆The ALU can perform three arithmetic and five logic ↓
┆19┆┆89┆┄┄functions controlled by the ALU FUNC field. Cin is the ↓
┆19┆┆89┆┄┄carry input to the least significant position of the ↓
┆19┆┆89┆┄┄ALU.↲
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆ALU FUNC   ALU FUNCTION↲
↲
         000        R + S + Cin↲
         001        -R + S -1 + Cin↲
         010        R - S - 1 + Cin↲
         011        R! S↲
         100        R & S↲
         101        -, R & S↲
         110        R exor S↲
         111        -, (R exor S)↲
↲
↲
┆b0┆┆a1┆4.3.1.7  C Field = MIR(16:17)↲
↲
         ┆84┆The C field controls the carry input to the least ↓
┆19┆┆89┆┄┄significant position, bit (23), of the ALU.↲
↲
         ┆b0┆┆a1┆C   CARRY INPUT, Cin↲
↲
         00  0↲
         01  1↲
         10  CARRY↲
         11  ADDCOND↲
↲
↲
┆b0┆┆a1┆4.3.1.8  I/O Field = MIR(18, 19)↲
↲
         ┆84┆The I/O field has two functions. Data transfer control ↓
┆19┆┆89┆┄┄on the RC8000 System Bus, and Unit Function control on ↓
┆19┆┆89┆┄┄the CPUBUS.↲
↲
         ┆84┆When the DEST REG field, MIR(120:23), addresses the I/O ↓
┆19┆┆89┆┄┄Address Register, the I/O field is used for System Bus ↓
┆19┆┆89┆┄┄control as specified below.↲
↲
         ┆b0┆┆a1┆I/O   FUNCTION↲
↲
         00    READ↲
         01    READ if I/O ADDRESS > 8↲
         10    WRITE↲
         11    WRITE if I/O ADDRESS > 8↲
↲
         READ means data transfer to CPU.↲
↲
         ┆84┆When the DEST REG field contains a CPUBUS destination ↓
┆19┆┆89┆┄┄address, the I/O field is used as the 2 least ↓
┆19┆┆89┆┄┄significant bits in the CPUBUS UNIT FUNCTION↲
↲
         UNIT FUNCTION(4,5): = MIR(18,19)↲
↲
         ┆84┆The 4 most significant bits of the unit function is ↓
┆19┆┆89┆┄┄controlled by the CPUBUS Control Register as described ↓
┆19┆┆89┆┄┄in chapter 4.1.18.↲
↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.3.1.9  DEST REG Field = MIR(20:23)↲
↲
         ┆84┆The register addressed by the DEST REG field is loaded ↓
┆19┆┆89┆┄┄with the contents of the RESBUS.↲
↲
         ┆b0┆┆a1┆DEST REG   REGISTER↲
↲
         0000       No load↲
         0001       CPU status↲
         0010       I/O Address, Start I/O↲
         0011       Data Out↲
         0100       Control Output↲
         0101       TCP Data Out↲
         0110       Instruction Register↲
         0111       Micro Index Register↲
         1000       Interrupt Register↲
         1001       CPUBUS Control Register↲
         11xx       CPUBUS Destination Registers↲
↲
         ┆84┆The 2 least significant bits of the CPUBUS destination ↓
┆19┆┆89┆┄┄address is controlled directly by MIR(22,23), when ↓
┆19┆┆89┆┄┄MIR(20,21) = 1,1. ↲
↲
         CPUBUS DESTINATION(4,5): = MIR(22,23)↲
↲
         ┆84┆The 4 most significant bits of the CPUBUS destination ↓
┆19┆┆89┆┄┄address is controlled by the CPUBUS Control Register as ↓
┆19┆┆89┆┄┄described in section 4.1.18.↲
↲
↲
┆b0┆┆a1┆4.3.1.10 SOURCE REG Field = MIR(24:27)↲
↲
         ┆84┆The contents of the register addressed by the SOURCE REG ↓
┆19┆┆89┆┄┄field is transferred to the SBUS.↲
↲
         ┆b0┆┆a1┆SOURCE REG   REGISTER↲
↲
         0000         Immediate Operand↲
         0001         Sign Extension↲
         0010         Half-Word Rotate↲
         0011         Data In↲
         0100         Interrupt Level↲
         0101         TCP Data In↲
         11xx         CPUBUS Source Registers↲
↲
         ┆84┆The 2 least significant bits of the CPUBUS source ↓
┆19┆┆89┆┄┄address is controlled directly by MIR(26,27), when ↓
┆19┆┆89┆┄┄MIR(24:25) = 1,1.↲
↲
         CPUBUS SOURCE(4,5): = MIR(26,27)↲
↲
         ┆84┆The 4 most significant bits of the CPUBUS source address ↓
┆19┆┆89┆┄┄is controlled by the CPUBUS Control Register as ↓
┆19┆┆89┆┄┄described in section 4.1.18.↲
↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.3.1.11 SPADDR Field = MIR(24:27)↲
↲
         ┆84┆The SPADDR field addresses 1 of the 16 words in the ↓
┆19┆┆89┆┄┄Scratchpad file. The microinstruction format determines ↓
┆19┆┆89┆┄┄whether the Scratchpad is used as source or ↓
┆19┆┆89┆┄┄destionation.↲
↲
↲
┆b0┆┆a1┆4.3.1.12 A Field = MIR(28:31)↲
↲
         ┆84┆The A field addresses 1 of the 16 General Registers, ↓
┆19┆┆89┆┄┄GRA. The addressed register may only be used as source ↓
┆19┆┆89┆┄┄and the usage is controlled by the ALU DEST and ALU OP ↓
┆19┆┆89┆┄┄fields.↲
↲
↲
┆b0┆┆a1┆4.3.1.13 B Field = MIR(32:35)↲
↲
         ┆84┆The B field addresses 1 of the 16 General Registers, ↓
┆19┆┆89┆┄┄GRB. The addressed register may be used as both source ↓
┆19┆┆89┆┄┄and destination. The usage is controlled by the ALU DEST ↓
┆19┆┆89┆┄┄and ALU OP fields.↲
↲
↲
┆b0┆┆a1┆4.3.1.14 T Field = MIR(18)↲
↲
         ┆84┆The T field is used in connection with the condition ↓
┆19┆┆89┆┄┄select field, COND SEL, to specify whether the true or ↓
┆19┆┆89┆┄┄the complemented value of the selected condition, ↓
┆19┆┆89┆┄┄SELCOND, is used as test condition, TESTCOND.↲
↲
         T = 0: TESTCOND = -, SELCOND↲
         T = 1: TESTCOND = SELCOND↲
↲
↲
┆b0┆┆a1┆4.3.1.15 COND SEL Field = MIR(19:23)↲
↲
         ┆84┆The COND SEL field is used to select 1 of 32 condition ↓
┆19┆┆89┆┄┄bits for control of conditional jumps and microprogram ↓
┆19┆┆89┆┄┄loops.↲
↲
         ┆b0┆┆a1┆COND SEL   SELECTED CONDITION, SELCOND↲
↲
         00 000     0↲
         00 001     NNEG (F> = 0)↲
         00 010     NZERO (F<┆1f┆> 0)↲
         00 011     OVFL (arithmetic overflow)↲
         00 100     CARRY (Carry from ALU bit(0))↲
         00 101     NORM (RESBUS(0) <> RESBUS(1))↲
         00 110     Unused↲
         00 111     -,FPU AVAILABLE↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆COND SEL   SELECTED CONDITION, SELCOND↲
↲
         01 000     MONITOR MODE↲
         01 001     ESCAPE MODE↲
         01 010     AFTER AM↲
         01 011     AFTER ESCAPE↲
         01 100     INTEGER MASK↲
         01 101     FLOATING POINT MASK↲
         01 110     IFIELD↲
         01 111     LINK (WFIELD(0) <> WFIELD(1))↲
↲
         10 000     -, MEMADRR (I/O ADDR < 8)↲
         10 001     -, WADDR (I/O ADDR < 0 : I/O ADDR > = 8)↲
         10 010     ODD (I/O ADDR(23))↲
         10 011     -,CPUBUS READY↲
         10 100     BUS ERROR↲
         10 101     BUS TIMEOUT↲
         10 110     BUS NACK↲
         10 111     BUS PARITY↲
↲
         11 000     INTERRUPT↲
         11 001     -,TCP INPUT INTERRUPT↲
         11 010     TPACK (TCP OUT ACK)↲
         11 011     RESTART ENABLE (-, OCP AUTOLOAD) INTERRUPT↲
         11 100     SHORT (TEST MODE switch SHORT)↲
         11 101     TSTON (TEST switch ON)↲
         11 110     PLOW (Power low warning)↲
         11 111     Unused↲
↲
         ┆84┆It should be noted that the conditions NNEG, NZERO, ↓
┆19┆┆89┆┄┄OVFL, CARRY, and NORM are updated by all ↓
┆19┆┆89┆┄┄microinstruction formats with the exception of formats 0 ↓
┆19┆┆89┆┄┄and 7. The above mentioned conditions are delayed one ↓
┆19┆┆89┆┄┄microcycle due to buffering, they may therefore be ↓
┆19┆┆89┆┄┄tested by the microinstruction following the ↓
┆19┆┆89┆┄┄microinstruction that generates the condition.↲
↲
↲
┆b0┆┆a1┆4.3.1.16 SI Field = MIR(24:25)↲
↲
         ┆84┆The SI field controls the input (SHIN) to the vacated ↓
┆19┆┆89┆┄┄position in shift microinstructions. SHIN depends on ↓
┆19┆┆89┆┄┄both the SI field and the shift direction.↲
↲
         ┆b0┆┆a1┆SI   SHIFT INPUT, SHIN↲
 ↲
         00   0↲
         01   SHLINK (shift link)↲
         10   Right shift: SIGN EXTENSION↲
              Left shift: ADDCOND↲
         11   Unused↲
 ↲
         ┆84┆SIGN EXTENSION requires that the ALU OP field specifies ↓
┆19┆┆89┆┄┄an arithmetic operation.↲
↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.3.1.17 TST Field = MIR(26:27)↲
↲
         ┆84┆The TST field controls ADDCOND and DIVSIGN, which are ↓
┆19┆┆89┆┄┄conditions intended to be used in multiply and divide ↓
┆19┆┆89┆┄┄microinstructions. These conditions are only affected by ↓
┆19┆┆89┆┄┄format 4, 5, and 6 microinstructions.↲

════════════════════════════════════════════════════════════════════════
↓
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
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↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
         Figure 4.1: Microinstruction Formats.↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆TST   FUNCTION↲
↲
         00    CONDITIONS UNCHANGED↲
         01    ADDCOND: = -, Q(23), ALU DEST = 100↲
         10    ADDCOND: = F(0) exor -, DIVSIGN↲
         11    DIVSIGN: = F(0)↲
↲
↲
┆b0┆┆a1┆4.3.2    Microinstruction Formats↲
↲
         ┆84┆The following subsections gives a short description of ↓
┆19┆┆89┆┄┄the characteristics of each of the eight ↓
┆19┆┆89┆┄┄microinstruction formats shown on fig. 4.1. the more ↓
┆19┆┆89┆┄┄detailed function of a microinstruction will normally ↓
┆19┆┆89┆┄┄appear from the description of the fields in subsection ↓
┆19┆┆89┆┄┄4.3.1.↲
↲
↲
┆b0┆┆a1┆4.3.2.1  Format 0: Load Immediate↲
↲
         ┆84┆The immediate Operand Register (IMOP) is loaded with the ↓
┆19┆┆89┆┄┄contents of the 24-bit IMMEDIATE OPERAND field of the ↓
┆19┆┆89┆┄┄microinstruction.↲
↲
         IMOP: = MIR(12:35)↲
↲
         ┆84┆The execution of this microinstruction does not change ↓
┆19┆┆89┆┄┄conditions.↲
↲
↲
┆b0┆┆a1┆4.3.2.2  Format 1: Load Scratchpad↲
↲
         ┆84┆This format operates on the General Registers, the Q-↓
┆19┆┆89┆┄┄register, and the Scratchpad. The addressed Scratchpad ↓
┆19┆┆89┆┄┄location is loaded with the contents of the RESBUS.↲
↲
         SCRATCHP(SPADDR): = RESBUS↲
↲
         Shifts cannot be specified with this format.↲
↲
         ALU DEST = 000, 001, 010 or 011.↲
↲
↲
┆b0┆┆a1┆4.3.2.3  Format 2: Read Scratchpad/Load Register↲
↲
         ┆84┆This microinstruction type operates on the General ↓
┆19┆┆89┆┄┄Registers, the Q-register, the Scratchpad, and the ↓
┆19┆┆89┆┄┄Destination Registers. The complement of the contents of ↓
┆19┆┆89┆┄┄the addressed Scratchpad location is transferred to the ↓
┆19┆┆89┆┄┄SBUS. The addressed Destination Register is loaded with ↓
┆19┆┆89┆┄┄the contents of the RESBUS.↲
↲
         SBUS: = -, SCRATCHP(SPADDR)↲
         Register(DEST REG): = RESBUS↲
↲

════════════════════════════════════════════════════════════════════════
↓
         Shifts cannot be specified with this format.↲
↲
         ALU DEST = 000, 001, 010, or 011.↲
↲
↲
┆b0┆┆a1┆4.3.2.4  Format 3: Read/Load Register↲
↲
         ┆84┆This format operates on: General Registers, Q-register, ↓
┆19┆┆89┆┄┄Source Registers, and Destination Registers. The ↓
┆19┆┆89┆┄┄contents of the addressed Source Register is transferred ↓
┆19┆┆89┆┄┄to the SBUS. The addressed Destination Register is ↓
┆19┆┆89┆┄┄loaded with the contents of the RESBUS.↲
↲
         SBUS: = Register(SOURCE REG)↲
         Register(DEST REG): = RESBUS↲
↲
         Shifts cannot be specified with this format.↲
↲
         ALU DEST = 000, 001, 010 or 011.↲
↲
↲
┆b0┆┆a1┆4.3.2.5  Format 4: Shift↲
↲
         ┆84┆The microinstruction operates on the General Registers ↓
┆19┆┆89┆┄┄and the Q-register, and is primarily intended to be used ↓
┆19┆┆89┆┄┄for shift operations. As the format includes the T and ↓
┆19┆┆89┆┄┄COND SEL fields it may be used with NEXT = 101 (loop ↓
┆19┆┆89┆┄┄return).↲
↲
↲
┆b0┆┆a1┆4.3.2.6  Format 5: Multiply↲
↲
         ┆84┆This format operatis on the General Registers and the Q-↓
┆19┆┆89┆┄┄register, and is primarily intended to be used for ↓
┆19┆┆89┆┄┄multiplication routines. Selection of the ALU operands ↓
┆19┆┆89┆┄┄are controlled by the ALU OP field and by ADDCOND.↲
↲
         ┆b0┆┆a1┆ALU OP   ADDCOND   OPERAND R   OPERAND S↲
↲
         0X0      0         GRA         Q↲
                  1         ZERO        Q↲
         0X1 *)   0         GRA         GRB↲
                  1         ZERO        GRB↲
         1X0      0         ZERO        GRA↲
                  1         SBUS        Q↲
         1X1      0         SBUS        GRA↲
                  1         SBUS        ZERO↲
↲
         *) 'Normal' value for multiplication.↲
↲
↲
┆b0┆┆a1┆4.3.2.7  Format 6: Divide↲
↲
         ┆84┆The microinstruction operates on the General Registers ↓
┆19┆┆89┆┄┄and the Q-register, and is primarily intended to be used ↓
┆19┆┆89┆┄┄for division routines. The ALU function is controlled by ↓
┆19┆┆89┆┄┄the ALU FUNC field and by ADDCOND.↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆ALU FUNC   ADDCOND   ALU FUNCTION↲
↲
         00X  *)    0         R + S + Cin↲
                    1         - R + S - 1 + Cin↲
         01X        0         R - S - 1 + Cin↲
                    1         R ! S↲
         10X        0         R & S↲
                    1         -, R & S↲
         11X        0         R exor S↲
                    1         -, (R exor S)↲
↲
         *) 'Normal' value for division.↲
↲
↲
┆b0┆┆a1┆4.3.2.8  Format 7: Conditional Jump↲
↲
         ┆84┆This microinstruction executes conditional jumps and ↓
┆19┆┆89┆┄┄conditional subroutine calls. In addition it may be used ↓
┆19┆┆89┆┄┄for synchronization with I/O operations on the System ↓
┆19┆┆89┆┄┄Bus. The function of the microinstruction is controlled ↓
┆19┆┆89┆┄┄by the W, S, and X fields, MIR (15, 16, 17), which ↓
┆19┆┆89┆┄┄respectively specifies: I/O synchronization, subroutine ↓
┆19┆┆89┆┄┄call, and jump address equal to contents of MIX.↲
↲
         W = 0: No synchronization↲
         W = 1: ┆84┆The execution of the microinstructions is delayed ↓
┆19┆┆90┆┄┄(clock stopped) until I/O is ready. ↓
┆19┆┆90┆┄┄Synchronization cannot be specified in a ↓
┆19┆┆90┆┄┄microinstruction immediately following the ↓
┆19┆┆90┆┄┄microinstruction starting an I/O operation. I/O ↓
┆19┆┆90┆┄┄Ready is delayed one clock period.↲
↲
         ┆84┆The condition (TEST COND) determines how the next ↓
┆19┆┆89┆┄┄microinstruction address is derived.↲
↲
         TESTCOND = 0: ┆84┆Next address selected by NEXT field as ↓
┆19┆┆97┆┄┄specified in 4.3.1.2.↲
         TESTCOND = 1: ┆84┆A jump is executed and next address is ↓
┆19┆┆97┆┄┄controlled by S and X fields as specified ↓
┆19┆┆97┆┄┄below.↲
↲
         ┆b0┆┆a1┆S, X   FUNCTION for TESTCOND = 1↲
↲
         00     CSADDR: = JUMP ADDR; MAR: = JUMP ADDR + 1↲
         01     CSADDR: = MIX; MAR: = MIX + 1↲
         10     CSADDR: = JUMP ADDR; SP: = SP + 1;↲
                STACK(SP): = MAR; MAR: = JUMP ADDR + 1↲
         11     CSADDR: = MIX; SP: = SP + 1; STACK(SP): = MAR;↲
                MAR: = MIX + 1↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆5.       LOGIC DIAGRAMS AND SIGNAL DESCRIPTIONS↲
↲
         ┆84┆The left hand pages of this chapter contains a ↓
┆19┆┆89┆┄┄description of the signals generated on the logic ↓
┆19┆┆89┆┄┄diagram on the corresponding right hand side. The column ↓
┆19┆┆89┆┄┄'Destination' refers to the diagram number, where the ↓
┆19┆┆89┆┄┄signal in question is used. All references between logic ↓
┆19┆┆89┆┄┄diagrams make use of the diagram number in the lower ↓
┆19┆┆89┆┄┄right corner of the diagrams.↲
↲
         ┆84┆Signal and diagram references are indicated on the logic ↓
┆19┆┆89┆┄┄diagrams as shown below.↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
         Signals preceded with '-,' are active low.↲

════════════════════════════════════════════════════════════════════════
↓
↲
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         SEQ (0:11)      5               ┆84┆Control Store Address ↓
┆19┆┆a9┆┄┄from Microprogram ↓
┆19┆┆a9┆┄┄Sequencer. Tri-state ↓
┆19┆┆a9┆┄┄outputs.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         S1, S0          1               ┆84┆Control signals for ↓
┆19┆┆a9┆┄┄microprogram sequencer. ↓
┆19┆┆a9┆┄┄Selects address source.↲
↲
         -, FE, PUP      1               ┆84┆Control signals for ↓
┆19┆┆a9┆┄┄microprogram sequencer. ↓
┆19┆┆a9┆┄┄Controls the subroutine ↓
┆19┆┆a9┆┄┄return stack.↲
↲
         -, ENSEQ        1               Enable signals which ↲
         -, ENJUMP       4               controls the address ↲
         -, ENMIX        4               sources for the control↲
         -, ENTABLE      4               ┆84┆store address bus, ↓
┆19┆┆a9┆┄┄CSADDR (0:11).↲
↲
         ONEA            2,3             Logic one generators for↲
         ONEB            3               unused inputs.↲
↲
         -, ENCONDGR(0)  2               Enable signals for jump↲
         -, ENCONDGR(1)  3               condition selectors. ↲
         -, ENCONDGR(2)  3               Selects respectively ↲
         -, ENCONDGR(3)  3               ┆84┆conditions (0:7), ↓
┆19┆┆a9┆┄┄(8:15),(16:23), and ↓
┆19┆┆a9┆┄┄(24:31).↲
↲
         SELCOND         2               ┆84┆The jump condition ↓
┆19┆┆a9┆┄┄selected by microin- ↓
┆19┆┆a9┆┄┄struction bits (18:23). ↓
┆19┆┆a9┆┄┄Tri-state output.↲
↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         SELCOND(1)      2               Outputs from jump con-↲
         SELCOND(2)      2               ditions 8 : 15, 16 : 23,↲
         SELCOND(3)      2               ┆84┆and 24 : 31. Tri-state ↓
┆19┆┆a9┆┄┄outputs.↲
↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         TABLE (0:11)    5               ┆84┆Control store address ↓
┆19┆┆a9┆┄┄from instruction ↓
┆19┆┆a9┆┄┄decoding table. Tri-↓
┆19┆┆a9┆┄┄state outputs.↲
↲
         JUMP (0:11)     5               ┆84┆Control store address ↓
┆19┆┆a9┆┄┄from microprogram jump ↓
┆19┆┆a9┆┄┄address register. Tri-↓
┆19┆┆a9┆┄┄state outputs.↲
↲
         MIX (0:11)      5               ┆84┆Control store address ↓
┆19┆┆a9┆┄┄from microprogram index ↓
┆19┆┆a9┆┄┄register. Tri-state ↓
┆19┆┆a9┆┄┄outputs.↲
↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         CSADDR (0:1)    1,5             ┆84┆Control store address, ↓
┆19┆┆a9┆┄┄bits (0:1)↲
↲
         CSADDR (2:11)   1,6,7           Control store address,↲
                         8,9,10          bits (2:11)↲
↲
         -, CSSELECT (0) 6,7,8           Enable signal for con-↲
                         9,10            ┆84┆trol store addresses ↓
┆19┆┆a9┆┄┄(0:1023).↲
↲
         -, CSSELECT (1) 6,7,8           Enable signal for con-↲
                         9,10            ┆84┆trol store addresses ↓
┆19┆┆a9┆┄┄(1024:2047).↲
↲
         -, CSSELECT (2) 6,7,8           Connected to 0V with ↲
                         9,10            ┆84┆jumper. May be connected ↓
┆19┆┆a9┆┄┄to CSADDR1 for control ↓
┆19┆┆a9┆┄┄store expansion.↲
↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         CS (0:7)        11              ┆84┆Control store, bits ↓
┆19┆┆a9┆┄┄(0:7).↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         CS (8:15)       11              ┆84┆Control store, bits ↓
┆19┆┆a9┆┄┄(8:15).↲
↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         CS (16:17)      11              ┆84┆Control store, bits ↓
┆19┆┆a9┆┄┄(16:17).↲
↲
         CS (18)         2,3,11,41       ┆84┆Control store, bit (18).↲
↲
         CS (19)         11,41           ┆84┆Control store, bit (19).↲
↲
         CS (20)         11              ┆84┆Control store, bit (20).↲
↲
         CS (21)         2,3,11          ┆84┆Control store, bit (21).↲
↲
         CS (22:23)      2,3,11,41       ┆84┆Control store, bits ↓
┆19┆┆a9┆┄┄(22:23).↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         CS (24:25)      4,11            ┆84┆Control store, bits ↓
┆19┆┆a9┆┄┄(24:25).↲
↲
         CS (26:27)      4,11,41         ┆84┆Control store, bits ↓
┆19┆┆a9┆┄┄(26:27).↲
↲
         CS (28:31)      4,11            ┆84┆Control store, bits ↓
┆19┆┆a9┆┄┄(28:31).↲
↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         CS (32:35)      4,11            ┆84┆Control store, bits ↓
┆19┆┆a9┆┄┄(32:35).↲
↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         TPACK           3               ┆84┆Acknowledge signal from ↓
┆19┆┆a9┆┄┄TCA810 synchronized with ↓
┆19┆┆a9┆┄┄CPU clock.↲
↲
         TSTON           3               ┆84┆Signals from the ↓
┆19┆┆a9┆┄┄switches 'TEST' and↲
         SHORT           3               ┆84┆'TEST MODE' on the PCBA ↓
┆19┆┆a9┆┄┄front panel.↲
↲
         MIR (0)         12↲
         MIR (1:2)       2,12↲
         MIR (3)         2,4,12↲
         MIR (4:6)       12,14↲
         MIR (7)         12,16,17,18↲
         MIR (8:9)       12,16,17,18,20↲
         MIR (10)        12,16,17,18↲
         MIR (11)        12,19↲
         MIR (12:14)     12,16,17,18,25↲
         MIR (15)        12,14,19,25     ┆84┆Microinstruction ↓
┆19┆┆a9┆┄┄register, bits (0:35)↲
         MIR (16:17)     2,12,19,25↲
         MIR (18)        12,15,25↲
         MIR (19)        2,12,15,25↲
         MIR (20)        2,12,14,25,41↲
         MIR (21)        12,14,25,41↲
         MIR (22:23)     12,14,25↲
         MIR (24:25)     12,14,20,24,↲
                         25,41↲
         MIR (26:27)     12,14,24,25↲
         MIR (28:31)     12,16,17,18,25↲
         MIR (32:33)     12,16,17,18,↲
                         19,25↲
         MIR (34:35)     12,19,25↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         CSPARERROR      41              ┆84┆Control store parity ↓
┆19┆┆a9┆┄┄error. Indicates parity ↓
┆19┆┆a9┆┄┄error in the word ↓
┆19┆┆a9┆┄┄contained in the ↓
┆19┆┆a9┆┄┄microinstruction ↓
┆19┆┆a9┆┄┄register. Odd parity is ↓
┆19┆┆a9┆┄┄used.↲
↲
         -, CSPARERROR   12              ┆84┆Same as above. Used to ↓
┆19┆┆a9┆┄┄drive the 'CONTROL STORE ↓
┆19┆┆a9┆┄┄PARITY ERROR' indicator ↓
┆19┆┆a9┆┄┄on the PCBA front panel.↲
↲
         TESTON          11              ┆84┆Control signal from the ↓
┆19┆┆a9┆┄┄switch 'TEST' on the ↓
┆19┆┆a9┆┄┄PCBA front panel.↲
↲
         TESTM SHORT     11              ┆84┆Control signal from the ↓
┆19┆┆a9┆┄┄switch 'TEST MODE' on ↓
┆19┆┆a9┆┄┄the PCBA front panel.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         10 MHz CLOCK    41              10 and 5 MHz clock ↲
          5 MHz CLOCK    41              ┆84┆signals used to ↓
┆19┆┆a9┆┄┄generated the 5 MHz ↓
┆19┆┆a9┆┄┄MASTERCLOCK signal with ↓
┆19┆┆a9┆┄┄25% duty cycle.↲
↲
         10 KHZCLOCK     31              ┆84┆10 kHz clock signal used ↓
┆19┆┆a9┆┄┄to control the Real Time ↓
┆19┆┆a9┆┄┄Clock by generating ↓
┆19┆┆a9┆┄┄interrupt every 0.1 ↓
┆19┆┆a9┆┄┄millisecond.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         -,FORMAT (0)    Unused          Decoding of the format-↲
         -,FORMAT (1)    14              field of the microin-↲
         -,FORMAT (2)    14,41           struction.↲
         -,FORMAT (3)    41↲
         -,FORMAT (4)    Unused↲
         -,FORMAT (5)    19↲
         -,FORMAT (6)    19↲
         -,FORMAT (7)    2↲
         CPUCLOCKB       30,31,32        CP for interrupt system.↲
         CPUCLOCKA       16,17,18        CP for the 2901A's.↲
         CPMIR           1,2,3,4,11      ┆84┆CP for Microinstruction ↓
┆19┆┆a9┆┄┄Register, microprogram ↓
┆19┆┆a9┆┄┄sequencer, jump ↓
┆19┆┆a9┆┄┄condition selectors, and ↓
┆19┆┆a9┆┄┄Microprogram Jump ↓
┆19┆┆a9┆┄┄Address Register.↲
         CPIMOP          25              ┆84┆CP for immediate Operand ↓
┆19┆┆a9┆┄┄Register.↲
         CPCOND          15              ┆84┆CP for Condition ↓
┆19┆┆a9┆┄┄Register.↲
         CPSCRATCHP      24              ┆84┆CP for Scratchpad ↓
┆19┆┆a9┆┄┄Memory.↲
         CONDLD (0,1)    15              ┆84┆Control load of ADDCOND ↓
┆19┆┆a9┆┄┄and -,DIVSIGN.↲
         CPCPUSTATUS     27              ┆84┆CP for CPU Status ↓
┆19┆┆a9┆┄┄Register.↲
         CPI/OADDR       15,33           ┆84┆CP for I/O Address ↓
┆19┆┆a9┆┄┄Register.↲
         CPDATAOUT       34              ┆84┆CP for Data Out Register↲
         CPCONTROLOUT    25              ┆84┆CP for Control Output ↓
┆19┆┆a9┆┄┄Register.↲
         CPTCPDATAOUT    28              ┆84┆CP for TCP Data Out ↓
┆19┆┆a9┆┄┄Register.↲
         CPINSTRREG      27              ┆84┆CP for Instruction ↓
┆19┆┆a9┆┄┄Register.↲
         CPMIX           4               ┆84┆CP for Microprogram ↓
┆19┆┆a9┆┄┄Index Register.↲
         CPINTR          30              ┆84┆Clears intr. bit ↓
┆19┆┆a9┆┄┄addressed by RESBUS ↓
┆19┆┆a9┆┄┄(18:23).↲
         CPCBCONTROL     41              ┆84┆CP for CPUBUS control ↓
┆19┆┆a9┆┄┄register.↲
         -,ENSCRATCHP    24↲
         -,ENIMOP        25↲
         -,ENSIGNEXT     26↲
         -,ENROTATE      26╞	       Enable signals for ↲
         -,ENDATAIN      35              registers connected to ↲
         -,ENINTRLEV     32              the source bus.↲
         -,ENTCPDATAIN   28↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
                                         ┆84┆JUMP CONDITIONS AND ↓
┆19┆┆a9┆┄┄STATUS BITS:↲
         NNEG            2               RESULT > = 0↲
         NZERO           2               RESULT <> 0↲
         OVFL            2               Arithmetic overflow↲
         CARRY           2,19            ┆84┆Carry out of bit (0) of ↓
┆19┆┆a9┆┄┄ALU↲
         SHLINK          20              ┆84┆Bit shifted out in shift ↓
┆19┆┆a9┆┄┄instruction.↲
         NORM            2               RESULT normalized↲
         ADDCOND         15,19,20        ┆84┆Controls ALU operands in ↓
┆19┆┆a9┆┄┄mulitply and ALU ↓
┆19┆┆a9┆┄┄function in divide ↓
┆19┆┆a9┆┄┄microinstructions.↲
         -,DIVSIGN       15              ┆84┆Used to store divisor ↓
┆19┆┆a9┆┄┄sign in divide ↓
┆19┆┆a9┆┄┄operations.↲
         DIVCOND         15              ┆84┆DIVCOND = RESULT (0) ↓
┆19┆┆a9┆┄┄exor -,DIVSIGN ↲
         RES(0) =┆a3┆┆e3┆ RES(1) 15              RESULT (0) <> RESULT (1)↲
         F < 0 ! F < 8   15              RESULT < 8↲
         ENBUSREQ        37              -,MIR (19) or RESULT >=8↲
         WRITE           37              ┆84┆Control signal for I/O ↓
┆19┆┆a9┆┄┄operations. Indicates ↓
┆19┆┆a9┆┄┄data transfer from CPU ↓
┆19┆┆a9┆┄┄to slave.↲
         -,MEMADDR       3               I/O ADDRESS < 8↲
         -,WADDR         3               ┆84┆I/O ADDRESS < 0 or I/O ↓
┆19┆┆a9┆┄┄ADDR >= 8↲
         WADDR (0,1)     19              ┆84┆WADDR (0,1) = I/O ADDR ↓
┆19┆┆a9┆┄┄(21,22). Used as ↓
┆19┆┆a9┆┄┄register address.↲
         ODD             3               ┆84┆I/O ADDRESS is an odd ↓
┆19┆┆a9┆┄┄number.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         SHIFT I/O R (0) 20              RAM-shifter in/out, bit↲
                                         (0), tri-state↲
         SHIFT I/O Q (0) 20              ┆84┆Q-shifter in/out, bit ↓
┆19┆┆a9┆┄┄(0), tri state↲
         F(0)            15,20           F(0) = RESULT(0)↲
         F(0:3) = 0      20              ┆84┆RESULT (0:3) = 0, open ↓
┆19┆┆a9┆┄┄collector output.↲
         -,G(0)          19              ┆84┆Carry generate for bits ↓
┆19┆┆a9┆┄┄(0:3)↲
         -,P(0)          19              ┆84┆Carry propagate for bits ↓
┆19┆┆a9┆┄┄(0:3)↲
         OVR             15,20           Arithmetic overflow.↲
         RESBUS (0:1)    15,24,26        RESULT BUS (0:1)↲
                         27,33,34,42↲
         RESBUS (2:3)    24,26,27        RESULT BUS (2:3)↲
                         33,34,42↲
         F(4:7) = 0      20              ┆84┆RESULT (4:7) = 0, open ↓
┆19┆┆a9┆┄┄collector output.↲
         -,G(1)          19              ┆84┆Carry generate for bits ↓
┆19┆┆a9┆┄┄(4:7)↲
         -,P(1)          19              ┆84┆Carry propagate for bits ↓
┆19┆┆a9┆┄┄(4:7)↲
         RESBUS (4:5)    24,26,27        RESULT BUS (4:5)↲
                         33,34,42↲
         RESBUS (6:7)    24,26,27        RESULT BUS (6:7)↲
                         33,34,41,42↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         SHIFT I/O R (8) 16              ┆84┆RAM-shifter in/out, bit ↓
┆19┆┆a9┆┄┄(8), tri-state↲
         SHIFT I/O Q (8) 16              ┆84┆Q-shifter in/out, bit ↓
┆19┆┆a9┆┄┄(8), tri-state.↲
         F(8:11) = 0     20              ┆84┆RESULT (8:11) = 0, open ↓
┆19┆┆a9┆┄┄collector output.↲
         -,G(2)          19              ┆84┆Carry generate for bits ↓
┆19┆┆a9┆┄┄(8:11)↲
         -,P(2)          19              ┆84┆Carry propagate for bits ↓
┆19┆┆a9┆┄┄(8:11)↲
         RESBUS (8:11)   24,26,27        RESULT BUS (8:11)↲
                         33,34,42↲
         F(12:15) = 0    20              ┆84┆RESULT (12:15) = 0, open ↓
┆19┆┆a9┆┄┄collector output.↲
         -,G(3)          19              ┆84┆Carry generate for bits ↓
┆19┆┆a9┆┄┄(12:15)↲
         -,P(3)          19              ┆84┆Carry propagate for bits ↓
┆19┆┆a9┆┄┄(12:15).↲
         RESBUS (12:15)  4,24,25,26      RESULT BUS (12:15)↲
                         32,33,41,43↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         SHIFT I/O R(16) 17              ┆84┆RAM-shifter in/out, bit ↓
┆19┆┆a9┆┄┄(16), tri-state↲
         SHIFT I/O Q(16) 17              ┆84┆Q-shifter in/out, bit ↓
┆19┆┆a9┆┄┄(16), tri-state↲
         F(16:19) = 0    20              ┆84┆RESULT (16:17) = 0, open ↓
┆19┆┆a9┆┄┄collector output.↲
         -,G(4)          19              ┆84┆Carry generate for bits ↓
┆19┆┆a9┆┄┄(16:19)↲
         -,P(4)          19              ┆84┆Carry propagate for bits ↓
┆19┆┆a9┆┄┄(16:19)↲
         RESBUS (16:17)  4,24,25         RESULT BUS (16:19)↲
                         26,28,33↲
                         34,43↲
         RESBUS(18:19)   4,24,25,26      RESULT BUS (18:19)↲
                         28,30,33↲
                         34,41,43↲
         F(20)           20              ┆84┆F(20) = RESULT (20)↲
         F(20:23) = 0    20              ┆84┆RESULT (20:23) = 0, open ↓
┆19┆┆a9┆┄┄collector output↲
         -,G(5)          19              ┆84┆Carry generate for bits ↓
┆19┆┆a9┆┄┄(20:23)↲
         -,P(5)          19              ┆84┆Carry propagate for bits ↓
┆19┆┆a9┆┄┄(20:23)↲
         RESBUS (20)     4,24,25         RESULT BUS (20)↲
                         26,28,30↲
                         30,34,41,43↲
         RESBUS (21)     4,15,24,25      RESULT BUS (21)↲
                         26,28,30,33↲
                         34,41,43↲
         RESBUS (22:23)  4,15,24         RESULT BUS (22:23)↲
                         25,26,28↲
                         30,33,34,43↲
         SHIFT I/O R(23) 20              ┆84┆RAM-shifter in/out, bit ↓
┆19┆┆a9┆┄┄(23), tri-state↲
         SHIFT I/O Q(23) 20              ┆84┆Q-shifter in/out, bit ↓
┆19┆┆a9┆┄┄(23), tri-state.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         CARRY(0)        15              Carry from ALU bit (0)↲
         CARRY(4)        16              ┆84┆Carry to 2901A bit (3)↲
         CARRY(8)        16              ┆84┆Carry to 2901A bit (7)↲
         CARRY(12)       17              Carry to 2901A bit (11)↲
         CARRY(16)       17              Carry to 2901A bit (15)↲
         CARRY(20)       18              Carry to 2901A bit (19)↲
         CARRY IN        18,19           ┆84┆Output from carry ↓
┆19┆┆a9┆┄┄selector. Carry to 2901A ↓
┆19┆┆a9┆┄┄bit (23)↲
         I1              16,17,18        ┆84┆Controls ALU operands in ↓
┆19┆┆a9┆┄┄multiply microinstruc-↓
┆19┆┆a9┆┄┄tions.↲
         I3              16,17,18        ┆84┆Controls ALU function in ↓
┆19┆┆a9┆┄┄divide microinstructions↲
         BADDR (2:3)     16,17,18        ┆84┆Two least significant ↓
┆19┆┆a9┆┄┄bits of B address to ↓
┆19┆┆a9┆┄┄2901A.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         RIGHT SHIN R(0) 16,20           ┆84┆Shift input to RAM-↓
┆19┆┆a9┆┄┄shifter bit (0) for ↓
┆19┆┆a9┆┄┄right shifts. Tri-state ↓
┆19┆┆a9┆┄┄signal.↲
         LEFT SHIN Q(23) 18,20           ┆84┆Shift input to Q-shifter ↓
┆19┆┆a9┆┄┄bit ( 23) for left ↓
┆19┆┆a9┆┄┄shifts. Tri-state ↓
┆19┆┆a9┆┄┄signal.↲
         LEFT SHIN R(23) 18,20           ┆84┆Shift input to RAM-↓
┆19┆┆a9┆┄┄shifter bit (23) for ↓
┆19┆┆a9┆┄┄left shifts. Tri-state ↓
┆19┆┆a9┆┄┄signal.↲
         SHIFTOUT        15              ┆84┆Bit shiftet out of RAM ↓
┆19┆┆a9┆┄┄or Q-shifter in shift ↓
┆19┆┆a9┆┄┄operation.↲
         RIGHT SHIN Q(0) 16,20           ┆84┆Shift input to Q-shifter ↓
┆19┆┆a9┆┄┄bit (0) for right ↓
┆19┆┆a9┆┄┄shifts. Tri-state ↓
┆19┆┆a9┆┄┄signal.↲
         -,MIR (8)       20              ┆84┆Control tri-state output ↓
┆19┆┆a9┆┄┄of multiplexers for ↓
┆19┆┆a9┆┄┄shift control.↲
         -,F(0)          15              -,F(0) = -,RESULT (0)↲
         MULTCOND        15              ┆84┆MULTCOND = -,Q(23) in ↓
┆19┆┆a9┆┄┄right shifts.↲
         -,F(20)         20              -,F(20) = -,RESULT (20)↲
         RES =┆a3┆┆e3┆ 0         15              RESULT <> 0↲
         F(0:20) =┆a3┆┆e3┆ 0     15              RESULT < 0 or RESULT >=8↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         SBUS (0:7)      16              ┆84┆SOURCE BUS (0:7). Input ↓
┆19┆┆a9┆┄┄to 2901A from external ↓
┆19┆┆a9┆┄┄source registers. Tri-↓
┆19┆┆a9┆┄┄state bus.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         SBUS (8:15)     17              ┆84┆SOURCE BUS (8:15). Input ↓
┆19┆┆a9┆┄┄to 2901A from external ↓
┆19┆┆a9┆┄┄source registers. Tri-↓
┆19┆┆a9┆┄┄state bus.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         SBUS (16:23)    18              ┆84┆SOURCE BUS (16:23). ↓
┆19┆┆a9┆┄┄Input to 2901A from ↓
┆19┆┆a9┆┄┄external source ↓
┆19┆┆a9┆┄┄registers. Tri-state ↓
┆19┆┆a9┆┄┄bus.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         SCRATCHP (0:7)  21              ┆84┆16 word Scratchpad ↓
┆19┆┆a9┆┄┄Memory.↲
         SCRATCHP (8:15) 22              ┆84┆Connected to SOURCE BUS.↲
         SCRATCHP (16:23)23              Tri-state outputs.↲

════════════════════════════════════════════════════════════════════════
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↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         IMOP (0:7)      21              ┆84┆Immediate Operand ↓
┆19┆┆a9┆┄┄Register.↲
         IMOP (8:15)     22              ┆84┆Connected to SOURCE BUS.↲
         IMOP (16:23)    23              Tri-state outputs.↲
         CPUSYSRST       40              ┆84┆System Reset signal ↓
┆19┆┆a9┆┄┄generated by CPU 811. ↓
┆19┆┆a9┆┄┄Connected to System Bus.↲
         RUN             29              ┆84┆Controls the 'RUN' lamp ↓
┆19┆┆a9┆┄┄on the OCP.↲
         AUTOLOADING     29              ┆84┆Controls the 'AUTOLOAD' ↓
┆19┆┆a9┆┄┄lamp on the OCP.↲
         SINGLEINSTR     28              ┆84┆Interrupt signal used to ↓
┆19┆┆a9┆┄┄control single ↓
┆19┆┆a9┆┄┄instruction execution.↲
         SET IV TIMER    31              ┆84┆Used to set the Interval ↓
┆19┆┆a9┆┄┄Timer interrupt flip-↓
┆19┆┆a9┆┄┄flop.↲
         TCPINACK        28              ┆84┆Acknowledge signal from ↓
┆19┆┆a9┆┄┄CPU to TCA.↲
         TCPOUTRDY       28              ┆84┆Ready signal from CPU to ↓
┆19┆┆a9┆┄┄TCA.↲
         TSTSYNC         -               ┆84┆Synchronization signal ↓
┆19┆┆a9┆┄┄controlled by micro-↓
┆19┆┆a9┆┄┄diagnostic routines. ↓
┆19┆┆a9┆┄┄Intended as scope ↓
┆19┆┆a9┆┄┄trigger.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         SIGNEXT (0:7)   21              Transfers bits (12:23)↲
         SIGNEXT (8:15)  22              from the RESULT BUS to ↲
         SIGNEXT (16:23) 23              ┆84┆the SOURCE BUS with bit ↓
┆19┆┆a9┆┄┄(12) extended as sign. ↓
┆19┆┆a9┆┄┄SIGNEXT (0:23) = 12 ext ↓
┆19┆┆a9┆┄┄RESBUS (12) con RESBUS ↓
┆19┆┆a9┆┄┄(12:23).↲
         ROTATE (0:7)    21              The contents of the ↲
         ROTATE (8:15)   22              RESULT BUS is rotated 12 ↲
         ROTATE (16:23)  23              ┆84┆bits and transferred to ↓
┆19┆┆a9┆┄┄the SOURCE BUS. ↓
┆19┆┆a9┆┄┄ROTATE(0:23) = ↓
┆19┆┆a9┆┄┄RESBUS(12:23) con ↓
┆19┆┆a9┆┄┄RESBUS(0:11)↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         FFIELD (0:5)    4               ┆84┆Instruction Register ↓
┆19┆┆a9┆┄┄bits (0:5). Contains the ↓
┆19┆┆a9┆┄┄function code of the ↓
┆19┆┆a9┆┄┄instruction being ↓
┆19┆┆a9┆┄┄executed.↲
         RFIELD          4               ┆84┆Instruction Register bit ↓
┆19┆┆a9┆┄┄(8). Relative ↓
┆19┆┆a9┆┄┄addressing.↲
         IFIELD          3               ┆84┆Instruction Register bit ↓
┆19┆┆a9┆┄┄(9). Indirect ↓
┆19┆┆a9┆┄┄addressing.↲
         LINK            3               W-FIELD <> 0↲
         WPRE (0,1)      19              ┆84┆WPRE selects first ↓
┆19┆┆a9┆┄┄register of a double ↓
┆19┆┆a9┆┄┄register.↲
         WFIELD(0)       19              Instruction Register ↲
         WFIELD(1)       19,27           ┆84┆bits (6,7). Selects ↓
┆19┆┆a9┆┄┄working register.↲
         XFIELD(0,1)     4,19            ┆84┆Instruction Register ↓
┆19┆┆a9┆┄┄bits (10,11). Selects ↓
┆19┆┆a9┆┄┄index register.↲
         ONE             14,27           ┆84┆Logic one generator for ↓
┆19┆┆a9┆┄┄unused inputs.↲
         MONMODE         3↲
         ESCMODE         3,4             Copy of bit (0:5) of ↲
         AFTERAM         3,4             STATUS word. Used as ↲
         AFTERESC        3,4             jump conditions and in ↲
         INTMASK         3               instruction decoding.↲
         FLOATPMASK      3↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         TCPBUSOUT (0:7) TCA             ┆84┆Data bus for data from ↓
┆19┆┆a9┆┄┄CPU to TCA.↲
         TCPDATAIN (0:7) 23              ┆84┆Data received from TCA. ↓
┆19┆┆a9┆┄┄Connected to SBUS ↓
┆19┆┆a9┆┄┄(16:23). Tri-state ↓
┆19┆┆a9┆┄┄outputs.↲
         -,TCPOUTRDY     TCA             ┆84┆Data ready signal from ↓
┆19┆┆a9┆┄┄CPU to TCA.↲
         -,TCPINACK      TCA             ┆84┆Acknowledge signal from ↓
┆19┆┆a9┆┄┄CPU to TCA.↲
         TCPINRDY        28              ┆84┆Ready signal received ↓
┆19┆┆a9┆┄┄from TCA.↲
         TCPOUTACK       3               ┆84┆Acknowledge signal ↓
┆19┆┆a9┆┄┄received from TCA.↲
         -,TCPINRDY      31              ┆84┆Ready signal received ↓
┆19┆┆a9┆┄┄from TCA. Generates ↓
┆19┆┆a9┆┄┄interrupt.↲
         -,SINGLEINSTR   31              ┆84┆Interrupt signal. ↓
┆19┆┆a9┆┄┄Controls single ↓
┆19┆┆a9┆┄┄instruction execution.↲
         1024 A21, B21,                  0 volt supply to TCA.↲
              A22, B22,↲
              A23↲
         1024 B23, A24,                  +5 volts supply to TCA.↲
              B24, A25,↲
              B25↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         RESTARTEN       31              ┆84┆RESTARTEN = 0 when the ↓
┆19┆┆a9┆┄┄'AUTOLOAD' push-button ↓
┆19┆┆a9┆┄┄on the OCP is activated.↲
         REMAUTOLOAD     31              ┆84┆Autoload signal from ↓
┆19┆┆a9┆┄┄external device.↲
         POWEROKLAMP +   OCP             Controls 'POWER OK' lamp ↲
         POWEROKLAMP -   OCP             on OCP.↲
         RUNLAMP +       OCP             Controls 'RUN' lamp on ↲
         RUNLAMP -       OCP             OCP.↲
         AUTOLOADLAMP +  OCP             Controls 'AUTOLOAD LAMP' ↲
         AUTOLOADLAMP -  OCP             on OCP.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         -,INTRREQ       30,36           ┆84┆External interrupt ↓
┆19┆┆a9┆┄┄request.↲
         INTRADDR(0:2)   30,31,32        Address a bit in the ↲
         INTRADDR(3:5)   32              interrupt register.↲
         -,CLEARREQ      30              ┆84┆A 0 indicates that the ↓
┆19┆┆a9┆┄┄intr. bit addressed by ↓
┆19┆┆a9┆┄┄INTRADDR should be ↓
┆19┆┆a9┆┄┄cleared.↲
         CLEARINTR(0:7)  31              ┆84┆Reset signal for intr. ↓
┆19┆┆a9┆┄┄bits (0:7).↲
         -,INTRREQSYN    not used        ┆84┆Synchronized ext. intr. ↓
┆19┆┆a9┆┄┄req.↲
         -,SETINTR       30,32           ┆84┆Sets intr. bit addressed ↓
┆19┆┆a9┆┄┄by INTRADDR.↲
         -,CLEARINTR     30,32           ┆84┆Clears intr. bit ↓
┆19┆┆a9┆┄┄addressed by INTRADDR.↲
         CLEARINTR       30              ┆84┆Selects address source ↓
┆19┆┆a9┆┄┄for INTRADDR.↲
         I/O END         14              ┆84┆Indicates that an I/O ↓
┆19┆┆a9┆┄┄transfer has been ↓
┆19┆┆a9┆┄┄completed.↲
         PLOW            3               ┆84┆Synchronized power low ↓
┆19┆┆a9┆┄┄signal from power ↓
┆19┆┆a9┆┄┄supply.↲
         -,POWERUPRST    1,2,14,41       ┆84┆Reset signal used to ↓
┆19┆┆a9┆┄┄initialize logic, when ↓
┆19┆┆a9┆┄┄power is turned on. The ↓
┆19┆┆a9┆┄┄signal is low for min. ↓
┆19┆┆a9┆┄┄one clock period.↲
         POWEROK         30              ┆84┆Power ok signal from ↓
┆19┆┆a9┆┄┄power supply↲
         BUSERROR        3               ┆84┆Indicates that at least ↓
┆19┆┆a9┆┄┄one of the I/O transfer ↓
┆19┆┆a9┆┄┄error bits is set.↲
         BUSTIMEOUT      3               ┆84┆The addressed unit did ↓
┆19┆┆a9┆┄┄not respond within ↓
┆19┆┆a9┆┄┄approximately 4 ↓
┆19┆┆a9┆┄┄microsec.↲
         BUSNACK         3               ┆84┆The addressed unit ↓
┆19┆┆a9┆┄┄responded with a NACK.↲
         BUSPARITY       3               ┆84┆Parity error in received ↓
┆19┆┆a9┆┄┄data.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         INTERRUPT       3               ┆84┆Indicates that one or ↓
┆19┆┆a9┆┄┄more bits in the ↓
┆19┆┆a9┆┄┄Interrupt Register is ↓
┆19┆┆a9┆┄┄set (=0).↲
         -,INTR (1:7)    31              ┆84┆Interrupt Register bits ↓
┆19┆┆a9┆┄┄(1:7). An interrupt is ↓
┆19┆┆a9┆┄┄represented by a 0.↲
         -,RSTINTR(4:7)  31              ┆84┆Reset signals for ↓
┆19┆┆a9┆┄┄interrupt bits (4:7).↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         INTR            31              ┆84┆Interrupt output from ↓
┆19┆┆a9┆┄┄interrupt priority ↓
┆19┆┆a9┆┄┄encoder.↲
         INTRLEV (0:7)   23              ┆84┆Interrupt level ↓
┆19┆┆a9┆┄┄register, which contains ↓
┆19┆┆a9┆┄┄the current interrupt ↓
┆19┆┆a9┆┄┄level with highest ↓
┆19┆┆a9┆┄┄priority. Tri-state ↓
┆19┆┆a9┆┄┄output connected to ↓
┆19┆┆a9┆┄┄source bus.↲

════════════════════════════════════════════════════════════════════════
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↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         I/O ADDR (0:22) 38              ┆84┆I/O Address Register. ↓
┆19┆┆a9┆┄┄Used to hold the I/O ↓
┆19┆┆a9┆┄┄address during ↓
┆19┆┆a9┆┄┄input/output operations.↲
         I/O ADDRPAR     38              ┆84┆Parity bit for I/O ↓
┆19┆┆a9┆┄┄address. Odd parity is ↓
┆19┆┆a9┆┄┄used.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         DATAOUT (0:23)  39              ┆84┆Data Out Register. ↓
┆19┆┆a9┆┄┄Contains data to be ↓
┆19┆┆a9┆┄┄transmitted via the ↓
┆19┆┆a9┆┄┄System Bus.↲
         DATAOUTPAR (0)  40              ┆84┆Parity bit for DATAOUT ↓
┆19┆┆a9┆┄┄(0:7). Odd parity.↲
         DATAOUTPAR (1)  40              ┆84┆Parity bit for DATAOUT ↓
┆19┆┆a9┆┄┄(8:15). Odd parity.↲
         DATAOUTPAR (2)  40              ┆84┆Parity bit for DATAOUT ↓
┆19┆┆a9┆┄┄(16:23). Odd parity.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         DATAIN (0:7)    21              Data In Register.↲
         DATAIN (8:15)   22              Contains data received ↲
         DATAIN (16:23)  23              ┆84┆via the System Bus. ↓
┆19┆┆a9┆┄┄Connected to SOURCE BUS. ↓
┆19┆┆a9┆┄┄Tri-state outputs.↲
         -,DATAPAROK     30,36           Parity check of data ↲
         DATAPAROK       36              ┆84┆received via the System ↓
┆19┆┆a9┆┄┄Bus.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         ADDRESSED       36              ┆84┆Indicates that the CPU ↓
┆19┆┆a9┆┄┄is addressed via the ↓
┆19┆┆a9┆┄┄System Bus.↲
         DATARDYDEL      36              ┆84┆Deskew delayed DATARDY ↓
┆19┆┆a9┆┄┄signal.↲
         CPUNACK         39              ┆84┆Negative response to ↓
┆19┆┆a9┆┄┄interrupt addressing due ↓
┆19┆┆a9┆┄┄to parity error in ↓
┆19┆┆a9┆┄┄received data.↲
         CPUACK          40              Positive response to ↲
         -,CPUACK        30              interrupt addressing.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         CPUBUSREQ       37,40           ┆84┆Indicates that the CPU ↓
┆19┆┆a9┆┄┄wants to obtain bus ↓
┆19┆┆a9┆┄┄master status.↲
         CPUSELOUT       40              Bus master selection ↲
         CPUSELACK       37,40           control signals.↲
         I/O READY       30              ┆84┆Indicates that an I/O ↓
┆19┆┆a9┆┄┄transfer has been ↓
┆19┆┆a9┆┄┄completed.↲
         MASTER          37              Indicates that the CPU ↲
         -,MASTER        37              ┆84┆has obtained master ↓
┆19┆┆a9┆┄┄status on the System Bus↲
         CPUDATARDY      37,40           ┆84┆Generates DATARDY and ↓
┆19┆┆a9┆┄┄BUSBUSY on the System ↓
┆19┆┆a9┆┄┄Bus.↲
         -,DELACK        37              ┆84┆A 0 indicates that an ↓
┆19┆┆a9┆┄┄ACK or NACK has been ↓
┆19┆┆a9┆┄┄received while the CPU ↓
┆19┆┆a9┆┄┄is bus master. The ↓
┆19┆┆a9┆┄┄signal is delayed to ↓
┆19┆┆a9┆┄┄compensate for skew ↓
┆19┆┆a9┆┄┄between data and ↓
┆19┆┆a9┆┄┄ACK/NACK.↲
         -,TIMEOUT       37              ┆84┆A 0 indicates that the ↓
┆19┆┆a9┆┄┄CPU has been bus master ↓
┆19┆┆a9┆┄┄for approx. 4 microsec.↲
         CPDATAIN        35              ┆84┆CP for the Data In ↓
┆19┆┆a9┆┄┄Register.↲
         -,CPUDATARDY    38              ┆84┆Enable signal for bus ↓
┆19┆┆a9┆┄┄transceivers for ↓
┆19┆┆a9┆┄┄address.↲
         -,SENDDATA      39,40           ┆84┆Enable signal for bus ↓
┆19┆┆a9┆┄┄transceivers for data.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         ADDR (0:22)     36              ┆84┆Address received via the ↓
┆19┆┆a9┆┄┄System Bus.↲
         ADDRPAR         36              ┆84┆Parity bit for the ↓
┆19┆┆a9┆┄┄received address. Odd ↓
┆19┆┆a9┆┄┄parity is used.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         DATA (0:17)     35              Data received via the ↲
         Data (18:23)    30,35           ┆84┆System Bus. Connected to ↓
┆19┆┆a9┆┄┄the Data In Register. ↓
┆19┆┆a9┆┄┄Bits (18:23) selects ↓
┆19┆┆a9┆┄┄interrupt level.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         DATAOUT         36              ┆84┆Indicates data transfer ↓
┆19┆┆a9┆┄┄from MASTER TO SLAVE.↲
         DATAPAR (2)     35              ┆84┆Parity bit for received ↓
┆19┆┆a9┆┄┄data bits (16:23).↲
         DATAPAR (1)     35              ┆84┆Parity bit for received ↓
┆19┆┆a9┆┄┄data bits (8:15).↲
         DATAPAR (0)     35              ┆84┆Parity bit for received ↓
┆19┆┆a9┆┄┄data bits (0:7).↲
         COMSEL          37              Bus master selection ↲
         SELIN           37              control signals.↲
         PINT            30,31           ┆84┆Power low warning signal ↓
┆19┆┆a9┆┄┄from power supply.↲
         NACK            30,37,40        ┆84┆Data transfer control ↓
┆19┆┆a9┆┄┄signal.↲
         SYSRESET        40              ┆84┆Master reset signal ↓
┆19┆┆a9┆┄┄received via System Bus.↲
         -,POK           30,40           ┆84┆Power ok signal from ↓
┆19┆┆a9┆┄┄power supply. A 0 ↓
┆19┆┆a9┆┄┄indicates that the dc ↓
┆19┆┆a9┆┄┄voltages are within ↓
┆19┆┆a9┆┄┄their limits.↲
         ACK             37,40 ↲
         BUSBUSY         37              ┆84┆Data transfer control ↲
         DATARDY         37              signals.↲
         -, (ACK ! NACK) 30              ┆84┆Controls the BUSTIMEOUT ↓
┆19┆┆a9┆┄┄status bit.↲
         ACK ! NACK      37              ┆84┆ACK or NACK received via ↓
┆19┆┆a9┆┄┄the System Bus.↲
         -,RESET         37,40           Reset signals generated ↲
         RESET           37              ┆84┆from System Reset and ↓
┆19┆┆a9┆┄┄Power OK signals.↲

════════════════════════════════════════════════════════════════════════
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↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         CBUNITF (0:3)   backplane       ┆84┆CPUBUS unit function, ↓
┆19┆┆a9┆┄┄bits (0:3).↲
         CBSOURCE (0:3)  backplane       ┆84┆CPUBUS source address, ↓
┆19┆┆a9┆┄┄bits (0:3)↲
         CBDEST (0:3)    backplane       ┆84┆CPUBUS destination ↓
┆19┆┆a9┆┄┄address, bits (0:3).↲
         -,CPUBUSRDY     3               ┆84┆Synchronized ready ↓
┆19┆┆a9┆┄┄signal from CPUBUS.↲
         CBUNITF(4:5)    backplane       ┆84┆CPUBUS unit function, ↓
┆19┆┆a9┆┄┄bits (4:5)↲
         CBSOURCE (4:5)  backplane       ┆84┆CPUBUS source address, ↓
┆19┆┆a9┆┄┄bits (4:5).↲
         CBDEST (4:5)    backplane       ┆84┆CPUBUS destination ↓
┆19┆┆a9┆┄┄address, bits (4:5).↲
         -,LOADDEST      41, backplane   ┆84┆Load enable signals for ↓
┆19┆┆a9┆┄┄CPUBUS destination ↓
┆19┆┆a9┆┄┄registers.↲
         ENCPUBUSOUT     41,42,43        ┆84┆Enable signal for CPUBUS ↓
┆19┆┆a9┆┄┄drivers on CPU board.↲
         -,READ (0:3)    backplane       ┆84┆Enable signals for ↓
┆19┆┆a9┆┄┄CPUBUS drivers on slave ↓
┆19┆┆a9┆┄┄modules. CPU811 can only ↓
┆19┆┆a9┆┄┄control one slave ↓
┆19┆┆a9┆┄┄module.↲
         MASTERCLOCK     14, backplane   ┆84┆5 MHz clock signal. All ↓
┆19┆┆a9┆┄┄other clock signals are ↓
┆19┆┆a9┆┄┄derived from this clock ↓
┆19┆┆a9┆┄┄signal.↲
         -,CBREADY       41              ┆84┆Ready signal from slave ↓
┆19┆┆a9┆┄┄units on CPUBUS.↲
         -,FPUAVAIL      2               ┆84┆A 0 indicates that the ↓
┆19┆┆a9┆┄┄floating point unit is ↓
┆19┆┆a9┆┄┄installed.↲

════════════════════════════════════════════════════════════════════════
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↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         CPUBUS (0:11 )  42 backplane    ┆84┆CPUBUS data lines, bits ↓
┆19┆┆a9┆┄┄(0:11). CPUBUS is a ↓
┆19┆┆a9┆┄┄bidirectional, tri-↓
┆19┆┆a9┆┄┄state, backplane bus.↲
         CPUBUSIN (0:7)  21              Buffered data input from ↲
         CPUBUSIN (8:11) 22              ┆84┆CPUBUS. Connected to ↓
┆19┆┆a9┆┄┄SBUS.↲

════════════════════════════════════════════════════════════════════════
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↲

════════════════════════════════════════════════════════════════════════
↓
         ┆b0┆┆a1┆SIGNAL          DESTINATION     DESCRIPTION            ↲
         CPUBUS(12:23)   43 backplane    ┆84┆CPUBUS data lines, bits ↓
┆19┆┆a9┆┄┄(12:23). CPUBUS is a ↓
┆19┆┆a9┆┄┄bidirectional, tri-↓
┆19┆┆a9┆┄┄state, backplane bus.↲
         CPUBUSIN(12:15) 22              Buffered data input from ↲
         CPUBUSIN(16:23) 23              ┆84┆CPUBUS. Connected to ↓
┆19┆┆a9┆┄┄SBUS.↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆6.       PAL AND PROM DESCRIPTIONS↲
↲
┆b0┆┆a1┆6.1      PAL Descriptions↲
↲
         ┆84┆The following PAL's are used on the CPU811 board↲
↲
         ┆b0┆┆a1┆PATTERN No.   PAL TYPE   IC POSITION↲
         PAT002        PAL16R4    138↲
         PAT003        PAL16R8    147↲
         PAT004        PAL16R8    157↲
         PAT005        PAL16R8    167↲
↲
         ┆84┆In this section the logical equations for the PAL ↓
┆19┆┆89┆┄┄outputs are listed. The following terminology is used:↲
↲
         /   complement, prefix to signal name↲
         x   logical AND↲
         +   logical OR↲
         =   combinatorial equality↲
         :=  ┆84┆sequential equality, register output after positive ↓
┆19┆┆8d┆┄┄transition of clock.↲
↲
         ┆84┆All the used PAL types have inverting outputs. The ↓
┆19┆┆89┆┄┄equations therefore specify the complemented output.↲
↲
↲
┆b0┆┆a1┆6.1.1    PAT002↲
↲
         Interrupt control logic.↲
↲
         INTRQSYN:= /POWUPRSTxINTRREQx/SETINTR↲
↲
         SETINTR:= POWUPRST↲
                   + INTRQSYNx/CLEARREQx/SETINTR↲
↲
         CLEARINTR:= POWUPRST↲
                     + CLEARREQx/CLRINTR↲
↲
         /CLEARINTR(0:7)= POWUPRST↲
                          + /CLRINTR↲
                          + IADR0↲
                          + IADR1↲
                          + IADR2↲
↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆6.1.2    PAT003↲
↲
         Interrupt register bits, 8 to 15.↲
↲
         IR8 :=  /IADR0x/IADR1xIADR2x/IADR3x/IADR4x/IADR5xSETINTR↲
               + /CLRINTRxIR8+IADR0xIR8+IADR1xIR8+/IADR2xIR8↲
               + IADR3xIR8+IADR4xIR8+IADR5xIR8↲
↲
         IR9 :=  /IADR0x/IADR1xIADR2x/IADR3x/IADR4xIADR5xSETINTR↲
               + /CLRINTRxIR9+IADR0xIR9+IADR1xIR9x/IADR2xIR9↲
               + IADR3xIR9+IADR4xIR9+/IADR5xIR9↲
↲
         IR10:=  /IADR0x/IADR1xIADR2x/IADR3xIADR4x/IADR5xSETINTR↲
               + /CLRINTRxIR10+IADR0xIR10+IADR1xIR10+/IADR2xIR10↲
               + IADR3xIR10+/IADR4xIR10+/IADR5xIR10↲
↲
         IR11:=  /IADR0x/IADR1xIADR2x/IADR3xIADR4xIADR5xSETINTR↲
               + /CLRINTRxIR11+IADR0xIR11+IADR1xIR11+/IADR2xIR11↲
               + IADR3xIR11+/IADR4xIR11+/IADR5xIR11↲
↲
         IR12:=  /IADR0x/IADR1xIADR2xIADR3x/IADR4x/IADR5xSETINTR↲
               + /CLRINTRxIR12+IADR0xIR12+IADR1xIR12+/IADR2xIR12↲
               + /IADR3xIR12+IADR4xIR12+/IADR5xIR12↲
↲
         IR13:=  /IADR0x/IADR1xIADR2xIADR3x/IADR4xIADR5xSETINTR↲
               + /CLRINTRxIR13+IADR0xIR13+IADR1xIR13+/IADR2xIR13↲
               + /IADR3xIR13+IADR4xIR13+/IADR5xIR13↲
↲
         IR14:=  /IADR0x/IADR1xIADR2xIADR3xIADR4x/IADR5xSETINTR↲
               + /CLRINTRxIR14+IADR0xIR14+IADR1xIR14+/IADR2xIR14↲
               + /IADR3xIR14+/IADR4xIR14+IADR5xIR14↲
↲
         IR15:=  /IADR0x/IADR1xIADR2xIADR3xIADR4xIADR5xSETINTR↲
               + /CLRINTRxIR15+IADR0xIR15+IADR1xIR15+/IADR2xIR15↲
               + /IADR3xIR15+/IADR4xIR15+/IADR5xIR15↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆6.1.3    PAT004↲
↲
         Interrupt register bits, 16 to 23.↲
↲
         IR16:=  /IADR0xIADR1x/IADR2x/IADR3x/IADR4x/IADR5xSETINTR↲
               + /CLRINTRxIR16+IADR0xIR16+/IADR1xIR16+IADR2xIR16↲
               + IADR3xIR16+IADR4xIR16+IADR5xIR16↲
↲
         IR17:=  /IADR0xIADR1x/IADR2x/IADR3x/IADR4xIADR5xSETINTR↲
               + /CLRINTRxIR17+IADR0xIR17+/IADR1xIR17xIADR2xIR17↲
               + IADR3xIR17+IADR4xIR17+/IADR5xIR17↲
↲
         IR18:=  /IADR0xIADR1x/IADR2x/IADR3xIADR4x/IADR5xSETINTR↲
               + /CLRINTRxIR18+IADR0xIR18+/IADR1xIR18+IADR2xIR18↲
               + IADR3xIR18+/IADR4xIR18+IADR5xIR18↲
↲
         IR19:=  /IADR0xIADR1x/IADR2x/IADR3xIADR4xIADR5xSETINTR↲
               + /CLRINTRxIR19+IADR0xIR19+/IADR1xIR19+IADR2xIR19↲
               + IADR3xIR19+/IADR4xIR19+/IADR5xIR19↲
↲
         IR20:=  /IADR0xIADR1x/IADR2xIADR3x/IADR4x/IADR5xSETINTR↲
               + /CLRINTRxIR20+IADR0xIR20+/IADR1xIR20+IADR2xIR20↲
               + /IADR3xIR20+IADR4xIR20+IADR5xIR20↲
↲
         IR21:=  /IADR0xIADR1x/IADR2xIADR3x/IADR4xIADR5xSETINTR↲
               + /CLRINTRxIR21+IADR0xIR21+/IADR1xIR21+IADR2xIR21↲
               + /IADR3xIR21+IADR4xIR21+/IADR5xIR21↲
↲
         IR22:=  /IADR0xIADR1x/IADR2xIADR3xIADR4x/IADR5xSETINTR↲
               + /CLRINTRxIR22+IADR0xIR22+/IADR1xIR22+IADR2xIR22↲
               + /IADR3xIR22+/IADR4xIR22+IADR5xIR22↲
↲
         IR23:=  /IADR0xIADR1x/IADR2xIADR3xIADR4xIADR5xSETINTR↲
               + /CLRINTRxIR23+IADR0xIR32+/IADR1xIR23+IADR2xIR23↲
               + /IADR3xIR23+/IADR4xIR23+/IADR5xIR23↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆6.1.4    PAT005↲
↲
         Interrupt register bits, 24 to 31.↲
↲
         IR24:=  /IADR0xIADR1xIADR2x/IADR3x/IADR4x/IADR5xSETINTR↲
               + /CLRINTRxIR24+IADR0xIR24+/IADR1xIR24+/IADR2xIR24↲
               + IADR3xIR24+IADR4xIR24+IADR5xIR24↲
↲
         IR25:=  /IADR0xIADR1xIADR2x/IADR3x/IADR4xIADR5xSETINTR↲
               + /CLRINTRxIR25+IADR0xIR25+/IADR1xIR25x/IADR2xIR25↲
               + IADR3xIR25+IADR4xIR25+/IADR5xIR25↲
↲
         IR26:=  /IADR0xIADR1xIADR2x/IADR3xIADR4x/IADR5xSETINTR↲
               + /CLRINTRxIR26+IADR0xIR26+/IADR1xIR26+/IADR2xIR26↲
               + IADR3xIR26+/IADR4xIR26+IADR5xIR26↲
↲
         IR27:=  /IADR0xIADR1xIADR2x/IADR3xIADR4xIADR5xSETINTR↲
               + /CLRINTRxIR27+IADR0xIR27+/IADR1xIR27+/IADR2xIR27↲
               + IADR3xIR27+/IADR4xIR27+/IADR5xIR27↲
↲
         IR28:=  /IADR0xIADR1xIADR2xIADR3x/IADR4x/IADR5xSETINTR↲
               + /CLRINTRxIR28+IADR0xIR28+/IADR1xIR28+/IADR2xIR28↲
               + /IADR3xIR28+IADR4xIR28+IADR5xIR28↲
↲
         IR29:=  /IADR0xIADR1xIADR2xIADR3x/IADR4xIADR5xSETINTR↲
               + /CLRINTRxIR29+IADR0xIR29+/IADR1xIR29+/IADR2xIR29↲
               + /IADR3xIR29+IADR4xIR29+/IADR5xIR29↲
↲
         IR30:=  /IADR0xIADR1xIADR2xIADR3xIADR4x/IADR5xSETINTR↲
               + /CLRINTRxIR30+IADR0xIR30+/IADR1xIR30+/IADR2xIR30↲
               + /IADR3xIR30+/IADR4xIR30+IADR5xIR30↲
↲
         IR31:=  /IADR0xIADR1xIADR2xIADR3xIADR4xIADR5xSETINTR↲
               + /CLRINTRxIR31+IADR0xIR31+/IADR1xIR31+/IADR2xIR31↲
               + /IADR3xIR31+/IADR4xIR31+/IADR5xIR31↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆6.2      PROM Descriptions↲
↲
         ┆84┆The contents of the PROM's used for decoding are listed ↓
┆19┆┆89┆┄┄here. The contents of the microprogram PROM's are shown ↓
┆19┆┆89┆┄┄in the microprogram listing.↲
↲
         ┆84┆The following decoding PROM's are used on the CPU811 ↓
┆19┆┆89┆┄┄board.↲
↲
         ┆b0┆┆a1┆PROM No.   TYPE      IC POSITION↲
↲
         ROB078     74S288    99↲
         ROA006     74S288    98↲
         ROA007     6309-1    97↲
↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆6.2.1    ROB078↲
↲
         ┆84┆Decodes microinstruction and generates the control ↓
┆19┆┆89┆┄┄signals S1, S0, -,FE and PUP for the microprogram ↓
┆19┆┆89┆┄┄sequencer.↲
↲
         ┆b0┆┆a1┆ADDRESS   Q0-Q3   Q4-Q7↲
↲
          0        0010    1110↲
          1        0010    1110↲
          2        0001    1110↲
          3        0000    1110↲
          4        1000    1110↲
          5        1010    1110↲
          6        1101    1110↲
          7        1101    1110↲
↲
         10        0010    1101↲
         11        0010    1101↲
         12        0001    1101↲
         13        0000    1101↲
         14        1000    1101↲
         15        1010    1101↲
         16        1101    1101↲
         17        1101    1101↲
↲
         20        0010    0010↲
         21        0010    1000↲
         22        0001    0001↲
         23        0000    0000↲
         24        1000    1000↲
         25        1010    0000↲
         26        1101    1101↲
         27        1101    1101↲
↲
         30        0010    0010↲
         31        0010    1000↲
         32        0001    0001↲
         33        0000    0000↲
         34        1000    1000↲
         35        1010    0000↲
         36        1101    1101↲
         37        1101    1101↲
↲
         Octal addresses.↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆6.2.2    ROA006↲
↲
         ┆84┆Decodes microinstruction and generates enable signals ↓
┆19┆┆89┆┄┄for the control store address sources.↲
↲
         ┆b0┆┆a1┆ADDRESS   Q0-Q3   Q4-Q7↲
↲
          0        0111    0111↲
          1        0111    0111↲
          2        0111    0111↲
          3        0111    0111↲
          4        0111    0111↲
          5        0111    0111↲
          6        0111    0111↲
          7        0111    0111↲
↲
         10        0111    0111↲
         11        0111    0111↲
         12        0111    0111↲
         13        0111    0111↲
         14        0111    0111↲
         15        0111    0111↲
         16        0111    0111↲
         17        0111    0111↲
↲
         20        0111    1011↲
         21        0111    1011↲
         22        0111    1011↲
         23        1110    1011↲
         24        0111    1101↲
         25        0111    1101↲
         26        0111    1101↲
         27        1110    1101↲
↲
         30        0111    0111↲
         31        0111    0111↲
         32        0111    0111↲
         33        1110    1110↲
         34        0111    0111↲
         35        0111    0111↲
         36        0111    0111↲
         37        1110    1110↲
↲
         Octal addresses.↲

════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆6.2.3    ROA007↲
↲
         ┆84┆Decodes microinstruction for clock control.↲
↲
         ┆b0┆┆a1┆ADDRESS     Q0-Q3   Q4-Q7       ADDRESS   Q0-Q3   Q4-Q7↲
↲
           0 to 177  1000    0001↲
         200 to 217  1100    0001↲
         220 to 237  1011    0001↲
         240 to 277  1010    1001↲
         300         1010    0001        340       1010    0001↲
         301         1010    0011        341       1010    0011↲
         302         1010    0101        342       1010    0101↲
         303         1010    0111        343       1010    0111↲
         304         1010    0001        344       1010    0001↲
         305         1010    0011        345       1010    0011↲
         306         1010    0101        346       1010    0101↲
         307         1010    0111        347       1010    0111↲
↲
         310         1010    0001        350       1010    0001↲
         311         1010    0011        351       1010    0011↲
         312         1010    0101        352       1010    0101↲
         313         1010    0111        353       1010    0111↲
         314         1010    0001        354       1010    0001↲
         315         1010    0011        355       1010    0011↲
         316         1010    0101        356       1010    0101↲
         317         1010    0111        357       1010    0111↲
↲
         320         1010    0001        360       1000    0001↲
         321         1010    0011        361       1000    0001↲
         322         1010    0101        362       1000    0001↲
         323         1010    0111        363       1000    0001↲
         324         1010    0001        364       1000    0001↲
         325         1010    0011        365       1000    0001↲
         326         1010    0101        366       1000    0001↲
         327         1010    0111        367       1000    0001↲
↲
         330         1010    0001        370       0000    0001↲
         331         1010    0011        371       0000    0001↲
         332         1010    0101        372       0000    0001↲
         333         1010    0111        373       0000    0001↲
         334         1010    0001        374       0000    0001↲
         335         1010    0011        375       0000    0001↲
         336         1010    0101        376       0000    0001↲
         337         1010    0111        377       0000    0001↲
↲
         Octal addresses↲

════════════════════════════════════════════════════════════════════════
↓
↲

════════════════════════════════════════════════════════════════════════
↓
┆1a┆┆1a┆   15        0111    0111↲
         16        0111    0111↲
                + IA

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