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Length: 10240 (0x2800)
Types: RcTekst
Names: »99110078.WP«
└─⟦7fab0c8ae⟧ Bits:30005866/disk3.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110078.WP«
╱04002d4c0a00050000000003013c3140000000000000000000000000000000000000000000000000050a0f19232d37414b555f69737d87ff04╱
┆b0┆┆a1┆┆f0┆┆e1┆┆06┆i↲
↲
┆b0┆┆a1┆TABLE OF CONTENTS┆05┆PAGE↲
↲
1. INTRODUCTION ....................................... 1↲
↲
2. FUNCTIONAL DESCRIPTION ............................. 2↲
2.1 Block Diagram ................................. 2↲
2.2 Pin Out ....................................... 3↲
2.3 Pin Designation ............................... 4↲
2.4 Register Addressing ........................... 7↲
2.5 Register Definitions .......................... 7↲
2.5.1 Control Register ....................... 7↲
2.5.2 Transmit Register ...................... 8↲
2.5.3 Receive Register ....................... 8↲
↲
3. CONFIGURATION ...................................... 9↲
3.1 Initializing .................................. 9↲
3.2 Running ....................................... 9↲
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↓
┆06┆ii↲
↲
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↓
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┆14┆┆b3┆┆06┆┆0b┆↲
↲
┆b0┆┆a1┆1. INTRODUCTION↲
↲
The Circuit II Protocol Communications (CPC551) is ↓
made as a peripheral device to interface be┄tween a CPU and ↓
the CIRCUIT II protocol developed by RC. This character ↓
oriented protocol is based on a polling mas┄ter and up to 32 ↓
slaves with the data transfer only between the Mas┄ter and ↓
one Slave device at a time. ↲
↲
The CPC551 is made as a satellite PCB solution used as back ↓
up PCB solution for the CPCC gate array within RC45 ↓
Terminals. The PCB in- and outputs are fet through a 28 pin ↓
socket adapter to make it possible to interchange CPC551 and ↓
CPCC without any change of surrounding hardware.↲
↲
Additional litterature:↲
╞ Circuit II Reference Manual 44-RT2157↲
CPCC General Description 99-1 09964↲
════════════════════════════════════════════════════════════════════════
↓
↲
┆b0┆┆a1┆2. FUNCTIONAL DESCRIPTION↲
↲
┆b0┆┆a1┆2.1 Block Diagram↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.2 Pin Out↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.3 Pin Designation↲
↲
┆a1┆Mnemonic Pin no Type Name and Function┆05┆↲
↲
┆b0┆D0..D7┆f0┆ 1-8 I/O ┆84┆This 3-state bidirectional 8 bit ↓
┆19┆┆9b┆┆81┆┄buffer is used to interface to ↓
┆19┆┆9b┆┆81┆┄the Control-, Data- and Statusre┄┄↓
┆19┆┆9b┆┆81┆┄gister.↲
↲
┆b0┆-,RD┆f0┆ 9 I ┆84┆A "low" on this input informs the ↓
┆19┆┆9b┆┆81┆┄CPCC that the CPU is reading data ↓
┆19┆┆9b┆┆81┆┄or status informations from the ↓
┆19┆┆9b┆┆81┆┄CPCC.↲
↲
┆b0┆-,WR┆f0┆ 10 I ┆84┆A "low" on this input informs the ↓
┆19┆┆9b┆┆81┆┄CPCC that the CPU is writing Con┄↓
┆19┆┆9b┆┆81┆┄trol or Data informations to the ↓
┆19┆┆9b┆┆81┆┄CPCC.↲
↲
┆b0┆-,CS┆f0┆ 11 I ┆84┆A "low" on this input selects the ↓
┆19┆┆9b┆┆81┆┄CPCC. No reading or writing will ↓
┆19┆┆9b┆┆81┆┄occur unless the device is selec┄↓
┆19┆┆9b┆┆81┆┄ted. When -,CS is high, the Data ↓
┆19┆┆9b┆┆81┆┄bus condition will have no effect ↓
┆19┆┆9b┆┆81┆┄on the chip.↲
↲
┆b0┆A0 ┆f0┆ 12, I ┆84┆These inputs in conjunction with ↓
┆19┆┆9b┆┆81┆┄the -,RD and -,WR inputs, informs ↓
┆19┆┆9b┆┆81┆┄the CPCC that the word on the da┄↓
┆19┆┆9b┆┆81┆┄ta bus is either control or data ↓
┆19┆┆9b┆┆81┆┄information.↲
↲
13 No connection↲
↲
┆b0┆Gnd ┆f0┆ 14 ┆84┆Ground: 0V input↲
↲
15 No connection↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆f0┆Mnemonic Pin no Type Name and Function┆05┆↲
↲
┆b0┆CLK┆e1┆┆f0┆ 16 ┆84┆The CPC551 must be driven by ↓
┆19┆┆9b┆┆81┆┄external clock though this input. ↓
┆19┆┆9b┆┆81┆┄Clock speed is 4 MHz↲
↲
┆b0┆TxRDY ┆f0┆ 17 0 ┆84┆Transmitter Ready.↲
┆84┆This output signals the CPU that ↓
┆19┆┆9b┆┄┄the transmitter is ready to ac┄┄↓
┆19┆┆9b┆┄┄cept a data character. ↲
┆84┆The TxRDY output pin can be used ↓
┆19┆┆9b┆┄┄as an interrupt to the system ↓
┆19┆┆9b┆┄┄or. TxRDY is automa┄tically reset ↓
┆19┆┆9b┆┄┄by the leading edge of WR when a ↓
┆19┆┆9b┆┄┄data character is loaded from the ↓
┆19┆┆9b┆┄┄CPU.↲
↲
┆b0┆RxRDY ┆f0┆ 18 0 Receiver Ready.↲
┆84┆This output indicates that the ↓
┆19┆┆9b┆┄┄CPCC contains a character that is ↓
┆19┆┆9b┆┄┄ready to be input to the CPU. ↓
┆19┆┆9b┆┄┄RxRDY can be connected to the in┄↓
┆19┆┆9b┆┄┄terrupt structure of the CPU. ↲
↲
┆84┆If failure to read the received ↓
┆19┆┆9b┆┄┄character from the Rx Data Output ↓
┆19┆┆9b┆┄┄Register prior to the assembly of ↓
┆19┆┆9b┆┄┄the next Rx Data character, the ↓
┆19┆┆9b┆┄┄old character will be lost.↲
↲
┆b0┆ ┆f0┆ 19,20,21 ┆84┆No connection.↲
┆b0┆↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆e1┆↲
┆a1┆Mnemonic Pin no Type Name and Function┆05┆↲
↲
┆b0┆┆b0┆-,RESET ┆f0┆ 22 I ┆84┆A "low" on this input forces the ↓
┆19┆┆9b┆┆82┆┄CPCC into an "Idle" mode. The de┄↓
┆19┆┆9b┆┆82┆┄vice will remain at "Idle" until ↓
┆19┆┆9b┆┆82┆┄a new control word is written ↓
┆19┆┆9b┆┆82┆┄into the CPCC to program its ↓
┆19┆┆9b┆┆82┆┄functional defintion. Minimum ↓
┆19┆┆9b┆┆82┆┄RESET pulse width is 4tCY (clock ↓
┆19┆┆9b┆┆82┆┄must be running).↲
↲
┆b0┆ ┆f0┆ 23 ┆84┆No connection.↲
↲
┆b0┆FMDIN ┆f0┆ 24 I ┆84┆Frequence MoDulated INput.↲
┆84┆The Biphase encoded incomming ↓
┆19┆┆9b┆┄┄data from the CIRCUIT II line ↓
┆19┆┆9b┆┄┄must be fed to this input.↲
↲
25 No connection↲
↲
┆b0┆NFMDO┆f0┆ 26 0 ┆84┆Negated Frequence MoDulated Out┄↓
┆19┆┆9b┆┆81┆┄put.↲
┆84┆This output contains the negative ↓
┆19┆┆9b┆┄┄part of the Biphase encoded data ↓
┆19┆┆9b┆┄┄to be transmitted on the CIRCUIT ↓
┆19┆┆9b┆┄┄II line.↲
↲
┆b0┆FMDO┆f0┆ 27 0 Frequence MoDulated Output.↲
┆84┆This output contains the positive ↓
┆19┆┆9b┆┄┄part of the Biphase encoded data ↓
┆19┆┆9b┆┄┄to be transmitted on the CIRCUIT ↓
┆19┆┆9b┆┄┄II line.↲
↲
┆b0┆VCC┆f0┆ 28 VCC: 5V input.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.4 Register Addressing↲
↲
┆a1┆┆e1┆ -,CS -,WR -,RD ┆82┆ ┆81┆A┆82┆0┆81┆ ↲
┆a1┆┆81┆┆05┆↲
0 0 1 1 CPU->Control register a↲
↲
0 0 1 0 CPU->Tx data register↲
↲
0 1 0 0 Rx data register->CPU↲
┆a1┆┆a1┆┆a1┆┆e1┆┆a1┆╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ↲
↲
↲
┆b0┆┆a1┆2.5 Register Definitions↲
↲
Upon power up the CPCC must be initialized before it is al┄↓
lowed to initiate any communication on the serial bus. This ↓
is done to prohibit the CPCC to answer an unspecified Ad┄┄┄↓
dress and thus violate communication on the bus. ↲
↲
↲
┆b0┆┆a1┆2.5.1 Control Register↲
↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! !↲
! X ! X ! CCEN ! Device Address !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
This register contains the recognition address of which the ↓
CPCC is to answer.↲
↲
┆b0┆CCEN ┆f0┆ ┆84┆The Communication ENable is the overall enable of the ↓
┆19┆┆87┆┆81┆┄CPCC. When all other registers have been initiated ↓
┆19┆┆87┆┆81┆┄this bit must be set high to enable the CPCC recep┄┄↓
┆19┆┆87┆┆81┆┄tion/transmission on the bus. Upon Reset CCEN is set ↓
┆19┆┆87┆┆81┆┄to 0 (disable).↲
↲
┆b0┆↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2.5.2 Transmit register↲
┆a1┆↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! !↲
! Tx-data !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
To this register the CPU must write the data to be transmit┄↓
ted on CIRCUIT II. If master mode is chosen this register ↓
must contain the leading byte.↲
↲
↲
┆b0┆┆a1┆┆b0┆┆a1┆2.5.3 Receive Register↲
┆a1┆↲
┆a1┆ msb lsb ↲
┆a1┆┆e1┆! ! ! ! ! ! ! ! ! ↲
! Rx-Data !↲
┆a1┆! ! ! ! ! ! ! ! !↲
↲
From this register the CPU can read the data received from ↓
CIRCUIT II.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆a1┆3┆a1┆. CONFIGURATION↲
↲
┆a1┆┆b0┆3.1 Initializing↲
↲
Prior to operation the Control register must be initiali┄↓
zed. The reception will be initiated upon CCEN high.↲
↲
↲
┆b0┆┆a1┆3.2 Running↲
↲
When the CPCC is initiated and CCEN is high the Reception is ↓
enabled and upon reception of a valid frame for the device, ↓
the transmission is initiated either with the previously ↓
loaded data byte or with the "no data" answer. Upon ↓
reception of a valid frame with a data byte the RxRDY is ↓
asserted and upon load of a byte to be transmitted TxRDY is ↓
asserted. Both RxRDY and TxRDY are cleared by the leading ↓
edge of read from the Rx-register and write to the Tx-↓
register respectively.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆Name ┆06┆Description┆05┆ ↲
BITVALUE╞ ╞ ╞ ┆84┆Actual received bitvalue. Set to "1" ↓
┆19┆┆98┆┄┄upon start of reception of bit and ↓
┆19┆┆98┆┄┄shifted to "0" if bit received is ↓
┆19┆┆98┆┄┄"0".↲
↲
BIT CLOCK╞ ╞ ┆84┆Bit clock signal pulses each time a ↓
┆19┆┆98┆┄┄bit is received.↲
↲
-,ABORT╞ ╞ ╞ ┆84┆Bit reception Abort. If a bit is ↓
┆19┆┆98┆┄┄received erroneously this signal ↓
┆19┆┆98┆┄┄goes to "0" to reset the entire ↓
┆19┆┆98┆┄┄receiver.↲
↲
500 KHz╞ ╞ ╞ ┆84┆500 KHz clock for the Tx-part.↲
↲
-,TXST╞ ╞ ╞ ┆84┆Transmit start signal. This signal ↓
┆19┆┆98┆┄┄goes to "0" after reception of a ↓
┆19┆┆98┆┄┄poll to initiate transmission.↲
↲
RXLD╞ ╞ ╞ ┆84┆If a data byte is received with a ↓
┆19┆┆98┆┄┄poll this signal clocks the byte ↓
┆19┆┆98┆┄┄into the Rx-flipflops.↲
↲
-,OBINIT╞ ╞ ╞ ┆84┆This signal is the overall enable of ↓
┆19┆┆98┆┄┄the circuit. It is set to "0" by a ↓
┆19┆┆98┆┄┄reset, and must be set to "1" by ↓
┆19┆┆98┆┄┄software to initiate communication.↲
↲
D0..D7 ╞ ╞ ╞ ┆84┆Databus from octal receive flipflop.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆a1┆4. DIAGRAMS↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆Name┆06┆Description┆05┆↲
-,TXCB╞ ╞ ╞ ┆84┆Clock output of U18 for the Tx-↓
┆19┆┆98┆┄┄bitcounter and -shift register.↲
↲
FMDO╞ ╞ ╞ ┆84┆Biphase encoded signal to be led to ↓
┆19┆┆98┆┄┄the line driver.↲
↲
NFMDO╞ ╞ ╞ ┆84┆Inverted biphase encoded signal to ↓
┆19┆┆98┆┄┄be led to the line driver.↲
↲
LASTBIT╞ ╞ ╞ ┆84┆Signal indicates lastbit is being ↓
┆19┆┆98┆┄┄transmitted.↲
↲
TXDB╞ ╞ ╞ ┆84┆Data to be transmitted is shifted ↓
┆19┆┆98┆┄┄seriel to this line from the serial ↓
┆19┆┆98┆┄┄shift register.↲
↲
-,RTSB╞ ╞ ╞ ┆84┆Initiates Transmission delayed 10 us ↓
┆19┆┆98┆┄┄from the TXST signal of the Rx-part.↲
↲
-,RxRD╞ ╞ ╞ ┆84┆Output enable for the octal receiver ↓
┆19┆┆98┆┄┄flipflop.↲
↲
RXRDY╞ ╞ ╞ ┆84┆This signal is asserted upon ↓
┆19┆┆98┆┄┄reception of a byte to be led to the ↓
┆19┆┆98┆┄┄CPU. It is reset by the leading edge ↓
┆19┆┆98┆┄┄from the read of the octal receiver ↓
┆19┆┆98┆┄┄flipflop.↲
↲
ETXRDY╞ ╞ ╞ ┆84┆This signal is asserted when a byte ↓
┆19┆┆98┆┄┄has been loaded from the Tx-buffer ↓
┆19┆┆98┆┄┄to the transmit part for ↓
┆19┆┆98┆┄┄transmission.↲
↲
DTRB╞ ╞ ╞ ┆84┆Is asserted when a byte is to be ↓
┆19┆┆98┆┄┄sent by the Circuit line.↲
↲
-,ADLD╞ ╞ ╞ ┆84┆Chip select for the control buffer.↲
↲
-,TXLD╞ ╞ ╞ ┆84┆Chip select for the Tx-buffer.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆Name┆06┆Description┆05┆↲
FMDIN╞ ╞ ╞ ┆84┆Biphase encoded signal from the line ↓
┆19┆┆98┆┄┄receiver to be led to the ↓
┆19┆┆98┆┄┄demodulator.↲
↲
-,Reset╞ ╞ ╞ ┆84┆Hard Reset from the CPU board.↲
↲
4 MHz╞ ╞ ╞ Input clock from the CPU board.↲
↲
D0..D7╞ ╞ ╞ Bidirectional CPU databus.↲
↲
-,RD╞ ╞ ╞ Read signal from CPU.↲
↲
-,WR╞ ╞ ╞ Write signal from CPU.↲
↲
-,CS╞ ╞ ╞ Chip Select.↲
↲
A0╞ ╞ ╞ ╞ ┆84┆Address bit to select addresses ↓
┆19┆┆98┆┄┄within the chip select address ↓
┆19┆┆98┆┄┄range.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆5. PAL LISTINGS↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆1a┆┆1a┆put selects the