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Length: 5632 (0x1600)
Types: RcTekst
Names: »99110055.WP«
└─⟦7fab0c8ae⟧ Bits:30005866/disk3.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110055.WP«
╱04002d4e0a00060000000003013c3100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
┆b0┆┆a1┆┆e1┆┆f0┆┆06┆i↲
↲
┆a1┆TABLE OF CONTENTS┆05┆PAGE↲
↲
1. INTRODUCTION ...................................... 1↲
↲
2. MEMORY ............................................ 2↲
↲
3. I/O ADRESSES ...................................... 3↲
3.1 CIRCUIT I Interface .......................... 3↲
3.2 CIRCUIT II Interface ......................... 4↲
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┆06┆ii↲
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┆15┆┆b1┆Reference Manual┆05┆RC45 Communications Board↲
┆15┆┆b1┆┆05┆Page ┆0b┆/18↲
┆15┆┆b2┆RC45 Communications Board┆05┆Reference Manual↲
┆15┆┆b2┆Page ┆0b┆/18↲
┆14┆┆b3┆ -┆06┆┆0b┆ -↲
↲
┆b0┆┆a1┆1. INTRODUCTION↲
↲
The RC45 Communications Board is an optional expansion for a ↓
RC45 data terminal. It provides the interface to the RC ↓
Circuit I and RC Circuit II networks, and expands the total ↓
Random Access Memory to 64 KBytes.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2. MEMORY↲
↲
The Communications Board holds 48 KBytes RAM which is ↓
accessible from address 0000H to BFFFH, virtually ↓
overlapping the CPU EPROM address space.↲
↲
╞ 0000H ┆a1┆ ┆e1┆ ┆a1┆ ↲
! ! ! !↲
!Data Control ! !Communications!↲
! Board ! ! Board !↲
! ! ! !↲
!48 KBytes ! !48 KBytes !↲
! EPROM ! ! RAM !↲
! ! ! !↲
! ! ! !↲
! ! ! !↲
╞ BFFFH ┆a1┆! !┆e1┆ ┆a1┆! !↲
↲
C000H ┆a1┆ ┆a1┆ ↲
!Data Control !↲
! Board !↲
! !↲
!16 KBytes !↲
! RAM !↲
╞ FFFFH ┆a1┆! !↲
↲
Wether the CPU runs in EPROM or RAM is controlled by a ↓
switch accessed at I/O port 28H to toggle from RAM to EPROM ↓
and I/O port 29H to toggle from EPROM to RAM. ↲
↲
The memory chips are 16Kx4 bit devices requiring 128 refresh ↓
cycles every 2mseconds. The refresh is generated by the CPU.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆3. I/O ADDRESSES↲
↲
The I/O addresses of the Communications Board is listed ↓
below:↲
↲
I/O DECODE:↲
↲
┆a1┆DEVICE┆06┆DESCRIPTION┆05┆ADDRESS↲
Z80A DMA╞ ╞ READ/WRITE REGISTERS 30H↲
↲
CIRCUIT II CONTROLLER *) DATA REGISTER 38H↲
╞ MASTER TX REGISTER/STATUS 39H↲
╞ ╞ ╞ CONTROL REGISTER A 3AH↲
╞ ╞ ╞ CONTROL REGISTER B 3BH↲
↲
CPC DAUGHTERBOARD *) DATA REGISTER 38H↲
╞ ╞ ╞ CONTROL REGISTER 3BH↲
↲
Z80ACTC╞ ╞ CHANNEL 0 (CII TRANSMIT ↲
╞ ╞ ╞ INTERRUPT) 3CH↲
╞ ╞ ╞ CHANNEL 1 (CII RECEIVE↲
╞ ╞ ╞ ╞ INTERRUPT) 3DH↲
╞ ╞ ╞ CHANNEL 2 UNUSED╞ 3EH↲
╞ ╞ ╞ CHANNEL 3 UNUSED 3FH↲
↲
*) Note: Only one of these are mounted.↲
↲
↲
┆b0┆┆a1┆3.1 CIRCUIT I Interface↲
↲
The interface to Circuit I is formed by the DMA controller, ↓
the Line driver electronics on the Communications Board, and ↓
one of the SIO channels on the Data Control Board. As ↓
════════════════════════════════════════════════════════════════════════
↓
Circuit I is a block oriented communications line, the SIO ↓
requests a DMA transfer of the block which is currently ↓
received or sent, and the physical transfer takes place ↓
transparently to the CPU.↲
↲
↲
┆b0┆┆a1┆3.2 CIRCUIT II inteface↲
↲
The interface to Circuit II is formed by a custom designed ↓
controller chip, proprietary to RC Computer. This chip ↓
handles the communications protocol exclusively and ↓
communicates its status to the CPU via two interrupt lines. ↓
This chip may be replaced by a daughter board, CPC551, which ↓
has most of the controller chip features. The user is ↓
referred to seperate manuals on these controllers, for ↓
detail diagrams and programming information.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Signal┆06┆Description┆05┆↲
↲
-,BUS REQ╞ ╞ ┆84┆Bus request to the CPU. Enables the ↓
┆19┆┆99┆┄┄DMA to drive the bus.↲
↲
CHAIN 3╞ ╞ ┆84┆Interrupt chain. Connected to the ↓
┆19┆┆99┆┄┄CTC.↲
↲
-,INT╞ ╞ ┆84┆Interrupt pin. Connected to the ↓
┆19┆┆99┆┄┄CPU.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Signal┆06┆Description┆05┆↲
↲
LINE0, LINEI╞ ╞ ┆84┆Circuit I line drive signals.↲
↲
REC DATA╞ ╞ ┆84┆Receive data from Circuit I. ↓
┆19┆┆99┆┄┄Connected to the demodulation ↓
┆19┆┆99┆┄┄Circuit.↲
↲
TXENABLE╞ ╞ ┆84┆Transmit enable. High whenever the ↓
┆19┆┆99┆┄┄Circuit line is not used.↲
↲
TXCB╞ ╞ ┆84┆Transmit clock, connected to SIO ↓
┆19┆┆99┆┄┄channel B.↲
↲
DATA OUT╞ ╞ ┆84┆Transmit data to the line drivers.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Signal┆06┆Description┆05┆↲
↲
-,CTSB╞ ╞ ┆84┆Clear to Send, connected to SIO ↓
┆19┆┆99┆┄┄channel B.↲
↲
-,DCDB╞ ╞ ┆84┆Data Carrier detect, connected to ↓
┆19┆┆99┆┄┄SIO channel B.↲
↲
RxDB╞ ╞ ┆84┆Receive data, connected to SIO ↓
┆19┆┆99┆┄┄manual B.↲
↲
RxCB╞ ╞ ┆84┆Receive clock, connected to SIO ↓
┆19┆┆99┆┄┄channel B.↲
↲
DATA 0-7╞ ╞ ┆84┆"Ghost interrupt generator", ↓
┆19┆┆99┆┄┄catches any fault interrupts from ↓
┆19┆┆99┆┄┄the SIO, connected to the system ↓
┆19┆┆99┆┄┄data bus.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Signal ┆06┆Description┆05┆↲
↲
DATA 0-7╞ ╞ ┆84┆Data to or from the dynamic RAM ↓
┆19┆┆99┆┄┄storage on the board. Connected to ↓
┆19┆┆99┆┄┄the system data bus.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Signal┆06┆Description┆05┆↲
↲
-,TXRDY ┆84┆Interrupt request to signal the CPU ↓
┆19┆┆99┆┄┄that a character is sent, and a new ↓
┆19┆┆99┆┄┄character may be loaded into the ↓
┆19┆┆99┆┄┄controller chip. Connected to the ↓
┆19┆┆99┆┄┄CTC.↲
↲
-,RxRDY╞ ╞ ┆84┆Interrupt request to signal the CPU ↓
┆19┆┆99┆┄┄that a character has been received ↓
┆19┆┆99┆┄┄from Circuit II. Connected to the ↓
┆19┆┆99┆┄┄CTC.↲
↲
LINE2, LINE3╞ ┆84┆ Circuit II line drive signals.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Signal ┆06┆Description┆05┆↲
↲
CHAIN END╞ ╞ ┆84┆End of interrupt chain.↲
↲
-,INT╞ ╞ ┆84┆Interrupt request to the CPU.↲
↲
-,CSB╞ ╞ Chip select to the CTC.↲
↲
-,CSA╞ ╞ ┆84┆Chip select to the Circuit II ↓
┆19┆┆99┆┄┄controller chip.↲
↲
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↓
↲
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↓
↲
┆1a┆┆1a┆┆ff┆┆ff┆┆ff┆┆00┆┆00┆┆00┆┆ff┆┆ff┆┆ff┆┆00┆┆00┆┆00┆┆ff┆┆ff┆┆ff┆┆00┆┆00┆┆00┆┆ff┆┆ff┆┆ff┆┆00┆┆00┆┆00┆┆ff┆┆ff┆┆ff┆┆00┆┆00┆┆00┆┆ff┆┆ff┆┆ff┆┆00┆┆00┆┆00┆ecified time (3oo ms.)