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Length: 5632 (0x1600)
Types: RcTekst
Names: »99110055.WP«
└─⟦7fab0c8ae⟧ Bits:30005866/disk3.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110055.WP«
╱04002d4e0a00060000000003013c3100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
┆b0┆┆a1┆┆e1┆┆f0┆┆06┆i↲
↲
┆a1┆TABLE OF CONTENTS┆05┆PAGE↲
↲
1. INTRODUCTION ...................................... 1↲
↲
2. MEMORY ............................................ 2↲
↲
3. I/O ADRESSES ...................................... 3↲
3.1 CIRCUIT I Interface .......................... 3↲
3.2 CIRCUIT II Interface ......................... 4↲
════════════════════════════════════════════════════════════════════════
↓
┆06┆ii↲
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════════════════════════════════════════════════════════════════════════
↓
┆15┆┆b1┆Reference Manual┆05┆RC45 Communications Board↲
┆15┆┆b1┆┆05┆Page ┆0b┆/18↲
┆15┆┆b2┆RC45 Communications Board┆05┆Reference Manual↲
┆15┆┆b2┆Page ┆0b┆/18↲
┆14┆┆b3┆ -┆06┆┆0b┆ -↲
↲
┆b0┆┆a1┆1. INTRODUCTION↲
↲
The RC45 Communications Board is an optional expansion for a ↓
RC45 data terminal. It provides the interface to the RC ↓
Circuit I and RC Circuit II networks, and expands the total ↓
Random Access Memory to 64 KBytes.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆2. MEMORY↲
↲
The Communications Board holds 48 KBytes RAM which is ↓
accessible from address 0000H to BFFFH, virtually ↓
overlapping the CPU EPROM address space.↲
↲
╞ 0000H ┆a1┆ ┆e1┆ ┆a1┆ ↲
! ! ! !↲
!Data Control ! !Communications!↲
! Board ! ! Board !↲
! ! ! !↲
!48 KBytes ! !48 KBytes !↲
! EPROM ! ! RAM !↲
! ! ! !↲
! ! ! !↲
! ! ! !↲
╞ BFFFH ┆a1┆! !┆e1┆ ┆a1┆! !↲
↲
C000H ┆a1┆ ┆a1┆ ↲
!Data Control !↲
! Board !↲
! !↲
!16 KBytes !↲
! RAM !↲
╞ FFFFH ┆a1┆! !↲
↲
Wether the CPU runs in EPROM or RAM is controlled by a ↓
switch accessed at I/O port 28H to toggle from RAM to EPROM ↓
and I/O port 29H to toggle from EPROM to RAM. ↲
↲
The memory chips are 16Kx4 bit devices requiring 128 refresh ↓
cycles every 2mseconds. The refresh is generated by the CPU.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆3. I/O ADDRESSES↲
↲
The I/O addresses of the Communications Board is listed ↓
below:↲
↲
I/O DECODE:↲
↲
┆a1┆DEVICE┆06┆DESCRIPTION┆05┆ADDRESS↲
Z80A DMA╞ ╞ READ/WRITE REGISTERS 30H↲
↲
CIRCUIT II CONTROLLER *) DATA REGISTER 38H↲
╞ MASTER TX REGISTER/STATUS 39H↲
╞ ╞ ╞ CONTROL REGISTER A 3AH↲
╞ ╞ ╞ CONTROL REGISTER B 3BH↲
↲
CPC DAUGHTERBOARD *) DATA REGISTER 38H↲
╞ ╞ ╞ CONTROL REGISTER 3BH↲
↲
Z80ACTC╞ ╞ CHANNEL 0 (CII TRANSMIT ↲
╞ ╞ ╞ INTERRUPT) 3CH↲
╞ ╞ ╞ CHANNEL 1 (CII RECEIVE↲
╞ ╞ ╞ ╞ INTERRUPT) 3DH↲
╞ ╞ ╞ CHANNEL 2 UNUSED╞ 3EH↲
╞ ╞ ╞ CHANNEL 3 UNUSED 3FH↲
↲
*) Note: Only one of these are mounted.↲
↲
↲
┆b0┆┆a1┆3.1 CIRCUIT I Interface↲
↲
The interface to Circuit I is formed by the DMA controller, ↓
the Line driver electronics on the Communications Board, and ↓
one of the SIO channels on the Data Control Board. As ↓
════════════════════════════════════════════════════════════════════════
↓
Circuit I is a block oriented communications line, the SIO ↓
requests a DMA transfer of the block which is currently ↓
received or sent, and the physical transfer takes place ↓
transparently to the CPU.↲
↲
↲
┆b0┆┆a1┆3.2 CIRCUIT II inteface↲
↲
The interface to Circuit II is formed by a custom designed ↓
controller chip, proprietary to RC Computer. This chip ↓
handles the communications protocol exclusively and ↓
communicates its status to the CPU via two interrupt lines. ↓
This chip may be replaced by a daughter board, CPC551, which ↓
has most of the controller chip features. The user is ↓
referred to seperate manuals on these controllers, for ↓
detail diagrams and programming information.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Signal┆06┆Description┆05┆↲
↲
-,BUS REQ╞ ╞ ┆84┆Bus request to the CPU. Enables the ↓
┆19┆┆99┆┄┄DMA to drive the bus.↲
↲
CHAIN 3╞ ╞ ┆84┆Interrupt chain. Connected to the ↓
┆19┆┆99┆┄┄CTC.↲
↲
-,INT╞ ╞ ┆84┆Interrupt pin. Connected to the ↓
┆19┆┆99┆┄┄CPU.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Signal┆06┆Description┆05┆↲
↲
LINE0, LINEI╞ ╞ ┆84┆Circuit I line drive signals.↲
↲
REC DATA╞ ╞ ┆84┆Receive data from Circuit I. ↓
┆19┆┆99┆┄┄Connected to the demodulation ↓
┆19┆┆99┆┄┄Circuit.↲
↲
TXENABLE╞ ╞ ┆84┆Transmit enable. High whenever the ↓
┆19┆┆99┆┄┄Circuit line is not used.↲
↲
TXCB╞ ╞ ┆84┆Transmit clock, connected to SIO ↓
┆19┆┆99┆┄┄channel B.↲
↲
DATA OUT╞ ╞ ┆84┆Transmit data to the line drivers.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Signal┆06┆Description┆05┆↲
↲
-,CTSB╞ ╞ ┆84┆Clear to Send, connected to SIO ↓
┆19┆┆99┆┄┄channel B.↲
↲
-,DCDB╞ ╞ ┆84┆Data Carrier detect, connected to ↓
┆19┆┆99┆┄┄SIO channel B.↲
↲
RxDB╞ ╞ ┆84┆Receive data, connected to SIO ↓
┆19┆┆99┆┄┄manual B.↲
↲
RxCB╞ ╞ ┆84┆Receive clock, connected to SIO ↓
┆19┆┆99┆┄┄channel B.↲
↲
DATA 0-7╞ ╞ ┆84┆"Ghost interrupt generator", ↓
┆19┆┆99┆┄┄catches any fault interrupts from ↓
┆19┆┆99┆┄┄the SIO, connected to the system ↓
┆19┆┆99┆┄┄data bus.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Signal ┆06┆Description┆05┆↲
↲
DATA 0-7╞ ╞ ┆84┆Data to or from the dynamic RAM ↓
┆19┆┆99┆┄┄storage on the board. Connected to ↓
┆19┆┆99┆┄┄the system data bus.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Signal┆06┆Description┆05┆↲
↲
-,TXRDY ┆84┆Interrupt request to signal the CPU ↓
┆19┆┆99┆┄┄that a character is sent, and a new ↓
┆19┆┆99┆┄┄character may be loaded into the ↓
┆19┆┆99┆┄┄controller chip. Connected to the ↓
┆19┆┆99┆┄┄CTC.↲
↲
-,RxRDY╞ ╞ ┆84┆Interrupt request to signal the CPU ↓
┆19┆┆99┆┄┄that a character has been received ↓
┆19┆┆99┆┄┄from Circuit II. Connected to the ↓
┆19┆┆99┆┄┄CTC.↲
↲
LINE2, LINE3╞ ┆84┆ Circuit II line drive signals.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆Signal ┆06┆Description┆05┆↲
↲
CHAIN END╞ ╞ ┆84┆End of interrupt chain.↲
↲
-,INT╞ ╞ ┆84┆Interrupt request to the CPU.↲
↲
-,CSB╞ ╞ Chip select to the CTC.↲
↲
-,CSA╞ ╞ ┆84┆Chip select to the Circuit II ↓
┆19┆┆99┆┄┄controller chip.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
↲
┆1a┆┆1a┆┆ff┆┆ff┆┆ff┆┆00┆┆00┆┆00┆┆ff┆┆ff┆┆ff┆┆00┆┆00┆┆00┆┆ff┆┆ff┆┆ff┆┆00┆┆00┆┆00┆┆ff┆┆ff┆┆ff┆┆00┆┆00┆┆00┆┆ff┆┆ff┆┆ff┆┆00┆┆00┆┆00┆┆ff┆┆ff┆┆ff┆┆00┆┆00┆┆00┆ecified time (3oo ms.)
0x0000…0020 (0,) 00 00 00 00 00 00 00 00 42 03 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4e 00 00 00 ┆ B N ┆
0x0020…0040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
0x0040…0047 00 00 00 00 00 00 00 ┆ ┆
0x0047…0080 Params {
0x0047…0080 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 3c 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N <1 ┆
0x0047…0080 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x0047…0080 }
0x0080…00a0 b0 a1 e1 f0 06 69 0d 0a 0d 0a a1 54 41 42 4c 45 20 4f 46 20 43 4f 4e 54 45 4e 54 53 05 50 41 47 ┆ i TABLE OF CONTENTS PAG┆
0x00a0…00c0 45 0d 0a 0d 0a 31 2e 20 20 49 4e 54 52 4f 44 55 43 54 49 4f 4e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆E 1. INTRODUCTION ..........┆
0x00c0…00e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 ┆............................ ┆
0x00e0…0100 31 0d 0a 0d 0a 32 2e 20 20 4d 45 4d 4f 52 59 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆1 2. MEMORY ................┆
0x0100…0120 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 ┆............................ ┆
0x0120…0140 32 0d 0a 0d 0a 33 2e 20 20 49 2f 4f 20 41 44 52 45 53 53 45 53 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆2 3. I/O ADRESSES ..........┆
0x0140…0160 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 ┆............................ ┆
0x0160…0180 33 0d 0a 20 20 20 20 33 2e 31 20 20 43 49 52 43 55 49 54 20 49 20 49 6e 74 65 72 66 61 63 65 20 ┆3 3.1 CIRCUIT I Interface ┆
0x0180…01a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 33 0d ┆.......................... 3 ┆
0x01a0…01c0 0a 20 20 20 20 33 2e 32 20 20 43 49 52 43 55 49 54 20 49 49 20 49 6e 74 65 72 66 61 63 65 20 2e ┆ 3.2 CIRCUIT II Interface .┆
0x01c0…01df 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 20 34 0d 0a ┆........................ 4 ┆
0x01df…01e2 FormFeed {
0x01df…01e2 0c 81 84 ┆ ┆
0x01df…01e2 }
0x01e2…01ea 0a 06 69 69 0d 0a 0d 0a ┆ ii ┆
0x01ea…01ed FormFeed {
0x01ea…01ed 0c 80 98 ┆ ┆
0x01ea…01ed }
0x01ed…0200 0a 15 b1 52 65 66 65 72 65 6e 63 65 20 4d 61 6e 75 61 6c ┆ Reference Manual┆
0x0200…0220 (1,) 05 52 43 34 35 20 43 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 73 20 42 6f 61 72 64 0d 0a 15 b1 05 50 ┆ RC45 Communications Board P┆
0x0220…0240 61 67 65 20 0b 2f 31 38 0d 0a 15 b2 52 43 34 35 20 43 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 73 20 ┆age /18 RC45 Communications ┆
0x0240…0260 42 6f 61 72 64 05 52 65 66 65 72 65 6e 63 65 20 4d 61 6e 75 61 6c 0d 0a 15 b2 50 61 67 65 20 0b ┆Board Reference Manual Page ┆
0x0260…0280 2f 31 38 0d 0a 14 b3 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆/18 ┆
0x0280…02a0 20 20 20 2d 06 0b 20 2d 0d 0a 0d 0a b0 a1 31 2e 20 49 4e 54 52 4f 44 55 43 54 49 4f 4e 0d 0a 0d ┆ - - 1. INTRODUCTION ┆
0x02a0…02c0 0a 54 68 65 20 52 43 34 35 20 43 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 73 20 42 6f 61 72 64 20 69 ┆ The RC45 Communications Board i┆
0x02c0…02e0 73 20 61 6e 20 6f 70 74 69 6f 6e 61 6c 20 65 78 70 61 6e 73 69 6f 6e 20 66 6f 72 20 61 20 0a 52 ┆s an optional expansion for a R┆
0x02e0…0300 43 34 35 20 64 61 74 61 20 74 65 72 6d 69 6e 61 6c 2e 20 49 74 20 70 72 6f 76 69 64 65 73 20 74 ┆C45 data terminal. It provides t┆
0x0300…0320 68 65 20 69 6e 74 65 72 66 61 63 65 20 74 6f 20 74 68 65 20 52 43 20 0a 43 69 72 63 75 69 74 20 ┆he interface to the RC Circuit ┆
0x0320…0340 49 20 61 6e 64 20 52 43 20 43 69 72 63 75 69 74 20 49 49 20 6e 65 74 77 6f 72 6b 73 2c 20 61 6e ┆I and RC Circuit II networks, an┆
0x0340…0360 64 20 65 78 70 61 6e 64 73 20 74 68 65 20 74 6f 74 61 6c 20 0a 52 61 6e 64 6f 6d 20 41 63 63 65 ┆d expands the total Random Acce┆
0x0360…037b 73 73 20 4d 65 6d 6f 72 79 20 74 6f 20 36 34 20 4b 42 79 74 65 73 2e 0d 0a 0d 0a ┆ss Memory to 64 KBytes. ┆
0x037b…037e FormFeed {
0x037b…037e 0c 80 e0 ┆ ┆
0x037b…037e }
0x037e…0380 0a b0 ┆ ┆
0x0380…03a0 a1 32 2e 20 4d 45 4d 4f 52 59 0d 0a 0d 0a 54 68 65 20 43 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 73 ┆ 2. MEMORY The Communications┆
0x03a0…03c0 20 42 6f 61 72 64 20 68 6f 6c 64 73 20 34 38 20 4b 42 79 74 65 73 20 52 41 4d 20 77 68 69 63 68 ┆ Board holds 48 KBytes RAM which┆
0x03c0…03e0 20 69 73 20 0a 61 63 63 65 73 73 69 62 6c 65 20 66 72 6f 6d 20 61 64 64 72 65 73 73 20 30 30 30 ┆ is accessible from address 000┆
0x03e0…0400 30 48 20 74 6f 20 42 46 46 46 48 2c 20 76 69 72 74 75 61 6c 6c 79 20 0a 6f 76 65 72 6c 61 70 70 ┆0H to BFFFH, virtually overlapp┆
0x0400…0420 (2,) 69 6e 67 20 74 68 65 20 43 50 55 20 45 50 52 4f 4d 20 61 64 64 72 65 73 73 20 73 70 61 63 65 2e ┆ing the CPU EPROM address space.┆
0x0420…0440 0d 0a 0d 0a 09 30 30 30 30 48 20 20 a1 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 e1 20 20 20 ┆ 0000H ┆
0x0440…0460 20 a1 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 0d 0a 20 20 20 20 20 20 20 20 20 20 20 21 ┆ !┆
0x0460…0480 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ! ┆
0x0480…04a0 20 21 0d 0a 20 20 20 20 20 20 20 20 20 20 20 21 44 61 74 61 20 43 6f 6e 74 72 6f 6c 20 21 20 20 ┆ ! !Data Control ! ┆
0x04a0…04c0 20 20 21 43 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 73 21 0d 0a 20 20 20 20 20 20 20 20 20 20 20 21 ┆ !Communications! !┆
0x04c0…04e0 20 20 20 42 6f 61 72 64 20 20 20 20 20 21 20 20 20 20 21 20 20 20 20 20 42 6f 61 72 64 20 20 20 ┆ Board ! ! Board ┆
0x04e0…0500 20 21 0d 0a 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 ┆ ! ! ! ┆
0x0500…0520 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 20 20 20 20 20 20 20 20 20 20 20 21 ┆ ! ! !┆
0x0520…0540 34 38 20 4b 42 79 74 65 73 20 20 20 20 21 20 20 20 20 21 34 38 20 4b 42 79 74 65 73 20 20 20 20 ┆48 KBytes ! !48 KBytes ┆
0x0540…0560 20 21 0d 0a 20 20 20 20 20 20 20 20 20 20 20 21 20 20 45 50 52 4f 4d 20 20 20 20 20 20 21 20 20 ┆ ! ! EPROM ! ┆
0x0560…0580 20 20 21 20 20 20 20 52 41 4d 20 20 20 20 20 20 20 21 0d 0a 20 20 20 20 20 20 20 20 20 20 20 21 ┆ ! RAM ! !┆
0x0580…05a0 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ! ┆
0x05a0…05c0 20 21 0d 0a 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 ┆ ! ! ! ┆
0x05c0…05e0 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 20 20 20 20 20 20 20 20 20 20 20 21 ┆ ! ! !┆
0x05e0…0600 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ! ┆
0x0600…0620 (3,) 20 21 0d 0a 20 09 42 46 46 46 48 20 20 a1 21 20 20 20 20 20 20 20 20 20 20 20 20 20 21 e1 20 20 ┆ ! BFFFH ! ! ┆
0x0620…0640 20 20 a1 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 20 20 20 20 0d 0a 20 20 20 20 43 ┆ ! ! C┆
0x0640…0660 30 30 30 48 20 20 20 20 20 20 20 20 20 20 20 a1 20 20 a1 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆000H ┆
0x0660…0680 20 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 44 61 74 61 20 43 6f 6e ┆ !Data Con┆
0x0680…06a0 74 72 6f 6c 20 20 21 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 ┆trol ! ! ┆
0x06a0…06c0 20 42 6f 61 72 64 20 20 20 20 20 20 21 0d 0a 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ Board ! ┆
0x06c0…06e0 20 20 20 21 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 0d 0a 20 20 20 20 20 20 20 20 20 20 20 ┆ ! ! ┆
0x06e0…0700 20 20 20 20 20 20 20 20 20 21 31 36 20 4b 42 79 74 65 73 20 20 20 20 20 21 0d 0a 20 20 20 20 20 ┆ !16 KBytes ! ┆
0x0700…0720 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 21 20 20 20 20 52 41 4d 20 20 20 20 20 20 20 21 0d ┆ ! RAM ! ┆
0x0720…0740 0a 09 46 46 46 46 48 20 20 20 20 20 20 20 20 20 20 20 a1 21 20 20 20 20 20 20 20 20 20 20 20 20 ┆ FFFFH ! ┆
0x0740…0760 20 20 21 0d 0a 0d 0a 57 65 74 68 65 72 20 74 68 65 20 43 50 55 20 72 75 6e 73 20 69 6e 20 45 50 ┆ ! Wether the CPU runs in EP┆
0x0760…0780 52 4f 4d 20 6f 72 20 52 41 4d 20 69 73 20 63 6f 6e 74 72 6f 6c 6c 65 64 20 62 79 20 61 20 0a 73 ┆ROM or RAM is controlled by a s┆
0x0780…07a0 77 69 74 63 68 20 61 63 63 65 73 73 65 64 20 61 74 20 49 2f 4f 20 70 6f 72 74 20 32 38 48 20 74 ┆witch accessed at I/O port 28H t┆
0x07a0…07c0 6f 20 74 6f 67 67 6c 65 20 66 72 6f 6d 20 52 41 4d 20 74 6f 20 45 50 52 4f 4d 20 0a 61 6e 64 20 ┆o toggle from RAM to EPROM and ┆
0x07c0…07e0 49 2f 4f 20 70 6f 72 74 20 32 39 48 20 74 6f 20 74 6f 67 67 6c 65 20 66 72 6f 6d 20 45 50 52 4f ┆I/O port 29H to toggle from EPRO┆
0x07e0…0800 4d 20 74 6f 20 52 41 4d 2e 20 0d 0a 0d 0a 54 68 65 20 6d 65 6d 6f 72 79 20 63 68 69 70 73 20 61 ┆M to RAM. The memory chips a┆
0x0800…0820 (4,) 72 65 20 31 36 4b 78 34 20 62 69 74 20 64 65 76 69 63 65 73 20 72 65 71 75 69 72 69 6e 67 20 31 ┆re 16Kx4 bit devices requiring 1┆
0x0820…0840 32 38 20 72 65 66 72 65 73 68 20 0a 63 79 63 6c 65 73 20 65 76 65 72 79 20 32 6d 73 65 63 6f 6e ┆28 refresh cycles every 2msecon┆
0x0840…0860 64 73 2e 20 54 68 65 20 72 65 66 72 65 73 68 20 69 73 20 67 65 6e 65 72 61 74 65 64 20 62 79 20 ┆ds. The refresh is generated by ┆
0x0860…086c 74 68 65 20 43 50 55 2e 0d 0a 0d 0a ┆the CPU. ┆
0x086c…086f FormFeed {
0x086c…086f 0c 83 8c ┆ ┆
0x086c…086f }
0x086f…0880 0a b0 a1 33 2e 20 49 2f 4f 20 41 44 44 52 45 53 53 ┆ 3. I/O ADDRESS┆
0x0880…08a0 45 53 0d 0a 0d 0a 54 68 65 20 49 2f 4f 20 61 64 64 72 65 73 73 65 73 20 6f 66 20 74 68 65 20 43 ┆ES The I/O addresses of the C┆
0x08a0…08c0 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 73 20 42 6f 61 72 64 20 69 73 20 6c 69 73 74 65 64 20 0a 62 ┆ommunications Board is listed b┆
0x08c0…08e0 65 6c 6f 77 3a 0d 0a 0d 0a 49 2f 4f 20 44 45 43 4f 44 45 3a 0d 0a 0d 0a a1 44 45 56 49 43 45 06 ┆elow: I/O DECODE: DEVICE ┆
0x08e0…0900 44 45 53 43 52 49 50 54 49 4f 4e 05 41 44 44 52 45 53 53 0d 0a 5a 38 30 41 20 44 4d 41 09 09 20 ┆DESCRIPTION ADDRESS Z80A DMA ┆
0x0900…0920 52 45 41 44 2f 57 52 49 54 45 20 52 45 47 49 53 54 45 52 53 20 20 20 20 20 20 20 20 33 30 48 0d ┆READ/WRITE REGISTERS 30H ┆
0x0920…0940 0a 0d 0a 43 49 52 43 55 49 54 20 49 49 20 43 4f 4e 54 52 4f 4c 4c 45 52 20 2a 29 20 44 41 54 41 ┆ CIRCUIT II CONTROLLER *) DATA┆
0x0940…0960 20 52 45 47 49 53 54 45 52 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 33 38 48 0d 0a 09 20 20 ┆ REGISTER 38H ┆
0x0960…0980 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 4d 41 53 54 45 52 20 54 58 20 52 45 47 ┆ MASTER TX REG┆
0x0980…09a0 49 53 54 45 52 2f 53 54 41 54 55 53 20 20 20 33 39 48 0d 0a 09 09 09 20 43 4f 4e 54 52 4f 4c 20 ┆ISTER/STATUS 39H CONTROL ┆
0x09a0…09c0 52 45 47 49 53 54 45 52 20 41 20 20 20 20 20 20 20 20 20 20 33 41 48 0d 0a 09 09 09 20 43 4f 4e ┆REGISTER A 3AH CON┆
0x09c0…09e0 54 52 4f 4c 20 52 45 47 49 53 54 45 52 20 42 20 20 20 20 20 20 20 20 20 20 33 42 48 0d 0a 0d 0a ┆TROL REGISTER B 3BH ┆
0x09e0…0a00 43 50 43 20 44 41 55 47 48 54 45 52 42 4f 41 52 44 20 2a 29 20 20 20 20 20 44 41 54 41 20 52 45 ┆CPC DAUGHTERBOARD *) DATA RE┆
0x0a00…0a20 (5,) 47 49 53 54 45 52 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 33 38 48 0d 0a 09 09 09 20 43 4f ┆GISTER 38H CO┆
0x0a20…0a40 4e 54 52 4f 4c 20 52 45 47 49 53 54 45 52 20 20 20 20 20 20 20 20 20 20 20 20 33 42 48 0d 0a 0d ┆NTROL REGISTER 3BH ┆
0x0a40…0a60 0a 5a 38 30 41 43 54 43 09 09 20 43 48 41 4e 4e 45 4c 20 30 20 28 43 49 49 20 54 52 41 4e 53 4d ┆ Z80ACTC CHANNEL 0 (CII TRANSM┆
0x0a60…0a80 49 54 20 0d 0a 09 09 09 20 20 20 20 20 20 20 20 20 20 20 20 49 4e 54 45 52 52 55 50 54 29 20 20 ┆IT INTERRUPT) ┆
0x0a80…0aa0 20 20 20 20 20 33 43 48 0d 0a 09 09 09 20 43 48 41 4e 4e 45 4c 20 31 20 28 43 49 49 20 52 45 43 ┆ 3CH CHANNEL 1 (CII REC┆
0x0aa0…0ac0 45 49 56 45 0d 0a 09 09 09 09 20 20 49 4e 54 45 52 52 55 50 54 29 20 20 20 20 20 20 20 33 44 48 ┆EIVE INTERRUPT) 3DH┆
0x0ac0…0ae0 0d 0a 09 09 09 20 43 48 41 4e 4e 45 4c 20 32 20 55 4e 55 53 45 44 09 20 20 20 20 20 20 20 20 20 ┆ CHANNEL 2 UNUSED ┆
0x0ae0…0b00 33 45 48 0d 0a 09 09 09 20 43 48 41 4e 4e 45 4c 20 33 20 55 4e 55 53 45 44 20 20 20 20 20 20 20 ┆3EH CHANNEL 3 UNUSED ┆
0x0b00…0b20 20 20 20 20 20 33 46 48 0d 0a 0d 0a 2a 29 20 4e 6f 74 65 3a 20 4f 6e 6c 79 20 6f 6e 65 20 6f 66 ┆ 3FH *) Note: Only one of┆
0x0b20…0b40 20 74 68 65 73 65 20 61 72 65 20 6d 6f 75 6e 74 65 64 2e 0d 0a 0d 0a 0d 0a b0 a1 33 2e 31 20 43 ┆ these are mounted. 3.1 C┆
0x0b40…0b60 49 52 43 55 49 54 20 49 20 49 6e 74 65 72 66 61 63 65 0d 0a 0d 0a 54 68 65 20 69 6e 74 65 72 66 ┆IRCUIT I Interface The interf┆
0x0b60…0b80 61 63 65 20 74 6f 20 43 69 72 63 75 69 74 20 49 20 69 73 20 66 6f 72 6d 65 64 20 62 79 20 74 68 ┆ace to Circuit I is formed by th┆
0x0b80…0ba0 65 20 44 4d 41 20 63 6f 6e 74 72 6f 6c 6c 65 72 2c 20 0a 74 68 65 20 4c 69 6e 65 20 64 72 69 76 ┆e DMA controller, the Line driv┆
0x0ba0…0bc0 65 72 20 65 6c 65 63 74 72 6f 6e 69 63 73 20 6f 6e 20 74 68 65 20 43 6f 6d 6d 75 6e 69 63 61 74 ┆er electronics on the Communicat┆
0x0bc0…0be0 69 6f 6e 73 20 42 6f 61 72 64 2c 20 61 6e 64 20 0a 6f 6e 65 20 6f 66 20 74 68 65 20 53 49 4f 20 ┆ions Board, and one of the SIO ┆
0x0be0…0c00 63 68 61 6e 6e 65 6c 73 20 6f 6e 20 74 68 65 20 44 61 74 61 20 43 6f 6e 74 72 6f 6c 20 42 6f 61 ┆channels on the Data Control Boa┆
0x0c00…0c08 (6,) 72 64 2e 20 41 73 20 0a ┆rd. As ┆
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0x0c0b…0c20 0a 43 69 72 63 75 69 74 20 49 20 69 73 20 61 20 62 6c 6f 63 6b ┆ Circuit I is a block┆
0x0c20…0c40 20 6f 72 69 65 6e 74 65 64 20 63 6f 6d 6d 75 6e 69 63 61 74 69 6f 6e 73 20 6c 69 6e 65 2c 20 74 ┆ oriented communications line, t┆
0x0c40…0c60 68 65 20 53 49 4f 20 0a 72 65 71 75 65 73 74 73 20 61 20 44 4d 41 20 74 72 61 6e 73 66 65 72 20 ┆he SIO requests a DMA transfer ┆
0x0c60…0c80 6f 66 20 74 68 65 20 62 6c 6f 63 6b 20 77 68 69 63 68 20 69 73 20 63 75 72 72 65 6e 74 6c 79 20 ┆of the block which is currently ┆
0x0c80…0ca0 0a 72 65 63 65 69 76 65 64 20 6f 72 20 73 65 6e 74 2c 20 61 6e 64 20 74 68 65 20 70 68 79 73 69 ┆ received or sent, and the physi┆
0x0ca0…0cc0 63 61 6c 20 74 72 61 6e 73 66 65 72 20 74 61 6b 65 73 20 70 6c 61 63 65 20 0a 74 72 61 6e 73 70 ┆cal transfer takes place transp┆
0x0cc0…0ce0 61 72 65 6e 74 6c 79 20 74 6f 20 74 68 65 20 43 50 55 2e 0d 0a 0d 0a 0d 0a b0 a1 33 2e 32 20 43 ┆arently to the CPU. 3.2 C┆
0x0ce0…0d00 49 52 43 55 49 54 20 49 49 20 69 6e 74 65 66 61 63 65 0d 0a 0d 0a 54 68 65 20 69 6e 74 65 72 66 ┆IRCUIT II inteface The interf┆
0x0d00…0d20 61 63 65 20 74 6f 20 43 69 72 63 75 69 74 20 49 49 20 69 73 20 66 6f 72 6d 65 64 20 62 79 20 61 ┆ace to Circuit II is formed by a┆
0x0d20…0d40 20 63 75 73 74 6f 6d 20 64 65 73 69 67 6e 65 64 20 0a 63 6f 6e 74 72 6f 6c 6c 65 72 20 63 68 69 ┆ custom designed controller chi┆
0x0d40…0d60 70 2c 20 70 72 6f 70 72 69 65 74 61 72 79 20 74 6f 20 52 43 20 43 6f 6d 70 75 74 65 72 2e 20 54 ┆p, proprietary to RC Computer. T┆
0x0d60…0d80 68 69 73 20 63 68 69 70 20 0a 68 61 6e 64 6c 65 73 20 74 68 65 20 63 6f 6d 6d 75 6e 69 63 61 74 ┆his chip handles the communicat┆
0x0d80…0da0 69 6f 6e 73 20 70 72 6f 74 6f 63 6f 6c 20 65 78 63 6c 75 73 69 76 65 6c 79 20 61 6e 64 20 0a 63 ┆ions protocol exclusively and c┆
0x0da0…0dc0 6f 6d 6d 75 6e 69 63 61 74 65 73 20 69 74 73 20 73 74 61 74 75 73 20 74 6f 20 74 68 65 20 43 50 ┆ommunicates its status to the CP┆
0x0dc0…0de0 55 20 76 69 61 20 74 77 6f 20 69 6e 74 65 72 72 75 70 74 20 6c 69 6e 65 73 2e 20 0a 54 68 69 73 ┆U via two interrupt lines. This┆
0x0de0…0e00 20 63 68 69 70 20 6d 61 79 20 62 65 20 72 65 70 6c 61 63 65 64 20 62 79 20 61 20 64 61 75 67 68 ┆ chip may be replaced by a daugh┆
0x0e00…0e20 (7,) 74 65 72 20 62 6f 61 72 64 2c 20 43 50 43 35 35 31 2c 20 77 68 69 63 68 20 0a 68 61 73 20 6d 6f ┆ter board, CPC551, which has mo┆
0x0e20…0e40 73 74 20 6f 66 20 74 68 65 20 63 6f 6e 74 72 6f 6c 6c 65 72 20 63 68 69 70 20 66 65 61 74 75 72 ┆st of the controller chip featur┆
0x0e40…0e60 65 73 2e 20 54 68 65 20 75 73 65 72 20 69 73 20 0a 72 65 66 65 72 72 65 64 20 74 6f 20 73 65 70 ┆es. The user is referred to sep┆
0x0e60…0e80 65 72 61 74 65 20 6d 61 6e 75 61 6c 73 20 6f 6e 20 74 68 65 73 65 20 63 6f 6e 74 72 6f 6c 6c 65 ┆erate manuals on these controlle┆
0x0e80…0ea0 72 73 2c 20 66 6f 72 20 0a 64 65 74 61 69 6c 20 64 69 61 67 72 61 6d 73 20 61 6e 64 20 70 72 6f ┆rs, for detail diagrams and pro┆
0x0ea0…0eb7 67 72 61 6d 6d 69 6e 67 20 69 6e 66 6f 72 6d 61 74 69 6f 6e 2e 0d 0a ┆gramming information. ┆
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0x0ec0…0ee0 0a a1 53 69 67 6e 61 6c 06 44 65 73 63 72 69 70 74 69 6f 6e 05 0d 0a 0d 0a 2d 2c 42 55 53 20 52 ┆ Signal Description -,BUS R┆
0x0ee0…0f00 45 51 09 09 20 84 42 75 73 20 72 65 71 75 65 73 74 20 74 6f 20 74 68 65 20 43 50 55 2e 20 45 6e ┆EQ Bus request to the CPU. En┆
0x0f00…0f20 61 62 6c 65 73 20 74 68 65 20 0a 19 99 80 80 44 4d 41 20 74 6f 20 64 72 69 76 65 20 74 68 65 20 ┆ables the DMA to drive the ┆
0x0f20…0f40 62 75 73 2e 0d 0a 0d 0a 43 48 41 49 4e 20 33 09 09 20 84 49 6e 74 65 72 72 75 70 74 20 63 68 61 ┆bus. CHAIN 3 Interrupt cha┆
0x0f40…0f60 69 6e 2e 20 43 6f 6e 6e 65 63 74 65 64 20 74 6f 20 74 68 65 20 0a 19 99 80 80 43 54 43 2e 0d 0a ┆in. Connected to the CTC. ┆
0x0f60…0f80 0d 0a 2d 2c 49 4e 54 09 09 20 84 49 6e 74 65 72 72 75 70 74 20 70 69 6e 2e 20 43 6f 6e 6e 65 63 ┆ -,INT Interrupt pin. Connec┆
0x0f80…0f96 74 65 64 20 74 6f 20 74 68 65 20 0a 19 99 80 80 43 50 55 2e 0d 0a ┆ted to the CPU. ┆
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0x0fa0…0fc0 a1 53 69 67 6e 61 6c 06 44 65 73 63 72 69 70 74 69 6f 6e 05 0d 0a 0d 0a 4c 49 4e 45 30 2c 20 4c ┆ Signal Description LINE0, L┆
0x0fc0…0fe0 49 4e 45 49 09 09 20 84 43 69 72 63 75 69 74 20 49 20 6c 69 6e 65 20 64 72 69 76 65 20 73 69 67 ┆INEI Circuit I line drive sig┆
0x0fe0…1000 6e 61 6c 73 2e 0d 0a 0d 0a 52 45 43 20 44 41 54 41 09 09 20 84 52 65 63 65 69 76 65 20 64 61 74 ┆nals. REC DATA Receive dat┆
0x1000…1020 (8,) 61 20 66 72 6f 6d 20 43 69 72 63 75 69 74 20 49 2e 20 0a 19 99 80 80 43 6f 6e 6e 65 63 74 65 64 ┆a from Circuit I. Connected┆
0x1020…1040 20 74 6f 20 74 68 65 20 64 65 6d 6f 64 75 6c 61 74 69 6f 6e 20 0a 19 99 80 80 43 69 72 63 75 69 ┆ to the demodulation Circui┆
0x1040…1060 74 2e 0d 0a 0d 0a 54 58 45 4e 41 42 4c 45 09 09 20 84 54 72 61 6e 73 6d 69 74 20 65 6e 61 62 6c ┆t. TXENABLE Transmit enabl┆
0x1060…1080 65 2e 20 48 69 67 68 20 77 68 65 6e 65 76 65 72 20 74 68 65 20 0a 19 99 80 80 43 69 72 63 75 69 ┆e. High whenever the Circui┆
0x1080…10a0 74 20 6c 69 6e 65 20 69 73 20 6e 6f 74 20 75 73 65 64 2e 0d 0a 0d 0a 54 58 43 42 09 09 20 84 54 ┆t line is not used. TXCB T┆
0x10a0…10c0 72 61 6e 73 6d 69 74 20 63 6c 6f 63 6b 2c 20 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 53 49 4f 20 ┆ransmit clock, connected to SIO ┆
0x10c0…10e0 0a 19 99 80 80 63 68 61 6e 6e 65 6c 20 42 2e 0d 0a 0d 0a 44 41 54 41 20 4f 55 54 09 09 20 84 54 ┆ channel B. DATA OUT T┆
0x10e0…1100 72 61 6e 73 6d 69 74 20 64 61 74 61 20 74 6f 20 74 68 65 20 6c 69 6e 65 20 64 72 69 76 65 72 73 ┆ransmit data to the line drivers┆
0x1100…1105 2e 0d 0a 0d 0a ┆. ┆
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0x110e…1120 0a a1 53 69 67 6e 61 6c 06 44 65 73 63 72 69 70 74 69 ┆ Signal Descripti┆
0x1120…1140 6f 6e 05 0d 0a 0d 0a 2d 2c 43 54 53 42 09 09 20 84 43 6c 65 61 72 20 74 6f 20 53 65 6e 64 2c 20 ┆on -,CTSB Clear to Send, ┆
0x1140…1160 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 53 49 4f 20 0a 19 99 80 80 63 68 61 6e 6e 65 6c 20 42 2e ┆connected to SIO channel B.┆
0x1160…1180 0d 0a 0d 0a 2d 2c 44 43 44 42 09 09 20 84 44 61 74 61 20 43 61 72 72 69 65 72 20 64 65 74 65 63 ┆ -,DCDB Data Carrier detec┆
0x1180…11a0 74 2c 20 63 6f 6e 6e 65 63 74 65 64 20 74 6f 20 0a 19 99 80 80 53 49 4f 20 63 68 61 6e 6e 65 6c ┆t, connected to SIO channel┆
0x11a0…11c0 20 42 2e 0d 0a 0d 0a 52 78 44 42 09 09 20 84 52 65 63 65 69 76 65 20 64 61 74 61 2c 20 63 6f 6e ┆ B. RxDB Receive data, con┆
0x11c0…11e0 6e 65 63 74 65 64 20 74 6f 20 53 49 4f 20 0a 19 99 80 80 6d 61 6e 75 61 6c 20 42 2e 0d 0a 0d 0a ┆nected to SIO manual B. ┆
0x11e0…1200 52 78 43 42 09 09 20 84 52 65 63 65 69 76 65 20 63 6c 6f 63 6b 2c 20 63 6f 6e 6e 65 63 74 65 64 ┆RxCB Receive clock, connected┆
0x1200…1220 (9,) 20 74 6f 20 53 49 4f 20 0a 19 99 80 80 63 68 61 6e 6e 65 6c 20 42 2e 0d 0a 0d 0a 44 41 54 41 20 ┆ to SIO channel B. DATA ┆
0x1220…1240 30 2d 37 09 09 20 84 22 47 68 6f 73 74 20 69 6e 74 65 72 72 75 70 74 20 67 65 6e 65 72 61 74 6f ┆0-7 "Ghost interrupt generato┆
0x1240…1260 72 22 2c 20 0a 19 99 80 80 63 61 74 63 68 65 73 20 61 6e 79 20 66 61 75 6c 74 20 69 6e 74 65 72 ┆r", catches any fault inter┆
0x1260…1280 72 75 70 74 73 20 66 72 6f 6d 20 0a 19 99 80 80 74 68 65 20 53 49 4f 2c 20 63 6f 6e 6e 65 63 74 ┆rupts from the SIO, connect┆
0x1280…12a0 65 64 20 74 6f 20 74 68 65 20 73 79 73 74 65 6d 20 0a 19 99 80 80 64 61 74 61 20 62 75 73 2e 0d ┆ed to the system data bus. ┆
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0x12ac…12c0 0a a1 53 69 67 6e 61 6c 20 06 44 65 73 63 72 69 70 74 69 6f ┆ Signal Descriptio┆
0x12c0…12e0 6e 05 0d 0a 0d 0a 44 41 54 41 20 30 2d 37 09 09 20 84 44 61 74 61 20 74 6f 20 6f 72 20 66 72 6f ┆n DATA 0-7 Data to or fro┆
0x12e0…1300 6d 20 74 68 65 20 64 79 6e 61 6d 69 63 20 52 41 4d 20 0a 19 99 80 80 73 74 6f 72 61 67 65 20 6f ┆m the dynamic RAM storage o┆
0x1300…1320 6e 20 74 68 65 20 62 6f 61 72 64 2e 20 43 6f 6e 6e 65 63 74 65 64 20 74 6f 20 0a 19 99 80 80 74 ┆n the board. Connected to t┆
0x1320…1337 68 65 20 73 79 73 74 65 6d 20 64 61 74 61 20 62 75 73 2e 0d 0a 0d 0a ┆he system data bus. ┆
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0x1340…1360 0a a1 53 69 67 6e 61 6c 06 44 65 73 63 72 69 70 74 69 6f 6e 05 0d 0a 0d 0a 2d 2c 54 58 52 44 59 ┆ Signal Description -,TXRDY┆
0x1360…1380 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 84 49 6e 74 65 72 72 75 70 74 20 72 65 71 ┆ Interrupt req┆
0x1380…13a0 75 65 73 74 20 74 6f 20 73 69 67 6e 61 6c 20 74 68 65 20 43 50 55 20 0a 19 99 80 80 74 68 61 74 ┆uest to signal the CPU that┆
0x13a0…13c0 20 61 20 63 68 61 72 61 63 74 65 72 20 69 73 20 73 65 6e 74 2c 20 61 6e 64 20 61 20 6e 65 77 20 ┆ a character is sent, and a new ┆
0x13c0…13e0 0a 19 99 80 80 63 68 61 72 61 63 74 65 72 20 6d 61 79 20 62 65 20 6c 6f 61 64 65 64 20 69 6e 74 ┆ character may be loaded int┆
0x13e0…1400 6f 20 74 68 65 20 0a 19 99 80 80 63 6f 6e 74 72 6f 6c 6c 65 72 20 63 68 69 70 2e 20 43 6f 6e 6e ┆o the controller chip. Conn┆
0x1400…1420 (10,) 65 63 74 65 64 20 74 6f 20 74 68 65 20 0a 19 99 80 80 43 54 43 2e 0d 0a 0d 0a 2d 2c 52 78 52 44 ┆ected to the CTC. -,RxRD┆
0x1420…1440 59 09 09 20 84 49 6e 74 65 72 72 75 70 74 20 72 65 71 75 65 73 74 20 74 6f 20 73 69 67 6e 61 6c ┆Y Interrupt request to signal┆
0x1440…1460 20 74 68 65 20 43 50 55 20 0a 19 99 80 80 74 68 61 74 20 61 20 63 68 61 72 61 63 74 65 72 20 68 ┆ the CPU that a character h┆
0x1460…1480 61 73 20 62 65 65 6e 20 72 65 63 65 69 76 65 64 20 0a 19 99 80 80 66 72 6f 6d 20 43 69 72 63 75 ┆as been received from Circu┆
0x1480…14a0 69 74 20 49 49 2e 20 43 6f 6e 6e 65 63 74 65 64 20 74 6f 20 74 68 65 20 0a 19 99 80 80 43 54 43 ┆it II. Connected to the CTC┆
0x14a0…14c0 2e 0d 0a 0d 0a 4c 49 4e 45 32 2c 20 4c 49 4e 45 33 09 20 84 20 20 20 20 20 20 20 20 20 20 43 69 ┆. LINE2, LINE3 Ci┆
0x14c0…14e0 72 63 75 69 74 20 49 49 20 6c 69 6e 65 20 64 72 69 76 65 20 73 69 67 6e 61 6c 73 2e 0d 0a 0d 0a ┆rcuit II line drive signals. ┆
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0x14e9…1500 0a a1 53 69 67 6e 61 6c 20 06 44 65 73 63 72 69 70 74 69 6f 6e 05 0d ┆ Signal Description ┆
0x1500…1520 0a 0d 0a 43 48 41 49 4e 20 45 4e 44 09 09 20 84 45 6e 64 20 6f 66 20 69 6e 74 65 72 72 75 70 74 ┆ CHAIN END End of interrupt┆
0x1520…1540 20 63 68 61 69 6e 2e 0d 0a 0d 0a 2d 2c 49 4e 54 09 09 20 84 49 6e 74 65 72 72 75 70 74 20 72 65 ┆ chain. -,INT Interrupt re┆
0x1540…1560 71 75 65 73 74 20 74 6f 20 74 68 65 20 43 50 55 2e 0d 0a 0d 0a 2d 2c 43 53 42 09 09 20 43 68 69 ┆quest to the CPU. -,CSB Chi┆
0x1560…1580 70 20 73 65 6c 65 63 74 20 74 6f 20 74 68 65 20 43 54 43 2e 0d 0a 0d 0a 2d 2c 43 53 41 09 09 20 ┆p select to the CTC. -,CSA ┆
0x1580…15a0 84 43 68 69 70 20 73 65 6c 65 63 74 20 74 6f 20 74 68 65 20 43 69 72 63 75 69 74 20 49 49 20 0a ┆ Chip select to the Circuit II ┆
0x15a0…15b8 19 99 80 80 63 6f 6e 74 72 6f 6c 6c 65 72 20 63 68 69 70 2e 0d 0a 0d 0a ┆ controller chip. ┆
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0x15e0…1600 ff 00 00 00 ff ff ff 00 00 00 65 63 69 66 69 65 64 20 74 69 6d 65 20 28 33 6f 6f 20 6d 73 2e 29 ┆ ecified time (3oo ms.)┆