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Names: »99110176.WP«
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╱04002d4e0a0006000000000201413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
┆06┆i↲
↲
↲
┆a1┆TABLE OF CONTENTS╞ ╞ ╞ ┆05┆PAGE ↲
↲
↲
1. INTRODUCTION ......................................... 1↲
↲
↲
2. THE BAUD RATE DETERMINATION MODE .....................╞ 2↲
↲
↲
3. THE INITIAL MEMORY TEST .............................. 3↲
3.2 Initial RAM Test ................................. 3↲
3.2.1 Memory Test Flow ........................... 3↲
3.2.2 Loop On Error .............................. 4↲
↲
↲
4. INTERRUPT HANDLING AND PVAM SWITCH ................... 5↲
4.1 Valid Interrupts .................................╞ 5↲
╞ 4.2 Protection Violations and Instruction Exeptions ..╞ 5↲
↲
↲
5. TEST 0 = RAM test .................................... 7↲
↲
↲
6. TEST 1 = Chip Select Test ............................ 9↲
↲
↲
7. TEST 2 = 8254 Programmable Interval Timer Test ....... 10↲
↲
↲
8. TEST 3 = Personality PROM Test ....................... 11↲
↲
↲
9. TEST 4 = RS 422 Test ................................. 12↲
↲
↲
10. TEST 5 = Real Time Clock (RTC) Test .................. 13↲
↲
↲
11. TEST 6 = Timeout Interrupt Test ...................... 14↲
↲
↲
12. TEST 7 = I/O Interrupt Test ........................... 15↲
↲
↲
13. TEST 8 = Numeric Processor Extension Test.............. 16↲
↲
↲
14. TEST 9 = Disc Channel Test ............................ 17↲
↲
↲
15. TEST 10 = Winchester Disc Test ........................ 18↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆TABLE OF CONTENTS (continued) PAGE↲
↲
16. TEST 11 = Multibus Configuration ...................... 20↲
↲
↲
17. TEST 12 = Parallel Port Test .......................... 22↲
↲
↲
18. TEST 13 = Multibus Out Interrupt Test ................. 23↲
↲
↲
19. TEST 14 = Real Time Clock (RTC) Programming Test ...... 24↲
↲
↲
20. TEST 15 = Extended RAM Test ........................... 25↲
20.1 Test Variables ................................... 25↲
20.1.1 Operating Mode ............................ 26↲
20.1.2 Address Range ............................. 26↲
20.1.3 Change Pattern ............................ 26↲
20.1.4 Execute Subtest Alone ..................... 26↲
20.1.5 Bus LOCK .................................. 26↲
20.1.6 BUS Select ................................ 26↲
20.2 Subtest 0 = Pattern test - WORD mode, EVEN Alignm. 27↲
20.3 Subtest 1 = Pattern test - WORD mode, ODD Alignm. 27↲
20.4 Subtest 2 = Pattern test - BYTE mode, ALL bytes .. 27↲
20.5 Subtest 3 = Pattern test - BYTE mode, EVEN bytes only 28↲
20.6 Subtest 4 = Pattern test - BYTE mode, ODD bytes only 28↲
20.7 Subtest 5 = ECC Error Correction Test ............ 29↲
20.8 Subtest 6 = ECC Error Detection Test ............. 30↲
↲
↲
21. TEST 16 = Floppy Test ................................. 31↲
↲
↲
22. TEST 17 = Printer Test ................................ 33↲
↲
↲
23. TEST 18 = Real Time Clock Adjustment Test ............. 34↲
↲
↲
24. LED OUTPUT ............................................ 35↲
↲
↲
APPENDICES:↲
↲
A. REFERENCES ............................................. 37↲
↲
↲
B. COMPLETE ERROR LIST .................................... 38↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆╞ ╞ ╞ ╞ ┆0b┆┆a1┆↲
┆a1┆┆a1┆┆b0┆1. INTRODUCTION.↲
↲
↲
The CPU 610 is an RC iAPX 286 processor based board, used as the ↓
main CPU in RC 39 products. The CPU 610 replaces an INTEL ↓
Manufactured board called CPU 691.↲
↲
↲
This manual assumes the reader is familiar with the RC 39 ↓
selftest concept as described in the manual called "The RC 39 ↓
Selftest Concept". The CPU 610 selftest includes 19 different ↓
tests which may be run in several modes. Twelwe of these tests ↓
are ┆b0┆default┆f0┆ tests which allways execute after a power on. One ↓
┆19┆┄┆81┆┄test is an ┆b0┆extended┆b0┆┆f0┆ test which may be appended to the default set ↓
┆19┆┄┆83┆┄when requested explicit by an operator. The last six tests are ↓
┆19┆┄┆83┆┄┆b0┆seperate┆b0┆l┆f0┆┆b0┆y┆f0┆ run tests, which may each be requested to execute as ↓
┆19┆┄┆86┆┄stand alone programs.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆┆a1┆┆b0┆2. THE BAUD RATE ┆a1┆DETERMINATION MODE.↲
↲
↲
If a terminal is connected to the V.24 line 1 interface (DSR ↓
activ) then the selftest enters the automatic Baud Rate ↓
Determination mode. The USART is initialized to 9600 Baud and ↓
stars (*****) are written to line 1. These stars may be seen as ↓
stars, other mixed characters or not seen at all depending on the ↓
Baud Rate of the attached console. The selftest waits for the ↓
operator to enter one or two upper case U. One upper case U is ↓
enough if the Baud Rate is 9600, 4800 or 2400 Baud. Baud Rates of ↓
1200, 600 or 300 requires two upper case U.↓
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆3. THE INITIAL MEMORY TEST.↲
↲
↲
After a power on the selftest at first initializes the peripheral ↓
devices, and then enters the initial memory test. This very first ↓
part of the selftest executes in 8086 mode with interrupts ↓
disabeled.↲
↲
↲
The initial memory test of the CPU 610 SBC selftest consists of ↓
two parts, a PROM checksum test and a RAM memory test. The ↓
contents of both the odd and the even PROM's are summarized ↓
ewise and the result must be a zero. For that reason the ↓
PROM's contain a compensation byte which is used to bring the sum ↓
to zero. The checksum test may produce the following errortext.↲
┆a1┆↲
↲
┆b0┆┆f0┆1. ┆b0┆checksum test: sum error exp.:<0000> rec.:<xyzw>↲
↲
↲
Checksum error usually means that the content of the PROM has ↓
been damaged and that the PROM must be changed.↲
↲
↲
┆a1┆┆b0┆3.2 Initial RAM Test.↲
↲
↲
The initial RAM test verifies the first 64 kbytes of RAM ↓
addresses 000000-00FFFF hexadecimal. This part of RAM is used to ↓
hold the protection tables plus selftest and monitor variables ↓
when the processor enters the protected mode of operation.↲
↲
↲
The memory test is a register based test and uses no memory space ↓
at all, neither for variables nor stack.↲
↲
↲
┆a1┆┆e1┆The test pattern is the convenient modulus 3 pattern consisting ↓
of three times 0000 followed by three times FFFF ( hexadecimal ).↲
↲
↲
┆a1┆┆b0┆3.2.1 Memory Test Flow.↲
↲
↲
The test starts in the highest RAM address of the lowes 64 K byte ↓
memory block (FFFF hex.) and inserts the pattern towards lower ↓
addresses.↲
↲
↲
When all initial memory words have been written and verified, ↓
they are tested again with the inversed pattern, this means, that ↓
all bits are tested for "zero" and "one" insertion. If an error ↓
occur the following message is written to the console.↲
↲
┆a1┆↲
┆b0┆┆f0┆2. ┆b0┆Initial RAM Test: RAM error segm.:<ssss> addr.:<aaaa>↲
┆19┆┄┆82┆┆82┆ exp.:<eeee>┆b0┆ rec.:<rrrr>↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
The secondary text is interpreted like this :↲
↲
<ssss> is the segment address (allways 0000)↲
<aaaa> is the segment offset↲
<eeee> is the expected pattern, should allways be 0000 or FFFF.↲
<rrrr> is the received pattern.↲
↲
↲
┆a1┆┆b0┆3.2.2 Loop On Error.↲
↲
↲
When a fault occur during the initial RAM test an error message ↓
is written to the console, and the RAM test starts from the ↓
beginning again. This will be the case until no error is ↓
discovered. If there is a RAM error and if an L is typed from the ↓
keyboard, then the RAM test will not start from the beginning ↓
again, but proceed trough the RAM test and write all RAM errors ↓
to the console, and finally enter the "test-administrator" to ↓
execute other tests if possible.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆4. INTERRUPT HANDLING AND PVAM SWITCH.↲
↲
↲
When the CPU 610 SBC selftest has terminated the initial memory ↓
test the protection tables are copied from EPROM to RAM. Then the ↓
iAPX 286 CPU and the board as well is switched into the Protected ↓
Virtual Address Mode, and a message is written to the console ↓
like this:↲
↲
↲
┆b0┆******* PVAM ENTERED *******↲
↲
↲
If an 80827 Numeric Coprocessor is present, then it is also ↓
switched into the protected mode and another message written to ↓
the console:↲
↲
↲
┆b0┆80287 NPX Found↲
↲
↲
┆a1┆┆b0┆4.1 Valid Interrupts.↲
↲
↲
A few interrupts are allways considered valid during the ↓
selftest:↲
↲
↲
┆a1┆Request line Interrupt name Vector type Event type ↲
↲
internal Step interrupt 1╞ ┆84┆instruction executed ↓
┆19┆┆ac┆┄┄with trap flag set↲
↲
internal╞ Break interrupt╞ 3╞ ┆84┆software interrupt ↓
┆19┆┆ac┆┄┄(debugger entry)↲
↲
CNTR0╞ Timer 0╞ ╞ 40╞ Timer 0 interrupt↲
↲
SER INTR╞ USART receive int.╞ 34╞ Keyboard interrupt↲
↲
↲
┆a1┆┆b0┆4.2 Protection Violations and Instruction Exceptions.↲
↲
↲
The protection violations and instruction exceptions will cause ↓
the selftest to write a message to the console and then execute ↓
a HALT instruction. The only way to get out of these exception is ↓
to hardware reset the CPU.↲
↲
↲
┆a1┆Vector type Error Text ↲
↲
0 Interrupt 0 at 'CS:IP' Divide By Zero↲
╞ ╞ HALTED - Hardware RESET required↲
↲
2╞ ╞ Interrupt 2 at 'CS:IP' NMI↲
╞ ╞ HALTED - Hardware RESET required↲
↲
┆8c┆┆83┆┆d0┆↓
4╞ ╞ Interrupt 4 at 'CS:IP' Overflow↲
╞ ╞ HALTED - Hardware RESET required↲
↲
5╞ ╞ Interrupt 5 at 'CS:IP' Bounds Check↲
╞ ╞ HALTED - Hardware RESET required↲
↲
6╞ ╞ Interrupt 6 at 'CS:IP' Undefined Operation↲
╞ ╞ HALTED - Hardware RESET required↲
↲
7╞ ╞ Interrupt 7 at 'CS:IP' Device Not Available↲
╞ ╞ HALTED - Hardware RESET required↲
↲
8╞ ╞ Interrupt 8 at 'CS:IP' Double Fault↲
╞ ╞ HALTED - Hardware RESET required↲
↲
9╞ ╞ Interrupt 9 at 'CS:IP' Math Address Error↲
╞ ╞ HALTED - Hardware RESET required↲
↲
10╞ ╞ Interrupt 10 at 'CS:IP' Invalid Task State Segment↲
- ECODE = XXXX↲
╞ ╞ HALTED - Hardware RESET required↲
↲
11╞ ╞ Interrupt 11 at 'CS:IP' Not Present - ECODE = XXXX↲
╞ ╞ HALTED - Hardware RESET required↲
↲
12╞ ╞ Interrupt 12 at 'CS:IP' Stack Protection↲
╞ ╞ - ECODE = XXXX↲
╞ ╞ HALTED - Hardware RESET required↲
↲
13╞ ╞ Interrupt 13 at 'CS:IP' General Protection↲
╞ ╞ - ECODE = XXXX↲
╞ ╞ HALTED - Hardware RESET required↲
↲
14╞ ╞ Interrupt 14 at 'CS:IP'↲
╞ ╞ HALTED - Hardware RESET required↲
↲
15╞ ╞ Interrupt 15 at 'CS:IP'↲
╞ ╞ HALTED - Hardware RESET required↲
↲
16╞ ╞ Interrupt 16 at 'CS:IP' Math Error↲
╞ ╞ HALTED - Hardware RESET required↲
↲
↲
The term 'CS:IP' refers to the logical location in the program, ↓
where the exception came. The errorcode pushed onto the stack by ↓
some exceptions (ECODE) may be hard to decode, and no attempt to ↓
document them in this manual will be done. Consult INTEL manuals ↓
for further description of the exceptions and their errorcodes.↲
↲
↲
All other interrupts that either refer to a NULL descriptor in ↓
the Interrupt Descriptor Table (IDT) or to a descriptor outside ↓
the IDT limit will cause one of the protection violations above. ↓
If a test uses interrupt vectors not mentioned above, then the ↓
test is responsible for loading the appropiate descriptor into ↓
the IDT prior to the test and to nullify the descriptor at the ↓
end of the test.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5. ┆b0┆TEST 0 =┆f0┆ RAM test.┆b0┆↲
↲
↲
After the switching of the iAPX 286 processor to the protected ↓
mode of operation this RAM test is responsible for verifying the ↓
rest of the CPU 610 memory. The memory size is variable between ↓
512 K bytes and 8 M bytes and a maximum of 4 memory boards may be ↓
connected to a CPU 610 (iLBX BUS width is 5 slots). The memory ↓
must be contiguous from address 0 (the XENIX operating system ↓
assumes this).↲
↲
↲
This RAM test, of course, dont verify the lowest part of memory ↓
addresses 0-FFFF hexadecimal, which is covered by the initial ↓
memory test and used to hold selftest variables.↲
↲
↲
This test divides the available memory space into 64 K byte ↓
blocks, the first starting at address 10000 hexadecimal and the ↓
last ending at address 7FFFFF hexadecimal. For every possible 64 ↓
K byte block the RAM test does:↲
↲
↲
1. ┆84┆Writes a pattern to the first byte of that block. Reads the ↓
┆19┆┆83┆┄┄byte back, and if the same pattern is read back memory is ↓
┆19┆┆83┆┄┄considered present and the verification of that block ↓
┆19┆┆83┆┄┄continues, otherwise the next 64 K byte block is tried.↲
↲
↲
2. ┆84┆The 64 K byte block considered present in step 1 is filled ↓
┆19┆┆83┆┄┄with ones. The content is read back, and if not all ones an ↓
┆19┆┆83┆┄┄error message is generated and the test terminated.↲
↲
↲
3. ┆84┆The 64 K byte block of memory is filled with zeroes. The ↓
┆19┆┆83┆┄┄content is read back, and if not all zeroes an error message ↓
┆19┆┆83┆┄┄is generated and the test terminated.↲
↲
↲
4. ┆84┆Step 1 is entered again until the last possible 64 K byte ↓
┆19┆┆83┆┄┄block has been checked.↲
↲
┆b0┆┆f0┆↲
The RAM test may produce the following error message:↲
↲
↲
1. ┆b0┆RAM test: RAM error segm.:<ssss> addr.:<aaaa> exp.:<eeee>↲
╞ ╞ ╞ ╞ ┆b0┆ rec.:<rrrr>↲
↲
↲
The secondary text is interpreted like this :↲
↲
↲
<ssss> ┆84┆is the segment LDT selector (use RC 39 Monitor to ↓
┆19┆┆87┆┄┄determine the physical address - XLDT <ssss>)↲
<aaaa> is the segment offset↲
<eeee> is the expected pattern, should allways be 0000 or FFFF.↲
┆8c┆┆83┆┆c8┆↓
<rrrr> is the received pattern.↲
↲
↲
The memory size is handed over to the Multibus configuration ↓
program and displayed in the Multibus Configuration Schedule.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆81┆┆a1┆┆b0┆6. ┆b0┆TEST 1 = ┆f0┆Chip Select Test.↲
↲
↲
To ease complex debugging, a simple chip select loop, combined ↓
with a RAM write/read, is supplied. ↲
↲
↲
This test generates chip selects to all peripheral devices by ↓
executing input instructions to all relevant I/O-devices. These ↓
are :↲
↲
↲
Port ┆84┆0C0, 0C2, 0C4, 0C6, 0C8, 0CA, 0CC, 0CE, 0D0, 0D2, 0D4, 0D6, ↓
┆19┆┆85┆┄┄0D8, 0DA, 0DC, 0DE.↲
↲
↲
When all the chip selects are made, a pattern AA55 hex. is ↓
written to a RAM cell and immediately read back.↲
↲
This test is unable to generate any error messages. It is meant ↓
only as a special fast scope loop test.↲
════════════════════════════════════════════════════════════════════════
↓
┆a2┆┆e2┆┆a1┆┆b0┆7. ┆b0┆TEST 2┆f0┆ = 8254 Programmable Interval Timer Test.↲
↲
↲
This test verifies the ability of the 8254 PIT timer 0, used as a ↓
real time clock in XENIX, to generate interrupts. Timer 0 is ↓
initialized as a real time clock which generates interrupt every ↓
20 millisecond. If no timer interrupt is generated then an error ↓
message is generated like this.↲
↲
↲
┆a1┆┆a1┆┆a1┆┆e1┆┆b0┆┆f0┆1. ┆b0┆PIT Test : missing timer 0 interrupt↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆8. ┆b0┆TEST 3┆f0┆ ┆f0┆= Personality PROM Test.↲
↲
↲
The personality PROM test calculates the checksum of the 256 * 4 ↓
bit bipolar PROM. All nibbles are added with carry, and the test ↓
displays the checksum hexadecimally like this.↲
↲
↲
┆b0┆Personality PROM test: Checksum = XYVZ↲
↲
↲
This test is unable to generate error messages.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆9. ┆b0┆TEST 4┆f0┆ = RS 422 Test.↲
↲
↲
This test program verifies the RS 422 multidrop interface and its ↓
status signals. On board loopback circuitry makes it possible to ↓
run this test without external hardware connected.↲
↲
↲
First the test verifies the function of the CTS status signal, ↓
which is toggled by DTR in loop back mode, and if an error occur ↓
a message is displayed.↲
↲
↲
1. ┆b0┆RS 422 test: RS422 Clear to Send error↲
↲
↲
If the status signal test succeeds then a serial data transport ↓
of a 2 K byte long source buffer to an equally long destination ↓
buffer is made. When the data transport has completed the two ↓
buffers are compared, and if not equal an error message is ↓
written to the console.↲
↲
↲
2. ┆b0┆RS 422 test: data error↲
↲
↲
If the data transport does'nt complete within 5 seconds a timeout ↓
message is generated.↲
↲
↲
3. ┆b0┆RS 422 test: transfer timeout↲
↲
↲
If a parity interrupt is generated another error message is ↓
generated. The USART is not initialized to operate with parity so ↓
this interrupt is truly unexpected.↲
↲
↲
4. ┆b0┆RS 422 test: parity interrupt error↲
↲
↲
The test executes at 9600 baud.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆10. ┆b0┆TEST 5┆f0┆ = Real Time Clock (RTC) Test.↲
↲
↲
The Real Time Clock test is used to display the state of the on ↓
board RTC chip. The normal output from the test looks like this.↲
↲
↲
┆b0┆RTC test: I Think it is: my:dm:hd:md:sh↲
↲
↲
my is month of year, dm is day of month, hd is hour of day, md is ↓
minute of hour and sh is second of minute.↲
↲
↲
If the RTC test reads an invalid BCD code from the clock chip an ↓
error message is generated.↲
↲
↲
1. ┆b0┆RTC test: read error↲
↲
↲
If it is impossible to read the RTC clock chip without status ↓
error after 50 attempts another error message is generated.↲
↲
↲
2. ┆b0┆RTC test: status error↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆11. ┆b0┆TEST 6┆f0┆ = Timeout Interrupt Test.↲
↲
↲
This test is supplied to verify the functionality of the timeout ↓
interrupt logic. This test generates a timeout by an out ↓
instruction to port 0FFFF hexadecimal. If no interrupt occur an ↓
error message is generated.╞ ↓
↲
↲
1. ┆f0┆┆b0┆Timeout interrupt test: missing interrupt rec.:<0032>↲
↲
↲
The received value display the type of the interrupt missing. If ↓
the interrupt is generated but unable to reset another message is ↓
written.↲
↲
↲
2. ┆b0┆Timeout interrupt test: cannot reset interrupt rec.:<0032>↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆12. ┆b0┆TEST 7┆f0┆ = I/O Interrupt Test.↲
↲
↲
This test verifies the 8 extra Multibus interrupt mapped in to ↓
I/O space. The interrupts is generated one by one starting with ↓
MB interrupt 15 (type 38) and ending with interrupt 8 (type 33). ↓
If no interrupt occur an error message is generated.╞ ↲
↲
1. ┆f0┆┆b0┆IO interrupt test: missing interrupt rec.:<00rr>↲
↲
↲
The received value display the type of the interrupt missing. If ↓
the interrupt is generated but unable to reset another message is ↓
written.↲
↲
↲
2. ┆b0┆IO interrupt test: cannot reset interrupt rec.:<00rr>↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆13. ┆b0┆TEST 8┆f0┆ =┆f0┆ Numeric Processor Extension Test.↲
↲
↲
The Numeric Processor Extension test program applies to the ↓
verification of the 80287 coprocessor and its interface circuits. ↓
If no 80287 coprocessor is present (bit 2 Machine Status Word ↓
"0") then a message is written to the console like this.↲
↲
1. ┆b0┆80287 NPX Test: NPX not present: OK↲
↲
↲
Otherwise if the NPX is present the test proceeds and verifies ↓
the NPX's function. If an error is discovered an error message ↓
like this is written to the console.↲
↲
↲
2. ┆b0┆80287 NPX Test: 80287 NPX not OK↲
↲
↲
This error might be caused by malfunction of the 80278 chip, by a ↓
fault of the interface circuits , or by something else. ↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆a1┆14. ┆b0┆TEST 9┆f0┆ = Disk Channel Test.↲
↲
↲
This test is used to exercise and verify the data channel between ↓
CPU 610 and the disk controller.↲
↲
↲
The first part of this test executes a "disc diagnostic command" ↓
to the disc controller. This command orders the disc controller ↓
to verify its sector buffer by the use of several critical data ↓
patterns. If the disc controller responds with an error to this ↓
command an error message is generated.↲
↲
↲
1. ┆b0┆Disc Channel test: disc diagnostic error↲
↲
↲
If the disc does'nt respond to the disc diagnostic command within ↓
800 milliseconds an error message is generated.↲
↲
↲
2. ┆b0┆Disc Channel test: transfer timeout or interrupt missing↲
↲
↲
The second part of this test executes a "write sector buffer ↓
command " followed by a "read sector buffer command". The data ↓
read back are compared to the written pattern and if not equal an ↓
error message is generated.↲
↲
↲
┆b0┆┆b0┆┆f0┆3. ┆b0┆Disc Channel test: disc channel error segm.:<ssss> addr.:<aaaa>↲
┆b0┆exp.:<eeee> rec.:<rrrr>↲
↲
↲
The secondary error text is interpreted like this :↲
↲
↲
<ssss> ┆84┆is the segment LDT selector (use RC 39 Monitor to ↓
┆19┆┆87┆┄┄determine the physical address - XLDT <ssss>)↲
<aaaa> is the segment offset↲
<eeee> is the expected pattern, should allways be 0000 or FFFF.↲
<rrrr> is the received pattern.↲
↲
↲
Otherwise. If an error of the disc is discovered an error message ↓
like this is written to the console.↲
↲
↲
┆82┆4. ┆b0┆Disc Channel test: disc command error↲
↲
↲
This error might be caused by malfunction of the disc, by a fault ↓
of the interface circuits , or by something else. ↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆┆b0┆15. ┆b0┆TEST 10┆f0┆ = Winchester Disc Test.↲
↲
↲
This test verifies the ┆b0┆┆f0┆functionality of the winchester disk ↓
┆19┆┄┆81┆┄drive and the disk controller board, not the winchester media ↓
┆19┆┄┆81┆┄itself. The format of the winchester disk track 1 must be ↓
┆19┆┄┆81┆┄formatted properly prior to the test, it is fixed and is.↲
↲
↲
╞ ╞ ╞ ┆84┆1024 bytes/sector.↲
╞ ╞ ╞ 9 sectors/track.↲
╞ ╞ ╞ 2 heads/cylinder.↲
╞ ╞ ╞ 1 cylinder/disk.↲
↲
↲
This test verifies only on track of the winchester disc the ↓
"test-track" given by the disc description on track 1. ↓
The first part of this test executes a "read command", this ↓
command reads disc characteristic parametres which specifies a ↓
default or current parameter value for disc and is placed on the ↓
sector 0 of track 1. This value remains unchanged and is used to ↓
initialize winchester disk controller.↲
↲
↲
If the disc controller responds with an error to this command an ↓
error message is generated.↲
↲
↲
1. ┆b0┆Winchester disk test: Winchester can not read rec.:<rrrr>↲
↲
↲
<rrrr> is the error code from the disc controller. The OMTI ↓
Reference Manual (SDC 691) Appendix B gives the information about ↓
this error code.↲
↲
↲
If the disk controller does'nt respond to a disk's command within ↓
1 second an error message is generated.↲
↲
↲
2┆b0┆. Winchester disk test: transfer timeout or interrupt missing↲
↲
↲
If the test discovers that the winchester disk isn't formatted a ↓
message is written to the console like this.↲
↲
↲
┆b0┆┆b0┆Winchester disk test: Winchester disk not formatted : OK↲
↲
↲
If the first step went succesfull the test going to the second ↓
part. The second part of this test executes a "write test sector ↓
command " followed by a "read test sector command". A pattern is ↓
written to the test sector, and the disc controller may respond ↓
with an error which makes the test program write an error ↓
message.↲
↲
↲
┆8c┆┆83┆┆d0┆↓
3. ┆b0┆Winchester disk test: Winchester can not write rec.:<rrrr>↲
↲
↲
<rrrr> is the error code from the disc controller. The OMTI ↓
Reference Manual (SDC 691) Appendix B gives the information about ↓
this error code.↲
↲
↲
If no error has happend until now the sector is read back and ↓
compared to the original one, and if equal the test is repeated ↓
on the next sector until end of test track , otherwise an error ↓
message is generated.↲
↲
↲
4. ┆b0┆Winchester disk test: bad test sector sector.:<dddd>, ↓
┆19┆┄┆81┆┆82┆ segm.:<ssss>,┆b0┆ addr.:<aaaa>, exp.:<eeee>, rec.:<rrrr>↲
↲
↲
The secondary error text is interpreted like this :↲
↲
↲
<dddd> gives the address of the bad test sector.↲
<ssss> ┆84┆is the segment LDT selector (use RC 39 Monitor to ↓
┆19┆┆87┆┄┄determine the physical address - XLDT <ssss>).↲
<aaaa> is the segment offset.↲
<eeee> is the expected pattern.↲
<rrrr> is the received pattern.↲
↲
↲
Otherwise. If an error of the disk controller or of the disk ↓
drive is discovered an error message like this is written to the ↓
console.↲
↲
↲
┆82┆5. ┆b0┆Winchester disk test: disk command error↲
↲
↲
This error might be caused by malfunction of the disc, by a fault ↓
of the interface circuits , or by something else.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆16. ┆b0┆TEST 11 =┆f0┆ Multibus Configuration.↲
↲
↲
When the CPU 610 has finished its own selftest it will make a ↓
Multibus configuration. Every RC-manufactured SBC card is located ↓
with its Dual-Ported RAM ending on a 64 KB boundary address. When ↓
a RC 39 SBC starts the execution of its selftest program it ↓
immediately initializes the last word in its Dual-Ported RAM with ↓
a special pattern corresponding to "not-ready". When the test is ↓
terminated with or without an error the pattern is changed to ↓
"ready". Ready indicates to the "test-master" that the SBC is ↓
ready to communicate. Both the "not-ready" pattern and the ↓
"ready" pattern must of course be different from the pattern ↓
which is read by the "test-master" when reading from a Multibus ↓
address with non-existing RAM (bus acknowledge timeout assumed).↲
↲
↲
The hardware configuration process is possible due to the fact ↓
that all the "test-slaves" communicates with the "test-master" ↓
trough DP-RAM located to end on 64 K boundaries. This minimizes ↓
the configuration attempts to a maximum of 32 entries ↓
(controllers are placed between Multibus addresses 800000-A00000 ↓
hexedecimal). During the configuration process the "test-master" ↓
starts reading from the top of the controller address space ↓
(address 9FFFFF hexadecimal). If a pattern equal to "not-ready" ↓
or "ready" is found the selftest assumes that an intelligent SBC ↓
card is present, and reads som further parameters such as card-↓
type, RAM-size and selftest execution time in seconds. If the ↓
card is marked "not-ready" the "test-master" may use the selftest ↓
execution time to decide how long to wait for that card to become ↓
"ready". Also a handshake protocol is executed to reassure that ↓
the "ready" pattern was not read by random. From the knowledge to ↓
the RAM-size the "test-master" calculates the address where to ↓
continue the Multibus configuration. If no "ready" or "not-ready" ↓
pattern is received then the "test-master" configuration writes ↓
to and reads back from the RAM cell to find out if some RAM ↓
really exists on that Multibus address. The configuration program ↓
ends with writing a configuration schedule to the console. The ↓
schedule might look like this:↲
↲
┆b0┆↲
╱04002d4e0c000600000000020147314000000000000000000000000000000000000000000000000008101820283038404b555f69737dffff04╱
╱04002d4e0a0006000000000201413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
┆b0┆Multibus Configuration:↲
┆b0┆======================================================================↲
┆b0┆┆b0┆MB entry - MB address - Card State - Card ID - MB RAM size - error no.↲
┆b0┆======================================================================↲
┆b0┆00000╞ 000000 master╞ CPU 610 02048 00000↲
┆b0┆┆b0┆00001╞ 9E0000╞ ready╞ ITC 602 00064╞ 00000↲
┆b0┆00002 8E0000╞ ready╞ COM 601 00064 00000↲
┆b0┆00003 800000 ready ETC 611 00512 00000↲
╱04002d4e0a000600000000020141314000000000000000000000000000000000000000000000000008101820283038404b555f69737dffff04╱
╱04002d4e0c000600000000020147314000000000000000000000000000000000000000000000000008101820283038404b555f69737dffff04╱
↓
↲
↲
The configuration data is stored in a specific data structure ↓
where it may be accessed by the system software.↲
↲
↲
The bootload is not inhibited if a "test-slave" has found an ↓
error during its default selftest, but a message is written to ↓
┆8c┆┆83┆┆c8┆↓
the console. The reason for this is that an incremental part of ↓
the system may still be running, and this might be sufficient for ↓
many users.↲
↲
↲
The default selftest terminates with directing all the "test-↓
slaves" found during the multibus configuration to their bootload ↓
phase and it may look like this.↲
↲
↲
┆b0┆<00001> sent to bootload↲
┆b0┆<00002> sent to bootload↲
┆b0┆<00003> sent to bootload↲
↲
↲
If some slave dosen't respond correctly to the boot command a ↓
message is written to the console like this.↲
↲
↲
┆b0┆<00002> slave answer timeout↲
↲
↲
Consult the manual called "The RC39 selftest concept" for further ↓
┆19┆┄┆81┆┄information about the Multibus configuration and details about ↓
┆19┆┄┆81┆┄how to run further diagnostics on the "test-slaves".↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆17.┆b0┆ TEST 12 =┆f0┆ Parallel Port Test.↲
↲
↲
The 8255A PPI test writes a pattern 10100000 binary to the output ↓
port A (I/O addr. C8H). Then it reads the pattern back and ↓
verifies it. If no error is detected the pattern is shifted one ↓
bit to the right, and the write/read verify procedure is repeated ↓
until the pattern becomes zero. The test may generate this error ↓
message:↲
↲
↲
┆b0┆┆e1┆┆a1┆┆e1┆┆f0┆1. ┆b0┆PPI test: port error exp.:00ee, rec.:00rr↲
↲
↲
Expected and received pattern tells you what bits went wrong with ↓
the test.↲
↲
↲
This error might be caused by malfunction of the 8255A chip, by ↓
an initialization fault (I/O space error), or by something else. ↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆18. ┆b0┆TEST 13┆f0┆ = Multibus Out Interrupt Test.↲
↲
↲
This ┆b0┆seperately ┆f0┆run test verifies the functionality of the 3 ↓
┆19┆┄┆81┆┄outgoing Multibus interrupts. In order to make this test work 3 ↓
┆19┆┄┆81┆┄straps must be installed in the interrupt strap feld W5, W5(33-↓
┆19┆┄┆81┆┄12), W5(32-13) and W5(43-2). The interrupt is generated one by ↓
┆19┆┄┆81┆┄one, first MBINT2 (type 44), second MBINT1 (type 54) and third ↓
┆19┆┄┆81┆┄MBINT0 (type 48). If an interrupt is generated but not serviced ↓
┆19┆┄┆81┆┄an error message is generated.↲
↲
↲
1. ┆b0┆MB out interrupt test: missing interrupt rec.:<00rr>↲
↲
↲
The received value is the type of the expected inetrrupt.↲
↲
↲
If an interrupt is generated but unable to reset another message ↓
is generated.↲
↲
↲
2. ┆b0┆MB out interrupt test: cannot reset interrupt rec.:<00rr>↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆19. ┆b0┆TEST 14┆f0┆ = Real Time Clock (RTC) Programming Test.↲
↲
↲
This ┆b0┆seperately┆f0┆ run test is supplied as a programming tool for ↓
┆19┆┄┆81┆┄the Real Time Clock chip. A series of question is asked line by ↓
┆19┆┄┆81┆┄line as this.↲
↲
↲
┆b0┆RTC programming:↲
┆b0┆Enter Month of Year ? , <1-12> 1/↲
┆b0┆Enter day of Month ? , <1-31> 1/↲
┆b0┆Enter Hour ? , <0-23> 0/↲
┆b0┆Enter Minute ? <0-59> 0/↲
┆b0┆Enter Seconds ? , <0-59> 0/↲
↲
↲
The questions must be answered with a value in the range given in ↓
brackets (<>), Or a carriage return only. In the latter case the ↓
default value left to the slash is taken.↲
↲
↲
This test is unable to generate error messages.↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆┆a1┆┆b0┆20. ┆b0┆TEST 1┆f0┆┆b0┆5┆f0┆ = Extended RAM Test.↲
↲
↲
This ┆b0┆seperately┆f0┆ run test is supplied to verify the functionality ↓
┆19┆┄┆81┆┄of the INTEL iSBC 012X or the RC MEM 602/603 memory boards. The ↓
┆19┆┄┆81┆┄test is divided into 6 different subtests, which must either ↓
┆19┆┄┆81┆┄execute alone or in a big sequential loop. The first time the ↓
┆19┆┄┆81┆┄test is run several variables must be supplied to the test.↲
↲
↲
┆a1┆┆b0┆20.1 Test Variables.↲
↲
↲
The first time the test is selected a menu is written to the ↓
console like this.↲
↲
↲
╱04002d4e0c00060000000002014d314000000000000000000000000000000000000000000000000008101820283038404b555f69737dffff04╱
╱04002d4e0a000600000000020141314000000000000000000000000000000000000000000000000008101820283038404b555f69737dffff04╱
↓
┆b0┆MEM 60X Test: ************** Extended RAM test - Operating Instructions↓
╱04002d4e0a000600000000020141314000000000000000000000000000000000000000000000000008101820283038404b555f69737dffff04╱
╱04002d4e0c00060000000002014d314000000000000000000000000000000000000000000000000008101820283038404b555f69737dffff04╱
↓
┆b0┆Press <ctl><X>= start MEM 60X test↲
┆b0┆Press <ctl><A>= Enter Debugger Loader↲
┆b0┆Press <escape>= Return to Test Administrator↲
↲
┆b0┆SUBTEST↲
┆b0┆ 0. Pattern test - WORD mode, EVEN alignment↲
┆b0┆ 1. Pattern test - WORD mode, ODD alignment↲
┆b0┆ 2. Pattern test - BYTE mode, ALL bytes↲
┆b0┆ 3. Pattern test - BYTE mode, EVEN bytes only↲
┆b0┆ 4. Pattern test - BYTE mode, ODD bytes only↲
┆b0┆ 5. ECC error correction test↲
┆b0┆ 6. ECC error detection test↲
↲
↲
When a <ctl><X> is entered the questions below will be asked line ↓
by line by the test program. Questions in paranthesis is only ↓
asked if the former question was answered with yes (Y).↲
↲
↲
┆b0┆Enter normal MEM 60X operating mode (ECR port) ? 0FH/↲
┆b0┆Enter test START 64 KB Block number ? <1-FF>, 1H/↲
┆b0┆Enter test START Offset address ? <0-FFFF>, 0H/↲
┆b0┆Enter test END 64 KB Block number ? <1-FF>, 1H/↲
┆b0┆Enter test END Offset address ? <0-FFFF>, 0H/↲
┆b0┆Enter MEM 60X PORT address ? <0-FFFF>, 1C0/↲
┆b0┆Change pattern ? <Y/N>, N/↲
┆b0┆(Enter Your Pattern !! /)↲
┆b0┆Run Subtest ? <Y/N>, N/↲
┆b0┆(Enter Subtest Number ? <0-7>, 0/)↲
┆b0┆Bus LOCK active ? <Y/N>, N/↲
┆b0┆iLBX BUS selected ? <Y/N>, Y/↲
↲
↲
Valid answers is shown in brackets (<>), except for the operating ↓
mode. If a carriage return is entered the value left to the slash ↓
is taken by default.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆20.1.1 Operating Mode.↲
↲
↲
It is not recommended to change the operating mode, except for ↓
disabeling the error correction logic (mode 0BH) during the ↓
execution of subtest 0-4. Subtest 5 is unable to execute ↓
succesfully with error correction disabeled.↲
↲
↲
┆a1┆┆b0┆20.1.2 Address Range.↲
↲
↲
This test divides the 16 M Byte physical memory space into 256 ↓
blocks of 64 K byte each. It is impossible to execute this test ↓
in the lowest 64 K byte block. That block is used for selftest ↓
stack and variables. The physical start or end address for the ↓
test is given as a block number 1-255 plus an offset 0-65536 ↓
which must be entered in hexadecimal. Normally the address range ↓
is selected not to go across Multibus memory board boundaries, ↓
but if subtest 0-4 is executed alone it is possible to execute ↓
the test across contiguous memory board boundaries.↲
↲
↲
┆a1┆┆b0┆20.1.3 Change Pattern.↲
↲
↲
The pattern used by the selftest is by default 6 words long (3 ↓
times 0000 and 3 times FFFF hexadecimal). If the change pattern ↓
question is answered with a yes, then it will be possible to ↓
change the pattern itself and the length of the pattern also. The ↓
minimum length of the pattern is one word and the maximum length ↓
is six words. The "Enter your pattern" question may be terminated ↓
by the <escape> button after 1,2,3,4 or 5 words, the number of ↓
words giving the length of the pattern.↲
↲
↲
┆a1┆┆b0┆20.1.4 Execute Subtest Alone.↲
↲
↲
If the Run Subtest question is answered with a yes, an additional ↓
question about the subtest number is asked.↲
↲
↲
┆a1┆┆b0┆20.1.5 Bus LOCK.↲
↲
↲
If the Bus Lock question is answered with a yes, then subtest 0-4 ↓
executes all memory read or write commands with the Bus Lock ↓
Prefix. It is impossible to lock the bus for more than the ↓
duration of one instruction.┆a1┆↲
↲
↲
┆a1┆┆b0┆20.1.6 BUS Select.↲
↲
↲
If the last question about iLBX bus selected is answered with a ↓
no (N), then CPU 610 uses the Multibus during this test.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆20.2 Subtest 0 = Pattern test - WORD mode, EVEN alignment.↲
↲
↲
Subtest 0 writes the pattern word by word from the pattern buffer ↓
to memory from the start address to the end address. EVEN ↓
alignment is forced on the start address (start address ↓
decremented if ODD). The pattern is read back and compared to the ↓
original one, and if equal the test is repeated with the inversed ↓
pattern, otherwise an error message is generated.↲
↲
↲
1. ┆b0┆MEM 60X Test: Subtest: 0 - RAM error segm.:<ssss> addr.:<aaaa>↲
┆19┆┄┆81┆┆82┆ exp.:<eeee> rec.:<rrrr>↲
↲
↲
The secondary text is interpreted like this :↲
↲
↲
<ssss> ┆84┆is the 64 K byte block number (1-FF).↲
<aaaa> is the offset within the block (0-FFFF).↲
<eeee> is the expected pattern.↲
<rrrr> is the received pattern.↲
↲
↲
┆a1┆┆b0┆20.3 Subtest 1 = Pattern test - WORD mode, ODD alignment.↲
↲
↲
Subtest 1 writes the pattern word by word from the pattern buffer ↓
to memory from the start address to the end address. ODD ↓
alignment is forced on the start address (start address ↓
incremented if EVEN). The pattern is read back and compared to ↓
the original one, and if equal the test is repeated with the ↓
inversed pattern, otherwise an error message is generated.↲
↲
↲
1. ┆b0┆MEM 60X Test: Subtest: 1 - RAM error segm.:<ssss> addr.:<aaaa>↲
┆19┆┄┆81┆┆82┆ exp.:<eeee> rec.:<rrrr>↲
↲
↲
The secondary text is interpreted like this :↲
↲
↲
<ssss> ┆84┆is the 64 K byte block number (1-FF).↲
<aaaa> is the offset within the block (0-FFFF).↲
<eeee> is the expected pattern.↲
<rrrr> is the received pattern.↲
↲
↲
┆a1┆┆b0┆20.4 Subtest 2 = Pattern test - BYTE mode, ALL bytes.↲
↲
↲
Subtest 2 writes the pattern byte by byte from the pattern buffer ↓
to memory from the start address to the end address. The pattern ↓
is read back and compared to the original one, and if equal the ↓
test is repeated with the inversed pattern, otherwise an error ↓
message is generated.↲
↲
↲
1. ┆b0┆MEM 60X Test: Subtest: 2 RAM error segm.:<ssss> addr.:<aaaa>↲
┆b0┆ exp.:<eeee> rec.:<rrrr>↲
↲
↲
┆8c┆┆83┆┆f0┆↓
The secondary text is interpreted like this :↲
↲
↲
<ssss> ┆84┆is the 64 K byte block number (1-FF).↲
<aaaa> is the offset within the block (0-FFFF).↲
<eeee> is the expected pattern.↲
<rrrr> is the received pattern.↲
↲
↲
┆a1┆┆b0┆20.5 Subtest 3 = Pattern test - BYTE mode, EVEN bytes only.↲
↲
↲
Subtest 3 writes the pattern byte by byte from the pattern buffer ↓
to the EVEN memory cells from the start address to the end ↓
address. EVEN alignment is forced on the start address (start ↓
address decremented if ODD). Before the EVEN byte is written the ↓
inversed pattern is written to the ODD byte (EVEN address + 1). ↓
The pattern is read back and compared to the original one, and if ↓
equal the test is repeated with the inversed pattern, otherwise ↓
an error message is generated. It is also checked if the writing ↓
of the EVEN memory cell disturbed the content of the ODD memory ↓
cell and if true an error message is generated.↲
↲
↲
1. ┆b0┆MEM 60X Test: Subtest: 3 - RAM error segm.:<ssss> addr.:<aaaa>↲
┆b0┆ exp.:<eeee> rec.:<rrrr>↲
↲
↲
The secondary text is interpreted like this :↲
↲
↲
<ssss> ┆84┆is the 64 K byte block number (1-FF).↲
<aaaa> is the offset within the block (0-FFFF).↲
<eeee> is the expected pattern.↲
<rrrr> is the received pattern.↲
↲
↲
┆a1┆┆b0┆20.6 Subtest 4 = Pattern test - BYTE mode, ODD bytes only.↲
↲
↲
Subtest 4 writes the pattern byte by byte from the pattern buffer ↓
to the ODD memory cells from the start address to the end ↓
address. ODD alignment is forced on the start address (start ↓
address incremented if ODD). Before the ODD byte is written the ↓
inversed pattern is written to the EVEN byte (ODD address - 1). ↓
The pattern is read back and compared to the original one, and if ↓
equal the test is repeated with the inversed pattern, otherwise ↓
an error message is generated. It is also checked if the writing ↓
of the ODD memory cell disturbed the content of the EVEN memory ↓
cell and if true an error message is generated.↲
↲
↲
1. ┆b0┆MEM 60X Test: Subtest: 4 - RAM error segm.:<ssss> addr.:<aaaa>↲
┆b0┆ exp.:<eeee> rec.:<rrrr>↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
The secondary text is interpreted like this :↲
↲
↲
<ssss> ┆84┆is the 64 K byte block number (1-FF).↲
<aaaa> is the offset within the block (0-FFFF).↲
<eeee> is the expected pattern.↲
<rrrr> is the received pattern.↲
↲
↲
┆a1┆┆a1┆┆b0┆20.7 Subtest 5 = ECC Error Correction Test.↲
↲
↲
Subtest 5 verifies the ability of the ECC hardware circiutry to ↓
correct single bit errors.↲
↲
↲
First the test resets all memory cells from the start address to ↓
the end address, and if unable to reset memory generates an error ↓
message like this.↲
↲
↲
1. ┆b0┆MEM 60X Test: Subtest: 5 - Could not reset RAM↲
↲
↲
If RAM is reset succesfully the then test proceeds and makes the ↓
start address EVEN aligned (decrement start address if ODD). Then ↓
a pattern equal to 0000000000000001 binary is written to the ↓
first memory cell in diagnostic mode (writing of checkbits ↓
inhibited), the checkbits is read and saved for an eventually ↓
error message. The operating mode is restored and the data is ↓
read back. The syndrome bits are read and if they does'nt ↓
indicate an error correct correction (the bit set in the pattern ↓
should get corrected to a 0) then an error message is written to ↓
the console.↲
↲
↲
2. ┆b0┆MEM 60X Test: Subtest: 5 - error correction error↲
┆b0┆synbit <yyyy> chkbit <cccc> segm.:<ssss> addr.:<aaaa>↲
┆19┆┄┆81┆┆82┆ exp.:<eeee> rec.:<rrrr>↲
┆a1┆↲
↲
The secondary text is interpreted like this :↲
↲
↲
<yyyy> ┆84┆is the syndrome bits that shoud indicate a one bit error ↓
┆19┆┆87┆┄┄correction.↲
<cccc> ┆84┆is the checkbits that was not written because diagnostic ↓
┆19┆┆87┆┄┄mode was selected.↲
<ssss> ┆84┆is the 64 K byte block number (1-FF).↲
<aaaa> is the offset within the block (0-FFFF).↲
<eeee> is the expected pattern, always 0000.↲
<rrrr> is the received pattern.↲
↲
↲
If no error occur then the pattern is shifted one position left ↓
until a carry and the test is repeated for every memory cell from ↓
the start address to the end address.↲
┆a1┆┆82┆↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆20.8 Subtest 6 = ECC Error Detection Test.↲
↲
↲
Subtest 6 verifies the ability of the ECC hardware circiutry to ↓
detect double bit errors.↲
↲
↲
First the test resets all memory cells from the start address to ↓
the end address, and if unable to reset memory generates an error ↓
message like this.↲
↲
↲
1. ┆b0┆MEM 60X Test: Subtest: 6 - Could not reset RAM↲
↲
↲
If RAM is reset succesfully then the test proceeds and makes the ↓
start address EVEN aligned (decrement start address if ODD). Then ↓
a pattern equal to 0000000000000101 binary is written to the ↓
memory in diagnostic mode (writing of checkbits inhibited), the ↓
checkbits is read and saved for an eventually error message. The ↓
operating mode is restored and the data is read back. The ↓
syndrome bits are read and if they does'nt indicate a double ↓
error detection then an error message is written to the console.↲
↲
↲
2. ┆b0┆MEM 60X Test: Subtest: 6 - error detection error↲
┆b0┆ synbit <yyyy> chkbit <cccc> segm.:<ssss> addr.:<aaaa> ↲
┆19┆┄┆81┆┆82┆ exp.:<eeee> rec.:<rrrr>↲
┆a1┆↲
↲
The secondary text is interpreted like this :↲
↲
↲
<yyyy> ┆84┆is the syndrome bits that shoud indicate a double bit ↓
┆19┆┆87┆┄┄error detection↲
<cccc> ┆84┆is the checkbits that was not written because diagnostic ↓
┆19┆┆87┆┄┄mode was selected.↲
<ssss> ┆84┆is the 64 K byte block number (1-FF).↲
<aaaa> is the offset within the block (0-FFFF).↲
<eeee> is the expected pattern, always 0000.↲
<rrrr> is the received pattern.↲
↲
↲
If no error occur then the pattern is shifted one position left ↓
until a carry and the test is repeated for every memory cell from ↓
the start address to the end address.↲
┆a1┆┆82┆↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆21. ┆b0┆TEST 16┆f0┆ ┆f0┆= Floppy Test.↲
↲
↲
This is a ┆b0┆seperately ┆f0┆run test supplied to verify the ↓
┆19┆┄┆81┆┄functionality of the floppy disk drive, not the floppy media ↓
┆19┆┄┆81┆┄itself.↲
↲
↲
This test will, if not terminated before the end, verify every ↓
single sector on the floppy disc. The format of the floppy disc, ↓
which must be formatted properly prio to the test, is fixed and ↓
is.↲
↲
↲
╞ ╞ ╞ ┆84┆1024 bytes/sector.↲
╞ ╞ ╞ 8 sectors/track.↲
╞ ╞ ╞ 2 heads/cylinder.↲
╞ ╞ ╞ 77 cylinders/disk.↲
↲
↲
This test verifies the floppy drive sector for sector, beginning ↓
with sector 0 (head 0 track 0 sector 0). Before the sector is ↓
written the content of the sector is read to a save buffer, which ↓
is restored if no disk error occur. This makes the floppy test, ↓
if the floppy drives is ok, non media destructive. If the test ↓
cannot read a sector an error message is generated.↲
↲
↲
1. ┆b0┆Floppy test: Floppy can not read ╞ ╞ rec.:<rrrr>↲
↲
↲
<rrrr> is the error code from the disc controller. The OMTI Reference ↓
Manual (SDC 691) Appendix B gives the information about this ↓
error code.↲
↲
↲
If the disk controller does'nt respond to a disk's command within ↓
1 second an error message is generated.↲
↲
↲
2. ┆b0┆Floppy test: transfer timeout↲
↲
↲
If the first step went succesfull, then a pattern is written to ↓
the sector, and the disc controller may respond with an error ↓
which makes the test program write an error message.↲
↲
↲
3. ┆b0┆Floppy test: Floppy can not write ╞ ╞ rec.:<rrrr>↲
↲
↲
If no error has happend until now the sector is read back and ↓
compared to the original one, and if equal the test is repeated ↓
on the next sector until end of disk, otherwise an error message ↓
is generated.↲
↲
↲
┆8c┆┆83┆┆c8┆↓
4. ┆b0┆Floppy test: bad sector sector:<dddd>, segm.:<ssss>,↲
╞ ╞ ┆b0┆addr.:<aaaa>, exp.:<eeee>, rec.:<rrrr>↲
↲
↲
The secondary error text is interpreted like this :↲
↲
↲
<dddd> gives the address of the bad sector.↲
<ssss> ┆84┆is the segment LDT selector (use RC 39 Monitor to ↓
┆19┆┆87┆┄┄determine the physical address - XLDT <ssss>).↲
<aaaa> is the segment offset.↲
<eeee> is the expected pattern.↲
<rrrr> is the received pattern.↲
↲
↲
Otherwise. If an error of the disk controller or of the disk ↓
drive is discovered an error message like this is written to the ↓
console.↲
↲
↲
┆82┆5. ┆b0┆Floppy test: floppy command error↲
↲
↲
This error might be caused by malfunction of the disc, by a fault ↓
of the interface circuits , or by something else. ↲
↲
↲
If no error happens, then the floppy test writes a '.' (period) ↓
to the console output for every cylinder verified like this.↲
↲
↲
┆b0┆Floppy test: ........... and so on↲
↲
↲
The Floppy test is terminated by the escape button.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆22.┆b0┆ TEST 17┆f0┆ = Printer Test.↲
↲
↲
A ┆b0┆seperately ┆f0┆run test is supplied to verify the functionality of ↓
┆19┆┄┆81┆┄the Centronix Printer Interface. The test writes a pattern to the ↓
┆19┆┄┆81┆┄printer like this:↲
↲
↲
╱04002d4e0c00060000000002014b314000000000000000000000000000000000000000000000000008101820283038404a4b555f69737dff04╱
╱04002d4e0a000600000000020141314000000000000000000000000000000000000000000000000008101820283038404b555f69737dffff04╱
↓
!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456↲
789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./012↲
3456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-.↲
/0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*↲
+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&↲
'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"↲
#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789↲
!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456↲
789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./012↲
3456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-.↲
/0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*↲
+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&↲
'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"↲
#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789!"#$%&'()*+,-./0123456789↲
↲
and so on.↲
╱04002d4e0a000600000000020141314000000000000000000000000000000000000000000000000008101820283038404a4b555f69737dff04╱
╱04002d4e0c00060000000002014b314000000000000000000000000000000000000000000000000008101820283038404a4b555f69737dff04╱
↓
↲
↲
The printer test is terminated by the escape button.↲
↲
↲
If the printer is'nt selected an error message is generated.↲
↲
↲
1. ┆b0┆Printer Test: printer not selected↲
↲
↲
If the does'nt respond to a character (STROBE signal) with an ↓
acknowledge interrupt then an error message is generated.↲
↲
↲
2. ┆b0┆Printer Test: missing interrupt↲
↲
↲
If the printer is busy for more than 1 minute an error message is ↓
generated.↲
↲
↲
3. ┆b0┆Printer Test: printer busy↲
↓
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆22. ┆b0┆TEST 18┆f0┆ = Real Time Clock Adjustment Test.↲
↲
↲
This ┆b0┆seperately ┆f0┆test must execute during Real Time Clock ↓
┆19┆┄┆81┆┄adjustment. The RTC is programmed to generate interrupt every ↓
┆19┆┄┆81┆┄second, and this program must execute in order to resets the ↓
┆19┆┄┆81┆┄interrupt every second. The test is terminated by the <escape> ↓
┆19┆┄┆81┆┄button.↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆23. LED OUTPUT.↲
↲
↲
During the execution of selftest the LED named "TEST" connected ↓
to bit 1 on the 8255 PPI port C (I/O address CC hex.) is lit. If ↓
an error occur, except checksum error and initial RAM error, then ↓
the LED is made flashing. This LED is placed on the front of the ↓
RC 39 cabinet.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆A. REFERENCES↲
↲
↲
RC 39 Selftest Concept, User's manual ╞ RCSL. 991 10092↲
↲
RC 3931 ETC611 hardware selftest, User's manual RCSL. 991 10096↲
↲
F641 COM 601 hardware selftest, User's manual RCSL. 991 10097↲
↲
ITC 602 hardware selftest, User's manual╞ RCSL. 991 10095↲
┆a1┆↲
RC39 monitor 8086 version, Reference manual╞ RCSL. 991 10134↲
↲
RC39 monitor 80286 version, Reference manual RCSL. 991 10093↲
↲
RC 3902 (CPU 691) hardware selftest, User's man. RCSL. 991 10094↲
↲
MEM 602, MEM 603 General Information╞ ╞ RCSL. 991 10083↲
↲
MEM 602, MEM 603 Technical Description╞ ╞ RCSL. 991 10084↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0c000600000000020150314000000000000000000000000000000000000000000000000008101820283038404a4b555f69737dff04╱
╱04002d4e0a000600000000020141314000000000000000000000000000000000000000000000000008101820283038404a4b555f69737dff04╱
↓
┆a1┆┆b0┆B. ┆a1┆COMPLETE ERROR LIST↲
↲
↲
!-----------------------------------------------------------------------------!↲
! Err. No !╞ ╞ ╞ ╞ Error Text ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
! 0 ! OK╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 1 ! Checksum Test: sum error ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 2╞ ! Initial Memory Test: RAM error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 2╞ ! RAM Test: RAM error╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 5 ! PPI test: port error ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 6 ! PIT test: missing timer 0 interrupt╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 11 ! RS 422 test: RS422 Clear to Send error╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 12 ! RS 422 test: data error╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 13 ! RS 422 test: transfer timeout ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 14 ! RS 422 test: parity interrupt error╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
┆8c┆┆83┆┆b8┆↓
!-----------------------------------------------------------------------------!↲
! 15 ! Printer Test: missing interrupt╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 16 ! Printer Test: printer not selected╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------;↲
! 17 ! Printer Test: printer busy╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 20 ! MEM 60X Test: Subtest: n - RAM error╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 21 ! MEM 60X Test: Subtest: n - Could not reset RAM !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 22 ! MEM 60X Test: Subtest: 5 - data correction error ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 23 ! MEM 60X Test: Subtest: 6 - error detection error ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 25 ! IO interrupt test: missing interrupt╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 26 ! IO interrupt test: cannot reset interrupt╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 27 ! Timeout interrupt test: missing interrupt╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 28 ! Timeout interrupt test: cannot reset interrupt╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 30 ! RTC test: I Think it is: status error╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
════════════════════════════════════════════════════════════════════════
↓
↲
↲
!-----------------------------------------------------------------------------!↲
! 31 ! RTC test: i Think it is: read error╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 40 ! Disc Channel test: transfer timeout or interrupt missing╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 41 ! Disc Channel test: disc diagnostic error╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 42 ! Disc Channel test: disc command error╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 43 ! Disc Channel test: disc channel error╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 45 ! MB out interrupt test: missing interrupt╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 46 ! MB out interrupt test: cannot reset interrupt ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 50 ! 80287 NPX test: 80287 not OK ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 60 ! Winchester disk test: transfer timeout or interrupt missing !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 61 ! Winchester disk test: disk command error ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 62 ! Winchester disk test: Winchester disk can not read !↲
!-----------------------------------------------------------------------------!↲
↲
↲
┆8c┆┆83┆┆c8┆↓
!-----------------------------------------------------------------------------!↲
! 63 ! Winchester disk test: Winchester disk can not write ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 64 ! Winchester disk test: bad test sector╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 80 ! Floppy test: transfer timeout╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 81 ! Floppy test: floppy command error ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 82 ! Floppy test: floppy can not read !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 83 ! Floppy test: floppy can not write ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
↲
↲
!-----------------------------------------------------------------------------!↲
! 84 ! Floppy test: bad sector╞ ╞ ╞ ╞ ╞ ╞ !↲
!-----------------------------------------------------------------------------!↲
════════════════════════════════════════════════════════════════════════
↓
↲
↓
↓
↓
↓
↓
↓
┆1a┆┆1a┆-----------------------------------------------------------------------------------------!↲
! 15 ! Printer Test