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Length: 89088 (0x15c00)
Types: RcTekst
Names: »99110324.WP«
└─⟦6fdfe4d4d⟧ Bits:30005866/disk5.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110324.WP«
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
┆06┆i↲
↲
┆a1┆┆b0┆TABLE OF CONTENTS┆05┆PAGE↲
↲
1. INTRODUCTION ............................................. 1 ↲
↲
2. GENERAL DESCRIPTION OF CPU610X ........................... 2↲
↲
3. BLOCK DIAGRAM ............................................ 3↲
↲
4. FUNCTIONAL DESCRIPTION ................................... 4↲
4.1 On board CPU ......................................... 4↲
4.1.1 80286 CPU ...................................... 4↲
4.1.2 Optional 80287 Numeric processor ............... 5↲
4.2 I/O Interface ........................................ 5↲
4.2.1 I/O adressing on board ......................... 5↲
4.2.2 Seriees interface .............................. 7↲
4.2.3 Parallel interface ............................. 8↲
4.3 Clock Generator ...................................... 11↲
4.4 Interrupt operation .................................. 11↲
4.4.1 Interrupt Source ............................... 11↲
4.4.2 Interrupt Generator ............................ 14↲
4.5 Software Reset and Power commands .................... 15↲
4.5.1 Software Reset ................................. 15↲
4.5.2 Power Down Operation ........................... 15↲
4.6 On board clock ....................................... 16↲
4.7 Memory addressing .................................... 17↲
4.7.1 On board EPROM ................................. 17↲
4.8 Bus Interface ........................................ 18↲
4.8.1 MULTIBUS ....................................... 18↲
4.8.2 iLBX bus ....................................... 19↲
4.8.3 iSBX bus ....................................... 19↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆06┆ii↲
↲
┆a1┆┆b0┆TABLE OF CONTENTS (continued)┆05┆PAGE↲
↲
5. TECHNICAL DESCRIPTION .................................... 20↲
5.1 Logic Diagrams with Signal Description ............... 20↲
5.2 PAL and PROM Descriptions ............................ 66↲
5.3 Timing Diagrams ...................................... 84↲
5.3.1 First ROM access on CPU610B .................... 85↲
5.3.2 8274 cycle on CPU610A .......................... 86↲
╞ 5.3.3 RTC cycle CPU610A .............................. 87↲
╞ 5.3.4 Multibus cycle on CPU610B to MEM691 ............ 88↲
╞ 5.3.5 iLBXbus cycle CPU610B to MEM691 ................ 89↲
5.4 Plugs ................................................ 90↲
╞ 5.4.1 P1 Multibus Connector .......................... 90↲
╞ 5.4.2 P2 extended Multibus Connector ↲
(iLBXbus connector) ............................ 91↲
╞ 5.4.3 J1 Console Interface Connector ................. 92↲
╞ 5.4.4 J2 RS422A Multidrop Interface Connector ........ 93↲
╞ 5.4.5 J3 Parallel Printer Interface Connector ........ 94↲
╞ 5.4.6 J4 LED603, BBC601 and Key Interrupt Connector .. 95↲
╞ 5.4.7 J5 iSBXbus Interface Connector ................. 96↲
5.5 Jumpers .............................................. 97↲
5.6 Environmental Specification .......................... 98↲
5.7 Physical Specifications .............................. 99↲
5.8 Power Specifications ................................. 99↲
↲
↲
┆a1┆┆b0┆APPENDIX↲
↲
A. REFERENCES ............................................... 101↲
════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆ ┆0b┆↲
┆a1┆┆b0┆┆b0┆┆a1┆┆b0┆┆a1┆1. INTRODUCTION.↲
↲
┆84┆This technical manual describes the CPU610X (CPU610A ↓
┆19┆┆89┆┄┄6MHz and CPU610B 8MHz).↲
┆84┆↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆2. GENERAL DESCRIPTION OF CPU610X.↲
↲
┆84┆┆84┆The CPU610X contains:↲
↲
1. INTEL's i APX 80286 Microprocessor.↲
↲
2. MULTIBUS interface.↲
↲
3. ┆84┆iLBX bus interface, the CPU610X acts as a primary ↓
┆19┆┆8c┆┄┄master.↲
↲
4. One iSBX bus without DMA channel support.↲
↲
5. Consol interface. (V24/RS232C).↲
↲
6. Multidrop interface. (RS422A).↲
↲
7. ┆84┆Parallel printer interface. (Centronics and RC750 ↓
┆19┆┆8c┆┄┄Partner compatibel).↲
↲
8. ┆84┆Interface to the light emmiting print LED603 and the ↓
┆19┆┆8c┆┄┄Battery Backup control unit BBC601.↲
↲
9. ┆84┆Up to 64K bytes (2*32K bytes) EPROM in two standard ↓
┆19┆┆8c┆┄┄JEDEC sockets. 128 bytes (256*4 bit) bipolar PROM.↲
↲
10. ┆84┆A real time clock shows the time of day, day of month ↓
┆19┆┆8c┆┄┄and the day of the year.↲
↲
11. ┆84┆As an option the CPU610X can include a numeric ↓
┆19┆┆8c┆┄┄processor 80287 from INTEL.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆b0┆┆a1┆3. BLOCK DIAGRAM.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆a1┆4. FUNCTIONAL DESCRIPTION.↲
↲
┆a1┆┆b0┆┆f0┆┆e1┆ ┆84┆This chapter describes the use of the elements on the ↓
┆19┆┆89┆┆81┆┄CPU board.↲
↲
↲
┆b0┆┆a1┆4.1 On board CPU.↲
↲
┆b0┆┆a1┆┆f0┆┆e1┆ ┆84┆This part describes the processors on the CPU board. The ↓
┆19┆┆89┆┆81┆┄CPU board use INTEL's 80286 as the central processor. As ↓
┆19┆┆89┆┆81┆┄an option the CPU board includes interface to the 80287 ↓
┆19┆┆89┆┆81┆┄numeric processor. (See litt 1 for further details of ↓
┆19┆┆89┆┆81┆┄the processors).↲
┆b0┆┆a1┆┆f0┆┆e1┆↲
↲
┆a1┆┆b0┆4.1.1 80286 CPU.↲
↲
┆84┆The INTEL's 80286-6 (6 MHz for CPU610A) or 80286 (8 Hz ↓
┆19┆┆89┆┄┄for CPU610B) is the central processor on the CPU board. ↓
┆19┆┆89┆┄┄The microprocessor work in to different modes:↲
↲
1. The real address mode.↲
↲
2. The protected virtual address mode. (PVAM)↲
↲
┆84┆In mode nr 1 the processor addresses up to 1 Mbytes. In ↓
┆19┆┆89┆┄┄mode nr 2 it addr┆84┆ess up 16 Mbytes.↲
↲
┆84┆The processor makes use of an on-chip memory mangement ↓
┆19┆┆89┆┄┄in the protected virtual address mode↲
↲
┆84┆The CPU board begins in the real address mode. When the ↓
┆19┆┆89┆┄┄80286 makes a word Out instrution on I/O address 00CA to ↓
┆19┆┆89┆┄┄the first parallel port, it switches to protected mode. ↓
┆19┆┆89┆┄┄Then it is impossible to switch back to real address ↓
┆19┆┆89┆┄┄mode.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆4.1.2 Optional 80287 Numeric processor.↲
↲
┆84┆The CPU board can be expanded with a numeric processor ↓
┆19┆┆89┆┄┄INTEL's 80287 (8 MHz) or 80287-3 (5 MHz). The processor ↓
┆19┆┆89┆┄┄is used to floating point operation and other difficult ↓
┆19┆┆89┆┄┄numeric operations.↲
↲
┆84┆All interface to the numeric processor is on the CPU ↓
┆19┆┆89┆┄┄board.↲
↲
↲
┆f0┆┆a1┆┆b0┆┆a1┆┆b0┆┆a1┆4.2 I/O Interface.↲
┆b0┆┆a1┆↲
┆b0┆┆a1┆┆f0┆┆e1┆ ┆84┆The next part of chapter four describes the use of the ↓
┆19┆┆89┆┆81┆┄iAPX286 I/O address space.↲
↲
↲
┆b0┆┆a1┆4.2.1 I/O addressing on board.↲
┆b0┆┆a1┆↲
┆b0┆┆a1┆Device Data size I/O address ↲
↲
PAL012. (Interrupt out). Byte : Reset 0082↲
PAL012. (Interrupt out). Byte : Set 0086↲
TBP24S10. (Bipolar PROM). 4 bit 0086↲
RTC. (MM158167A/RTC58321) Byte/4 bit 008A↲
8259A-2 PIC. (Slave2). Byte: Status. 0094┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8259A-2 PIC. (Slave2). Byte: MASK. 0096┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8255A-5 PPI. (Parallel 2) Byte: Port A Out. 0098┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8255A-5 PPI. (Parallel 2) Byte: Port B In. 009A↲
8255A-5 PPI. (Parallel 2) Byte: Port C Out. 009C┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8255A-5 PPI. (Parallel 2) Byte: Control. 009E┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
iSBX bus. Byte/word 00A0-00BF┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8259A-2 PIC. (Master). Byte: Status. 00C0┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8259A-2 PIC. (Master). Byte: MASK. 00C2┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8259A-2 PIC. (Slave1). Byte: Status. 00C4┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8259A-2 PIC. (Slave1). Byte: MASK. 00C6┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆Device Data size I/O address ↲
↲
8255A-5 PPI. (Parallel 1) Byte: Port A Out. 00C8┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8255A-5 PPI. (Parallel 1) Byte: Port B In. 00CA↲
word: WR PVAM 00CA↲
8255A-5 PPI. (Parallel 1) Byte: Port C Out. 00CC┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8255A-5 PPI. (Parallel 1) Byte: Control. 00CE┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8254 PIT. (Timer). Byte: Counter 0 00D0┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8254 PIT. (Timer). Byte: Counter 1 00D2┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8254 PIT. (Timer). Byte: Counter 2 00D4┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8254 PIT. (Timer). Byte: Control. 00D6┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8274 MPSC. CH A. Byte: Data. 00D8┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8274 MPSC. CH B. Byte: Data. 00DA┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8274 MPSC. CH A. Byte: Control. 00DC┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
8274 MPSC. CH B. Byte: Control. 00DE┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
80287 Numric Processor. Word: RD status.↲
WR Opcode. 00F8↲
80287 Numric Processor. Word: Data. 00FA┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
80287 Numric Processor. Word: Address. 00FC┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
↲
┆b0┆ -------------------------------------------------------↲
↲
Fig 4.2.1 ┆84┆I/O addresses on the CPU board.↲
↲
┆b0┆┆a1┆Target Data size I/O address ↲
↲
MULIBUS byte/word 0000-007F↲
-"- -"- 0100-FFFF↲
↲
┆b0┆ -------------------------------------------------------↲
↲
Fig 4.2.2 ┆84┆I/O addresses from i APX 80286 to the ↓
┆19┆┆93┆┄┄MULTIBUS.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆Target Chip select Data size I/O address ↲
↲
iSBX bus /MCS0 byte 00A0-00AF↲
-"- /MCS1 byte 00B0-00BF↲
iSBX bus /MCS0 word 00A0-00A8↲
-"- /MCS1 word 00A0-00AF↲
↲
┆b0┆ -------------------------------------------------------↲
↲
Fig 4.2.3 ┆84┆I/O addresses from i APX 80286 to the iSBX ↓
┆19┆┆93┆┄┄bus.↲
↲
↲
┆b0┆┆a1┆4.2.2 Seriees ┆a1┆┆b0┆interface.↲
┆b0┆┆a1┆┆f0┆┆e1┆↲
┆84┆The CPU board has two seriees channels A and B. Channel A ↓
┆19┆┆89┆┄┄makes the connection to the multidrop RS422A line. ↓
┆19┆┆89┆┄┄Channel B takes care of the consol with RS232C ↓
┆19┆┆89┆┄┄interface.↲
┆84┆The INTEL's 8274 Multi-protocol Serial Controller (MPSC) ↓
┆19┆┆89┆┄┄takes care of most of the seriees communication. Two ↓
┆19┆┆89┆┄┄extra signals in channel B /DSRB (Data Set Ready) and ↓
┆19┆┆89┆┄┄/CIB (Calling Indicator) interface to the parallel port ↓
┆19┆┆89┆┄┄1.↲
↲
┆84┆The used signals in channel A are :↲
↲
┆b0┆ ┆84┆ ┆b0┆┆a1┆Signal Meaning ↲
↲
TXDA Transmitted Data↲
RXDA Received Data↲
/RTSA Request To Send↲
/CTSA Ready For Sending↲
/CDA Carrier On↲
-------------------------------↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆The used signals in channal B are :↲
↲
┆b0┆ ┆84┆ ┆b0┆┆a1┆Signal Meaning ↲
↲
TXDB Transmitted Data↲
RXDB Received Data↲
/RTSB Request To Send↲
/CTSB Ready For Sending↲
/DSRB Data Set Ready↲
/CDB Carrier On↲
/CIB Calling Indicator↲
-------------------------------↲
↲
↲
┆b0┆┆a1┆4.2.3 Parallel interface.↲
↲
┆84┆There are two parallel ports on the board. The INTEL's ↓
┆19┆┆89┆┄┄parallel port 8255A-5 is used in both cases. The port A ↓
┆19┆┆89┆┄┄and C are output ports and B is an input port.↲
┆84┆The first parallel port connect a printer to the CPU ↓
┆19┆┆89┆┄┄board. The printer interface must be a RC750 ("PARTNER") ↓
┆19┆┆89┆┄┄or Centronics compatible interface.↲
↲
┆84┆The next parallel port includes the addresses to the ↓
┆19┆┆89┆┄┄Real Time Clock, the bipolar PROM and some special ↓
┆19┆┆89┆┄┄signals. (See the list below).↲
┆b0┆┆a1┆┆f0┆┆e1┆↲
Signals from parallel port nr. 1↲
↲
┆a1┆┆b0┆Pin Signal ↲
↲
PA0 DATA 0 (Printer)↲
PA1 DATA 1 (Printer)↲
PA2 DATA 2 (Printer)↲
PA3 DATA 3 (Printer)↲
PA4 DATA 4 (Printer)↲
PA5 DATA 5 (Printer)↲
PA6 DATA 6 (Printer)↲
PA7 DATA 7 (Printer)↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Pin Signal ↲
↲
PB0 Not in use.↲
PB1 /CIB (Calling Indicator to consol)↲
PB2 /DSRB (Data Set Ready to consol)↲
PB3 BUSY (Printer)↲
PB4 /ACK (Printer)↲
PB5 /FAULT (Printer)↲
PB6 SELECTED (Printer)↲
PB7 PAPER END (Printer)↲
PC0 STROBE (Printer)↲
PC1 /SELECT (Printer)↲
PC2 /LPINIT┆84┆ (Printer)↲
PC3 /TIMEOUT INT (┆84┆Used to generate a timeout ↓
┆19┆┆a2┆┄┄interrupt).↲
PC4 /AUTOLF (Printer)↲
PC5 ┆84┆/LED2 (The light signal control a light ↓
┆19┆┆94┆┄┄emiting diode. It indicates when the CPU ↓
┆19┆┆94┆┄┄makes access to a disk).↲
PC6 ┆84┆SER LB (Used to loopback with the 8274 multi- ↓
┆19┆┆94┆┄┄protocol controller).↲
PC7 LPINT (┆84┆Used if /ACK is low to generate an ↓
┆19┆┆9b┆┄┄interrupt from the lineprinter).↲
↲
┆b0┆-------------------------------------------------------↲
↲
Signals from parallel port nr. 2↲
↲
┆a1┆┆b0┆Pin Signal ↲
↲
PA0 SLIOADR 0 (RTC and BPROM address)↲
PA1 SLIOADR 1 (RTC and BPROM address)↲
PA2 SLIOADR 2 (RTC and BPROM address)↲
PA3 SLIOADR 3 (RTC and BPROM address)↲
PA4 SLIOADR 4 (RTC and BPROM address)↲
PA5 SLIOADR 5 (RTC and BPROM address)↲
PA6 SLIOADR 6 (RTC and BPROM address)↲
PA7 SLIOADR 7 (RTC and BPROM address)↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆Pin Signal ↲
↲
PB0 ┆84┆/Testslave. (If two CPU is used, it indicates ↓
┆19┆┆94┆┄┄which is the test master). A testmaster is ↓
┆19┆┆94┆┄┄the multibus board which teststhe ↓
┆19┆┆94┆┄┄multibus.(See litt 7)).↲
PB1 If low there is only access to the Multibus.↲
PB2 Teststrap.↲
PB3 /PINTR2 unlock┆84┆ power interrupt from the batteri ↓
┆19┆┆94┆┄┄backup unit BBC601.↲
PB4 ┆84┆BBCINT a latched signal from the BBC601.↲
PB5 ┆84┆XOPT0 (An undefinite signal from the iSBX ↓
┆19┆┆94┆┄┄bus).↲
PB6 ┆84┆XOPT1 (An undefinite signal from the iSBX ↓
┆19┆┆94┆┄┄bus).↲
PB7 ┆84┆/XPST (If low an iSBX modul is on the CPU ↓
┆19┆┆94┆┄┄board).↲
PC0 ┆84┆/LED1 (The /LED1 signal control a light ↓
┆19┆┆94┆┄┄emiting diode which indicates when the CPU is ↓
┆19┆┆94┆┄┄in test mode).↲
PC1 ┆84┆PINT2EN (Enable a BBC601 interrupt from the ↓
┆19┆┆94┆┄┄BBC601).↲
PC2 ┆84┆/iLBX (When low it enables the iLBX bus; ↓
┆19┆┆94┆┄┄otherwise the CPU uses the MULTIBUS.↲
PC3 Not in use.↲
PC4 OPTO0 (An undefinite signal to the iSBX bus).↲
PC5 ┆84┆/OPT0EN (When low the it enables the signal ↓
┆19┆┆94┆┄┄OPT0 as an output signal to the iSBX bus).↲
PC6 OPTO0 (An undefinite signal to the iSBX bus).↲
PC7 ┆84┆/OPT1EN (When low the it enables the signal ↓
┆19┆┆94┆┄┄OPT1 as an output signal to the iSBX bus).↲
↲
┆b0┆-------------------------------------------------------↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆a1┆┆b0┆┆b0┆┆a1┆4.3 Clock Generator.↲
↲
┆84┆The CPU board uses an external clock generator 82284. ↓
┆19┆┆89┆┄┄(82284-6 on CPU610A and 82284-8 on CPU610B). The clock ↓
┆19┆┆89┆┄┄generator generates CPUCLK and a clock for the 8254 ↓
┆19┆┆89┆┄┄Programmable Interval Timer (PIT). ┆07┆The interval timer ↓
┆19┆┆89┆┄┄includes three programmable counters.↲
↲
┆84┆There is a 9,8405 MHz clock generator to the multibus. ↓
┆19┆┆89┆┄┄This clock is divided by two to generate a 4,9 Mhz clock ↓
┆19┆┆89┆┄┄signal. The 80287-3 numeric processor extension unit can ↓
┆19┆┆89┆┄┄run with this clock signal.↲
┆a1┆┆b0┆↲
↲
┆b0┆┆a1┆4.4 Interrupt operation.↲
↲
┆84┆The CPU610X includes three programable interrupt ↓
┆19┆┆89┆┄┄controllers (PIC's). The interrupt controllers take care ↓
┆19┆┆89┆┄┄of the interrupt input to the 80286. They are working in ↓
┆19┆┆89┆┄┄master slave relationship. The interrupt controllers ↓
┆19┆┆89┆┄┄make it possible to connect up to 22 interrupts to the ↓
┆19┆┆89┆┄┄80286. (Futher details are included in litt 6).↲
┆84┆The 80286 is able to generate up to three independent ↓
┆19┆┆89┆┄┄multibus interrupts. A PAL takes care of the interrupt ↓
┆19┆┆89┆┄┄output control.↲
↲
↲
┆a1┆┆b0┆4.4.1 Interrupt Source.↲
↲
┆84┆The priority of the input interrupts are showed in fig ↓
┆19┆┆89┆┄┄4.4.1.1. It is possible to change priority, but then the ↓
┆19┆┆89┆┄┄wiring must be modificated.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆Interrupt nr. Signal Source Destination. ↲
↲
NMI PINTR1/2 Key/BBC601 CPU80286↲
0 COUNT 0 Interval timer Master PIC IR 0↲
1 MBINT 1 Multibus Master PIC IR 1↲
2 MBINT 2 Multibus Master PIC IR 2↲
3 MBINT 3 Multibus Master PIC IR 3↲
4 MBINT 4 Multibus Master PIC IR 4↲
5 MBINT 5 Multibus Master PIC IR 5↲
6 SERINT Serial I/O Master PIC IR 6↲
7 SLINT1 Slave1 PIC Master PIC IR 7↲
8 MBINT 6 Multibus Slave1 PIC IR 0↲
9 MBINT 7 Multibus Slave1 PIC IR 1↲
10 TMOUTINT Time out Slave1 PIC IR 2↲
11 XINT 0 iSBX bus Slave1 PIC IR 3↲
12 XINT 1 iSBX bus Slave1 PIC IR 4↲
13 MBINT 0 Multibus Slave1 PIC IR 5↲
14 LPINT Line printer Slave1 PIC IR 6↲
15 SLINT2 Slave2 PIC Slave1 PIC IR 7↲
16 MBINT 8 Multibus Slave2 PIC IR 0↲
17 MBINT 9 Multibus Slave2 PIC IR 1↲
18 MBINT 10 Multibus Slave2 PIC IR 2↲
19 MBINT 11 Multibus Slave2 PIC IR 3↲
20 MBINT 12 Multibus Slave2 PIC IR 4↲
21 MBINT 13 Multibus Slave2 PIC IR 5↲
22 MBINT 14 Multibus Slave2 PIC IR 6↲
23 MBINT 15 Multibus Slave2 PIC IR 7↲
↲
┆b0┆ --------------------------------------------------------↲
↲
┆84┆Fig 4.4.1.1 Standard interrupts on the board. The ↓
┆19┆┆89┆┄┄priority is from top to down. The NMI is a non mask able ↓
┆19┆┆89┆┄┄interrupt which occurs when mains is low or from the ↓
┆19┆┆89┆┄┄front key.↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆It is possible to send eight extra multibus interrupts ↓
┆19┆┆89┆┄┄to the CPU from the multibus. (MBINT 8 - MBINT 15). An ↓
┆19┆┆89┆┄┄I/O write with the following format interrupts the CPU.↲
┆f0┆┆e1┆┆a1┆┆b0┆↲
┆84┆Format of an I/O write extended multibus interrupt ↓
┆19┆┆89┆┄┄instruction to the CPU :↲
↲
┆b0┆┆a1┆┆84┆┆f0┆┆e1┆ ┆b0┆┆a1┆MULTIBUS I/O address Destination. ↲
┆b0┆┆a1┆┆f0┆↲
0900 Testmaster CPU610X↲
0908 Testslave CPU610X↲
↲
┆b0┆┆b0┆-----------------------------------------↲
↲
┆b0┆┆a1┆┆84┆MULTIBUS Data field Destination. ↲
┆b0┆┆a1┆┆f0┆┆e1┆↲
00FF MBINT 8 (Reset)↲
00EF MBINT 8 (Set)↲
↲
00DF MBINT 9 (Reset)↲
00CF MBINT 9 (Set)↲
↲
00BF MBINT 10 (Reset)↲
00AF MBINT 10 (Set)↲
↲
009F MBINT 11 (Reset)↲
008F MBINT 11 (Set)↲
↲
007F MBINT 12 (Reset)↲
006F MBINT 12 (Set)↲
↲
005F MBINT 13 (Reset)↲
004F MBINT 13 (Set)↲
↲
003F MBINT 14 (Reset)↲
002F MBINT 14 (Set)↲
↲
001F MBINT 15 (Reset)↲
000F MBINT 15 (Set)↲
↲
┆b0┆┆b0┆------------------------------------------↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.4.2 Interrupt Generator.↲
↲
┆84┆The CPU is able to set up to three independt multibus ↓
┆19┆┆89┆┄┄interrupts. (Jumpers make the connection). The CPU or ↓
┆19┆┆89┆┄┄another multibus master is able to reset these ↓
┆19┆┆89┆┄┄interrupts.↲
↲
┆84┆Format of an I/O write extended multibus interrupt reset ↓
┆19┆┆89┆┄┄instruction to the CPU :↲
↲
┆b0┆┆a1┆┆84┆MULTIBUS I/O address Destination. ↲
┆b0┆┆a1┆┆f0┆↲
0900 Testmaster CPU610X↲
0908 Testslave CPU610X↲
↲
┆b0┆┆b0┆-------------------------------------------↲
↲
┆b0┆┆a1┆┆84┆MULTIBUS Data field Destination.↲
┆b0┆┆a1┆┆f0┆┆e1┆↲
0009 /MBOUT1↲
000A /MBOUT2↲
000B /MBOUT3↲
↲
┆b0┆┆b0┆-------------------------------------↲
↲
┆84┆Format of an output interrupt reset or set instruction ↓
┆19┆┆89┆┄┄from the CPU :↲
↲
┆b0┆┆a1┆┆84┆CPU I/O address Destination. ↲
┆b0┆┆a1┆┆f0┆↲
0086 Reset MBOUTX *↲
0082 Set MBOUTX↲
↲
┆b0┆┆b0┆----------------------------------------↲
↲
┆84┆* The data field selects the MBOUTX signal. (X=1,2,3).↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆84┆CPU Data field Destination. ↲
┆b0┆┆a1┆┆f0┆┆e1┆↲
0009 /MBOUT1 ↲
000A /MBOUT2↲
000B /MBOUT3↲
↲
┆b0┆┆b0┆-------------------------------------↲
↲
↲
┆b0┆┆a1┆4.5 Software Reset and Power commands.↲
↲
┆84┆This part describes the software Reset and power down ↓
┆19┆┆89┆┄┄functions.↲
↲
↲
┆b0┆┆a1┆4.5.1 Software Reset.↲
↲
┆84┆An out instruction to I/O address 0082H with data equal ↓
┆19┆┆89┆┄┄zero reset the CPU and the multibus in 5ms.↲
↲
↲
┆b0┆┆a1┆4.5.2 Power Down Operation.↲
↲
┆84┆This part desribes the power sense and power swich ↓
┆19┆┆89┆┄┄function on the CPU board.↲
↲
┆84┆The non-maskable interrupt (NMI) in 80286 is used to ↓
┆19┆┆89┆┄┄indicate power down interrupts. There is two source to ↓
┆19┆┆89┆┄┄generate a power down interrupt. One is the front panel ↓
┆19┆┆89┆┄┄key and the secound is the optionel batteri backup unit ↓
┆19┆┆89┆┄┄BBC601.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆The key at the front panel generate a NMI interrupt ↓
┆19┆┆89┆┄┄(PINT1).↲
↲
┆84┆If the RC39 includes a batteri backup unit BBC(601) (An ↓
┆19┆┆89┆┄┄option), then the NMI interrupt input is connected to ↓
┆19┆┆89┆┄┄the BBC601 and is activated under main power fail. In ↓
┆19┆┆89┆┄┄this case it is posible to distinct it from the key ↓
┆19┆┆89┆┄┄interrupt with an input instruction to PPI2 on address ↓
┆19┆┆89┆┄┄009AH. If data bit four is high then it is from BBC601 ↓
┆19┆┆89┆┄┄and the batteries is on else from the front key. If it ↓
┆19┆┆89┆┄┄is from the BBC601, then databit three indicates main ↓
┆19┆┆89┆┄┄power on or off (on when high).↲
↲
┆84┆The CPU610X power down when it make an output ↓
┆19┆┆89┆┄┄instruction to I/O address:↲
↲
009CH with data equal XXX8H↲
↲
↲
┆b0┆┆a1┆4.6 On board clock.↲
↲
┆84┆The CPU board includes a Real Time Clock (RTC) . The RTC ↓
┆19┆┆89┆┄┄IC is the MM158167 (National) (Fist source) or RTC58321 ↓
┆19┆┆89┆┄┄from Suwa Seikosha (second source). The two sources are ↓
┆19┆┆89┆┄┄not compatible. Special programming is necessary in each ↓
┆19┆┆89┆┄┄case. (See the manuals from the factory). The addresses ↓
┆19┆┆89┆┄┄to the RTC come from the second parallel port. The RTC ↓
┆19┆┆89┆┄┄is non sensitive to power fails. The CPU board gives ↓
┆19┆┆89┆┄┄battery backup for at least nine years. In a month the ↓
┆19┆┆89┆┄┄first source will differ at the most 0.2 sec and the ↓
┆19┆┆89┆┄┄second source 40 sec.↲
┆b0┆┆a1┆↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆4.7 Memory addressing.↲
┆b0┆┆a1┆↲
┆84┆The EPROMs are ┆81┆┆82┆the only onboard memories. (The bipolar ↓
┆19┆┆89┆┄┄PROM is in I/O addressing space). Fig 4.7.1-2 shows the ↓
┆19┆┆89┆┄┄total memory address map of the CPU board in real and ↓
┆19┆┆89┆┄┄protected virtual address mode. ┆b0┆┆a1┆↲
↲
┆b0┆┆a1┆Target memory size Real address space↲
↲
EPROM (UV) 64 K bytes 0F0000-0FFFFF↲
MULTIBUS 66 K bytes 0E0000-0EFFFF↲
iLBX bus 896 K bytes 000000-0DFFFF↲
┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
┆b0┆ -------------------------------------------------------↲
↲
Fig 4.7.1 ┆84┆The Memory Map of the CPU in Real Address ↓
┆19┆┆93┆┄┄Mode.↲
┆b0┆┆a1┆┆f0┆┆e1┆ ┆b0┆┆a1┆Target memory size Real address space↲
↲
EPROM (UV) 64 K bytes FF0000-FFFFFF↲
MULTIBUS 8128 K bytes 800000-FEFFFF↲
iLBX bus 8192 K bytes 000000-7FFFFF↲
┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆┆e1┆┆f0┆↲
┆b0┆ -------------------------------------------------------↲
↲
Fig 4.7.2 ┆84┆The Memory Map of the CPU in Protected Virtual ↓
┆19┆┆93┆┄┄Address Mode (PVAM).↲
↲
↲
┆b0┆┆a1┆┆81┆┆b0┆┆a1┆4.7.1 On board EPROM.↲
↲
┆84┆The CPU board contains two 28 pins JEDEC sockes to the ↓
┆19┆┆89┆┄┄EROM (UV erasable). In each socket it is possible to ↓
┆19┆┆89┆┄┄mount IC's of the types : 2732 (4k), 2764 (8k), 27128 ↓
┆19┆┆89┆┄┄(16k) and 27256 (32k). A jumper must be insert when the ↓
┆19┆┆89┆┄┄27256 is in use. (All the EPROM's must be 27XXX, ↓
════════════════════════════════════════════════════════════════════════
↓
┆19┆┆89┆┄┄27XXX-2, 27XXX-2.5 0V 27XXX-3. The EPROM's have to be ↓
┆19┆┆89┆┄┄addressed in the top of the memory adressing space. (See ↓
┆19┆┆89┆┄┄the addressing map below).↲
┆b0┆┆a1┆↲
EPROM's address map :↲
↲
┆b0┆┆a1┆Type memory size Real address space PVAM space┆b0┆┆a1┆ ↲
↲
2764 16 K bytes 0FC000-0FFFFF FFC000-FFFFFF↲
┆e1┆┆f0┆ 27128 32 K bytes 0F8000-0FFFFF FF8000-FFFFFF↲
┆b0┆┆a1┆┆f0┆┆e1┆ 27256 64 K bytes 0F0000-0FFFFF FF0000-FFFFFF↲
↲
┆b0┆ -------------------------------------------------------↲
↲
↲
┆b0┆┆a1┆┆b0┆┆a1┆4.8 Bus Interface.↲
↲
┆84┆The next part shows the uses of busses. All the busses ↓
┆19┆┆89┆┄┄are INTEL compatible. (See lit 2,3 and 4 for further ↓
┆19┆┆89┆┄┄information.).↲
↲
The CPU board use three busses:↲
↲
1. MULTIBUS.↲
↲
2. iLBX bus.↲
↲
3. iSBX bus.↲
↲
↲
┆a1┆┆b0┆4.8.1 MULTIBUS.↲
↲
┆84┆The interface to the MULTIBUS makes use of:↲
↲
1. ┆84┆One 8289 Bus Arbiter and a PAL.↲
↲
2. One bus controller 82288.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆4.8.2 iLBX bus.↲
↲
┆84┆The iLBX bus is a very fast memory bus. The iLBX bus ↓
┆19┆┆89┆┄┄interfaces to the CPU board with use of standard TTL ↓
┆19┆┆89┆┄┄IC's and PAL'S. The CPU board always acts as a primary ↓
┆19┆┆89┆┄┄master on the iLBX bus. It is possible to disconnect the ↓
┆19┆┆89┆┄┄iLBX bus when the PC2 bit in the second parallel port is ↓
┆19┆┆89┆┄┄high.↲
↲
↲
┆b0┆┆a1┆┆a1┆┆b0┆4.8.3 iSBX bus.↲
↲
┆84┆There is only one iSBX bus on the CPU board. There is no ↓
┆19┆┆89┆┄┄DMA support to the iSBX bus on the board. The iSBX bus ↓
┆19┆┆89┆┄┄interfaces to the CPU board with a 8255A-5 parallel port ↓
┆19┆┆89┆┄┄and with no extra latch or trancievers.↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5 TECHNICAL DESCRIPTION.↲
↲
┆84┆This chapter includes logic diagrams, PAL, PROM ↓
┆19┆┆89┆┄┄description and timming diagrams.↲
↲
↲
┆b0┆┆a1┆5.1 Logic Diagrams with Signal Descriptions.↲
↲
┆84┆This part includes the logic diagrams and signal ↓
┆19┆┆89┆┄┄descriptions. The notation of the signals is:↲
↲
A0, active ┆b0┆high┆f0┆ (2.4V - 5.25V)↲
/A0, active ┆b0┆low┆f0┆ (0V - 0.8V)↲
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
╱04002d4e0a0006000000000301413100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
↓
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
A0 - A2 3,5,15 A0-A17 is a 24 bit↲
A3 - A7 3,5,15,19 address bus. Bits (0-F)↲
A8 - AA 3,5,6,15,19 are used for both memory↲
AB - AF 3,5,15,19 and I/O addressing. Bits↲
A10 - A17 5,15,19 (10-17) are the 8 most↲
significiant memory↲
address bits.↲
↲
D0 - D7 3,5,11,15 16 bit bidirectionnal↲
D8 - DF 3,5,11,15,16 data bus.↲
↲
/BHE 4,18 ┆84┆Controls byte transfer ↓
┆19┆┆a9┆┄┄on data bus lines D8-DF.↲
↲
╞ /S0 2,4,14,21 CPU status line.↲
╞ /S1 2,4,14,18,21 CPU status line.↲
M(/IO) 1,4,14,19 CPU status line.↲
COD(/INTA) 1,2 CPU status line.↲
↲
/LOCK 14 ┆84┆Used to give the CPU ↓
┆19┆┆a9┆┄┄exclusive access to the ↓
┆19┆┆a9┆┄┄Multibus and the ↓
┆19┆┆a9┆┄┄iLBXbus.↲
↲
╞ /PEACK 2 ┆84┆Use to signals the ↓
┆19┆┆a9┆┄┄processor extension when ↓
┆19┆┆a9┆┄┄the requested operand is ↓
┆19┆┆a9┆┄┄being transferred.↲
↲
╞ HLDA 2,18 ┆84┆Used to pass control of ↓
┆19┆┆a9┆┄┄the iLBXbus to a ↓
┆19┆┆a9┆┄┄secondary master board.↲
↲
╞ INTR CYC╞ 4,19╞ ┆84┆Indicates an interrupt ↓
┆19┆┆a9┆┄┄cycle.↲
↲
╞ INTA/(/C)╞ 19╞ ┆84┆A status signal from the ↓
┆19┆┆a9┆┄┄80286.↲
↲
╞ BM/(/IO)╞ 1╞ ┆84┆A status signal from the ↓
┆19┆┆a9┆┄┄80286.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ /INIT 2 ┆84┆Reset the multibus and ↓
┆19┆┆a9┆┄┄the CPU board.↲
↲
80287RESET 2 Reset the 80287.↲
↲
RESET 1,2,4,8,12,16 Reset the CPU board.↲
╞ /RESET 7,9,12,13,14↲
17,18,20,21↲
↲
╞ CPUCLK 1,2,4,12,14 ┆84┆12MHz (CPU610A) or 16MHz ↓
┆19┆┆a9┆┄┄(CPU610B) clock with 50% ↓
┆19┆┆a9┆┄┄duty cycle.↲
╞ /CPUCLK 14,20,21↲
↲
PCLK 2,4,12,14 ┆84┆6MHz (CPU610A) or 8MHz ↓
┆19┆┆a9┆┄┄(CPU610B) clock with 50% ↓
┆19┆┆a9┆┄┄duty cycle.↲
↲
╞ MCLK 2,3,4,16 ┆84┆10MHz clock with 50% ↓
┆19┆┆a9┆┄┄duty cycle.↲
╞ /MCLK 3↲
↲
/READY 1,2,4,12,14 ┆84┆It indicates when the ↓
┆19┆┆a9┆┄┄current bus cycle is to ↓
┆19┆┆a9┆┄┄be completed.↲
↲
╞ 80287CLK 2 ┆84┆A clock signal to the ↓
┆19┆┆a9┆┄┄80287.↲
↲
PEREQ 1 ┆84┆It indicates when the ↓
┆19┆┆a9┆┄┄80287 is ready to ↓
┆19┆┆a9┆┄┄transfer data.↲
↲
/BUSY 1 ┆84┆80287 is currently ↓
┆19┆┆a9┆┄┄executing a command.↲
↲
/ERROR 1 ┆84┆An unmasked error ↓
┆19┆┆a9┆┄┄condition exists in ↓
┆19┆┆a9┆┄┄80287.↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ PUADR0 20,21 PUADR0-PUADRF is a 16↲
╞ PUADR1 2,6,7,8,9 bit address bus to both↲
10,11,12,13, memory and I/O.↲
14,20 Combinations of PUADR0↲
╞ PUADR2 2,6,7,8,9, and /BHE indicate byte↲
10,11,12,13, or word transfer.↲
14,20↲
╞ PUADR3 11,16,20↲
PUADR4 11,20↲
PUADR5-PUADRF 11↲
↲
╞ /BCLK 3,14 ┆84┆10MHz clock signal for ↓
┆19┆┆a9┆┄┄the 8289 bus arbiter and ↓
┆19┆┆a9┆┄┄the multibus.↲
↲
╞ /CCLK╞ 3 ┆84┆10MHz clock signal. ↓
┆19┆┆a9┆┄┄/CCLK is inverse to ↓
┆19┆┆a9┆┄┄/BCLK.↲
↲
╞ /MBIOWC 7 Multibus I/O write.↲
↲
╞ /MBACK╞ 20╞ Multibus acknowledge↲
↲
IODAT0-IODAT1╞ 2,6,7,8,9,10, 16 bit bidirectional↲
11,12,13,16,17 data bus for on board↲
╞ IODAT2-IODAT3╞ 2,6,8,9,10,11, devices. (Note that↲
╞ 12,13,16,17 the iSBXbus acts as an↲
╞ IODAT4-IODAT7 2,6,8,9,10,12 onboard device).↲
╞ ╞ 13,16,17↲
╞ IODAT7-IODATF 2,16↲
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ /LMRDC╞ 11,18╞ ┆84┆Local Memory Read ↓
┆19┆┆a9┆┄┄Command.(Note that the ↓
┆19┆┆a9┆┄┄iLBXbus acts as on board ↓
┆19┆┆a9┆┄┄memory).↲
╞ /LMWTC╞ 18╞ ┆84┆Local Memory Write ↓
┆19┆┆a9┆┄┄Command.↲
╞ /LIORD 2,6,8,9,10,11, Local I/O Read.↲
╞ ╞ 12,13,16,17,18↲
╞ LIORD ╞ 17↲
╞ /LIOWR 2,6,7,8,9,10, Local I/O Write.↲
╞ ╞ 11,12,13,16,↲
╞ ╞ 17,18↲
╞ /LINTA╞ 6,13,19,20 ┆84┆Local Interrupt ↓
┆19┆┆a9┆┄┄Acknowledge.↲
╞ OBDT/R╞ 3,5,21╞ ┆84┆Controls the direction ↓
┆19┆┆a9┆┄┄the data flow. If high ↓
┆19┆┆a9┆┄┄then a write cycle is ↓
┆19┆┆a9┆┄┄performed.↲
╞ LBXDEN╞ 19╞ ┆84┆Enables the data to the ↓
┆19┆┆a9┆┄┄iLBXbus.↲
╞ LMCE╞ 6 ┆84┆Enables cascade ↓
┆19┆┆a9┆┄┄addresses from the ↓
┆19┆┆a9┆┄┄master 8259A interrupt ↓
┆19┆┆a9┆┄┄controller to the CPU ↓
┆19┆┆a9┆┄┄address bus.↲
╞ /LALE╞ 3,4,12,14,19, Controls the address↲
21 latchs.↲
╞ LALE╞ 20↲
╞ /OBDEN╞ 3╞ ┆84┆Enables the onbard data ↓
┆19┆┆a9┆┄┄transeivers.↲
╞ MBINT0-MBINT7╞ 13╞ ┆84┆Interrupts from the ↓
┆19┆┆a9┆┄┄multibus.↲
╞ 5 MHz CLK╞ 2 ┆84┆50% duty cycle clock to ↓
┆19┆┆a9┆┄┄the 80287 in 5.0 MHz ↓
┆19┆┆a9┆┄┄version.↲
╞ SERCLK╞ 9 ┆84┆Is the CPUCLK divided by ↓
┆19┆┆a9┆┄┄four to the 8274 MPSC.↲
╞ TCLK╞ 10╞ ┆84┆1.25MHz 50% duty cycle ↓
┆19┆┆a9┆┄┄clock to baud rate ↓
┆19┆┆a9┆┄┄generation.↲
╞ /LBHE╞ 18,20,21 ┆84┆It controls the data ↓
┆19┆┆a9┆┄┄flow to the multibus on ↓
┆19┆┆a9┆┄┄the data lines D8-DF.↲
╞ LINTR CYC╞ 2,4 ┆84┆It indicates the current ↓
┆19┆┆a9┆┄┄bus cycle services a ↓
┆19┆┆a9┆┄┄local interrupt.↲
╞ /LBUS EN╞ 4╞ ┆84┆The current bus cycle is ↓
┆19┆┆a9┆┄┄a local I/O cycle↲
╞ MBREQ╞ 14,20 ┆84┆The current bus cycle is ↓
┆19┆┆a9┆┄┄a multibus cycle.↲
╞ SLCS╞ 20 ┆84┆Chip select signal to ↓
┆19┆┆a9┆┄┄the interrupt ↓
┆19┆┆a9┆┄┄controllers, the ↓
┆19┆┆a9┆┄┄interrupt outputs, the ↓
┆19┆┆a9┆┄┄RTC and the bipolar ↓
┆19┆┆a9┆┄┄PROM's.↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ AB0-AB23╞ 5╞ ┆84┆iLBXbus address ↓
┆19┆┆a9┆┄┄transeivers.↲
↲
╞ DB0-DB15 ╞ 5 ┆84┆iLBXbus data ↓
┆19┆┆a9┆┄┄transeivers.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ INTR╞ 1╞ ┆84┆Interrupt to 80286.↲
↲
╞ /MEN╞ 14 ┆84┆Master enables signal to ↓
┆19┆┆a9┆┄┄the data latch.↲
↲
╞ CAS 0-CAS 2 6,13,20 ┆84┆Used in the second ↓
┆19┆┆a9┆┄┄interrupt acknowledge ↓
┆19┆┆a9┆┄┄cycle to select a slave ↓
┆19┆┆a9┆┄┄interrrupt controller or ↓
┆19┆┆a9┆┄┄the 8274 MPSC.↲
↲
╞ A8,A9,AA╞ 1,3,15,19 ┆84┆Addresses on the local ↓
┆19┆┆a9┆┄┄address bus used to the ↓
┆19┆┆a9┆┄┄cascaded address.↲
↲
╞ SLINT1╞ 6╞ ┆84┆Interrupts to the master ↓
┆19┆┆a9┆┄┄interrupt controller.↲
↲
╞ /SLEN 1╞ 14╞ ┆84┆Used to enable the data ↓
┆19┆┆a9┆┄┄transeivers.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ /MBINTCS╞ 7 ┆84┆Opens the multibus ↓
┆19┆┆a9┆┄┄interrupt logic.↲
↲
╞ /SWRESET╞ 2╞ ┆84┆Resets the multibus and ↓
┆19┆┆a9┆┄┄the CPU board.↲
↲
╞ /MBOUT1-╞ 7╞ ┆84┆Generates a interrupt to↲
/MBOUT3 the multibus.↲
↲
╞ /PWDEN╞ 12╞ ┆84┆Enables the power down ↓
┆19┆┆a9┆┄┄signal from the PPI2↲
↲
╞ /XACK╞ 3,7 ╞ ┆84┆Acknowledges from a ↓
┆19┆┆a9┆┄┄device on the multibus.↲
↲
╞ MBINT8-MBINT15╞ 13 ┆84┆Extended multibus ↓
┆19┆┆a9┆┄┄interrupts. It is set or ↓
┆19┆┆a9┆┄┄reset from another ↓
┆19┆┆a9┆┄┄multibus master.↲
↲
╞ /INT0-/INT7╞ 4,7╞ ┆84┆Multibus interrupt lines↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ DATA0-DATA7╞ 8╞ ┆84┆Data lines to the ↓
┆19┆┆a9┆┄┄centronics parallel ↓
┆19┆┆a9┆┄┄printer.↲
↲
╞ /STROBE╞ 8╞ Data strobe signal.↲
↲
╞ /LPINIT╞ 8╞ Lineprinter reset.↲
↲
╞ /AUTOLF╞ 8╞ Auto line feed.↲
↲
╞ /LED2╞ 8╞ ┆84┆Signal to the disk ↓
┆19┆┆a9┆┄┄access indication led.↲
↲
╞ SERLB╞ 11╞ ┆84┆Used in test mode to ↓
┆19┆┆a9┆┄┄loopback in the RS422A ↓
┆19┆┆a9┆┄┄interface.↲
↲
╞ LPINT╞ 13╞ ┆84┆Lineprinter interrupt.↲
↲
╞ KEYINT╞ 8╞ ┆84┆Interrupt from the front ↓
┆19┆┆a9┆┄┄key.↲
↲
╞ TIME OUT INT╞ 13╞ ┆84┆Timeout interrupt.↲
↲
╞ NMI╞ 1╞ Non Maskable Interrupt.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ SERINT╞ 13╞ ┆84┆Interrupts from the 8274 ↓
┆19┆┆a9┆┄┄MPSC.↲
↲
╞ TxDALOOP╞ 11╞ ┆84┆Transmits data. (Channel ↓
┆19┆┆a9┆┄┄A).↲
↲
╞ /RTSA╞ 10╞ ┆84┆Request To Send (Channel ↓
┆19┆┆a9┆┄┄A).↲
↲
╞ /DTRA╞ 10╞ ┆84┆Data Terminal Ready ↓
┆19┆┆a9┆┄┄(Channel a).↲
↲
╞ TxDB╞ 9╞ ┆84┆Transmit Data (Channel ↓
┆19┆┆a9┆┄┄B).↲
↲
╞ /RTSB╞ 9╞ ┆84┆Requests To Send ↓
┆19┆┆a9┆┄┄(Channel B).↲
↲
╞ /DTRB╞ 9╞ ┆84┆Data Terminal Ready ↓
┆19┆┆a9┆┄┄(Channel B).↲
↲
╞ RxDB╞ 9╞ ┆84┆Received Data ↓
┆19┆┆a9┆┄┄(ChannelB).↲
↲
╞ /CTSB╞ 9╞ ┆84┆Clear To Send ↓
┆19┆┆a9┆┄┄(ChannelB).↲
↲
╞ /DSRB╞ 8╞ ┆84┆Data Set Ready ↓
┆19┆┆a9┆┄┄(ChannelB).↲
↲
╞ /CDB╞ 9╞ ┆84┆Carrier Detect ↓
┆19┆┆a9┆┄┄(ChannelB).↲
↲
╞ /CIB╞ 8╞ ┆84┆Calling Indicator ↓
┆19┆┆a9┆┄┄(Channel B).↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ COUNT0╞ 13╞ ┆84┆Interrupt from timer.↲
↲
╞ BAUDA,BAUDB╞ 9╞ ┆84┆Baud rate clock signals ↓
┆19┆┆a9┆┄┄to channel A and B in ↓
┆19┆┆a9┆┄┄8274 MPSC.↲
↲
╞ RxDALOOP╞ 11╞ ┆84┆Receives data. (Channel ↓
┆19┆┆a9┆┄┄A).↲
↲
╞ TT╞ 11╞ Terminal Timing.↲
↲
╞ /CTSALOOP╞ 11╞ ┆84┆Clear To Send. (Channel ↓
┆19┆┆a9┆┄┄A).↲
↲
╞ /CDA╞ 9╞ ┆84┆Carrier Detect. (Channel ↓
┆19┆┆a9┆┄┄A).↲
↲
╞ /RTSALOOP╞ 10,11╞ ┆84┆Ready To Send. (Channel ↓
┆19┆┆a9┆┄┄A).↲
↲
╞ RD(A)╞ 10╞ ┆84┆Transmit data. (Channel ↓
┆19┆┆a9┆┄┄A).↲
╞ RD(B)╞ 10╞ Inverted signal.↲
↲
╞ RT(A)╞ 10╞ ┆84┆Transmit Timing. ↓
┆19┆┆a9┆┄┄(Channel A).↲
╞ RT(B)╞ 10╞ Inverted signal.↲
↲
╞ CS(A)╞ 10╞ ┆84┆Ready To Send. (Channel ↓
┆19┆┆a9┆┄┄A).↲
╞ CS(B)╞ 10╞ Inverted signal.↲
↲
╞ DM(A)╞ 10╞ ┆84┆Data Mode. (Channel A).↲
╞ DM(B)╞ 10 ╞ Inverted signal.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
D0 - D7 3,5,11,15 16 bit bidirectionnal↲
D8 - DF 3,5,11,15,16 data bus.↲
↲
IODAT0-IODAT1╞ 2,6,7,8,9,10, 16 bit bidirectional↲
11,12,13,16,17 data bus for on board↲
╞ IODAT2-IODAT3╞ 2,6,8,9,10,11, devices.↲
╞ 12,13,16,17↲
↲
╞ TxDA╞ 10╞ ┆84┆Transmits Data. (Channel ↓
┆19┆┆a9┆┄┄A).↲
↲
╞ RxDA╞ 9╞ ┆84┆Receives Data. (Channel ↓
┆19┆┆a9┆┄┄A).↲
↲
╞ /RxCA╞ 9╞ ┆84┆Receiver Clock. (Channel ↓
┆19┆┆a9┆┄┄A).↲
↲
╞ /CTSA╞ 9╞ ┆84┆Clear To Send. (Channel ↓
┆19┆┆a9┆┄┄A).↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆Description↲
↲
╞ SLIOADR0-╞ 11,17╞ Address bus↲
SLIOADR4 to address infreqently↲
used onboard components.↲
╞ SLIOADR5-╞ 11↲
╞ SLIOADR8↲
↲
╞ /LED1╞ 12╞ Signal to the test led.↲
↲
╞ PINT2EN╞ 8╞ ┆84┆Enables the key ↓
┆19┆┆a9┆┄┄interrupt.↲
↲
╞ /iLBX╞ 18,19╞ ┆84┆If low the iLBXbus is ↓
┆19┆┆a9┆┄┄selected to memory ↓
┆19┆┆a9┆┄┄transfers.↲
↲
╞ OPTO0╞ 16╞ ┆84┆Optional signal zero to ↓
┆19┆┆a9┆┄┄the iSBXbus.↲
↲
╞ /OPT0EN╞ 16╞ ┆84┆Enables signal OPT00 to ↓
┆19┆┆a9┆┄┄the iSBXbus.↲
↲
╞ OPT10╞ 16╞ ┆84┆Optional signal one to ↓
┆19┆┆a9┆┄┄the iSBXbus.↲
↲
╞ /OPT1EN╞ 16╞ ┆84┆Enables signal OPT10 to ↓
┆19┆┆a9┆┄┄the iSBXbus.↲
↲
╞ PDMD╞ 12╞ Power Down Demand.↲
↲
╞ TESTSLAVE╞ 3╞ ┆84┆If low the CPU board is ↓
┆19┆┆a9┆┄┄testslave.↲
↲
╞ /TESTSLAVE╞ 7↲
↲
╞ /PINTR2╞ 8╞ ┆84┆Un latched key ↓
┆19┆┆a9┆┄┄interrupt.↲
↲
╞ /CLTMOUT╞ 12╞ ┆84┆Clears the timeout ↓
┆19┆┆a9┆┄┄circuit.↲
↲
╞ /TMOUT╞ 8,20╞ Timeout signal.↲
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
↓
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ IRM0-IRM6╞ 6╞ ┆84┆Interrupts to the master ↓
┆19┆┆a9┆┄┄interrupt controller.↲
↲
╞ IRSL1 0-IRSL1 7╞ 6╞ ┆84┆Interrupts to the slave ↓
┆19┆┆a9┆┄┄one interrupt ↓
┆19┆┆a9┆┄┄controller.↲
↲
╞ IRSL2 0-IRSL2 7╞ 6╞ ┆84┆Interrupts to the slave ↓
┆19┆┆a9┆┄┄two interrupt ↓
┆19┆┆a9┆┄┄controller.↲
↲
╞ SLINT2╞ 6╞ ┆84┆Interrupt to the master ↓
┆19┆┆a9┆┄┄interrupt controller.↲
↲
╞ /SLEN2╞ 14╞ ┆84┆Enables the data ↓
┆19┆┆a9┆┄┄transeivers.↲
↲
╞ 2NDINTRCYC╞ 20╞ Indicates the second↲
/2NDINTRCYC 13 interrupt acknowledge↲
cycle.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ /DELBUSAEN╞ 20╞ ┆84┆Used to delay the BUSAEN ↓
┆19┆┆a9┆┄┄signal.↲
↲
╞ BUSAEN╞ 14╞ Multibus address enable↲
/BUSAEN 14,15,20 signal.↲
↲
╞ /LOCK╞ 14╞ ┆84┆Is used to extend mutual ↓
┆19┆┆a9┆┄┄exclusion to dualport ↓
┆19┆┆a9┆┄┄RAM's on the multibus.↲
↲
╞ OBLOCK╞ 18╞ It indicates that the↲
/OBLOCK╞ 14 CPU lock dualport RAM's↲
on the iLBXbus↲
↲
╞ AEN╞ 14╞ ┆84┆Enables the addrress ↓
┆19┆┆a9┆┄┄lines on the multibus.↲
↲
╞ /BPRO╞ 14╞ ┆84┆Used in applications ↓
┆19┆┆a9┆┄┄with seriel priority in ↓
┆19┆┆a9┆┄┄the arbitration phase on ↓
┆19┆┆a9┆┄┄the multibus.↲
↲
╞ /BREQ╞ 14 ╞ Multibus request.↲
↲
╞ /BUSY╞ 14╞ ┆84┆Used when a master use ↓
┆19┆┆a9┆┄┄the multibus to a data ↓
┆19┆┆a9┆┄┄transfer.↲
↲
╞ /CBRQ╞ 14╞ ┆84┆It instructs the arbiter ↓
┆19┆┆a9┆┄┄if there are any other ↓
┆19┆┆a9┆┄┄arbiters of lower ↓
┆19┆┆a9┆┄┄prority requesting the ↓
┆19┆┆a9┆┄┄use of the multibus.↲
↲
╞ /MBRDC╞ 14╞ ┆84┆Multibus memory reads ↓
┆19┆┆a9┆┄┄signal.↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
↓
↲
┆8c┆┄┆88┆↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ /MBWTC╞ 14╞ ┆84┆Multibus memory writes ↓
┆19┆┆a9┆┄┄signal.↲
↲
╞ /MBIORC╞ 14╞ ┆84┆Multibus I/O reads ↓
┆19┆┆a9┆┄┄signal.↲
↲
╞ /MBIOWC╞ 14╞ ┆84┆Multibus I/O writes ↓
┆19┆┆a9┆┄┄signal.↲
↲
╞ /MBINTA╞ 14╞ ┆84┆Multibus Interrupt ↓
┆19┆┆a9┆┄┄Acknowledge.↲
↲
╞ MBDT(/R)╞ 15,16╞ ┆84┆┆84┆Indicates the direction ↓
┆19┆┆a9┆┄┄of the data flow on the ↓
┆19┆┆a9┆┄┄multibus.↲
↲
╞ MBALE╞ 15╞ ┆84┆Latch the addresses to ↓
┆19┆┆a9┆┄┄the multibus.↲
↲
╞ /INTEN╞ 4,20╞ ┆84┆Enables the interrupt ↓
┆19┆┆a9┆┄┄vetors to the I/O data ↓
┆19┆┆a9┆┄┄bus.↲
↲
╞ MBDEN╞ 21╞ ┆84┆Enables the data ↓
┆19┆┆a9┆┄┄transeivers to the ↓
┆19┆┆a9┆┄┄multibus.↲
↲
╞ /DAT0-/DAT1╞ 7,15,16╞ Data signals on the↲
/DAT2-/DAT3 15,16 multibus.↲
╞ /DAT4-/DAT7 7,15,16↲
╞ /DAT8-/DATF╞ 15↲
↲
╞ /ADR0-/ADR2╞ 15╞ Address signals on the↲
╞ /ADR3╞ 7,15 multibus.↲
╞ /ADR4-/ADR5╞ 15↲
╞ /ADR6-/ADRF╞ 7,15↲
╞ /ADR10-ADR23╞ 15↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
↓
↲
════════════════════════════════════════════════════════════════════════
↓
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↓
↲
╞ MD0-MDF╞ 16╞ ┆84┆iSBXbus bidirectional ↓
┆19┆┆a9┆┄┄data lines.↲
↲
╞ MA0-MA2╞ 16╞ ┆84┆iSBXbus address lines.↲
↲
╞ RESET╞ 16╞ Reset to the iSBXbus.↲
↲
╞ MCLK╞ 16╞ ┆84┆10 MHz 50% duty cycle ↓
┆19┆┆a9┆┄┄clock to the iSBXbus.↲
↲
╞ /IORD╞ 16╞ ┆84┆I/O read to the iSBXbus.↲
↲
╞ /IOWRT╞ 16╞ ┆84┆I/O write to the ↓
┆19┆┆a9┆┄┄iSBXbus.↲
↲
╞ /MCS0-/MCS1 16╞ ┆84┆Chip select lines to the ↓
┆19┆┆a9┆┄┄iSBXbus.↲
↲
╞ OPT0-OPT1╞ 12╞ ┆84┆Optional lines to or ↓
┆19┆┆a9┆┄┄from the iSBXbus.↲
↲
╞ /XPST╞ 12,19╞ ┆84┆Indicates that an iSBX ↓
┆19┆┆a9┆┄┄board is present.↲
↲
╞ XINT0-XINT1╞ 13╞ ┆84┆Interrupts from the iSBX ↓
┆19┆┆a9┆┄┄board.↲
↲
╞ /XWAIT╞ 20╞ ┆84┆Used to indicates that ↓
┆19┆┆a9┆┄┄the iSBX board is busy.↲
↲
╞ /DAT0-/DAT1╞ 7,15,16╞ Data signals on the↲
/DAT2-/DAT3 15,16 multibus.↲
╞ /DAT4-/DAT7 7,15,16↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
IODAT0-IODAT1╞ 2,6,7,8,9,10, 16 bit bidirectional↲
11,12,13,16,17 data bus for on board↲
╞ IODAT2-IODAT3╞ 2,6,8,9,10,11, devices.↲
╞ 12,13,16,17↲
╞ IODAT4-IODAT7 2,6,8,9,10,12↲
╞ ╞ 13,16,17↲
↲
╞ /RTCBUSY1╞ 20╞ Used when the RTC is↲
/RTCBUSY2 20 busy.↲
↲
╞ VBBU╞ 17╞ ┆84┆Power to the RTCs from ↓
┆19┆┆a9┆┄┄the battery.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ RTCAWR╞ 17,18╞ ┆84┆This signal is used to ↓
┆19┆┆a9┆┄┄transfer an address to ↓
┆19┆┆a9┆┄┄the secound source RTC.↲
↲
╞ RTCDWR╞ 17 ╞ ┆84┆This signal is used to ↓
┆19┆┆a9┆┄┄transfer data to the ↓
┆19┆┆a9┆┄┄secound source RTC.↲
↲
╞ UAEN╞ 19╞ ┆84┆This bit is set when the ↓
┆19┆┆a9┆┄┄80286 switch to ↓
┆19┆┆a9┆┄┄protected virtual ↓
┆19┆┆a9┆┄┄address mode.↲
↲
╞ /ASTB╞ 19╞ iLBXbus address strobe.↲
↲
╞ BHEN╞ 19╞ ┆84┆This signal together ↓
┆19┆┆a9┆┄┄with address line AB0 ↓
┆19┆┆a9┆┄┄indicates when the data ↓
┆19┆┆a9┆┄┄transport on the iLBXbus ↓
┆19┆┆a9┆┄┄is a byte transfer (Low ↓
┆19┆┆a9┆┄┄byte or high byte) or a ↓
┆19┆┆a9┆┄┄word transfer.↲
↲
╞ R(/W)╞ 18╞ ┆84┆If high the CPU board ↓
┆19┆┆a9┆┄┄read from the iLBXbus ↓
┆19┆┆a9┆┄┄otherwise it write from ↓
┆19┆┆a9┆┄┄the bus.↲
↲
╞ /LOCK╞ 18╞ ┆84┆Is used to extend mutual ↓
┆19┆┆a9┆┄┄exclusion to dualport ↓
┆19┆┆a9┆┄┄RAM's on the iLBXbus.↲
↲
╞ /DSTB╞ 18 ╞ ┆84┆Data strobe to the ↓
┆19┆┆a9┆┄┄iLBXbus.↲
↲
╞ SMACK╞ 5╞ ┆84┆Secondary Master ↓
┆19┆┆a9┆┄┄Acknowledge. It gives a ↓
┆19┆┆a9┆┄┄secondary master on the ↓
┆19┆┆a9┆┄┄iLBXbus the control of ↓
┆19┆┆a9┆┄┄the iLBXbus.↲
════════════════════════════════════════════════════════════════════════
↓
↲
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆Description↲
↲
╞ /EPROMCS╞ 11,20╞ ┆84┆Chip select to the ↓
┆19┆┆a9┆┄┄EPROM's.↲
↲
╞ /BVI╞ 19,20╞ ┆84┆Bus vector interrupt.↲
↲
╞ /EPCS╞ 19╞ ┆84┆Un latch chip select to ↓
┆19┆┆a9┆┄┄the EPROM's.↲
↲
╞ /iLBXCS╞ 19╞ ┆84┆Chip select to the ↓
┆19┆┆a9┆┄┄iLBXbus.↲
↲
╞ iLBXBUSEN╞ 20╞ Enable the iLBXbus.↲
↲
╞ /iLBXDEN╞ 5╞ ┆84┆iLBX data enable signal.↲
↲
╞ /IOACCESS╞ 4,19,20╞ ┆84┆The current cycle is an ↓
┆19┆┆a9┆┄┄I/O cycle.↲
↲
╞ SLREQ╞ 4 ┆84┆An unlatch chip select ↓
┆19┆┆a9┆┄┄signal to the↓
┆19┆┆a9┆┄┄interrupt outputs, the ↓
┆19┆┆a9┆┄┄RTC and the bipolar ↓
┆19┆┆a9┆┄┄PROM's.↲
↲
╞ /PICCS╞ 20╞ ┆84┆Chip select to the ↓
┆19┆┆a9┆┄┄interrupt controllers.↲
↲
╞ /PPICS╞ 20,21╞ ┆84┆Chip select to the ↓
┆19┆┆a9┆┄┄parallel ports.↲
↲
╞ /PITCS╞ 10╞ Timer chip select.↲
↲
╞ /SERCS╞ 9,21╞ ┆84┆8274 MPSC chip select.↲
↲
╞ /PECS╞ 2╞ 80287 chip select.↲
↲
╞ /SBXCS╞ 20╞ iSBX chip select.↲
↲
╞ /OBACCESS ╞ 4,14╞ ┆84┆Onboard access. (Note ↓
┆19┆┆a9┆┄┄that iLBX cycles is ↓
┆19┆┆a9┆┄┄onbord accesses).↲
↲
╞ ASTB╞ 18╞ ┆84┆Address strobe to the ↓
┆19┆┆a9┆┄┄iLBXbus.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ /PICS1-/PICS2╞ 6╞ ┆84┆Chip select to the ↓
┆19┆┆a9┆┄┄master and slave number ↓
┆19┆┆a9┆┄┄one interrupt ↓
┆19┆┆a9┆┄┄controllers.↲
↲
╞ /PICS3╞ 1╞ ┆84┆Chip select to slave ↓
┆19┆┆a9┆┄┄interrupt controller ↓
┆19┆┆a9┆┄┄number two.↲
↲
╞ /PPICS1╞ 8,18╞ ┆84┆Chip select to parallel ↓
┆19┆┆a9┆┄┄port one.↲
↲
╞ /PPICS2╞ 12 ╞ ┆84┆Chip select to parallel ↓
┆19┆┆a9┆┄┄port two.↲
↲
╞ /MCS0-/MCS1╞ 16╞ ┆84┆Chip selects to the ↓
┆19┆┆a9┆┄┄iSBXbus.↲
↲
╞ /INTOUTCS╞ 7╞ ┆84┆Chip select to multibus ↓
┆19┆┆a9┆┄┄interrupt generation.↲
↲
╞ RTCS╞ 17,18,20╞ Chip select to the↲
/RTCS 17 Real Time Clock.↲
↲
╞ /BPROMCS╞ 11╞ ┆84┆Bipolar PROM chip ↓
┆19┆┆a9┆┄┄select.↲
↲
╞ /SRDY╞ 2╞ Syncron Ready.↲
↲
╞ /DLYINTA╞ 9,20╞ ┆84┆Delays the interrupt ↓
┆19┆┆a9┆┄┄acknowledge to the 8274 ↓
┆19┆┆a9┆┄┄MPSC.↲
↲
╞ /IOWAIT╞ 20╞ ┆84┆Generates longer onboard ↓
┆19┆┆a9┆┄┄I/O cycles.↲
↲
╞ SEREN╞ 14,20╞ ┆84┆Enables the interrupt ↓
┆19┆┆a9┆┄┄vectors from the 8274 ↓
┆19┆┆a9┆┄┄MPSC to the local data ↓
┆19┆┆a9┆┄┄bus.↲
↲
╞ /TIMEOUT TRIG╞ 12╞ ┆84┆Initiates the timeout ↓
┆19┆┆a9┆┄┄logic.↲
↲
╞ /ASYNC RDY╞ 2╞ Asyncron Ready.↲
════════════════════════════════════════════════════════════════════════
↓
↲
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆ Signal┆e1┆┆a1┆ ┆e1┆ ┆a1┆Destination┆e1┆ ┆a1┆┆e1┆ ┆a1┆Description↲
↲
╞ /MBSWAP╞ 16╞ ┆84┆Exchange data bytes ↓
┆19┆┆a9┆┄┄between the high and low ↓
┆19┆┆a9┆┄┄end of the data lines.↲
↲
╞ /BHEN╞ 21╞ ┆84┆This signal together ↓
┆19┆┆a9┆┄┄with address line /ADR0 ↓
┆19┆┆a9┆┄┄indicates when the data ↓
┆19┆┆a9┆┄┄transport on the ↓
┆19┆┆a9┆┄┄multibus is a byte ↓
┆19┆┆a9┆┄┄transfer (Low byte or ↓
┆19┆┆a9┆┄┄high byte) or a word ↓
┆19┆┆a9┆┄┄transfer.↲
↲
╞ /MBHEN╞ 15╞ ┆84┆Enables the high bytes ↓
┆19┆┆a9┆┄┄to the multibus.↲
↲
╞ /MBLEN╞ 15╞ ┆84┆Enables the low bytes to ↓
┆19┆┆a9┆┄┄the multibus.↲
↲
╞ /DLYCMD╞ 4,20╞ ┆84┆Delays the commands from ↓
┆19┆┆a9┆┄┄the local bus ↓
┆19┆┆a9┆┄┄controller.↲
↲
╞ /ARDYEN╞ 2╞ ┆84┆Enables the asyncron ↓
┆19┆┆a9┆┄┄ready.↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
↓
┆b0┆┆a1┆5.2 PAL and PROM Descriptions.↲
↲
PAL16L8 PAL DESIGN SPECIFICATIONS↲
PAT012 821228 AAJ↲
3-BIT ADFDRESSABLE LATCH↲
↲
/INIT /WRT /CS A6 A1 IODO IOD1 /CLR /MBDO GND↲
/MBD1 NC Q3 IQ3 Q2 IQ2 Q1 IQ1 /FO VCC↲
↲
IF(VCC) FO= WRT*CS*A6*/A1*/IOD1*/IODO↲
↲
IF(VCC) /Q1= INIT↲
+WRT*CS*A6*A1*/IOD1*IODO↲
+CLR*/MBD1*MBDO↲
+IQ1↲
↲
IF(VCC) /IQ1= WRT*CS*A6*/A1*/IOD1*IODO↲
+Q1↲
↲
IF(VCC) /Q2= INIT↲
+WRT*CS*A6*A1*IOD1*/IODO↲
+CLR*MBD1*/MBDO↲
+IQ2↲
↲
IF(VCC) /IQ2= WRT*CS*A6*/A1*IOD1*/IODO↲
+Q2↲
↲
IF(VCC) /Q3= INIT↲
+WRT*CS*A6*A1*IOD1*IODO↲
+CLR*MBD1*MBDO↲
+IQ3↲
↲
IF(VCC) /IQ3= WRT*CS*A6*/A1*IOD1*IODO↲
+Q3↲
↲
DESCRIPTION:↲
↲
THE CIRCUIT CONTAINS THREE SET-RESET LATCHES (Q1,Q2,Q3) AND↲
NON LATCHED OUTPUT (FO).↲
WRT*CS*A6*/A1 SETS THE LATCH (Q=1,IQ=0) SELECTED BY IOD1,IODO,↲
OR PULSES THE OUTPUT FO IF IODA1=IODO=0.↲
WRT*CS*A6*A1 RESETS THE LATCH (Q=0,IQ=1) SELECTED BY IOD1,IODO↲
CLR RESETS THE LATCH SELECTED BY MBD1,MBDO.↲
INIT RESETS ALL LATCHES.↲
↲
════════════════════════════════════════════════════════════════════════
↓
************** **************↲
* * * *↲
**** ****↲
/INIT * 1* *20* VCC↲
**** ****↲
* *↲
**** ****↲
/WRT * 2* *19* /FO↲
**** ****↲
* *↲
**** ****↲
/CS * 3* *18* IQ1↲
**** ****↲
* *↲
**** ****↲
A6 * 4* *17* Q1↲
**** ****↲
* *↲
**** ****↲
A1 * 5* *16* IQ2↲
**** ****↲
* *↲
**** ****↲
IODO * 6* *15* Q2↲
**** ****↲
* *↲
**** ****↲
IOD1 * 7* *14* IQ3↲
**** ****↲
* *↲
**** ****↲
/CLR * 8* *13* Q3↲
**** ****↲
* *↲
**** ****↲
/MBDO * 9* *12* NC↲
**** ****↲
* *↲
**** ****↲
GND *10* *11* /MBD1↲
**** ****↲
* *↲
*******************************↲
↲
════════════════════════════════════════════════════════════════════════
↓
PAL16R6A PAL DESIGN SPECIFICATIONS↲
PAT069 841022 HEP↲
CPU610 82289 EMULATOR.↲
↲
/CPUCLK LALE /READY /RESET MBREQ /BLOCK NC VCC VCC GND↲
GND NC /Q0 /Q1 AENOUT NC /S0S1S2 CCLK /DLOCK VCC↲
↲
Q0:=READY*/RESET↲
↲
Q1:=Q0*/RESET↲
↲
S0S1S2:= /Q0*MBREQ*/RESET↲
↲
/AENOUT:= /S0S1S2*/MBREQ↲
+Q0↲
↲
/CCLK:=Q1*/RESET↲
↲
IF (VCC) DLOCK= BLOCK↲
↲
DESCRIPTION:↲
↲
PAT069 AND 8289 EMULATES AN 82289 BUS ARBITER. (CHECKSUM= 01E0).↲
════════════════════════════════════════════════════════════════════════
↓
↲
************** **************↲
* * * *↲
**** ****↲
/CPUCLK * 1* *20* VCC↲
**** ****↲
* *↲
**** ****↲
LALE * 2* *19* /DLOCK↲
**** ****↲
* *↲
**** ****↲
/READY * 3* *18* CCLK↲
**** ****↲
* *↲
**** ****↲
/RESET * 4* *17* /S0S1S2↲
**** ****↲
* *↲
**** ****↲
MBREQ * 5* *16* NC↲
**** ****↲
* *↲
**** ****↲
/BLOCK * 6* *15* AENOUT↲
**** ****↲
* *↲
**** ****↲
NC * 7* *14* /Q1↲
**** ****↲
* *↲
**** ****↲
VCC * 8* *13* /Q0↲
**** ****↲
* *↲
**** ****↲
VCC * 9* *12* NC↲
**** ****↲
* *↲
**** ****↲
GND *10* *11* GND↲
**** ****↲
* *↲
*******************************↲
════════════════════════════════════════════════════════════════════════
↓
PAT070 841023 HEP↲
CPU610 MEMORY ADDRESS DECODER.↲
↲
A10 A11 A12 A13 A14 A15 A16 A17 MIO GND↲
UAEN /EPCS /ILBX INTCY INTAC NC /BVI NC /ILBXCS VCC↲
↲
IF(VCC) ILBXCS= ILBX*MIO*/UAEN*/A13 ; REAL ADDRESS MODE.↲
+ILBX*MIO*/UAEN*/A12 ; REAL ADDRESS MODE.↲
+ILBX*MIO*/UAEN*/A11 ; REAL ADDRESS MODE.↲
+ILBX*MIO*UAEN*/A17 ; PVAM.↲
↲
IF(VCC) EPCS= MIO*/UAEN*A10*A11*A12*A13 ; REAL ADDRESS MODE.↲
+MIO*UAEN*A10*A11*A12*A13*A14*A15*A16*A17 ; PVAM.↲
↲
IF(VCC) BVI= INTCY ; BUS VECTOR INTERRUPT↲
↲
DESCRIPTION:↲
↲
PAT070 IS DECODES THE MEMORY ADDRESSES TO THE ILBX BUS AND THE↲
EPROM'S. FURTHER IT DECODES BUS VECTOR INTERRUPTS.↲
(CHECKSUM = 040C)↲
════════════════════════════════════════════════════════════════════════
↓
↲
************** **************↲
* * * *↲
**** ****↲
A10 * 1* *20* VCC↲
**** ****↲
* *↲
**** ****↲
A11 * 2* *19* /ILBXCS↲
**** ****↲
* *↲
**** ****↲
A12 * 3* *18* NC↲
**** ****↲
* *↲
**** ****↲
A13 * 4* *17* /BVI↲
**** ****↲
* *↲
**** ****↲
A14 * 5* *16* NC↲
**** ****↲
* *↲
**** ****↲
A15 * 6* *15* INTAC↲
**** ****↲
* *↲
**** ****↲
A16 * 7* *14* INTCY↲
**** ****↲
* *↲
**** ****↲
A17 * 8* *13* /ILBX↲
**** ****↲
* *↲
**** ****↲
MIO * 9* *12* /EPCS↲
**** ****↲
* *↲
**** ****↲
GND *10* *11* UAEN↲
**** ****↲
* *↲
*******************************↲
════════════════════════════════════════════════════════════════════════
↓
PAT071 841018 HEP↲
CPU610 FIRST I/O ADDRESS DECODER.↲
↲
LALE A A7 A3 A4 A5 A6 /XPST B GND↲
GND /IOA /PICCS /PPICS /PITCS /SERCS /PECS /SBXCS SLREQ VCC↲
↲
PICCS:= A*B*/A3*/A4*/A5*A6*A7 ; PIC 1 AND PIC 2↲
+A*B*/A3*A4*/A5*/A6*A7 ; PIC 3 (SLAVE 2)↲
↲
PPICS:= A*B*A3*/A4*/A5*A6*A7 ; PARALLEL PORT 1↲
+A*B*A3*A4*/A5*/A6*A7 ; PARALLEL PORT 2↲
↲
PITCS:= A*B*/A3*A4*/A5*A6*A7 ; INTERVAL TIMER↲
↲
SERCS:= A*B*A3*A4*/A5*A6*A7 ; SERIAL PORT↲
↲
PECS:= A*B*A3*A4*A5*A6*A7 ; NUMERIC PROCESSOR EXTENSION↲
↲
SBXCS:= XPST*A*B*A5*/A6*A7 ; ISBX BUS↲
↲
IF(VCC) IOA= A*B↲
↲
IF(VCC) SLREQ= /A ; RTC, BPROM AND INTERRUPT OUT↲
+/B ; CHIP SELECTION↲
+A4↲
+A5↲
+A6↲
+/A7↲
↲
DESCRIPTION:↲
↲
PAT071 INCLUDES THE FIRST I/O DECODING TO THE ONBOARD I/O PORTS.↲
↲
(CHECKSUM = 056F)↲
════════════════════════════════════════════════════════════════════════
↓
↲
************** **************↲
* * * *↲
**** ****↲
LALE * 1* *20* VCC↲
**** ****↲
* *↲
**** ****↲
A * 2* *19* SLREQ↲
**** ****↲
* *↲
**** ****↲
A7 * 3* *18* /SBXCS↲
**** ****↲
* *↲
**** ****↲
A3 * 4* *17* /PECS↲
**** ****↲
* *↲
**** ****↲
A4 * 5* *16* /SERCS↲
**** ****↲
* *↲
**** ****↲
A5 * 6* *15* /PITCS↲
**** ****↲
* *↲
**** ****↲
A6 * 7* *14* /PPICS↲
**** ****↲
* *↲
**** ****↲
/XPST * 8* *13* /PICCS↲
**** ****↲
* *↲
**** ****↲
B * 9* *12* /IOA↲
**** ****↲
* *↲
**** ****↲
GND *10* *11* GND↲
**** ****↲
* *↲
*******************************↲
════════════════════════════════════════════════════════════════════════
↓
PAT072 841023 HEP↲
CPU610 SECONDARY I/O ADDRESS DECODER.↲
↲
PUADR0 PUADR2 PUADR3 PUADR4 NC /LBHE /PICCS /PPICS SLCS GND↲
/SBXCS /PICCS1 /PICCS2 /PICCS3 /PPICS1 /PPICS2 /MCS0 /MCS1 ↓
/INTOUT VCC↲
↲
IF(VCC) PICCS1= PICCS*/PUADR4*/PUADR2 ; MASTER PIC↲
↲
IF(VCC) PICCS2= PICCS*/PUADR4*PUADR2 ; SLAVE 1 PIC↲
↲
IF(VCC) PICCS3= PICCS*PUADR4 ; SLAVE 2 PIC↲
↲
IF(VCC) PPICS1= PPICS*/PUADR4 ; PPI 1↲
↲
IF(VCC) PPICS2= PPICS*PUADR4 ; PPI 2↲
↲
IF(VCC) MCS0= SBXCS*LBHE*PUADR0*/PUADR4 ; ISBX BYTE↲
+SBXCS*/LBHE*/PUADR0*/PUADR4 ; -"-↲
+SBXCS*LBHE*/PUADR0*/PUADR3 ; ISBX WORD↲
↲
IF(VCC) MCS1= SBXCS*LBHE*PUADR0*PUADR4 ; ISBX BYTE↲
+SBXCS*/LBHE*/PUADR0*PUADR4 ; -"-↲
+SBXCS*LBHE*/PUADR0*PUADR3 ; ISBX WORD↲
↲
IF(VCC) INTOUT= SLCS*/PUADR3 ; INTERRUPT OUT↲
↲
DESCRIPTION:↲
↲
PAT072 INCLUDES THE FIRST I/O DECODING TO THE ONBOARD I/O PORTS.↲
(CHECKSUM = 087C)↲
════════════════════════════════════════════════════════════════════════
↓
↲
************** **************↲
* * * *↲
**** ****↲
PUADR0 * 1* *20* VCC↲
**** ****↲
* *↲
**** ****↲
PUADR2 * 2* *19* /INTOUT↲
**** ****↲
* *↲
**** ****↲
PUADR3 * 3* *18* /MCS1↲
**** ****↲
* *↲
**** ****↲
PUADR4 * 4* *17* /MCS0↲
**** ****↲
* *↲
**** ****↲
NC * 5* *16* /PPICS2↲
**** ****↲
* *↲
**** ****↲
/LBHE * 6* *15* /PPICS1↲
**** ****↲
* *↲
**** ****↲
/PICCS * 7* *14* /PICCS3↲
**** ****↲
* *↲
**** ****↲
/PPICS * 8* *13* /PICCS2↲
**** ****↲
* *↲
**** ****↲
SLCS * 9* *12* /PICCS1↲
**** ****↲
* *↲
**** ****↲
GND *10* *11* /SBXCS↲
**** ****↲
* *↲
*******************************↲
════════════════════════════════════════════════════════════════════════
↓
PAT073 841023 HEP↲
CPU610 WAIT STATE GENERATOR.↲
↲
/CPUCLK SEREN LINTR 2INTCY /INTEN /IOACC /EPROM /DLYCMD /LALE GND↲
GND /DEBUAE /LINTA /Q0 /Q1 /Q2 /IOMBWA /DLINTA /IOWAIT VCC↲
↲
Q0:= /LALE*/DLYCMD*/Q0 ; 3 BIT COUNTER↲
↲
Q1:= /LALE*/DLYCMD*/Q1*Q0↲
+/LALE*/DLYCMD*/Q0*Q1↲
↲
Q2:= /LALE*/DLYCMD*/Q2*Q1*Q0↲
+/LALE*/DLYCMD*/Q0*/Q1*Q2↲
+/LALE*/DLYCMD*Q0*/Q1*Q2↲
+/LALE*/DLYCMD*/Q0*Q1*Q2↲
↲
IOMBWA:= IOACC*/Q1 ; I/O (ONBOARD) AND↲
+DEBUAE ; MULTIBUS WAITSTATES↲
+/IOACC*/Q2 ; GENERATION↲
↲
IF(VCC) IOWAIT= LALE*EPROM ; FIRST EPROM WAITSTATE↲
+EPROM*/Q2 ; 2 EPROM WAITSTATES↲
+LALE*IOACC ; FIRST I/O WAITSTATE↲
+IOMBWA ; MULTIBUS AND I/O↲
+LALE*LINTR ; FIRST INTERRUPT ↓
WAITSTATE↲
+SEREN*2INTCY*/Q2 ; 8274 INTERRUPT ↓
WAITSTATE↲
↲
IF(VCC) DLINTA= SEREN*/2INTCY*LINTA ; DELAY OF INTERRUPT↲
+SEREN*2INTCY*LINTA ; ACKNOWLEDGE TO 8274↲
↲
DESCRIPTION:↲
↲
PAT073 IS A WAIT STATE GENERATOR. FURTHER IT DELAY THE INTA↲
SIGNAL TO THE 8274↲
(CHECKSUM = 06C6)↲
════════════════════════════════════════════════════════════════════════
↓
↲
************** **************↲
* * * *↲
**** ****↲
/CPUCLK * 1* *20* VCC↲
**** ****↲
* *↲
**** ****↲
SEREN * 2* *19* /IOWAIT↲
**** ****↲
* *↲
**** ****↲
LINTR * 3* *18* /DLINTA↲
**** ****↲
* *↲
**** ****↲
2INTCY * 4* *17* /IOMBWA↲
**** ****↲
* *↲
**** ****↲
/INTEN * 5* *16* /Q2↲
**** ****↲
* *↲
**** ****↲
/IOACC * 6* *15* /Q1↲
**** ****↲
* *↲
**** ****↲
/EPROM * 7* *14* /Q0↲
**** ****↲
* *↲
**** ****↲
/DLYCMD * 8* *13* /LINTA↲
**** ****↲
* *↲
**** ****↲
/LALE * 9* *12* /DEBUAE↲
**** ****↲
* *↲
**** ****↲
GND *10* *11* GND↲
**** ****↲
* *↲
*******************************↲
════════════════════════════════════════════════════════════════════════
↓
PAT074 841023 HEP↲
CPU610 ASYNCRON READY GENERATOR↲
↲
/IOWAIT /DLINTA LINTR BVI /RTCBSY /XWAIT /TMOUT /BUAEN LBXEN GND↲
MBREQ SEREN NC CAS0 CAS1 CAS2 /MBXACK /TMTRIG /ARDY VCC↲
↲
IF(VCC) ARDY= /XWAIT*/RTCBSY*/IOWAIT*/LBXEN*/MBREQ ; LOCAL OR ↓
ILBX↲
+MBXACK*MBREQ*BUAEN ; MULITIBUS↲
+TMOUT ; -"-↲
↲
IF(VCC) TMTRIG= /MBXACK*MBREQ*BUAEN ; MULTIBUS↲
+LBXEN ; ILBX BUS↲
+LINTR ; LOCAL INTR↲
+RTCBSY ; RTC↲
↲
IF(VCC) /SEREN= CAS0 ; SELECTION OF ↓
THE↲
+/CAS1 ; 8274 FROM ↓
THE MASTER↲
+/CAS2 ; PIC↲
↲
DESCRIPTION:↲
↲
PAT074 IS AN ASYNCRON READY GENERATOR. FURTHER IT INCLUDES ↓
CIRCUIT SELECTION AND SELECTION OF THE 8274 IN THE INTERUPT ↓
ACKNOWLEDGE PHASE.↲
(CHECKSUM = 0593)↲
════════════════════════════════════════════════════════════════════════
↓
************** **************↲
* * * *↲
**** ****↲
/IOWAIT * 1* *20* VCC↲
**** ****↲
* *↲
**** ****↲
/DLINTA * 2* *19* /ARDY↲
**** ****↲
* *↲
**** ****↲
LINTR * 3* *18* /TMTRIG↲
**** ****↲
* *↲
**** ****↲
BVI * 4* *17* /MBXACK↲
**** ****↲
* *↲
**** ****↲
/RTCBSY * 5* *16* CAS2↲
**** ****↲
* *↲
**** ****↲
/XWAIT * 6* *15* CAS1↲
**** ****↲
* *↲
**** ****↲
/TMOUT * 7* *14* CAS0↲
**** ****↲
* *↲
**** ****↲
/BUAEN * 8* *13* NC↲
**** ****↲
* *↲
**** ****↲
LBXEN * 9* *12* SEREN↲
**** ****↲
* *↲
**** ****↲
GND *10* *11* MBREQ↲
**** ****↲
* *↲
*******************************↲
↲
════════════════════════════════════════════════════════════════════════
↓
PAL16R6A PAL DESIGN SPECIFICATIONS↲
PAT075 841023 HEP↲
CPU610 COMMAND DELAY GENERATOR↲
↲
/CPUCLK /S0 /S1 OBDTR NC LALE /SERCS /RESET /CPUCLK GND↲
GND /PPICS /DTR /Q0 /DLYCMD /Q1 /Q2 /Q3 /ARDYEN VCC↲
↲
Q0:= /RESET*DLYCMD*/Q0 ; COMMAND DELAY COUNTER↲
↲
Q1:= /RESET*DLYCMD*/Q1*Q0 ; -"-↲
+/RESET*DLYCMD*/Q0*Q1↲
↲
Q2:= /RESET*DLYCMD*Q0*Q1*/Q2 ; -"-↲
+/RESET*DLYCMD*/Q0*/Q1*Q2↲
+/RESET*DLYCMD*Q0*/Q1*Q2↲
+/RESET*DLYCMD*/Q0*Q1*Q2↲
↲
Q3:= /RESET*DLYCMD*Q0*Q1*Q2*/Q3 ; -"-↲
+/RESET*DLYCMD*/Q0*/Q1*/Q2*Q3↲
+/RESET*DLYCMD*Q0*/Q1*/Q2*Q3↲
+/RESET*DLYCMD*/Q0*Q1*/Q2*Q3↲
+/RESET*DLYCMD*Q0*Q1*/Q2*Q3↲
+/RESET*DLYCMD*/Q0*/Q1*Q2*Q3↲
+/RESET*DLYCMD*Q0*/Q1*Q2*Q3↲
↲
/DTR:= /OBDTR*RESET ; WRITE I/O CYCLE↲
↲
DLYCMD:= /RESET*SERCS*/S0*S1*/LALE ; 8274 STATUS CYCLE↲
+/RESET*SERCS*S0*/S1*/LALE ; -"-↲
+/RESET*SERCS*/Q1*/Q2*/Q3*DLYCMD ; 8274 COMMAND DELAY↲
+/RESET*PPICS*/S0*S1*/LALE ; 8255 STATUS CYCLE↲
+/RESET*PPICS*S0*/S1*/LALE ; 8255 COMMAND DELAY↲
+/RESET*PPICS*/Q3*DLYCMD ; -"-↲
+/RESET*PPICS*/Q1*/Q2*Q3*DLYCMD ; -"-↲
↲
IF(VCC) ARDYEN= S0*S1 ; ENABLE THE ASYNCRON↲
+/S0*/S1 ; READY INPUT ON 82284↲
↲
DESCRIPTION:↲
↲
PAT075 IS A COMMAND DELAY GENERATOR. FURTHER IT INCLUDES A ENABLE ↓
SIGNAL ARDYEN FOR THE 82284 READY GENERATIONS CIRCUIT↲
(CHECKSUM = 06A6)↲
════════════════════════════════════════════════════════════════════════
↓
↲
************** **************↲
* * * *↲
**** ****↲
/CPUCLK * 1* *20* VCC↲
**** ****↲
* *↲
**** ****↲
/S0 * 2* *19* /ARDYEN↲
**** ****↲
* *↲
**** ****↲
/S1 * 3* *18* /Q3↲
**** ****↲
* *↲
**** ****↲
OBDTR * 4* *17* /Q2↲
**** ****↲
* *↲
**** ****↲
NC * 5* *16* /Q1↲
**** ****↲
* *↲
**** ****↲
LALE * 6* *15* /DLYCMD↲
**** ****↲
* *↲
**** ****↲
/SERCS * 7* *14* /Q0↲
**** ****↲
* *↲
**** ****↲
/RESET * 8* *13* /DTR↲
**** ****↲
* *↲
**** ****↲
/CPUCLK * 9* *12* /PPICS↲
**** ****↲
* *↲
**** ****↲
GND *10* *11* GND↲
**** ****↲
* *↲
*******************************↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
↓
┆b0┆┆a1┆LAR001↲
↲
┆84┆This bipolar PROM includes identity data. The format of ↓
┆19┆┆89┆┄┄the data :↲
↲
┆a1┆┆b0┆Address range information. ↲
↲
00H-0BH Indentiti nr↲
C9H-D4H Name in Ascii (LAR001)↲
D5H-E0H production date (Year/Month/Day in Ascii)↲
E5H-F0H PLS nr of the bipolar PROM 74S287 in Ascii↲
FCH-FFH checksum↲
↲
┆b0┆---------------------------------------------------↲
↲
════════════════════════════════════════════════════════════════════════
↓
;ROC416 CPU610 Multibus I/O address identification. 841121 HEP.↲
;↲
0000' ╞ ASEG╞ ╞ ; ↓
Prom start address↲
╞ ORG╞ 3DBH╞ ;↲
╞ ╞ ╞ ;↲
03DB F0 ╞ DB 0F0H ; select ↓
extended multibus interrupts.↲
03DC FFFF ╞ DW╞ 0FFFFH╞ ;↲
03DE FFFF ╞ DW╞ 0FFFFH╞ ;↲
03E0 FFFF ╞ DW╞ 0FFFFH╞ ;↲
03E2 FFFF ╞ DW╞ 0FFFFH╞ ;↲
03E4 FFFF ╞ DW╞ 0FFFFH╞ ;↲
03E6 FFFF ╞ DW╞ 0FFFFH╞ ;↲
03E8 FFFF ╞ DW╞ 0FFFFH╞ ;↲
03EA FFFF ╞ DW╞ 0FFFFH╞ ;↲
03EC FFFF ╞ DW╞ 0FFFFH╞ ;↲
03EE FFFF ╞ DW╞ 0FFFFH╞ ;↲
03F0 FFFF ╞ DW╞ 0FFFFH╞ ;↲
03F2 FFFF ╞ DW╞ 0FFFFH╞ ;↲
03F4 FFFF ╞ DW╞ 0FFFFH╞ ;↲
03F6 FFFF ╞ DW╞ 0FFFFH╞ ;↲
03F8 FFFF ╞ DW╞ 0FFFFH╞ ;↲
03FA FFFF ╞ DW╞ 0FFFFH╞ ;↲
03FC FFFF ╞ DW╞ 0FFFFH╞ ;↲
03FE FFFF ╞ DW╞ 0FFFFH╞ ;↲
;↲
╞ END↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆┆b0┆┆a1┆5.3 Timing Diagrams.↲
↲
╞ ┆84┆This part describes the behaviour of the signals in ↓
┆19┆┆89┆┄┄time. The dokumentation is from a logic analyzer model ↓
┆19┆┆89┆┄┄1630D from Hewelt Packard.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆5.3.1 First ROM access on CPU610B.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆5.3.2 8274 cycle on CPU610A.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆88┆┆b0┆┆a1┆5.3.3 RTC cycle CPU610A.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆5.3.4 Multibus cycle on CPU610B to MEM691.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆5.3.5 iLBXbus cycle CPU610B to MEM691.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5.4 Plugs.↲
↲
┆84┆This part descibes the plugs on CPU610X. The Multibus ↓
┆19┆┆8a┆┄┄(P1) and iLBX (P2) connectors is edge connectors. The ↓
┆19┆┆8a┆┄┄rest connectors is ITT CANNON G08 connectors.↲
↲
┆b0┆┆a1┆5.4.1 P1 Multibus Connector.↲
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a1a2a37414b555f69737d8791ffffff04╱
↓
↲
╞ ┆b0┆┆a1┆Pin╞ Signal╞ Pin╞ Signal. ↲
↲
╞ 1╞ GND╞ 2╞ GND↲
╞ 3╞ +5V╞ 4╞ +5V↲
╞ 5╞ +5V╞ 6╞ +5V↲
╞ 7╞ +12V╞ 8╞ +12V↲
╞ 9╞ Reserved╞ 10╞ Reserved↲
╞ 11╞ GND╞ 12╞ GND↲
╞ 13╞ /BCLK╞ 14╞ /INIT↲
╞ 15╞ /BPRN╞ 16╞ /BPRO↲
╞ 17╞ /BUSY╞ 18╞ /BREQ↲
╞ 19╞ /MRDC╞ 20╞ /MWTC↲
╞ 21╞ /IORC╞ 22╞ /IOWC↲
╞ 23╞ /XACK╞ 24╞ /INH1↲
╞ 25╞ /LOCK╞ 26╞ /INH2↲
╞ 27╞ /BHEN╞ 28╞ /AD10↲
╞ 29╞ /CBRQ╞ 30╞ /AD11↲
╞ 31╞ /CCLK╞ 32╞ /AD12↲
╞ 33╞ /INTA╞ 34╞ /AD13↲
╞ 35╞ /INT6╞ 36╞ /INT7↲
╞ 37╞ /INT4╞ 38╞ /INT5↲
╞ 39╞ /INT2╞ 40╞ /INT3↲
╞ 41╞ /INT0╞ 42╞ /INT1↲
╞ 43╞ /ADRE╞ 44╞ /ADRF↲
╞ 45╞ /ADRC╞ 46╞ /ADRD↲
╞ 47╞ /ADRA╞ 48╞ /ADRB↲
╞ 49╞ /ADR8╞ 50╞ /ADR9↲
╞ 51╞ /ADR6╞ 52╞ /ADR7↲
╞ 53╞ /ADR4╞ 54╞ /ADR5↲
╞ 55╞ /ADR2╞ 56╞ /ADR3↲
╞ 57╞ /ADR0╞ 58╞ /ADR1↲
╞ 59╞ /DATE╞ 60╞ /DATF↲
╞ 61╞ /DATC╞ 62╞ /DATD↲
╞ 63╞ /DATA╞ 64╞ /DATB↲
╞ 65╞ /DAT8╞ 66╞ /DAT9↲
╞ 67╞ /DAT6╞ 68╞ /DAT7↲
╞ 69╞ /DAT4╞ 70╞ /DAT5↲
╞ 71╞ /DAT2╞ 72╞ /DAT3↲
╞ 73╞ /DAT0╞ 74╞ /DAT1↲
╞ 75╞ GND╞ 76╞ GND↲
╞ 77╞ Reserved╞ 78╞ Reserved↲
╞ 79╞ -12V╞ 80╞ -12V↲
╞ 81╞ +5V╞ 82╞ +5V↲
╞ 83╞ +5V╞ 84╞ +5V↲
╞ 85╞ GND╞ 86╞ GND↲
╞ ┆b0┆---------------------------------------↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
Fig 5.4.1 P1 and P2 Pin assignment.↲
↲
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
↲
┆a1┆┆b0┆5.4.2 P2 extended Multibus Connector (iLBXbus connector).↲
↲
╞ ┆b0┆┆a1┆Pin╞ Signal╞ Pin╞ Signal. ↲
↲
╞ 1╞ DB0╞ 2╞ DB1↲
╞ 3╞ DB2╞ 4╞ DB3↲
╞ 5╞ DB4╞ 6╞ DB5↲
╞ 7╞ DB6 ╞ 8╞ DB7↲
╞ 9╞ GND ╞ 10╞ DB8↲
╞ 11╞ DB9 ╞ 12╞ DB10↲
╞ 13╞ DB11 ╞ 14╞ DB12↲
╞ 15╞ DB13 ╞ 16╞ DB14↲
╞ 17╞ DB15 ╞ 18╞ GND↲
╞ 19╞ AB0 ╞ 20╞ AB1↲
╞ 21╞ AB2 ╞ 22╞ AB3↲
╞ 23╞ AB4 ╞ 24╞ AB5↲
╞ 25╞ AB6 ╞ 26╞ AB7↲
╞ 27╞ GND ╞ 28╞ AB8↲
╞ 29╞ AB9 ╞ 30╞ AB10↲
╞ 31╞ AB11 ╞ 32╞ AB12↲
╞ 33╞ AB13 ╞ 34╞ AB14↲
╞ 35╞ AB15 ╞ 36╞ GND↲
╞ 37╞ AB16╞ 38╞ AB17↲
╞ 39╞ AB18 ╞ 40╞ AB19↲
╞ 41╞ AB20 ╞ 42╞ AB21↲
╞ 43╞ AB22 ╞ 44╞ AB23↲
╞ 45╞ GND ╞ 46╞ /ACK↲
╞ 47╞ BHEN ╞ 48╞ R/(/W)↲
╞ 49╞ /ASTB╞ 50╞ /DSTB↲
╞ 51╞ /SMRQ╞ 52╞ /SMACK↲
╞ 53╞ /LOCK╞ 54╞ GND↲
╞ 55╞ /ADR22╞ 56╞ /ADR23↲
╞ 57╞ /ADR20╞ 58╞ /ADR21↲
╞ 59╞ Reserved╞ 60╞ /TPAR↲
╞ ┆b0┆---------------------------------------↲
════════════════════════════════════════════════════════════════════════
↓
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
┆b0┆┆a1┆5.4.3 J1 Console interface connector.↲
↲
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
┆a1┆┆b0┆┆f0┆┆a1┆┆e1┆┆a1┆┆b0┆J1 Console (RS232C) Signals↲
↲
1┆a1┆┆e1┆ ┆e1┆┆a1┆┆e1┆ RETUR┆a1┆┆e1┆N↲
2 ┆a1┆┆e1┆ ┆a1┆┆e1┆ Non Connected↲
3 ┆a1┆┆e1┆ Non Connected↲
┆e1┆ 4 ┆a1┆┆a1┆┆e1┆ Non Connected↲
5 ┆a1┆┆e1┆ RETURN↲
6 ┆a1┆┆a1┆┆e1┆ Non Connected↲
7 ┆a1┆┆e1┆ CALLING INDICATOR B↲
8 ┆a1┆┆a1┆┆e1┆ CARRIER DET B↲
┆b0┆┆a1┆┆f0┆┆e1┆┆b0┆┆a1┆┆e1┆┆f0┆ 9 ┆a1┆┆e1┆ RETURN↲
10 ┆a1┆┆e1┆ DATA TERM. RDY B↲
11┆a1┆┆e1┆ RETURN↲
12 DATA SET READY B↲
13 ┆a1┆┆e1┆ RETURN↲
14 ┆a1┆┆e1┆ C┆a1┆┆e1┆LEAR TO SEN┆e1┆┆a1┆┆e1┆D B↲
15 ┆a1┆┆e1┆ RETURN↲
16 ┆a1┆┆e1┆ ┆a1┆┆e1┆REQUEST TO SEND B↲
17 ┆a1┆┆e1┆ RETURN↲
18 ┆a1┆┆e1┆ ┆a1┆┆e1┆/RECIEVE DATA B↲
19 ┆a1┆┆e1┆ RETURN↲
20 /TRANSMIT DATA B↲
┆b0┆ ---------------------------------↲
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
Fig 5.4.2 J1 pin assignment.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆5.4.4 J2 RS422A Multidrop Interface Connector.↲
↲
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
┆b0┆┆a1┆┆e1┆ ┆a1┆┆b0┆┆f0┆┆a1┆┆e1┆┆a1┆┆b0┆J2 Printer Signals ↲
↲
1┆a1┆┆e1┆ ┆e1┆┆a1┆┆e1┆ RETURN┆a1┆┆a1┆┆a1┆┆e1┆┆a1┆┆a1┆┆e1┆┆a1┆┆b0┆┆e1┆┆f0┆↲
2 ┆a1┆┆e1┆ ┆a1┆┆e1┆ RECIEVE ┆e1┆┆a1┆┆e1┆COMMON↲
3 ┆a1┆┆e1┆ Non Connected↲
┆e1┆ 4 ┆a1┆┆a1┆┆e1┆ TERMINAL TIMMING↲
5 ┆a1┆┆e1┆ /TERMINAL TIMMING↲
6 ┆a1┆┆a1┆┆e1┆ SEND DATA↲
7 ┆a1┆┆e1┆ /SEND DATA↲
8 ┆a1┆┆a1┆┆e1┆ Non Connected↲
┆b0┆┆a1┆┆f0┆┆e1┆┆b0┆┆a1┆┆e1┆┆f0┆ 9 ┆a1┆┆e1┆ Non Connected↲
10 ┆a1┆┆e1┆ ┆a1┆┆e1┆ RECEIVE D┆e1┆┆a1┆┆e1┆ATA↲
11 ┆a1┆┆e1┆ /RECEIVE DATA↲
12 ┆a1┆┆e1┆ ┆a1┆┆e1┆REQUEST TO SEND↲
13 ┆a1┆┆e1┆ ┆a1┆┆e1┆ /REQUEST TO SEND↲
14 ┆a1┆┆e1┆ R┆e1┆ECEIVE TIMING (B)↲
15 ┆e1┆ RECEIVE TIMING (A)↲
16 ┆a1┆┆e1┆ ┆a1┆┆e1┆ CLEAR TO SEND↲
17 ┆a1┆┆e1┆ /CLEAR TO SEND↲
18 ┆a1┆┆e1┆ ┆a1┆┆e1┆ Non Connected↲
19 ┆a1┆┆e1┆ Non Connected↲
20 DATA MODE↲
21 ┆a1┆┆e1┆ /DATA MODE↲
22 ┆a1┆┆e1┆ ┆a1┆┆e1┆ TERMINAL READY↲
23 ┆a1┆┆e1┆ /TERMINAL READY↲
24 ┆a1┆┆e1┆ ┆a1┆┆e1┆ Non Connected↲
25 ┆a1┆┆a1┆┆e1┆ Non Connected↲
26 Non Connected↲
┆b0┆------------------------------↲
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
Fig 5.4.3 J2 pin assignment.↲
↲
↲
┆8c┆┆83┆┆9c┆↓
┆b0┆┆a1┆5.4.5 J3 Parallel Printer Interface Connector.↲
↲
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
┆b0┆┆a1┆┆b0┆┆a1┆┆e1┆ ┆a1┆┆b0┆┆f0┆┆a1┆┆e1┆┆a1┆┆b0┆J3 Printer Signals↲
↲
1┆a1┆┆e1┆ ┆e1┆┆a1┆┆e1┆ /STROBE┆a1┆┆a1┆┆a1┆┆e1┆┆a1┆┆a1┆┆e1┆┆a1┆┆b0┆┆e1┆┆f0┆↲
2 ┆a1┆┆e1┆ ┆a1┆┆e1┆ /AUTO LF┆e1┆┆a1┆↲
3 ┆a1┆┆e1┆ DATA 0┆e1┆┆e1┆↲
┆e1┆ 4 ┆a1┆┆a1┆┆e1┆ /FAULT↲
5 ┆a1┆┆e1┆ DATA 1↲
6 ┆a1┆┆a1┆┆e1┆ /LP INIT↲
7 ┆a1┆┆e1┆ DATA 2↲
8 ┆a1┆┆a1┆┆e1┆ /SELECT↲
┆b0┆┆a1┆┆f0┆┆e1┆┆b0┆┆a1┆┆e1┆┆f0┆ 9 ┆a1┆┆e1┆ DATA 3↲
10 ┆a1┆┆e1┆ ┆a1┆┆e1┆ RETURN┆e1┆┆a1┆┆e1┆↲
11 ┆a1┆┆e1┆ DATA 4↲
12 ┆a1┆┆e1┆ ┆a1┆┆e1┆ RETURN┆e1┆┆a1┆┆e1┆┆a1┆┆e1┆↲
13 ┆a1┆┆e1┆ DATA 5↲
14 ┆a1┆┆e1┆ ┆a1┆┆e1┆ RETURN┆e1┆┆a1┆┆e1┆↲
15 ┆a1┆┆e1┆ DATA 6↲
16 ┆a1┆┆e1┆ ┆a1┆┆e1┆ RETURN┆e1┆┆a1┆┆e1┆↲
17 ┆a1┆┆e1┆ DATA 7↲
18 ┆a1┆┆e1┆ ┆a1┆┆e1┆ RETURN┆e1┆┆a1┆┆e1┆↲
19 ┆a1┆┆e1┆ /ACK↲
20 RETURN┆e1┆┆a1┆┆e1┆┆e1┆↲
21 ┆a1┆┆e1┆ BUSY↲
22 ┆a1┆┆e1┆ ┆a1┆┆e1┆ RETURN┆e1┆┆a1┆↲
23 ┆a1┆┆e1┆ PAPER END↲
24 ┆a1┆┆e1┆ ┆a1┆┆e1┆ RETURN┆e1┆┆a1┆↲
25 ┆a1┆┆a1┆┆e1┆ SELECTED↲
26 non connected↲
┆b0┆ ----------------------------↲
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
Fig 5.4.4 J3 pin assignment.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5.4.6 ┆84┆J4 LED603, BBC601 and Key Interrupt Connector.↲
↲
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
┆b0┆┆a1┆┆b0┆┆a1┆┆e1┆ ┆a1┆┆b0┆┆f0┆┆a1┆┆e1┆┆a1┆┆b0┆J4 Signals ↲
↲
1┆a1┆┆e1┆ ┆e1┆┆a1┆┆e1┆ LED 1 CATHODE↲
2 ┆a1┆┆e1┆ ┆a1┆┆e1┆ LED 1 ANOD┆a1┆┆e1┆E↲
3 ┆a1┆┆e1┆ LED 2 CATHODE┆e1┆┆e1┆↲
┆e1┆ 4 ┆a1┆┆a1┆┆e1┆ LED 2 ANODE↲
5 ┆a1┆┆e1┆ /PINTR1↲
6 ┆a1┆┆a1┆┆e1┆ RETURN↲
7 ┆a1┆┆e1┆ /PINTR2↲
8 ┆a1┆┆a1┆┆e1┆ RETURN↲
┆b0┆┆a1┆┆f0┆┆e1┆┆b0┆┆a1┆┆e1┆┆f0┆ 9 ┆a1┆┆e1┆ PDMD↲
10 ┆a1┆┆e1┆ ┆a1┆┆e1┆ RETURN┆e1┆┆a1┆┆e1┆↲
11 ┆a1┆┆e1┆ +12V SENSE↲
12 ┆a1┆┆e1┆ ┆a1┆┆e1┆ +5V SENSE┆e1┆┆a1┆┆e1┆┆a1┆┆e1┆↲
13┆a1┆┆e1┆ /PINTR2↲
14 ┆a1┆┆e1┆ ┆a1┆┆e1┆ RETURN┆e1┆┆a1┆┆e1┆↲
15 ┆a1┆┆e1┆ Non Connected↲
16 ┆a1┆┆e1┆ ┆a1┆┆e1┆Non Connected↲
┆b0┆ ----------------------------↲
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
Fig 5.4.5 J4 pin assignment.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆5.4.7 J5 iSBXbus Interface Connector.↲
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
↲
╞ ┆b0┆┆a1┆Pin╞ Signal╞ Pin╞ Signal. ↲
↲
╞ 1╞ +12V╞ 2╞ -12V↲
╞ 3╞ GND╞ 4╞ +5V↲
╞ 5╞ RESET╞ 6╞ MCLK↲
╞ 7╞ MA2 ╞ 8╞ /MPST↲
╞ 9╞ MA1 ╞ 10╞ Reserved↲
╞ 11╞ MA0 ╞ 12╞ MINTR1↲
╞ 13╞ /IOWRT╞ 14╞ MINTR0↲
╞ 15╞ /IORD╞ 16╞ /MWAIT↲
╞ 17 GND ╞ 18╞ +5↲
╞ 19╞ MD7 ╞ 20╞ /MCS1↲
╞ 21╞ MD6 ╞ 22╞ /MCS0↲
╞ 23╞ MD5 ╞ 24╞ Reserved↲
╞ 25╞ MD4 ╞ 26╞ (TDMA)*↲
╞ 27╞ MD3 ╞ 28╞ OPT1↲
╞ 29╞ MD2 ╞ 30╞ OPT0↲
╞ 31╞ MD1 ╞ 32╞ (/MDACK)*↲
╞ 33╞ MD0 ╞ 34╞ (MDRQT)*↲
╞ 35╞ GND ╞ 36╞ +5V↲
╞ 37╞ MDE ╞ 38╞ MDF↲
╞ 39╞ MDC ╞ 40╞ MDD↲
╞ 41╞ MDA ╞ 42╞ MDB↲
╞ 43╞ MD8 ╞ 44╞ MD9↲
╞ ┆b0┆---------------------------------------↲
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
╞ * ┆84┆Note this DMA signals are not included on the CPU610X ↓
┆19┆┆8b┆┄┄board.↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
↲
Fig 5.4.6 J5 pin assignment.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5.5 ╞ Jumpers.↲
↲
╞ ┆84┆The CPU board includes only one standard detachable ↓
┆19┆┆89┆┄┄jumper W11. The rest of the jumpers is connected direct ↓
┆19┆┆89┆┄┄on the printed board. It can be disconnected with a ↓
┆19┆┆89┆┄┄knife.↲
↲
╞ The standard jumpers on the CPU610X are listed below :↲
↲
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
┆b0┆┆a1┆Jumper connections Function. ↲
↲
W1 NC Test Jumper (Not in Use).↲
W2 NC -"- ┆84┆(Disconnects the ↓
┆19┆┆b0┆┄┄iLBXbus).↲
W3 NC -"- ┆84┆(Test master else ↓
┆19┆┆b0┆┄┄test slave).↲
╞ W4 NC╞ ┆84┆Bus Priority Out. (Only used ↓
┆19┆┆a4┆┄┄in systems with seriel ↓
┆19┆┆a4┆┄┄arbitrations logic).↲
W5 1 - 44 ┆84┆Timer interrupt to Master PIC ↓
┆19┆┆a4┆┄┄level 0.↲
╞ W5 2 - 43 ┆84┆Multibus interrupt 2 to ↓
┆19┆┆a4┆┄┄Master PIC level 2.↲
╞ W5 3 - 42 ┆84┆Multibus interrupt 3 to ↓
┆19┆┆a4┆┄┄Master PIC level 3.↲
╞ W5 4 - 41 ┆84┆Multibus interrupt 4 to ↓
┆19┆┆a4┆┄┄Master PIC level 4.↲
╞ W5 5 - 40 ┆84┆Multibus interrupt 5 to ↓
┆19┆┆a4┆┄┄Master PIC level 5.↲
W5 6 - 39 ┆84┆8274 interrupt to Master PIC ↓
┆19┆┆a4┆┄┄level 6.↲
W5 7 - 38 ┆84┆Multibus interrupt 6 to Slave ↓
┆19┆┆a4┆┄┄PIC1 level 0.↲
╞ W5 8 - 37 ┆84┆Multibus interrupt 7 to Slave ↓
┆19┆┆a4┆┄┄PIC level 1.↲
W5 9 - 36 ┆84┆Time out interrupt to Slave ↓
┆19┆┆a4┆┄┄PIC1 level 2.↲
W5 10 - 35 ┆84┆iSBXbus interrupt 0 to Slave ↓
┆19┆┆a4┆┄┄PIC1 level 3.↲
W5 11 - 34 ┆84┆iSBXbus interrupt 1 to Slave ↓
┆19┆┆a4┆┄┄PIC1 level 4.↲
╞ W5 12 - 33 ┆84┆Multibus interrupt 0 to Slave ↓
┆19┆┆a4┆┄┄PIC1 level 5.↲
╞ W5 13 - 32 ┆84┆Multibus interrupt 1 to Slave ↓
┆19┆┆a4┆┄┄PIC1 level 6.↲
W5 14 - 31 ┆84┆Line Printer interrupt to ↓
┆19┆┆a4┆┄┄Slave PIC1 level 7.↲
W5 15 - 30 ┆84┆Extended multibus interrupt 8 ↓
┆19┆┆a4┆┄┄to Slave PIC2 level 0.↲
W5 16 - 29 ┆84┆Extended multibus interrupt 9 ↓
┆19┆┆a4┆┄┄to Slave PIC2 level 1.↲
W5 17 - 28 ┆84┆Extended multibus interrupt ↓
┆19┆┆a4┆┄┄10 to Slave PIC2 level 2.↲
════════════════════════════════════════════════════════════════════════
↓
┆b0┆┆a1┆Jumper connections Function. ↲
↲
W5 18 - 27 ┆84┆Extended multibus interrupt ↓
┆19┆┆a4┆┄┄11 to Slave PIC2 level 3.↲
W5 19 - 26 ┆84┆Extended multibus interrupt ↓
┆19┆┆a4┆┄┄12 to Slave PIC2 level 4.↲
W5 20 - 25 ┆84┆Extended multibus interrupt ↓
┆19┆┆a4┆┄┄13 to Slave PIC2 level 5.↲
W5 21 - 24 ┆84┆Extended multibus interrupt ↓
┆19┆┆a4┆┄┄14 to Slave PIC2 level 6.↲
W5 22 - 23 ┆84┆Extended multibus interrupt ↓
┆19┆┆a4┆┄┄15 to Slave PIC2 level 7.↲
W6 NC ┆84┆Used to generate interrupts ↓
┆19┆┆a4┆┄┄out to the multibus.↲
W7 2 - 3 ┆84┆Select the baud rate signal A ↓
┆19┆┆a4┆┄┄as a receiver clock in the ↓
┆19┆┆a4┆┄┄RS422A interface, else the TT ↓
┆19┆┆a4┆┄┄signal (Terminal Timing) is ↓
┆19┆┆a4┆┄┄in use.↲
W8 NC Test Jumper. (Not in use).↲
W9 NC ┆84┆Used to the (80287). NC it ↓
┆19┆┆a4┆┄┄indicates that the 80287 use ↓
┆19┆┆a4┆┄┄the CPU clock else it is ↓
┆19┆┆a4┆┄┄divided by three.↲
W10 1 - 3 ┆84┆Select the 80287 clock. It ↓
┆19┆┆a4┆┄┄use the cpu clock divided by ↓
┆19┆┆a4┆┄┄two in the standard ↓
┆19┆┆a4┆┄┄configuration else cut W10 ↓
┆19┆┆a4┆┄┄1-3 5MHz clock or W10 3-4 (W9 ↓
┆19┆┆a4┆┄┄1-2) the exact CPU clock. ↓
┆19┆┆a4┆┄┄(But intern in the 80287 it ↓
┆19┆┆a4┆┄┄is divided by three.↲
┆b0┆ ┆f0┆W11 1 - 2 ┆84┆On PCB715 it is the only standard ↓
┆19┆┆a4┆┆81┆┄detachable jumper. It used to ↓
┆19┆┆a4┆┆81┆┄27256 EPROM's. If 27128 or ↓
┆19┆┆a4┆┆81┆┄2764 EPROM's is use it is ↓
┆19┆┆a4┆┆81┆┄disconnected. On PCB771 it is ↓
┆19┆┆a4┆┆81┆┄opposite, here there is no ↓
┆19┆┆a4┆┆81┆┄standard jumpers.↲
┆b0┆----------------------------------------------------↲
╱04002d4e0a00060000000003014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
╱04002d4e0a00060000000002014131000000000000000000000000000000000000000000000000000a12232a37414b555f69737d8791ffff04╱
↓
↲
┆a1┆┆b0┆5.6 Enviromental Specification.↲
↲
Operating Temperature: 0┆81┆0┆82┆ - 55┆81┆0┆82┆↲
↲
Relative Humidity: 20% - 80% (Non condensing).↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆5.7 Physical Specifications.↲
↲
Width: 304.8mm↲
↲
Lenght: 179.1mm↲
↲
Height: 12mm↲
↲
↲
┆a1┆┆b0┆5.8 Power Specifications.↲
↲
Power Dissipation 36.8 W (max).↲
╞ VCC +5V +/- 5% (7.1A max)↲
VDD+ +12V +/-10% (50mA max)↲
VDD- -12V +/-10% (50mA max)↲
════════════════════════════════════════════════════════════════════════
↓
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆b0┆A References.↲
↲
1. ┆84┆INTEL Microsystem Components Handbook. 1984. ↓
┆19┆┆8e┆┄┄230843-001.↲
↲
2. INTEL MULTIBUS Specification 9800683-04↲
↲
3. INTEL iLBX Bus Specification 145695-REV A↲
↲
4. INTEL iSBX Bus Specification 142686-001↲
↲
5. ┆84┆Central Processor Unit CPU610. Rev 1.2 . Hardware ↓
┆19┆┆8e┆┄┄Reference Manual manual. RCSL 99-1 09863↲
↲
6. ┆84┆RC 3902 (CPU 610) Hardware Selftest. User's Manual. ↓
┆19┆┆8e┆┄┄RCSL 99-1 10176↲
↲
7. ┆84┆RC 39 Selftest Concept. User's Manual.RCSL 99-1 ↓
┆19┆┆8e┆┄┄10092↲
════════════════════════════════════════════════════════════════════════
↓
↲
┆1a┆┆1a┆ 15 - 30 ┆84┆Extended munterrupt 8 ↓
┆19┆┆a4┆┄┄tURN┆e1┆┆a1┆┆e1┆↲