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Length: 16000 (0x3e80)
Types: RcTekst
Names: »99110047.WP«
└─⟦7fab0c8ae⟧ Bits:30005866/disk3.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110047.WP«
╱04002d4e0a00060000000003013c3100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
┆06┆i↲
↲
┆a1┆┆b0┆TABLE OF CONTENTS┆05┆PAGE↲
↲
1. INTRODUCTION ....................................... 1↲
↲
2. THE TESTROUTER ..................................... 2↲
2.1 Switch Parameters .............................. 2↲
2.2 Keyboard Management ............................ 4↲
2.3 Output ......................................... 5↲
↲
3. THE MEMORY TEST .................................... 6↲
3.1 Checksum Test .................................. 6↲
3.2 Ram Test ....................................... 6↲
↲
4. MEMORY REFRESH TEST ................................ 9↲
4.1 Battery Test ................................... 9↲
↲
5. KEYBOARD TEST ...................................... 10↲
↲
6. SIO TEST ........................................... 11↲
6.1 Modem Signal Response .......................... 11↲
6.2 SIO Channel Test ............................... 12↲
↲
7. RCCIRCUIT I TEST ................................... 14↲
↲
8. CTC TEST ........................................... 15↲
↲
9. PARALLEL PORT TEST ................................. 16↲
↲
10. DMA TEST ........................................... 17↲
↲
11. CRT TEST ........................................... 18↲
════════════════════════════════════════════════════════════════════════
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┆06┆ii↲
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════════════════════════════════════════════════════════════════════════
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┆14┆┆b3┆┆06┆┆0b┆↲
┆a1┆1. INTRODUCTION↲
↲
┆84┆This manual describes the diagnostic testprograms for the RC45 ↓
terminalsystems.↲
↲
┆84┆The testprograms are testing the basic functions of the different ↓
parts of the hardware in the terminal.↲
↲
┆84┆┆84┆The sequence of the different testprograms in the test systems is ↓
organized with rising complexity. As far as possible, no part of ↓
the hardware is used before it is tested.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆2.╞ THE TEST ROUTER↲
↲
┆84┆The test router is the kernal in the testsystem, which main ↓
purpose is to compute the address of the next test in the ↓
sequence. The address of the next test is derived from a variable ↓
holding the present test number and normally incremented by one. ↓
Every time a test has finished and is not in looping mode, the ↓
test router is entered.↲
↲
↲
┆a1┆2.1╞ Switch Parameters↲
↲
┆84┆The variable holding the test number also contains four switch ↓
bits, by which the testrouter decides how to administer the ↓
tests.↲
↲
╞ MSB LSB↲
╞ -------------------------------------------------↲
╞ ! ! ! ! ! ! ! ! !↲
╞ ! ! ! ! ! ! ! ! !↲
╞ ! ! ! ! ! ! ! ! !↲
╞ -------------------------------------------------↲
! ! ! ! ! ! ! !↲
! ! ! ! !-----!-----!-----!--test no.↲
! ! ! !--------------------------use V.24↲
! ! !--------------------------------ext. test↲
! !--------------------------------------loop↲
!--------------------------------------------halt↲
↲
halt:╞ 0: halt if error (default)↲
╞ ╞ 1: proceed even if error↲
↲
loop:╞ 0: sequential, big loop af all tests (default)↲
╞ ╞ 1: looping in a selected test↲
↲
ext. test:╞ 0: power-up test↲
╞ ╞ 1: extended test↲
↲
════════════════════════════════════════════════════════════════════════
↓
V.24:╞ 0: test plug in the V.24 connection↲
╞ ╞ 1: ┆84┆no test plug in the V.24 connection. The channel ↓
┆19┆┆91┆┄┄is used as V.24 output (1200 baud, 7 bit, 1 ↓
┆19┆┆91┆┄┄stopbit)↲
↲
┆84┆The HALT and LOOP bits are initiated to zero.↲
↲
┆84┆The test mode bit is set to one, if the test plug (KBL 721) is ↓
installed in the parallel printer connection (J3) or if the ↓
'TEST' key is pressed immediately after power-up test, when the ↓
RC logo appears in the lower left corner.↲
↲
┆a1┆┆b0┆WARNING! Be aware of connecting the plugs in the right ↓
┆19┆┄┆81┆┆86┆connections or the terminal may be damaged.↲
┆a1┆↲
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┆06┆Figure 1: Testmode plug (KBL 721).↲
↲
┆84┆The V.24 bit is set/reset every time the RAM test has finished. ↓
If the SIO-test plug (CBL 998 see fig. 3) is installed in the ↓
V.24 output connection (SIO channel A), the bit is reset, ↓
otherwise it is set to indicate, that the testoutput is directed ↓
to the V.24 channel (1200 baud, 7 bit, 1 stopbit and even parity) ↓
too.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆2.2╞ Keyboard Management↲
↲
Valid keys are as follows:↲
↲
╞ ╞ H: set halt bit to 0↲
╞ ╞ R: set halt bit to 1↲
╞ ╞ G: set loop bit to 0↲
╞ ╞ L: set loop bit to 1↲
↲
┆84┆Numbers between 0-8 will insert a new test number into the ↓
test number variable. ↲
↲
All other keys will give no response.↲
↲
┆84┆If one for example wants to loop in test 6 and not go into a HALT ↓
state if error, then strike the keys R, L, 6 (not necessarily ↓
this sequence).↲
↲
┆a1┆┆84┆Note┆e1┆ it is the last valid key, which is pressed, that determines ↓
the test parameter or test number (e.g. if "L" and "G" is pressed ↓
in this sequence, the loop bit is reset.)↲
↲
┆84┆Relationship between the test numbers and actual test is as ↓
follows.↲
↲
╞ ┆a1┆test No╞ Test name↲
↲
╞ 0╞ RAM test↲
╞ 1 ╞ REFRESH test↲
╞ 2╞ KEYBOARD test↲
╞ 3╞ SIO test↲
╞ 4╞ RCCIRCUIT I test↲
╞ 5╞ CTC test↲
╞ 6╞ PARALLEL PORT test↲
╞ 7╞ DMA test↲
╞ 8╞ CRT test↲
↲
┆84┆↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆2.3╞ Output↲
↲
┆84┆The test router will respond with some output. After the RAM test ↓
has finished, a test menu (se fig. 2) is shown for a few seconds. ↓
This test menu shows the tests with the relational numbers and ↓
the possible test modes (looping, halt on error etc). By pressing ↓
the 'M' key will force the menu to retain on the screen. To ↓
continue press "RETURN". It also responds with a status line, in ↓
which the state of the test is shown. This could be either going, ↓
stopped, looping or halted. Furthermore the state of the 'HALT-↓
bit' (R-SWITCH/H-SWITCH) and a passcounter is shown. ↲
↲
RC45 testsystem version x.x↲
↲
┆19┆┄┄┆84┆┆e1┆ MENU╞ ╞ Select↲
╞ RAM_test:╞ ╞ 0↲
╞ Refresh_test:╞ 1↲
╞ Keyboard_test:╞ 2↲
╞ SIO_test:╞ ╞ 3↲
╞ RcCircuit1_test:╞ 4↲
╞ CTC_test:╞ ╞ 5↲
╞ Parallel_port_test:╞ 6↲
╞ DMA_test:╞ ╞ 7↲
╞ CRT_test:╞ ╞ 8↲
↲
╞ Looping in a selected test L↲
╞ Go through tests╞ G↲
╞ Run even if error╞ R↲
╞ Halt if error╞ H↲
↲
Select any combination from menu and type 'RETURN':↲
↲
┆06┆Figure 2: Test menu.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆3.╞ THE MEMORY TEST↲
↲
┆84┆The memory test performs a test of the dynamic, if installed, and ↓
the static RAM memory. All memory cells but the upper 512 are ↓
tested by the memory test. Incorporated in the memory test is a ↓
checksum of the bootprom. This checksum is performed as the very ↓
first test.↲
↲
↲
┆a1┆3.1╞ Checksum test↲
↲
┆84┆The checksum is made on the 16K image of the bootprom. The ↓
checksum must end up with the sum 0.↲
↲
┆a1┆Text from this part of the memory test:↲
↲
╞ ╞ <RC45 rom error>↲
↲
↲
┆a1┆3.2╞ Ram test↲
↲
┆84┆First the memory addresses from 48 - 64 K (except for the upper ↓
512 bytes) is tested. If this addressroom is failurefree, the ↓
testsystem is moved to this memory area, and it is tested if the ↓
RAM from 0 - 48 K is installed. In this case this memory area is ↓
tested, and thereafter the testsystem is moved back.↲
↲
┆84┆The test pattern for the dynamic RAM memory consisting of chips ↓
of 4 bit x 16 k is three times 00 followed by three times FF ↓
(Hex). When all memory cells have been tested, they are again ↓
tested with the inverted pattern. This means that all bits are ↓
tested for "zero" and "one" insertion. ↲
↲
┆84┆┆a1┆If an error occurs, a message will be written:↲
↲
╞ ╞ <RC45 memory error ha la ex re>↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆where "ha" is high address, "la" is below address, "ex" is ↓
expected value and "re" is received value. All numbers are in ↓
hexadecimal notations. (To find any defective chip, consult fig. ↓
3).↲
↲
If the memory is found failurefree no message is written.↲
↲
┆84┆┆a1┆If an error occurs in the memory test (rom error or ram error) ↓
┆19┆┄┄┆84┆the test will stop hard i.e. it is not possible to continue the ↓
┆19┆┄┄┆84┆testsequence.↲
════════════════════════════════════════════════════════════════════════
↓
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┆88┆┆81┆↲
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┆06┆Figure 3: Memory lay-out↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆4┆a1┆.╞ MEMORY REFRESH TEST↲
↲
The dynamic RAM refresh test is a test, which verifies the ↓
function of the CPU refresh counting. As an additional feature ↓
the test checks the battery circuit.↲
↲
┆84┆The test writes a pattern in memory consisting of an XOR of high ↓
and low address part. The pattern is written from the memory ↓
address 8000H until the hexadecimal address D500H (where the ↓
display image starts). If no dynamic RAM is installed, the test ↓
starts at memory address C000H.↲
↲
┆84┆When the pattern has been written, the test waits for 5 seconds ↓
in a waiting loop before it performs a check of the data.↲
↲
┆84┆The main purpose of this test is to discover modification of the ↓
data occurring in the delay time, due to malfunction of the ↓
refresh counting in the CPU. Note that the memory higher than ↓
C000H (48K) is static RAM and has no refresh counting.↲
↲
┆84┆┆a1┆Possible messages are:↲
↲
╞ <OK>↲
↲
╞ <data modified in byte xx xx exp: xx rec: xx>↲
↲
↲
┆a1┆4.1╞ Battery test↲
↲
┆84┆When the refresh counting is tested, the test checks 4 bytes in ↓
the NVM-area. If theese 4 bytes does not match a testpattern (00 ↓
FF 00 FF), the bytes will be initiated to this testpattern, and ↓
the text "battery test initiated" will be written. To check the ↓
battery circuit turn off and on the power and restart the ↓
testsytem. When performing the refresh test, the text "battery ↓
test initiated" must not appear. ┆a1┆Note that the test must be ↓
┆19┆┄┄┆84┆started with the testcable KBL 721 in the printerconnector, if ↓
┆19┆┄┄┆84┆this part of the test shall act correct.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆5.╞ KEYBOARD TEST┆e1┆↲
↲
┆84┆The keyboard contains a checksum test of the keyboard-PROM, a RAM ↓
test of keyboard-CPU and a scan test of the keyboard- matrix. ↓
Theese three tests can be activated by writing some specifically ↓
codes (keyboard-PROM test: 186, keyboard-RAM test: 184 and ↓
keyboard scan test: 188) to the keyboard. The keyboard will ↓
respond with OK (the same code) or not OK (the code + 1).↲
↲
┆a1┆Possible messages are:↲
↲
╞ <OK>↲
↲
╞ <romerror>↲
↲
╞ <ramerror>↲
↲
╞ <scanerror>↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆6.╞ SIO TEST↲
↲
┆84┆If the SIO-test plug (CBL 998) is inserted in the V.24 ↓
connection, the SIO test is performed.↲
↲
┆84┆The SIO test is testing the modem signals and data transports on ↓
SIO channel A.↲
↲
┆84┆Channel B see RCCIRCUIT I test.↓
↲
↲
┆a1┆6.1╞ Modem Signal Response↲
↲
┆84┆The responses of DTR and RTS are tested on the DCD and CTS pins. ↓
Test plug as shown in fig. 4 must be installed on the V.24 ↓
connection of the terminal.↲
↲
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┆06┆Figure 4: CBL 998↲
↲
┆84┆If an error occurs on the modem signals CTS or DCD the received ↓
hex. value should be interpreted as shown in fig. 5↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆┆a1┆Error messages from this part of the test:↲
↲
╞ CTS or DCD error, exp: <xx> rec: <xx>↲
↲
Received value differs from expected; cf. fig. 5.↲
↲
↲
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┆06┆Figure 5: Modem signal response.↲
↲
↲
┆a1┆6.2╞ SIO Channel Test↲
↲
┆84┆When the modem signal responses have been checked, the SIO ↓
channel A is initiated.↲
↲
┆84┆The SIO channel is initiated to 19200 bps. Baud rate generator is ↓
the CTC.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆A timer interrupt generated approx. 1760 times/s transmits the ↓
data from the transmit buffer. ↲
↲
┆84┆The channel transmit a databuffer of 1 k bytes consisting of a ↓
counting pattern (00 FF FE FD etc.). The test loop will check the ↓
received buffer, as soon as the pattern have been transfered. It ↓
also monitors the channel for timeout.↲
↲
┆a1┆Error messages from the SIO channel test:↲
↲
╞ ┆84┆<illegal interrupt, port: <xx>>↲
↲
┆84┆An interrupt has occured from a device that was not intended to ↓
interrupt, or the SIO has given a status interrupt (any change on ↓
the modem signals during data transfer will respond with this ↓
message).↲
↲
╞ <parity error>↲
↲
A special receive interrupt with parity bit has occured.↲
↲
╞ <data error, byte no: <xx xx> exp: <xx> rec: <xx>>↲
↲
The received buffer does not contain the expected pattern.↲
↲
╞ <receiver overrun>↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆7.╞ RCCIRCUIT I TEST↲
↲
┆84┆Before the test starts, it is tested, if Circuit 1 is installed.↲
↲
┆84┆The SIO channel B is initiated to full duplex and the DMA is ↓
initiated to receive 1K bytes from the SIO.↲
↲
┆84┆A timer interrupt generated approx. 1760 times/s transmits the ↓
data from the transmit buffer. ↲
↲
┆84┆The channel transmit a databuffer of 1 k bytes consisting of a ↓
counting pattern (00 FF FE FD etc.). The test loop will check the ↓
received buffer as soon as the pattern have been transfered. It ↓
also monitors the channel for timeout.↲
↲
┆84┆┆a1┆Possible messages are:↲
↲
╞ <OK>↲
↲
╞ <TIMEOUT>↲
↲
The data has not been transmitted completely.↲
↲
╞ <data error, byte no: <xx xx> exp: <xx> rec: <xx>>↲
↲
The received buffer does not contain the expected pattern.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆8.╞ CTC TEST↲
↲
┆84┆This program tests the counter/timer circuit, which is used for ↓
baud rate generator and as interrupt circuit for the CRT and the ↓
keyboard.↲
↲
┆84┆┆84┆It is tested, that the circuit will generate interrupts, and that ↓
the vector (interrupt address) is correct.↲
↲
┆84┆The four channels 0, 1, 2, and 3 are tested. If two CTC's are ↓
installed also the channels 4, 5, 6 and 7 are tested. The ↓
channels are tested in the timer mode, and the timing starts ↓
automatically. The channel under test should be giving interrupt ↓
after approx. 423 mikro s. ↲
↲
┆84┆The test is based on a timeout loop, so it is checked if the ↓
interrupt was received within a specified time (3oo ms.). It is ↓
also checked that only the specified channel interrupts.↲
↲
┆84┆┆a1┆Possible messages are:↲
↲
╞ <OK>↲
↲
╞ ┆84┆<illegal interrupt, port: xx>↲
┆84┆meaning that another channel than the specified has interrupted.↲
↲
╞ ┆84┆<no interrupt, ch:>↲
┆84┆meaning that the test has timed out before interrupt was ↓
received.↲
↲
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆9.╞ PARALLEL PORT TEST┆e1┆↲
↲
┆84┆This test is a quick test of the three output signals (strobe, ↓
init and select) from the cpu to the port 19H routed back to port ↓
19H. All eight combinations are tested.↲
↲
┆a1┆Possible message are:↲
↲
╞ <OK>↲
↲
╞ <data error exp xx rec xx>↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆10.╞ DMA Test↲
↲
┆84┆At first it is tested if DMA is installed, before the test ↓
starts.↲
↲
┆84┆The DMA test is tested by a memory to memory transport. ↲
↲
┆84┆The transmitted pattern is a buffer of 1 k containing a counting ↓
pattern. The pattern is as follows: 00 FF FE FD etc. repeated 4 ↓
times.↲
↲
┆84┆When the transport is finished, the receiving buffer is checked ↓
against the transmitted buffer byte by byte.↲
↲
┆84┆If the transport is correct it is tested if the DMA can respond ↓
with an interrupt after end of block is reached.↲
↲
┆84┆┆a1┆Possible messages are:↲
↲
╞ ┆84┆<OK>↲
↲
╞ <not installed>↲
↲
╞ when testing transfer:↲
↲
╞ ╞ <End of Block timeout 200 ms>↲
╞ ╞ <data error, byte no: xx xx exp: xx rec: xx>↲
↲
╞ when testing interrupt:↲
↲
╞ ╞ <timeout>↲
↲
╞ ╞ <┆84┆data error, byte no: xx xx exp: xx rec: xx in ↓
┆19┆┆8f┆┄┄interrupt>↲
↲
┆84┆All numbers are in hexadecimal notation. "End of Block timeout ↓
200 ms" shows that the end of block bit in the DMA status ↓
register has not been set within 200 ms, and the transport is ↓
therefore not succesful.↲
↲
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆11.╞ CRT TEST↲
↲
This is a visual test.↲
↲
┆84┆It is possibly to stop the test by pressing the "H" key. To ↓
continue press the "RETURN" KEY.↲
↲
The following should appear on the screen.↲
↲
The character-PROM is written.↲
↲
┆84┆Field attributes test. The field attributes are tested on the ↓
character-PROM. The 25 lines appear as follows:↲
↲
╞ ┆84┆a: 5 lines with highlight↲
b: 4 lines with reverse video+highlight↲
c: 4 lines with reverse video↲
d: 4 lines with invisible↲
e: 4 lines with underline↲
f: 4 lines with blink↲
↲
┆84┆The screen is filled with "H". To adjust the screen "H" ↓
is often used.↲
↲
┆84┆The contrast and brigthness are tested. First the contrast and ↓
then the brigtness are tested. For both, first maximum, then ↓
minimum and finally normally should appear.↲
↲
┆84┆If not a paperwhite monitor then the test ends up with the 132 ↓
character set written.↲
┆8c┆┆82┆┆e8┆↓
┆a1┆↲
════════════════════════════════════════════════════════════════════════
↓
┆1a┆┆1a┆ ┆1a┆┆1a┆ is a test, which verifies the ↓
funct