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Length: 16000 (0x3e80)
Types: RcTekst
Names: »99110047.WP«
└─⟦7fab0c8ae⟧ Bits:30005866/disk3.imd Dokumenter i RcTekst format (RCSL 99-1-*)
└─⟦this⟧ »99110047.WP«
╱04002d4e0a00060000000003013c3100000000000000000000000000000000000000000000000000050f19232d37414b555f69737d8791ff04╱
┆06┆i↲
↲
┆a1┆┆b0┆TABLE OF CONTENTS┆05┆PAGE↲
↲
1. INTRODUCTION ....................................... 1↲
↲
2. THE TESTROUTER ..................................... 2↲
2.1 Switch Parameters .............................. 2↲
2.2 Keyboard Management ............................ 4↲
2.3 Output ......................................... 5↲
↲
3. THE MEMORY TEST .................................... 6↲
3.1 Checksum Test .................................. 6↲
3.2 Ram Test ....................................... 6↲
↲
4. MEMORY REFRESH TEST ................................ 9↲
4.1 Battery Test ................................... 9↲
↲
5. KEYBOARD TEST ...................................... 10↲
↲
6. SIO TEST ........................................... 11↲
6.1 Modem Signal Response .......................... 11↲
6.2 SIO Channel Test ............................... 12↲
↲
7. RCCIRCUIT I TEST ................................... 14↲
↲
8. CTC TEST ........................................... 15↲
↲
9. PARALLEL PORT TEST ................................. 16↲
↲
10. DMA TEST ........................................... 17↲
↲
11. CRT TEST ........................................... 18↲
════════════════════════════════════════════════════════════════════════
↓
┆06┆ii↲
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════════════════════════════════════════════════════════════════════════
↓
┆14┆┆b3┆┆06┆┆0b┆↲
┆a1┆1. INTRODUCTION↲
↲
┆84┆This manual describes the diagnostic testprograms for the RC45 ↓
terminalsystems.↲
↲
┆84┆The testprograms are testing the basic functions of the different ↓
parts of the hardware in the terminal.↲
↲
┆84┆┆84┆The sequence of the different testprograms in the test systems is ↓
organized with rising complexity. As far as possible, no part of ↓
the hardware is used before it is tested.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆2.╞ THE TEST ROUTER↲
↲
┆84┆The test router is the kernal in the testsystem, which main ↓
purpose is to compute the address of the next test in the ↓
sequence. The address of the next test is derived from a variable ↓
holding the present test number and normally incremented by one. ↓
Every time a test has finished and is not in looping mode, the ↓
test router is entered.↲
↲
↲
┆a1┆2.1╞ Switch Parameters↲
↲
┆84┆The variable holding the test number also contains four switch ↓
bits, by which the testrouter decides how to administer the ↓
tests.↲
↲
╞ MSB LSB↲
╞ -------------------------------------------------↲
╞ ! ! ! ! ! ! ! ! !↲
╞ ! ! ! ! ! ! ! ! !↲
╞ ! ! ! ! ! ! ! ! !↲
╞ -------------------------------------------------↲
! ! ! ! ! ! ! !↲
! ! ! ! !-----!-----!-----!--test no.↲
! ! ! !--------------------------use V.24↲
! ! !--------------------------------ext. test↲
! !--------------------------------------loop↲
!--------------------------------------------halt↲
↲
halt:╞ 0: halt if error (default)↲
╞ ╞ 1: proceed even if error↲
↲
loop:╞ 0: sequential, big loop af all tests (default)↲
╞ ╞ 1: looping in a selected test↲
↲
ext. test:╞ 0: power-up test↲
╞ ╞ 1: extended test↲
↲
════════════════════════════════════════════════════════════════════════
↓
V.24:╞ 0: test plug in the V.24 connection↲
╞ ╞ 1: ┆84┆no test plug in the V.24 connection. The channel ↓
┆19┆┆91┆┄┄is used as V.24 output (1200 baud, 7 bit, 1 ↓
┆19┆┆91┆┄┄stopbit)↲
↲
┆84┆The HALT and LOOP bits are initiated to zero.↲
↲
┆84┆The test mode bit is set to one, if the test plug (KBL 721) is ↓
installed in the parallel printer connection (J3) or if the ↓
'TEST' key is pressed immediately after power-up test, when the ↓
RC logo appears in the lower left corner.↲
↲
┆a1┆┆b0┆WARNING! Be aware of connecting the plugs in the right ↓
┆19┆┄┆81┆┆86┆connections or the terminal may be damaged.↲
┆a1┆↲
↲
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↲
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┆06┆Figure 1: Testmode plug (KBL 721).↲
↲
┆84┆The V.24 bit is set/reset every time the RAM test has finished. ↓
If the SIO-test plug (CBL 998 see fig. 3) is installed in the ↓
V.24 output connection (SIO channel A), the bit is reset, ↓
otherwise it is set to indicate, that the testoutput is directed ↓
to the V.24 channel (1200 baud, 7 bit, 1 stopbit and even parity) ↓
too.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆2.2╞ Keyboard Management↲
↲
Valid keys are as follows:↲
↲
╞ ╞ H: set halt bit to 0↲
╞ ╞ R: set halt bit to 1↲
╞ ╞ G: set loop bit to 0↲
╞ ╞ L: set loop bit to 1↲
↲
┆84┆Numbers between 0-8 will insert a new test number into the ↓
test number variable. ↲
↲
All other keys will give no response.↲
↲
┆84┆If one for example wants to loop in test 6 and not go into a HALT ↓
state if error, then strike the keys R, L, 6 (not necessarily ↓
this sequence).↲
↲
┆a1┆┆84┆Note┆e1┆ it is the last valid key, which is pressed, that determines ↓
the test parameter or test number (e.g. if "L" and "G" is pressed ↓
in this sequence, the loop bit is reset.)↲
↲
┆84┆Relationship between the test numbers and actual test is as ↓
follows.↲
↲
╞ ┆a1┆test No╞ Test name↲
↲
╞ 0╞ RAM test↲
╞ 1 ╞ REFRESH test↲
╞ 2╞ KEYBOARD test↲
╞ 3╞ SIO test↲
╞ 4╞ RCCIRCUIT I test↲
╞ 5╞ CTC test↲
╞ 6╞ PARALLEL PORT test↲
╞ 7╞ DMA test↲
╞ 8╞ CRT test↲
↲
┆84┆↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆2.3╞ Output↲
↲
┆84┆The test router will respond with some output. After the RAM test ↓
has finished, a test menu (se fig. 2) is shown for a few seconds. ↓
This test menu shows the tests with the relational numbers and ↓
the possible test modes (looping, halt on error etc). By pressing ↓
the 'M' key will force the menu to retain on the screen. To ↓
continue press "RETURN". It also responds with a status line, in ↓
which the state of the test is shown. This could be either going, ↓
stopped, looping or halted. Furthermore the state of the 'HALT-↓
bit' (R-SWITCH/H-SWITCH) and a passcounter is shown. ↲
↲
RC45 testsystem version x.x↲
↲
┆19┆┄┄┆84┆┆e1┆ MENU╞ ╞ Select↲
╞ RAM_test:╞ ╞ 0↲
╞ Refresh_test:╞ 1↲
╞ Keyboard_test:╞ 2↲
╞ SIO_test:╞ ╞ 3↲
╞ RcCircuit1_test:╞ 4↲
╞ CTC_test:╞ ╞ 5↲
╞ Parallel_port_test:╞ 6↲
╞ DMA_test:╞ ╞ 7↲
╞ CRT_test:╞ ╞ 8↲
↲
╞ Looping in a selected test L↲
╞ Go through tests╞ G↲
╞ Run even if error╞ R↲
╞ Halt if error╞ H↲
↲
Select any combination from menu and type 'RETURN':↲
↲
┆06┆Figure 2: Test menu.↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆┆a1┆3.╞ THE MEMORY TEST↲
↲
┆84┆The memory test performs a test of the dynamic, if installed, and ↓
the static RAM memory. All memory cells but the upper 512 are ↓
tested by the memory test. Incorporated in the memory test is a ↓
checksum of the bootprom. This checksum is performed as the very ↓
first test.↲
↲
↲
┆a1┆3.1╞ Checksum test↲
↲
┆84┆The checksum is made on the 16K image of the bootprom. The ↓
checksum must end up with the sum 0.↲
↲
┆a1┆Text from this part of the memory test:↲
↲
╞ ╞ <RC45 rom error>↲
↲
↲
┆a1┆3.2╞ Ram test↲
↲
┆84┆First the memory addresses from 48 - 64 K (except for the upper ↓
512 bytes) is tested. If this addressroom is failurefree, the ↓
testsystem is moved to this memory area, and it is tested if the ↓
RAM from 0 - 48 K is installed. In this case this memory area is ↓
tested, and thereafter the testsystem is moved back.↲
↲
┆84┆The test pattern for the dynamic RAM memory consisting of chips ↓
of 4 bit x 16 k is three times 00 followed by three times FF ↓
(Hex). When all memory cells have been tested, they are again ↓
tested with the inverted pattern. This means that all bits are ↓
tested for "zero" and "one" insertion. ↲
↲
┆84┆┆a1┆If an error occurs, a message will be written:↲
↲
╞ ╞ <RC45 memory error ha la ex re>↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆where "ha" is high address, "la" is below address, "ex" is ↓
expected value and "re" is received value. All numbers are in ↓
hexadecimal notations. (To find any defective chip, consult fig. ↓
3).↲
↲
If the memory is found failurefree no message is written.↲
↲
┆84┆┆a1┆If an error occurs in the memory test (rom error or ram error) ↓
┆19┆┄┄┆84┆the test will stop hard i.e. it is not possible to continue the ↓
┆19┆┄┄┆84┆testsequence.↲
════════════════════════════════════════════════════════════════════════
↓
↲
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┆88┆┆81┆↲
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┆06┆Figure 3: Memory lay-out↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆4┆a1┆.╞ MEMORY REFRESH TEST↲
↲
The dynamic RAM refresh test is a test, which verifies the ↓
function of the CPU refresh counting. As an additional feature ↓
the test checks the battery circuit.↲
↲
┆84┆The test writes a pattern in memory consisting of an XOR of high ↓
and low address part. The pattern is written from the memory ↓
address 8000H until the hexadecimal address D500H (where the ↓
display image starts). If no dynamic RAM is installed, the test ↓
starts at memory address C000H.↲
↲
┆84┆When the pattern has been written, the test waits for 5 seconds ↓
in a waiting loop before it performs a check of the data.↲
↲
┆84┆The main purpose of this test is to discover modification of the ↓
data occurring in the delay time, due to malfunction of the ↓
refresh counting in the CPU. Note that the memory higher than ↓
C000H (48K) is static RAM and has no refresh counting.↲
↲
┆84┆┆a1┆Possible messages are:↲
↲
╞ <OK>↲
↲
╞ <data modified in byte xx xx exp: xx rec: xx>↲
↲
↲
┆a1┆4.1╞ Battery test↲
↲
┆84┆When the refresh counting is tested, the test checks 4 bytes in ↓
the NVM-area. If theese 4 bytes does not match a testpattern (00 ↓
FF 00 FF), the bytes will be initiated to this testpattern, and ↓
the text "battery test initiated" will be written. To check the ↓
battery circuit turn off and on the power and restart the ↓
testsytem. When performing the refresh test, the text "battery ↓
test initiated" must not appear. ┆a1┆Note that the test must be ↓
┆19┆┄┄┆84┆started with the testcable KBL 721 in the printerconnector, if ↓
┆19┆┄┄┆84┆this part of the test shall act correct.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆5.╞ KEYBOARD TEST┆e1┆↲
↲
┆84┆The keyboard contains a checksum test of the keyboard-PROM, a RAM ↓
test of keyboard-CPU and a scan test of the keyboard- matrix. ↓
Theese three tests can be activated by writing some specifically ↓
codes (keyboard-PROM test: 186, keyboard-RAM test: 184 and ↓
keyboard scan test: 188) to the keyboard. The keyboard will ↓
respond with OK (the same code) or not OK (the code + 1).↲
↲
┆a1┆Possible messages are:↲
↲
╞ <OK>↲
↲
╞ <romerror>↲
↲
╞ <ramerror>↲
↲
╞ <scanerror>↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆6.╞ SIO TEST↲
↲
┆84┆If the SIO-test plug (CBL 998) is inserted in the V.24 ↓
connection, the SIO test is performed.↲
↲
┆84┆The SIO test is testing the modem signals and data transports on ↓
SIO channel A.↲
↲
┆84┆Channel B see RCCIRCUIT I test.↓
↲
↲
┆a1┆6.1╞ Modem Signal Response↲
↲
┆84┆The responses of DTR and RTS are tested on the DCD and CTS pins. ↓
Test plug as shown in fig. 4 must be installed on the V.24 ↓
connection of the terminal.↲
↲
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↲
┆06┆Figure 4: CBL 998↲
↲
┆84┆If an error occurs on the modem signals CTS or DCD the received ↓
hex. value should be interpreted as shown in fig. 5↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆┆a1┆Error messages from this part of the test:↲
↲
╞ CTS or DCD error, exp: <xx> rec: <xx>↲
↲
Received value differs from expected; cf. fig. 5.↲
↲
↲
↲
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↲
┆06┆Figure 5: Modem signal response.↲
↲
↲
┆a1┆6.2╞ SIO Channel Test↲
↲
┆84┆When the modem signal responses have been checked, the SIO ↓
channel A is initiated.↲
↲
┆84┆The SIO channel is initiated to 19200 bps. Baud rate generator is ↓
the CTC.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆84┆A timer interrupt generated approx. 1760 times/s transmits the ↓
data from the transmit buffer. ↲
↲
┆84┆The channel transmit a databuffer of 1 k bytes consisting of a ↓
counting pattern (00 FF FE FD etc.). The test loop will check the ↓
received buffer, as soon as the pattern have been transfered. It ↓
also monitors the channel for timeout.↲
↲
┆a1┆Error messages from the SIO channel test:↲
↲
╞ ┆84┆<illegal interrupt, port: <xx>>↲
↲
┆84┆An interrupt has occured from a device that was not intended to ↓
interrupt, or the SIO has given a status interrupt (any change on ↓
the modem signals during data transfer will respond with this ↓
message).↲
↲
╞ <parity error>↲
↲
A special receive interrupt with parity bit has occured.↲
↲
╞ <data error, byte no: <xx xx> exp: <xx> rec: <xx>>↲
↲
The received buffer does not contain the expected pattern.↲
↲
╞ <receiver overrun>↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆7.╞ RCCIRCUIT I TEST↲
↲
┆84┆Before the test starts, it is tested, if Circuit 1 is installed.↲
↲
┆84┆The SIO channel B is initiated to full duplex and the DMA is ↓
initiated to receive 1K bytes from the SIO.↲
↲
┆84┆A timer interrupt generated approx. 1760 times/s transmits the ↓
data from the transmit buffer. ↲
↲
┆84┆The channel transmit a databuffer of 1 k bytes consisting of a ↓
counting pattern (00 FF FE FD etc.). The test loop will check the ↓
received buffer as soon as the pattern have been transfered. It ↓
also monitors the channel for timeout.↲
↲
┆84┆┆a1┆Possible messages are:↲
↲
╞ <OK>↲
↲
╞ <TIMEOUT>↲
↲
The data has not been transmitted completely.↲
↲
╞ <data error, byte no: <xx xx> exp: <xx> rec: <xx>>↲
↲
The received buffer does not contain the expected pattern.↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆8.╞ CTC TEST↲
↲
┆84┆This program tests the counter/timer circuit, which is used for ↓
baud rate generator and as interrupt circuit for the CRT and the ↓
keyboard.↲
↲
┆84┆┆84┆It is tested, that the circuit will generate interrupts, and that ↓
the vector (interrupt address) is correct.↲
↲
┆84┆The four channels 0, 1, 2, and 3 are tested. If two CTC's are ↓
installed also the channels 4, 5, 6 and 7 are tested. The ↓
channels are tested in the timer mode, and the timing starts ↓
automatically. The channel under test should be giving interrupt ↓
after approx. 423 mikro s. ↲
↲
┆84┆The test is based on a timeout loop, so it is checked if the ↓
interrupt was received within a specified time (3oo ms.). It is ↓
also checked that only the specified channel interrupts.↲
↲
┆84┆┆a1┆Possible messages are:↲
↲
╞ <OK>↲
↲
╞ ┆84┆<illegal interrupt, port: xx>↲
┆84┆meaning that another channel than the specified has interrupted.↲
↲
╞ ┆84┆<no interrupt, ch:>↲
┆84┆meaning that the test has timed out before interrupt was ↓
received.↲
↲
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆9.╞ PARALLEL PORT TEST┆e1┆↲
↲
┆84┆This test is a quick test of the three output signals (strobe, ↓
init and select) from the cpu to the port 19H routed back to port ↓
19H. All eight combinations are tested.↲
↲
┆a1┆Possible message are:↲
↲
╞ <OK>↲
↲
╞ <data error exp xx rec xx>↲
↲
↲
════════════════════════════════════════════════════════════════════════
↓
┆a1┆10.╞ DMA Test↲
↲
┆84┆At first it is tested if DMA is installed, before the test ↓
starts.↲
↲
┆84┆The DMA test is tested by a memory to memory transport. ↲
↲
┆84┆The transmitted pattern is a buffer of 1 k containing a counting ↓
pattern. The pattern is as follows: 00 FF FE FD etc. repeated 4 ↓
times.↲
↲
┆84┆When the transport is finished, the receiving buffer is checked ↓
against the transmitted buffer byte by byte.↲
↲
┆84┆If the transport is correct it is tested if the DMA can respond ↓
with an interrupt after end of block is reached.↲
↲
┆84┆┆a1┆Possible messages are:↲
↲
╞ ┆84┆<OK>↲
↲
╞ <not installed>↲
↲
╞ when testing transfer:↲
↲
╞ ╞ <End of Block timeout 200 ms>↲
╞ ╞ <data error, byte no: xx xx exp: xx rec: xx>↲
↲
╞ when testing interrupt:↲
↲
╞ ╞ <timeout>↲
↲
╞ ╞ <┆84┆data error, byte no: xx xx exp: xx rec: xx in ↓
┆19┆┆8f┆┄┄interrupt>↲
↲
┆84┆All numbers are in hexadecimal notation. "End of Block timeout ↓
200 ms" shows that the end of block bit in the DMA status ↓
register has not been set within 200 ms, and the transport is ↓
therefore not succesful.↲
↲
↓
════════════════════════════════════════════════════════════════════════
↓
┆a1┆11.╞ CRT TEST↲
↲
This is a visual test.↲
↲
┆84┆It is possibly to stop the test by pressing the "H" key. To ↓
continue press the "RETURN" KEY.↲
↲
The following should appear on the screen.↲
↲
The character-PROM is written.↲
↲
┆84┆Field attributes test. The field attributes are tested on the ↓
character-PROM. The 25 lines appear as follows:↲
↲
╞ ┆84┆a: 5 lines with highlight↲
b: 4 lines with reverse video+highlight↲
c: 4 lines with reverse video↲
d: 4 lines with invisible↲
e: 4 lines with underline↲
f: 4 lines with blink↲
↲
┆84┆The screen is filled with "H". To adjust the screen "H" ↓
is often used.↲
↲
┆84┆The contrast and brigthness are tested. First the contrast and ↓
then the brigtness are tested. For both, first maximum, then ↓
minimum and finally normally should appear.↲
↲
┆84┆If not a paperwhite monitor then the test ends up with the 132 ↓
character set written.↲
┆8c┆┆82┆┆e8┆↓
┆a1┆↲
════════════════════════════════════════════════════════════════════════
↓
┆1a┆┆1a┆ ┆1a┆┆1a┆ is a test, which verifies the ↓
funct
0x0000…0020 (0,) 00 00 00 00 00 00 00 00 42 03 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4e 00 00 00 ┆ B N ┆
0x0020…0040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ ┆
0x0040…0047 00 00 00 00 00 00 00 ┆ ┆
0x0047…0080 Params {
0x0047…0080 04 00 2d 4e 0a 00 06 00 00 00 00 03 01 3c 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ┆ -N <1 ┆
0x0047…0080 00 00 00 00 00 00 00 00 05 0f 19 23 2d 37 41 4b 55 5f 69 73 7d 87 91 ff 04 ┆ #-7AKU_iså ┆
0x0047…0080 }
0x0080…00a0 06 69 0d 0a 0d 0a a1 b0 54 41 42 4c 45 20 4f 46 20 43 4f 4e 54 45 4e 54 53 05 50 41 47 45 0d 0a ┆ i TABLE OF CONTENTS PAGE ┆
0x00a0…00c0 0d 0a 31 2e 20 20 49 4e 54 52 4f 44 55 43 54 49 4f 4e 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ 1. INTRODUCTION .............┆
0x00c0…00e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 31 0d 0a ┆.......................... 1 ┆
0x00e0…0100 0d 0a 32 2e 20 20 54 48 45 20 54 45 53 54 52 4f 55 54 45 52 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ 2. THE TESTROUTER ...........┆
0x0100…0120 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 32 0d 0a ┆.......................... 2 ┆
0x0120…0140 20 20 20 20 32 2e 31 20 53 77 69 74 63 68 20 50 61 72 61 6d 65 74 65 72 73 20 2e 2e 2e 2e 2e 2e ┆ 2.1 Switch Parameters ......┆
0x0140…0160 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 32 0d 0a 20 20 ┆........................ 2 ┆
0x0160…0180 20 20 32 2e 32 20 4b 65 79 62 6f 61 72 64 20 4d 61 6e 61 67 65 6d 65 6e 74 20 2e 2e 2e 2e 2e 2e ┆ 2.2 Keyboard Management ......┆
0x0180…01a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 34 0d 0a 20 20 20 20 ┆...................... 4 ┆
0x01a0…01c0 32 2e 33 20 4f 75 74 70 75 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆2.3 Output .....................┆
0x01c0…01e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 35 0d 0a 0d 0a 33 2e 20 20 ┆.................... 5 3. ┆
0x01e0…0200 54 48 45 20 4d 45 4d 4f 52 59 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆THE MEMORY TEST ................┆
0x0200…0220 (1,) 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 36 0d 0a 20 20 20 20 33 2e ┆.................... 6 3.┆
0x0220…0240 31 20 43 68 65 63 6b 73 75 6d 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆1 Checksum Test ................┆
0x0240…0260 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 36 0d 0a 20 20 20 20 33 2e 32 20 ┆.................. 6 3.2 ┆
0x0260…0280 52 61 6d 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆Ram Test .......................┆
0x0280…02a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 36 0d 0a 0d 0a 34 2e 20 20 4d 45 4d 4f ┆................ 6 4. MEMO┆
0x02a0…02c0 52 59 20 52 45 46 52 45 53 48 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆RY REFRESH TEST ................┆
0x02c0…02e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 39 0d 0a 20 20 20 20 34 2e 31 20 42 61 ┆................ 9 4.1 Ba┆
0x02e0…0300 74 74 65 72 79 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ttery Test .....................┆
0x0300…0320 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 20 39 0d 0a 0d 0a 35 2e 20 20 4b 45 59 42 4f 41 ┆.............. 9 5. KEYBOA┆
0x0320…0340 52 44 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆RD TEST ........................┆
0x0340…0360 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 30 0d 0a 0d 0a 36 2e 20 20 53 49 4f 20 54 45 ┆.............. 10 6. SIO TE┆
0x0360…0380 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ST .............................┆
0x0380…03a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 31 0d 0a 20 20 20 20 36 2e 31 20 4d 6f 64 65 ┆.............. 11 6.1 Mode┆
0x03a0…03c0 6d 20 53 69 67 6e 61 6c 20 52 65 73 70 6f 6e 73 65 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆m Signal Response ..............┆
0x03c0…03e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 31 0d 0a 20 20 20 20 36 2e 32 20 53 49 4f 20 43 68 ┆............ 11 6.2 SIO Ch┆
0x03e0…0400 61 6e 6e 65 6c 20 54 65 73 74 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆annel Test .....................┆
0x0400…0420 (2,) 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 32 0d 0a 0d 0a 37 2e 20 20 52 43 43 49 52 43 55 49 54 20 ┆.......... 12 7. RCCIRCUIT ┆
0x0420…0440 49 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆I TEST .........................┆
0x0440…0460 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 34 0d 0a 0d 0a 38 2e 20 20 43 54 43 20 54 45 53 54 20 2e ┆.......... 14 8. CTC TEST .┆
0x0460…0480 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0480…04a0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 35 0d 0a 0d 0a 39 2e 20 20 50 41 52 41 4c 4c 45 4c 20 50 ┆.......... 15 9. PARALLEL P┆
0x04a0…04c0 4f 52 54 20 54 45 53 54 20 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆ORT TEST .......................┆
0x04c0…04e0 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 36 0d 0a 0d 0a 31 30 2e 20 44 4d 41 20 54 45 53 54 20 2e ┆.......... 16 10. DMA TEST .┆
0x04e0…0500 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0500…0520 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 37 0d 0a 0d 0a 31 31 2e 20 43 52 54 20 54 45 53 54 20 2e ┆.......... 17 11. CRT TEST .┆
0x0520…0540 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e ┆................................┆
0x0540…0550 2e 2e 2e 2e 2e 2e 2e 2e 2e 2e 20 20 31 38 0d 0a ┆.......... 18 ┆
0x0550…0553 FormFeed {
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0x0553…055b 0a 06 69 69 0d 0a 0d 0a ┆ ii ┆
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0x055e…0560 0a 14 ┆ ┆
0x0560…0580 b3 06 0b 0d 0a a1 31 2e 20 20 49 4e 54 52 4f 44 55 43 54 49 4f 4e 0d 0a 0d 0a 84 54 68 69 73 20 ┆ 1. INTRODUCTION This ┆
0x0580…05a0 6d 61 6e 75 61 6c 20 64 65 73 63 72 69 62 65 73 20 74 68 65 20 64 69 61 67 6e 6f 73 74 69 63 20 ┆manual describes the diagnostic ┆
0x05a0…05c0 74 65 73 74 70 72 6f 67 72 61 6d 73 20 66 6f 72 20 74 68 65 20 52 43 34 35 20 0a 74 65 72 6d 69 ┆testprograms for the RC45 termi┆
0x05c0…05e0 6e 61 6c 73 79 73 74 65 6d 73 2e 0d 0a 0d 0a 84 54 68 65 20 74 65 73 74 70 72 6f 67 72 61 6d 73 ┆nalsystems. The testprograms┆
0x05e0…0600 20 61 72 65 20 74 65 73 74 69 6e 67 20 74 68 65 20 62 61 73 69 63 20 66 75 6e 63 74 69 6f 6e 73 ┆ are testing the basic functions┆
0x0600…0620 (3,) 20 6f 66 20 74 68 65 20 64 69 66 66 65 72 65 6e 74 20 0a 70 61 72 74 73 20 6f 66 20 74 68 65 20 ┆ of the different parts of the ┆
0x0620…0640 68 61 72 64 77 61 72 65 20 69 6e 20 74 68 65 20 74 65 72 6d 69 6e 61 6c 2e 0d 0a 0d 0a 84 84 54 ┆hardware in the terminal. T┆
0x0640…0660 68 65 20 73 65 71 75 65 6e 63 65 20 6f 66 20 74 68 65 20 64 69 66 66 65 72 65 6e 74 20 74 65 73 ┆he sequence of the different tes┆
0x0660…0680 74 70 72 6f 67 72 61 6d 73 20 69 6e 20 74 68 65 20 74 65 73 74 20 73 79 73 74 65 6d 73 20 69 73 ┆tprograms in the test systems is┆
0x0680…06a0 20 0a 6f 72 67 61 6e 69 7a 65 64 20 77 69 74 68 20 72 69 73 69 6e 67 20 63 6f 6d 70 6c 65 78 69 ┆ organized with rising complexi┆
0x06a0…06c0 74 79 2e 20 41 73 20 66 61 72 20 61 73 20 70 6f 73 73 69 62 6c 65 2c 20 6e 6f 20 70 61 72 74 20 ┆ty. As far as possible, no part ┆
0x06c0…06e0 6f 66 20 0a 74 68 65 20 68 61 72 64 77 61 72 65 20 69 73 20 75 73 65 64 20 62 65 66 6f 72 65 20 ┆of the hardware is used before ┆
0x06e0…06f3 69 74 20 69 73 20 74 65 73 74 65 64 2e 0d 0a 0d 0a 0d 0a ┆it is tested. ┆
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0x06f6…0700 0a a1 32 2e 09 54 48 45 20 54 ┆ 2. THE T┆
0x0700…0720 45 53 54 20 52 4f 55 54 45 52 0d 0a 0d 0a 84 54 68 65 20 74 65 73 74 20 72 6f 75 74 65 72 20 69 ┆EST ROUTER The test router i┆
0x0720…0740 73 20 74 68 65 20 6b 65 72 6e 61 6c 20 69 6e 20 74 68 65 20 74 65 73 74 73 79 73 74 65 6d 2c 20 ┆s the kernal in the testsystem, ┆
0x0740…0760 77 68 69 63 68 20 6d 61 69 6e 20 0a 70 75 72 70 6f 73 65 20 69 73 20 74 6f 20 63 6f 6d 70 75 74 ┆which main purpose is to comput┆
0x0760…0780 65 20 74 68 65 20 61 64 64 72 65 73 73 20 6f 66 20 74 68 65 20 6e 65 78 74 20 74 65 73 74 20 69 ┆e the address of the next test i┆
0x0780…07a0 6e 20 74 68 65 20 0a 73 65 71 75 65 6e 63 65 2e 20 54 68 65 20 61 64 64 72 65 73 73 20 6f 66 20 ┆n the sequence. The address of ┆
0x07a0…07c0 74 68 65 20 6e 65 78 74 20 74 65 73 74 20 69 73 20 64 65 72 69 76 65 64 20 66 72 6f 6d 20 61 20 ┆the next test is derived from a ┆
0x07c0…07e0 76 61 72 69 61 62 6c 65 20 0a 68 6f 6c 64 69 6e 67 20 74 68 65 20 70 72 65 73 65 6e 74 20 74 65 ┆variable holding the present te┆
0x07e0…0800 73 74 20 6e 75 6d 62 65 72 20 61 6e 64 20 6e 6f 72 6d 61 6c 6c 79 20 69 6e 63 72 65 6d 65 6e 74 ┆st number and normally increment┆
0x0800…0820 (4,) 65 64 20 62 79 20 6f 6e 65 2e 20 0a 45 76 65 72 79 20 74 69 6d 65 20 61 20 74 65 73 74 20 68 61 ┆ed by one. Every time a test ha┆
0x0820…0840 73 20 66 69 6e 69 73 68 65 64 20 61 6e 64 20 69 73 20 6e 6f 74 20 69 6e 20 6c 6f 6f 70 69 6e 67 ┆s finished and is not in looping┆
0x0840…0860 20 6d 6f 64 65 2c 20 74 68 65 20 0a 74 65 73 74 20 72 6f 75 74 65 72 20 69 73 20 65 6e 74 65 72 ┆ mode, the test router is enter┆
0x0860…0880 65 64 2e 0d 0a 0d 0a 0d 0a a1 32 2e 31 09 53 77 69 74 63 68 20 50 61 72 61 6d 65 74 65 72 73 0d ┆ed. 2.1 Switch Parameters ┆
0x0880…08a0 0a 0d 0a 84 54 68 65 20 76 61 72 69 61 62 6c 65 20 68 6f 6c 64 69 6e 67 20 74 68 65 20 74 65 73 ┆ The variable holding the tes┆
0x08a0…08c0 74 20 6e 75 6d 62 65 72 20 61 6c 73 6f 20 63 6f 6e 74 61 69 6e 73 20 66 6f 75 72 20 73 77 69 74 ┆t number also contains four swit┆
0x08c0…08e0 63 68 20 0a 62 69 74 73 2c 20 62 79 20 77 68 69 63 68 20 74 68 65 20 74 65 73 74 72 6f 75 74 65 ┆ch bits, by which the testroute┆
0x08e0…0900 72 20 64 65 63 69 64 65 73 20 68 6f 77 20 74 6f 20 61 64 6d 69 6e 69 73 74 65 72 20 74 68 65 20 ┆r decides how to administer the ┆
0x0900…0920 0a 74 65 73 74 73 2e 0d 0a 0d 0a 09 20 20 4d 53 42 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆ tests. MSB ┆
0x0920…0940 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 4c 53 42 0d 0a 09 2d 2d ┆ LSB --┆
0x0940…0960 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x0960…0980 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 0d 0a 09 21 20 20 20 20 20 21 20 20 20 20 20 21 20 ┆--------------- ! ! ! ┆
0x0980…09a0 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 ┆ ! ! ! ! ! ┆
0x09a0…09c0 20 20 21 0d 0a 09 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 20 ┆ ! ! ! ! ! ! ┆
0x09c0…09e0 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 0d 0a 09 21 20 20 20 20 20 ┆ ! ! ! ! ! ┆
0x09e0…0a00 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 20 ┆! ! ! ! ! ! ┆
0x0a00…0a20 (5,) 20 20 20 20 21 20 20 20 20 20 21 0d 0a 09 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ ! ! ------------------┆
0x0a20…0a40 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 0d ┆------------------------------- ┆
0x0a40…0a60 0a 20 20 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 ┆ ! ! ! ! ┆
0x0a60…0a80 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 0d 0a 20 20 20 20 20 20 20 21 20 20 20 ┆! ! ! ! ! ┆
0x0a80…0aa0 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 20 20 20 20 20 21 2d 2d 2d 2d 2d 21 2d 2d 2d 2d 2d ┆ ! ! ! !-----!-----┆
0x0aa0…0ac0 21 2d 2d 2d 2d 2d 21 2d 2d 74 65 73 74 20 6e 6f 2e 0d 0a 20 20 20 20 20 20 20 21 20 20 20 20 20 ┆!-----!--test no. ! ┆
0x0ac0…0ae0 21 20 20 20 20 20 21 20 20 20 20 20 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆! ! !-------------------┆
0x0ae0…0b00 2d 2d 2d 2d 2d 2d 2d 75 73 65 20 56 2e 32 34 0d 0a 20 20 20 20 20 20 20 21 20 20 20 20 20 21 20 ┆-------use V.24 ! ! ┆
0x0b00…0b20 20 20 20 20 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆ !---------------------------┆
0x0b20…0b40 2d 2d 2d 2d 2d 65 78 74 2e 20 74 65 73 74 0d 0a 20 20 20 20 20 20 20 21 20 20 20 20 20 21 2d 2d ┆-----ext. test ! !--┆
0x0b40…0b60 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆--------------------------------┆
0x0b60…0b80 2d 2d 2d 2d 6c 6f 6f 70 0d 0a 20 20 20 20 20 20 20 21 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d ┆----loop !--------------┆
0x0b80…0ba0 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 2d 68 61 ┆------------------------------ha┆
0x0ba0…0bc0 6c 74 0d 0a 0d 0a 68 61 6c 74 3a 09 30 3a 20 68 61 6c 74 20 69 66 20 65 72 72 6f 72 20 28 64 65 ┆lt halt: 0: halt if error (de┆
0x0bc0…0be0 66 61 75 6c 74 29 0d 0a 09 09 31 3a 20 70 72 6f 63 65 65 64 20 65 76 65 6e 20 69 66 20 65 72 72 ┆fault) 1: proceed even if err┆
0x0be0…0c00 6f 72 0d 0a 0d 0a 6c 6f 6f 70 3a 09 30 3a 20 73 65 71 75 65 6e 74 69 61 6c 2c 20 62 69 67 20 6c ┆or loop: 0: sequential, big l┆
0x0c00…0c20 (6,) 6f 6f 70 20 61 66 20 61 6c 6c 20 74 65 73 74 73 20 28 64 65 66 61 75 6c 74 29 0d 0a 09 09 31 3a ┆oop af all tests (default) 1:┆
0x0c20…0c40 20 6c 6f 6f 70 69 6e 67 20 69 6e 20 61 20 73 65 6c 65 63 74 65 64 20 74 65 73 74 0d 0a 0d 0a 65 ┆ looping in a selected test e┆
0x0c40…0c60 78 74 2e 20 74 65 73 74 3a 09 30 3a 20 70 6f 77 65 72 2d 75 70 20 74 65 73 74 0d 0a 09 09 31 3a ┆xt. test: 0: power-up test 1:┆
0x0c60…0c72 20 65 78 74 65 6e 64 65 64 20 74 65 73 74 0d 0a 0d 0a ┆ extended test ┆
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0x0c75…0c80 0a 56 2e 32 34 3a 09 30 3a 20 74 ┆ V.24: 0: t┆
0x0c80…0ca0 65 73 74 20 70 6c 75 67 20 69 6e 20 74 68 65 20 56 2e 32 34 20 63 6f 6e 6e 65 63 74 69 6f 6e 0d ┆est plug in the V.24 connection ┆
0x0ca0…0cc0 0a 09 09 31 3a 20 84 6e 6f 20 74 65 73 74 20 70 6c 75 67 20 69 6e 20 74 68 65 20 56 2e 32 34 20 ┆ 1: no test plug in the V.24 ┆
0x0cc0…0ce0 63 6f 6e 6e 65 63 74 69 6f 6e 2e 20 54 68 65 20 63 68 61 6e 6e 65 6c 20 0a 19 91 80 80 69 73 20 ┆connection. The channel is ┆
0x0ce0…0d00 75 73 65 64 20 61 73 20 56 2e 32 34 20 6f 75 74 70 75 74 20 28 31 32 30 30 20 62 61 75 64 2c 20 ┆used as V.24 output (1200 baud, ┆
0x0d00…0d20 37 20 62 69 74 2c 20 31 20 0a 19 91 80 80 73 74 6f 70 62 69 74 29 0d 0a 0d 0a 84 54 68 65 20 48 ┆7 bit, 1 stopbit) The H┆
0x0d20…0d40 41 4c 54 20 61 6e 64 20 4c 4f 4f 50 20 62 69 74 73 20 61 72 65 20 69 6e 69 74 69 61 74 65 64 20 ┆ALT and LOOP bits are initiated ┆
0x0d40…0d60 74 6f 20 7a 65 72 6f 2e 0d 0a 0d 0a 84 54 68 65 20 74 65 73 74 20 6d 6f 64 65 20 62 69 74 20 69 ┆to zero. The test mode bit i┆
0x0d60…0d80 73 20 73 65 74 20 74 6f 20 6f 6e 65 2c 20 69 66 20 74 68 65 20 74 65 73 74 20 70 6c 75 67 20 28 ┆s set to one, if the test plug (┆
0x0d80…0da0 4b 42 4c 20 37 32 31 29 20 69 73 20 0a 69 6e 73 74 61 6c 6c 65 64 20 69 6e 20 74 68 65 20 70 61 ┆KBL 721) is installed in the pa┆
0x0da0…0dc0 72 61 6c 6c 65 6c 20 70 72 69 6e 74 65 72 20 63 6f 6e 6e 65 63 74 69 6f 6e 20 28 4a 33 29 20 6f ┆rallel printer connection (J3) o┆
0x0dc0…0de0 72 20 69 66 20 74 68 65 20 0a 27 54 45 53 54 27 20 6b 65 79 20 69 73 20 70 72 65 73 73 65 64 20 ┆r if the 'TEST' key is pressed ┆
0x0de0…0e00 69 6d 6d 65 64 69 61 74 65 6c 79 20 61 66 74 65 72 20 70 6f 77 65 72 2d 75 70 20 74 65 73 74 2c ┆immediately after power-up test,┆
0x0e00…0e20 (7,) 20 77 68 65 6e 20 74 68 65 20 0a 52 43 20 6c 6f 67 6f 20 61 70 70 65 61 72 73 20 69 6e 20 74 68 ┆ when the RC logo appears in th┆
0x0e20…0e40 65 20 6c 6f 77 65 72 20 6c 65 66 74 20 63 6f 72 6e 65 72 2e 0d 0a 0d 0a a1 b0 57 41 52 4e 49 4e ┆e lower left corner. WARNIN┆
0x0e40…0e60 47 21 20 42 65 20 61 77 61 72 65 20 6f 66 20 63 6f 6e 6e 65 63 74 69 6e 67 20 74 68 65 20 70 6c ┆G! Be aware of connecting the pl┆
0x0e60…0e80 75 67 73 20 69 6e 20 74 68 65 20 72 69 67 68 74 20 0a 19 80 81 86 63 6f 6e 6e 65 63 74 69 6f 6e ┆ugs in the right connection┆
0x0e80…0ea0 73 20 6f 72 20 74 68 65 20 74 65 72 6d 69 6e 61 6c 20 6d 61 79 20 62 65 20 64 61 6d 61 67 65 64 ┆s or the terminal may be damaged┆
0x0ea0…0ec0 2e 0d 0a a1 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a ┆. ┆
0x0ec0…0ee0 0d 0a 0d 0a 0d 0a 0d 0a 06 46 69 67 75 72 65 20 31 3a 20 54 65 73 74 6d 6f 64 65 20 70 6c 75 67 ┆ Figure 1: Testmode plug┆
0x0ee0…0f00 20 28 4b 42 4c 20 37 32 31 29 2e 0d 0a 0d 0a 84 54 68 65 20 56 2e 32 34 20 62 69 74 20 69 73 20 ┆ (KBL 721). The V.24 bit is ┆
0x0f00…0f20 73 65 74 2f 72 65 73 65 74 20 65 76 65 72 79 20 74 69 6d 65 20 74 68 65 20 52 41 4d 20 74 65 73 ┆set/reset every time the RAM tes┆
0x0f20…0f40 74 20 68 61 73 20 66 69 6e 69 73 68 65 64 2e 20 0a 49 66 20 74 68 65 20 53 49 4f 2d 74 65 73 74 ┆t has finished. If the SIO-test┆
0x0f40…0f60 20 70 6c 75 67 20 28 43 42 4c 20 39 39 38 20 73 65 65 20 66 69 67 2e 20 33 29 20 69 73 20 69 6e ┆ plug (CBL 998 see fig. 3) is in┆
0x0f60…0f80 73 74 61 6c 6c 65 64 20 69 6e 20 74 68 65 20 0a 56 2e 32 34 20 6f 75 74 70 75 74 20 63 6f 6e 6e ┆stalled in the V.24 output conn┆
0x0f80…0fa0 65 63 74 69 6f 6e 20 28 53 49 4f 20 63 68 61 6e 6e 65 6c 20 41 29 2c 20 74 68 65 20 62 69 74 20 ┆ection (SIO channel A), the bit ┆
0x0fa0…0fc0 69 73 20 72 65 73 65 74 2c 20 0a 6f 74 68 65 72 77 69 73 65 20 69 74 20 69 73 20 73 65 74 20 74 ┆is reset, otherwise it is set t┆
0x0fc0…0fe0 6f 20 69 6e 64 69 63 61 74 65 2c 20 74 68 61 74 20 74 68 65 20 74 65 73 74 6f 75 74 70 75 74 20 ┆o indicate, that the testoutput ┆
0x0fe0…1000 69 73 20 64 69 72 65 63 74 65 64 20 0a 74 6f 20 74 68 65 20 56 2e 32 34 20 63 68 61 6e 6e 65 6c ┆is directed to the V.24 channel┆
0x1000…1020 (8,) 20 28 31 32 30 30 20 62 61 75 64 2c 20 37 20 62 69 74 2c 20 31 20 73 74 6f 70 62 69 74 20 61 6e ┆ (1200 baud, 7 bit, 1 stopbit an┆
0x1020…103a 64 20 65 76 65 6e 20 70 61 72 69 74 79 29 20 0a 74 6f 6f 2e 0d 0a 0d 0a 0d 0a ┆d even parity) too. ┆
0x103a…103d FormFeed {
0x103a…103d 0c 83 f8 ┆ ┆
0x103a…103d }
0x103d…1040 0a a1 32 ┆ 2┆
0x1040…1060 2e 32 09 4b 65 79 62 6f 61 72 64 20 4d 61 6e 61 67 65 6d 65 6e 74 0d 0a 0d 0a 56 61 6c 69 64 20 ┆.2 Keyboard Management Valid ┆
0x1060…1080 6b 65 79 73 20 61 72 65 20 61 73 20 66 6f 6c 6c 6f 77 73 3a 0d 0a 0d 0a 09 09 48 3a 20 73 65 74 ┆keys are as follows: H: set┆
0x1080…10a0 20 68 61 6c 74 20 62 69 74 20 74 6f 20 30 0d 0a 09 09 52 3a 20 73 65 74 20 68 61 6c 74 20 62 69 ┆ halt bit to 0 R: set halt bi┆
0x10a0…10c0 74 20 74 6f 20 31 0d 0a 09 09 47 3a 20 73 65 74 20 6c 6f 6f 70 20 62 69 74 20 74 6f 20 30 0d 0a ┆t to 1 G: set loop bit to 0 ┆
0x10c0…10e0 09 09 4c 3a 20 73 65 74 20 6c 6f 6f 70 20 62 69 74 20 74 6f 20 31 0d 0a 0d 0a 84 4e 75 6d 62 65 ┆ L: set loop bit to 1 Numbe┆
0x10e0…1100 72 73 20 62 65 74 77 65 65 6e 20 30 2d 38 20 77 69 6c 6c 20 69 6e 73 65 72 74 20 61 20 6e 65 77 ┆rs between 0-8 will insert a new┆
0x1100…1120 20 74 65 73 74 20 6e 75 6d 62 65 72 20 69 6e 74 6f 20 74 68 65 20 0a 74 65 73 74 20 6e 75 6d 62 ┆ test number into the test numb┆
0x1120…1140 65 72 20 76 61 72 69 61 62 6c 65 2e 20 0d 0a 0d 0a 41 6c 6c 20 6f 74 68 65 72 20 6b 65 79 73 20 ┆er variable. All other keys ┆
0x1140…1160 77 69 6c 6c 20 67 69 76 65 20 6e 6f 20 72 65 73 70 6f 6e 73 65 2e 0d 0a 0d 0a 84 49 66 20 6f 6e ┆will give no response. If on┆
0x1160…1180 65 20 66 6f 72 20 65 78 61 6d 70 6c 65 20 77 61 6e 74 73 20 74 6f 20 6c 6f 6f 70 20 69 6e 20 74 ┆e for example wants to loop in t┆
0x1180…11a0 65 73 74 20 36 20 61 6e 64 20 6e 6f 74 20 67 6f 20 69 6e 74 6f 20 61 20 48 41 4c 54 20 0a 73 74 ┆est 6 and not go into a HALT st┆
0x11a0…11c0 61 74 65 20 69 66 20 65 72 72 6f 72 2c 20 74 68 65 6e 20 73 74 72 69 6b 65 20 74 68 65 20 6b 65 ┆ate if error, then strike the ke┆
0x11c0…11e0 79 73 20 52 2c 20 4c 2c 20 36 20 28 6e 6f 74 20 6e 65 63 65 73 73 61 72 69 6c 79 20 0a 74 68 69 ┆ys R, L, 6 (not necessarily thi┆
0x11e0…1200 73 20 73 65 71 75 65 6e 63 65 29 2e 0d 0a 0d 0a a1 84 4e 6f 74 65 e1 20 69 74 20 69 73 20 74 68 ┆s sequence). Note it is th┆
0x1200…1220 (9,) 65 20 6c 61 73 74 20 76 61 6c 69 64 20 6b 65 79 2c 20 77 68 69 63 68 20 69 73 20 70 72 65 73 73 ┆e last valid key, which is press┆
0x1220…1240 65 64 2c 20 74 68 61 74 20 64 65 74 65 72 6d 69 6e 65 73 20 0a 74 68 65 20 74 65 73 74 20 70 61 ┆ed, that determines the test pa┆
0x1240…1260 72 61 6d 65 74 65 72 20 6f 72 20 74 65 73 74 20 6e 75 6d 62 65 72 20 28 65 2e 67 2e 20 69 66 20 ┆rameter or test number (e.g. if ┆
0x1260…1280 22 4c 22 20 61 6e 64 20 22 47 22 20 69 73 20 70 72 65 73 73 65 64 20 0a 69 6e 20 74 68 69 73 20 ┆"L" and "G" is pressed in this ┆
0x1280…12a0 73 65 71 75 65 6e 63 65 2c 20 74 68 65 20 6c 6f 6f 70 20 62 69 74 20 69 73 20 72 65 73 65 74 2e ┆sequence, the loop bit is reset.┆
0x12a0…12c0 29 0d 0a 0d 0a 84 52 65 6c 61 74 69 6f 6e 73 68 69 70 20 62 65 74 77 65 65 6e 20 74 68 65 20 74 ┆) Relationship between the t┆
0x12c0…12e0 65 73 74 20 6e 75 6d 62 65 72 73 20 61 6e 64 20 61 63 74 75 61 6c 20 74 65 73 74 20 69 73 20 61 ┆est numbers and actual test is a┆
0x12e0…1300 73 20 0a 66 6f 6c 6c 6f 77 73 2e 0d 0a 0d 0a 09 a1 74 65 73 74 20 4e 6f 09 54 65 73 74 20 6e 61 ┆s follows. test No Test na┆
0x1300…1320 6d 65 0d 0a 0d 0a 09 20 20 30 09 52 41 4d 20 74 65 73 74 0d 0a 09 20 20 31 20 20 20 09 52 45 46 ┆me 0 RAM test 1 REF┆
0x1320…1340 52 45 53 48 20 74 65 73 74 0d 0a 09 20 20 32 09 4b 45 59 42 4f 41 52 44 20 74 65 73 74 0d 0a 09 ┆RESH test 2 KEYBOARD test ┆
0x1340…1360 20 20 33 09 53 49 4f 20 74 65 73 74 0d 0a 09 20 20 34 09 52 43 43 49 52 43 55 49 54 20 49 20 74 ┆ 3 SIO test 4 RCCIRCUIT I t┆
0x1360…1380 65 73 74 0d 0a 09 20 20 35 09 43 54 43 20 74 65 73 74 0d 0a 09 20 20 36 09 50 41 52 41 4c 4c 45 ┆est 5 CTC test 6 PARALLE┆
0x1380…13a0 4c 20 50 4f 52 54 20 74 65 73 74 0d 0a 09 20 20 37 09 44 4d 41 20 74 65 73 74 0d 0a 09 20 20 38 ┆L PORT test 7 DMA test 8┆
0x13a0…13b0 09 43 52 54 20 74 65 73 74 0d 0a 0d 0a 84 0d 0a ┆ CRT test ┆
0x13b0…13b3 FormFeed {
0x13b0…13b3 0c 83 c8 ┆ ┆
0x13b0…13b3 }
0x13b3…13c0 0a a1 32 2e 33 09 4f 75 74 70 75 74 0d ┆ 2.3 Output ┆
0x13c0…13e0 0a 0d 0a 84 54 68 65 20 74 65 73 74 20 72 6f 75 74 65 72 20 77 69 6c 6c 20 72 65 73 70 6f 6e 64 ┆ The test router will respond┆
0x13e0…1400 20 77 69 74 68 20 73 6f 6d 65 20 6f 75 74 70 75 74 2e 20 41 66 74 65 72 20 74 68 65 20 52 41 4d ┆ with some output. After the RAM┆
0x1400…1420 (10,) 20 74 65 73 74 20 0a 68 61 73 20 66 69 6e 69 73 68 65 64 2c 20 61 20 74 65 73 74 20 6d 65 6e 75 ┆ test has finished, a test menu┆
0x1420…1440 20 28 73 65 20 66 69 67 2e 20 32 29 20 69 73 20 73 68 6f 77 6e 20 66 6f 72 20 61 20 66 65 77 20 ┆ (se fig. 2) is shown for a few ┆
0x1440…1460 73 65 63 6f 6e 64 73 2e 20 0a 54 68 69 73 20 74 65 73 74 20 6d 65 6e 75 20 73 68 6f 77 73 20 74 ┆seconds. This test menu shows t┆
0x1460…1480 68 65 20 74 65 73 74 73 20 77 69 74 68 20 74 68 65 20 72 65 6c 61 74 69 6f 6e 61 6c 20 6e 75 6d ┆he tests with the relational num┆
0x1480…14a0 62 65 72 73 20 61 6e 64 20 0a 74 68 65 20 70 6f 73 73 69 62 6c 65 20 74 65 73 74 20 6d 6f 64 65 ┆bers and the possible test mode┆
0x14a0…14c0 73 20 28 6c 6f 6f 70 69 6e 67 2c 20 68 61 6c 74 20 6f 6e 20 65 72 72 6f 72 20 65 74 63 29 2e 20 ┆s (looping, halt on error etc). ┆
0x14c0…14e0 42 79 20 70 72 65 73 73 69 6e 67 20 0a 74 68 65 20 27 4d 27 20 6b 65 79 20 77 69 6c 6c 20 66 6f ┆By pressing the 'M' key will fo┆
0x14e0…1500 72 63 65 20 74 68 65 20 6d 65 6e 75 20 74 6f 20 72 65 74 61 69 6e 20 6f 6e 20 74 68 65 20 73 63 ┆rce the menu to retain on the sc┆
0x1500…1520 72 65 65 6e 2e 20 54 6f 20 0a 63 6f 6e 74 69 6e 75 65 20 70 72 65 73 73 20 22 52 45 54 55 52 4e ┆reen. To continue press "RETURN┆
0x1520…1540 22 2e 20 49 74 20 61 6c 73 6f 20 72 65 73 70 6f 6e 64 73 20 77 69 74 68 20 61 20 73 74 61 74 75 ┆". It also responds with a statu┆
0x1540…1560 73 20 6c 69 6e 65 2c 20 69 6e 20 0a 77 68 69 63 68 20 74 68 65 20 73 74 61 74 65 20 6f 66 20 74 ┆s line, in which the state of t┆
0x1560…1580 68 65 20 74 65 73 74 20 69 73 20 73 68 6f 77 6e 2e 20 54 68 69 73 20 63 6f 75 6c 64 20 62 65 20 ┆he test is shown. This could be ┆
0x1580…15a0 65 69 74 68 65 72 20 67 6f 69 6e 67 2c 20 0a 73 74 6f 70 70 65 64 2c 20 6c 6f 6f 70 69 6e 67 20 ┆either going, stopped, looping ┆
0x15a0…15c0 6f 72 20 68 61 6c 74 65 64 2e 20 46 75 72 74 68 65 72 6d 6f 72 65 20 74 68 65 20 73 74 61 74 65 ┆or halted. Furthermore the state┆
0x15c0…15e0 20 6f 66 20 74 68 65 20 27 48 41 4c 54 2d 0a 62 69 74 27 20 28 52 2d 53 57 49 54 43 48 2f 48 2d ┆ of the 'HALT- bit' (R-SWITCH/H-┆
0x15e0…1600 53 57 49 54 43 48 29 20 61 6e 64 20 61 20 70 61 73 73 63 6f 75 6e 74 65 72 20 69 73 20 73 68 6f ┆SWITCH) and a passcounter is sho┆
0x1600…1620 (11,) 77 6e 2e 20 0d 0a 0d 0a 52 43 34 35 20 74 65 73 74 73 79 73 74 65 6d 20 76 65 72 73 69 6f 6e 20 ┆wn. RC45 testsystem version ┆
0x1620…1640 78 2e 78 0d 0a 0d 0a 19 80 80 84 e1 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆x.x ┆
0x1640…1660 20 4d 45 4e 55 09 09 20 20 20 20 20 20 53 65 6c 65 63 74 0d 0a 09 20 20 20 20 20 20 20 20 20 20 ┆ MENU Select ┆
0x1660…1680 20 20 20 20 20 20 20 52 41 4d 5f 74 65 73 74 3a 09 09 20 20 20 20 20 20 30 0d 0a 09 20 20 20 20 ┆ RAM_test: 0 ┆
0x1680…16a0 20 20 20 20 20 20 20 20 20 20 20 20 20 52 65 66 72 65 73 68 5f 74 65 73 74 3a 09 20 20 20 20 20 ┆ Refresh_test: ┆
0x16a0…16c0 20 31 0d 0a 09 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 4b 65 79 62 6f 61 72 64 5f 74 ┆ 1 Keyboard_t┆
0x16c0…16e0 65 73 74 3a 09 20 20 20 20 20 20 32 0d 0a 09 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆est: 2 ┆
0x16e0…1700 53 49 4f 5f 74 65 73 74 3a 09 09 20 20 20 20 20 20 33 0d 0a 09 20 20 20 20 20 20 20 20 20 20 20 ┆SIO_test: 3 ┆
0x1700…1720 20 20 20 20 20 20 52 63 43 69 72 63 75 69 74 31 5f 74 65 73 74 3a 09 20 20 20 20 20 20 34 0d 0a ┆ RcCircuit1_test: 4 ┆
0x1720…1740 09 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 43 54 43 5f 74 65 73 74 3a 09 20 20 20 09 ┆ CTC_test: ┆
0x1740…1760 20 20 20 20 20 20 35 0d 0a 09 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 50 61 72 61 6c ┆ 5 Paral┆
0x1760…1780 6c 65 6c 5f 70 6f 72 74 5f 74 65 73 74 3a 09 20 20 20 20 20 20 36 0d 0a 09 20 20 20 20 20 20 20 ┆lel_port_test: 6 ┆
0x1780…17a0 20 20 20 20 20 20 20 20 20 20 44 4d 41 5f 74 65 73 74 3a 09 09 20 20 20 20 20 20 37 0d 0a 09 20 ┆ DMA_test: 7 ┆
0x17a0…17c0 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 43 52 54 5f 74 65 73 74 3a 09 09 20 20 20 20 20 ┆ CRT_test: ┆
0x17c0…17e0 20 38 0d 0a 0d 0a 09 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 4c 6f 6f 70 69 6e 67 20 ┆ 8 Looping ┆
0x17e0…1800 69 6e 20 61 20 73 65 6c 65 63 74 65 64 20 74 65 73 74 20 20 20 4c 0d 0a 09 20 20 20 20 20 20 20 ┆in a selected test L ┆
0x1800…1820 (12,) 20 20 20 20 20 20 20 20 20 20 47 6f 20 74 68 72 6f 75 67 68 20 74 65 73 74 73 09 20 20 20 20 20 ┆ Go through tests ┆
0x1820…1840 20 47 0d 0a 09 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 52 75 6e 20 65 76 65 6e 20 69 ┆ G Run even i┆
0x1840…1860 66 20 65 72 72 6f 72 09 20 20 20 20 20 20 52 0d 0a 09 20 20 20 20 20 20 20 20 20 20 20 20 20 20 ┆f error R ┆
0x1860…1880 20 20 20 48 61 6c 74 20 69 66 20 65 72 72 6f 72 09 20 20 20 20 20 20 48 0d 0a 0d 0a 53 65 6c 65 ┆ Halt if error H Sele┆
0x1880…18a0 63 74 20 61 6e 79 20 63 6f 6d 62 69 6e 61 74 69 6f 6e 20 66 72 6f 6d 20 6d 65 6e 75 20 61 6e 64 ┆ct any combination from menu and┆
0x18a0…18c0 20 74 79 70 65 20 27 52 45 54 55 52 4e 27 3a 0d 0a 0d 0a 06 46 69 67 75 72 65 20 32 3a 20 54 65 ┆ type 'RETURN': Figure 2: Te┆
0x18c0…18ce 73 74 20 6d 65 6e 75 2e 0d 0a 0d 0a 0d 0a ┆st menu. ┆
0x18ce…18d1 FormFeed {
0x18ce…18d1 0c 83 a4 ┆ ┆
0x18ce…18d1 }
0x18d1…18e0 0a a1 a1 33 2e 09 54 48 45 20 4d 45 4d 4f 52 ┆ 3. THE MEMOR┆
0x18e0…1900 59 20 54 45 53 54 0d 0a 0d 0a 84 54 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 70 65 72 66 6f ┆Y TEST The memory test perfo┆
0x1900…1920 72 6d 73 20 61 20 74 65 73 74 20 6f 66 20 74 68 65 20 64 79 6e 61 6d 69 63 2c 20 69 66 20 69 6e ┆rms a test of the dynamic, if in┆
0x1920…1940 73 74 61 6c 6c 65 64 2c 20 61 6e 64 20 0a 74 68 65 20 73 74 61 74 69 63 20 52 41 4d 20 6d 65 6d ┆stalled, and the static RAM mem┆
0x1940…1960 6f 72 79 2e 20 41 6c 6c 20 6d 65 6d 6f 72 79 20 63 65 6c 6c 73 20 62 75 74 20 74 68 65 20 75 70 ┆ory. All memory cells but the up┆
0x1960…1980 70 65 72 20 35 31 32 20 61 72 65 20 0a 74 65 73 74 65 64 20 62 79 20 74 68 65 20 6d 65 6d 6f 72 ┆per 512 are tested by the memor┆
0x1980…19a0 79 20 74 65 73 74 2e 20 49 6e 63 6f 72 70 6f 72 61 74 65 64 20 69 6e 20 74 68 65 20 6d 65 6d 6f ┆y test. Incorporated in the memo┆
0x19a0…19c0 72 79 20 74 65 73 74 20 69 73 20 61 20 0a 63 68 65 63 6b 73 75 6d 20 6f 66 20 74 68 65 20 62 6f ┆ry test is a checksum of the bo┆
0x19c0…19e0 6f 74 70 72 6f 6d 2e 20 54 68 69 73 20 63 68 65 63 6b 73 75 6d 20 69 73 20 70 65 72 66 6f 72 6d ┆otprom. This checksum is perform┆
0x19e0…1a00 65 64 20 61 73 20 74 68 65 20 76 65 72 79 20 0a 66 69 72 73 74 20 74 65 73 74 2e 0d 0a 0d 0a 0d ┆ed as the very first test. ┆
0x1a00…1a20 (13,) 0a a1 33 2e 31 09 43 68 65 63 6b 73 75 6d 20 74 65 73 74 0d 0a 0d 0a 84 54 68 65 20 63 68 65 63 ┆ 3.1 Checksum test The chec┆
0x1a20…1a40 6b 73 75 6d 20 69 73 20 6d 61 64 65 20 6f 6e 20 74 68 65 20 31 36 4b 20 69 6d 61 67 65 20 6f 66 ┆ksum is made on the 16K image of┆
0x1a40…1a60 20 74 68 65 20 62 6f 6f 74 70 72 6f 6d 2e 20 54 68 65 20 0a 63 68 65 63 6b 73 75 6d 20 6d 75 73 ┆ the bootprom. The checksum mus┆
0x1a60…1a80 74 20 65 6e 64 20 75 70 20 77 69 74 68 20 74 68 65 20 73 75 6d 20 30 2e 0d 0a 0d 0a a1 54 65 78 ┆t end up with the sum 0. Tex┆
0x1a80…1aa0 74 20 66 72 6f 6d 20 74 68 69 73 20 70 61 72 74 20 6f 66 20 74 68 65 20 6d 65 6d 6f 72 79 20 74 ┆t from this part of the memory t┆
0x1aa0…1ac0 65 73 74 3a 0d 0a 0d 0a 09 09 3c 52 43 34 35 20 72 6f 6d 20 65 72 72 6f 72 3e 0d 0a 0d 0a 0d 0a ┆est: <RC45 rom error> ┆
0x1ac0…1ae0 a1 33 2e 32 09 52 61 6d 20 74 65 73 74 0d 0a 0d 0a 84 46 69 72 73 74 20 74 68 65 20 6d 65 6d 6f ┆ 3.2 Ram test First the memo┆
0x1ae0…1b00 72 79 20 61 64 64 72 65 73 73 65 73 20 66 72 6f 6d 20 34 38 20 2d 20 36 34 20 4b 20 28 65 78 63 ┆ry addresses from 48 - 64 K (exc┆
0x1b00…1b20 65 70 74 20 66 6f 72 20 74 68 65 20 75 70 70 65 72 20 0a 35 31 32 20 62 79 74 65 73 29 20 69 73 ┆ept for the upper 512 bytes) is┆
0x1b20…1b40 20 74 65 73 74 65 64 2e 20 49 66 20 74 68 69 73 20 61 64 64 72 65 73 73 72 6f 6f 6d 20 69 73 20 ┆ tested. If this addressroom is ┆
0x1b40…1b60 66 61 69 6c 75 72 65 66 72 65 65 2c 20 74 68 65 20 0a 74 65 73 74 73 79 73 74 65 6d 20 69 73 20 ┆failurefree, the testsystem is ┆
0x1b60…1b80 6d 6f 76 65 64 20 74 6f 20 74 68 69 73 20 6d 65 6d 6f 72 79 20 61 72 65 61 2c 20 61 6e 64 20 69 ┆moved to this memory area, and i┆
0x1b80…1ba0 74 20 69 73 20 74 65 73 74 65 64 20 69 66 20 74 68 65 20 0a 52 41 4d 20 66 72 6f 6d 20 30 20 2d ┆t is tested if the RAM from 0 -┆
0x1ba0…1bc0 20 34 38 20 4b 20 69 73 20 69 6e 73 74 61 6c 6c 65 64 2e 20 49 6e 20 74 68 69 73 20 63 61 73 65 ┆ 48 K is installed. In this case┆
0x1bc0…1be0 20 74 68 69 73 20 6d 65 6d 6f 72 79 20 61 72 65 61 20 69 73 20 0a 74 65 73 74 65 64 2c 20 61 6e ┆ this memory area is tested, an┆
0x1be0…1c00 64 20 74 68 65 72 65 61 66 74 65 72 20 74 68 65 20 74 65 73 74 73 79 73 74 65 6d 20 69 73 20 6d ┆d thereafter the testsystem is m┆
0x1c00…1c20 (14,) 6f 76 65 64 20 62 61 63 6b 2e 0d 0a 0d 0a 84 54 68 65 20 74 65 73 74 20 70 61 74 74 65 72 6e 20 ┆oved back. The test pattern ┆
0x1c20…1c40 66 6f 72 20 74 68 65 20 64 79 6e 61 6d 69 63 20 52 41 4d 20 6d 65 6d 6f 72 79 20 63 6f 6e 73 69 ┆for the dynamic RAM memory consi┆
0x1c40…1c60 73 74 69 6e 67 20 6f 66 20 63 68 69 70 73 20 0a 6f 66 20 34 20 62 69 74 20 78 20 31 36 20 6b 20 ┆sting of chips of 4 bit x 16 k ┆
0x1c60…1c80 69 73 20 74 68 72 65 65 20 74 69 6d 65 73 20 30 30 20 66 6f 6c 6c 6f 77 65 64 20 62 79 20 74 68 ┆is three times 00 followed by th┆
0x1c80…1ca0 72 65 65 20 74 69 6d 65 73 20 46 46 20 0a 28 48 65 78 29 2e 20 57 68 65 6e 20 61 6c 6c 20 6d 65 ┆ree times FF (Hex). When all me┆
0x1ca0…1cc0 6d 6f 72 79 20 63 65 6c 6c 73 20 68 61 76 65 20 62 65 65 6e 20 74 65 73 74 65 64 2c 20 74 68 65 ┆mory cells have been tested, the┆
0x1cc0…1ce0 79 20 61 72 65 20 61 67 61 69 6e 20 0a 74 65 73 74 65 64 20 77 69 74 68 20 74 68 65 20 69 6e 76 ┆y are again tested with the inv┆
0x1ce0…1d00 65 72 74 65 64 20 70 61 74 74 65 72 6e 2e 20 54 68 69 73 20 6d 65 61 6e 73 20 74 68 61 74 20 61 ┆erted pattern. This means that a┆
0x1d00…1d20 6c 6c 20 62 69 74 73 20 61 72 65 20 0a 74 65 73 74 65 64 20 66 6f 72 20 22 7a 65 72 6f 22 20 61 ┆ll bits are tested for "zero" a┆
0x1d20…1d40 6e 64 20 22 6f 6e 65 22 20 69 6e 73 65 72 74 69 6f 6e 2e 20 0d 0a 0d 0a 84 a1 49 66 20 61 6e 20 ┆nd "one" insertion. If an ┆
0x1d40…1d60 65 72 72 6f 72 20 6f 63 63 75 72 73 2c 20 61 20 6d 65 73 73 61 67 65 20 77 69 6c 6c 20 62 65 20 ┆error occurs, a message will be ┆
0x1d60…1d80 77 72 69 74 74 65 6e 3a 0d 0a 0d 0a 09 09 20 3c 52 43 34 35 20 6d 65 6d 6f 72 79 20 65 72 72 6f ┆written: <RC45 memory erro┆
0x1d80…1d92 72 20 68 61 20 6c 61 20 65 78 20 72 65 3e 0d 0a 0d 0a ┆r ha la ex re> ┆
0x1d92…1d95 FormFeed {
0x1d92…1d95 0c 83 bc ┆ ┆
0x1d92…1d95 }
0x1d95…1da0 0a 84 77 68 65 72 65 20 22 68 61 ┆ where "ha┆
0x1da0…1dc0 22 20 69 73 20 68 69 67 68 20 61 64 64 72 65 73 73 2c 20 22 6c 61 22 20 69 73 20 62 65 6c 6f 77 ┆" is high address, "la" is below┆
0x1dc0…1de0 20 61 64 64 72 65 73 73 2c 20 22 65 78 22 20 69 73 20 0a 65 78 70 65 63 74 65 64 20 76 61 6c 75 ┆ address, "ex" is expected valu┆
0x1de0…1e00 65 20 61 6e 64 20 22 72 65 22 20 69 73 20 72 65 63 65 69 76 65 64 20 76 61 6c 75 65 2e 20 41 6c ┆e and "re" is received value. Al┆
0x1e00…1e20 (15,) 6c 20 6e 75 6d 62 65 72 73 20 61 72 65 20 69 6e 20 0a 68 65 78 61 64 65 63 69 6d 61 6c 20 6e 6f ┆l numbers are in hexadecimal no┆
0x1e20…1e40 74 61 74 69 6f 6e 73 2e 20 28 54 6f 20 66 69 6e 64 20 61 6e 79 20 64 65 66 65 63 74 69 76 65 20 ┆tations. (To find any defective ┆
0x1e40…1e60 63 68 69 70 2c 20 63 6f 6e 73 75 6c 74 20 66 69 67 2e 20 0a 33 29 2e 0d 0a 0d 0a 49 66 20 74 68 ┆chip, consult fig. 3). If th┆
0x1e60…1e80 65 20 6d 65 6d 6f 72 79 20 69 73 20 66 6f 75 6e 64 20 66 61 69 6c 75 72 65 66 72 65 65 20 6e 6f ┆e memory is found failurefree no┆
0x1e80…1ea0 20 6d 65 73 73 61 67 65 20 69 73 20 77 72 69 74 74 65 6e 2e 0d 0a 0d 0a 84 a1 49 66 20 61 6e 20 ┆ message is written. If an ┆
0x1ea0…1ec0 65 72 72 6f 72 20 6f 63 63 75 72 73 20 69 6e 20 74 68 65 20 6d 65 6d 6f 72 79 20 74 65 73 74 20 ┆error occurs in the memory test ┆
0x1ec0…1ee0 28 72 6f 6d 20 65 72 72 6f 72 20 6f 72 20 72 61 6d 20 65 72 72 6f 72 29 20 0a 19 80 80 84 74 68 ┆(rom error or ram error) th┆
0x1ee0…1f00 65 20 74 65 73 74 20 77 69 6c 6c 20 73 74 6f 70 20 68 61 72 64 20 69 2e 65 2e 20 69 74 20 69 73 ┆e test will stop hard i.e. it is┆
0x1f00…1f20 20 6e 6f 74 20 70 6f 73 73 69 62 6c 65 20 74 6f 20 63 6f 6e 74 69 6e 75 65 20 74 68 65 20 0a 19 ┆ not possible to continue the ┆
0x1f20…1f32 80 80 84 74 65 73 74 73 65 71 75 65 6e 63 65 2e 0d 0a ┆ testsequence. ┆
0x1f32…1f35 FormFeed {
0x1f32…1f35 0c 80 f8 ┆ ┆
0x1f32…1f35 }
0x1f35…1f40 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a ┆ ┆
0x1f40…1f60 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 88 81 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a ┆ ┆
0x1f60…1f80 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a ┆ ┆
0x1f80…1f9f 0d 0a 06 46 69 67 75 72 65 20 33 3a 20 4d 65 6d 6f 72 79 20 6c 61 79 2d 6f 75 74 0d 0a 0d 0a ┆ Figure 3: Memory lay-out ┆
0x1f9f…1fa2 FormFeed {
0x1f9f…1fa2 0c 83 d4 ┆ ┆
0x1f9f…1fa2 }
0x1fa2…1fc0 0a a1 34 a1 2e 09 4d 45 4d 4f 52 59 20 52 45 46 52 45 53 48 20 54 45 53 54 0d 0a 0d 0a 54 ┆ 4 . MEMORY REFRESH TEST T┆
0x1fc0…1fe0 68 65 20 64 79 6e 61 6d 69 63 20 52 41 4d 20 72 65 66 72 65 73 68 20 74 65 73 74 20 69 73 20 61 ┆he dynamic RAM refresh test is a┆
0x1fe0…2000 20 74 65 73 74 2c 20 77 68 69 63 68 20 76 65 72 69 66 69 65 73 20 74 68 65 20 0a 66 75 6e 63 74 ┆ test, which verifies the funct┆
0x2000…2020 (16,) 69 6f 6e 20 6f 66 20 74 68 65 20 43 50 55 20 72 65 66 72 65 73 68 20 63 6f 75 6e 74 69 6e 67 2e ┆ion of the CPU refresh counting.┆
0x2020…2040 20 41 73 20 61 6e 20 61 64 64 69 74 69 6f 6e 61 6c 20 66 65 61 74 75 72 65 20 0a 74 68 65 20 74 ┆ As an additional feature the t┆
0x2040…2060 65 73 74 20 63 68 65 63 6b 73 20 74 68 65 20 62 61 74 74 65 72 79 20 63 69 72 63 75 69 74 2e 0d ┆est checks the battery circuit. ┆
0x2060…2080 0a 0d 0a 84 54 68 65 20 74 65 73 74 20 77 72 69 74 65 73 20 61 20 70 61 74 74 65 72 6e 20 69 6e ┆ The test writes a pattern in┆
0x2080…20a0 20 6d 65 6d 6f 72 79 20 63 6f 6e 73 69 73 74 69 6e 67 20 6f 66 20 61 6e 20 58 4f 52 20 6f 66 20 ┆ memory consisting of an XOR of ┆
0x20a0…20c0 68 69 67 68 20 0a 61 6e 64 20 6c 6f 77 20 61 64 64 72 65 73 73 20 70 61 72 74 2e 20 54 68 65 20 ┆high and low address part. The ┆
0x20c0…20e0 70 61 74 74 65 72 6e 20 69 73 20 77 72 69 74 74 65 6e 20 66 72 6f 6d 20 74 68 65 20 6d 65 6d 6f ┆pattern is written from the memo┆
0x20e0…2100 72 79 20 0a 61 64 64 72 65 73 73 20 38 30 30 30 48 20 75 6e 74 69 6c 20 74 68 65 20 68 65 78 61 ┆ry address 8000H until the hexa┆
0x2100…2120 64 65 63 69 6d 61 6c 20 61 64 64 72 65 73 73 20 44 35 30 30 48 20 28 77 68 65 72 65 20 74 68 65 ┆decimal address D500H (where the┆
0x2120…2140 20 0a 64 69 73 70 6c 61 79 20 69 6d 61 67 65 20 73 74 61 72 74 73 29 2e 20 49 66 20 6e 6f 20 64 ┆ display image starts). If no d┆
0x2140…2160 79 6e 61 6d 69 63 20 52 41 4d 20 69 73 20 69 6e 73 74 61 6c 6c 65 64 2c 20 74 68 65 20 74 65 73 ┆ynamic RAM is installed, the tes┆
0x2160…2180 74 20 0a 73 74 61 72 74 73 20 61 74 20 6d 65 6d 6f 72 79 20 61 64 64 72 65 73 73 20 43 30 30 30 ┆t starts at memory address C000┆
0x2180…21a0 48 2e 0d 0a 0d 0a 84 57 68 65 6e 20 74 68 65 20 70 61 74 74 65 72 6e 20 68 61 73 20 62 65 65 6e ┆H. When the pattern has been┆
0x21a0…21c0 20 77 72 69 74 74 65 6e 2c 20 74 68 65 20 74 65 73 74 20 77 61 69 74 73 20 66 6f 72 20 35 20 73 ┆ written, the test waits for 5 s┆
0x21c0…21e0 65 63 6f 6e 64 73 20 0a 69 6e 20 61 20 77 61 69 74 69 6e 67 20 6c 6f 6f 70 20 62 65 66 6f 72 65 ┆econds in a waiting loop before┆
0x21e0…2200 20 69 74 20 70 65 72 66 6f 72 6d 73 20 61 20 63 68 65 63 6b 20 6f 66 20 74 68 65 20 64 61 74 61 ┆ it performs a check of the data┆
0x2200…2220 (17,) 2e 0d 0a 0d 0a 84 54 68 65 20 6d 61 69 6e 20 70 75 72 70 6f 73 65 20 6f 66 20 74 68 69 73 20 74 ┆. The main purpose of this t┆
0x2220…2240 65 73 74 20 69 73 20 74 6f 20 64 69 73 63 6f 76 65 72 20 6d 6f 64 69 66 69 63 61 74 69 6f 6e 20 ┆est is to discover modification ┆
0x2240…2260 6f 66 20 74 68 65 20 0a 64 61 74 61 20 6f 63 63 75 72 72 69 6e 67 20 69 6e 20 74 68 65 20 64 65 ┆of the data occurring in the de┆
0x2260…2280 6c 61 79 20 74 69 6d 65 2c 20 64 75 65 20 74 6f 20 6d 61 6c 66 75 6e 63 74 69 6f 6e 20 6f 66 20 ┆lay time, due to malfunction of ┆
0x2280…22a0 74 68 65 20 0a 72 65 66 72 65 73 68 20 63 6f 75 6e 74 69 6e 67 20 69 6e 20 74 68 65 20 43 50 55 ┆the refresh counting in the CPU┆
0x22a0…22c0 2e 20 4e 6f 74 65 20 74 68 61 74 20 74 68 65 20 6d 65 6d 6f 72 79 20 68 69 67 68 65 72 20 74 68 ┆. Note that the memory higher th┆
0x22c0…22e0 61 6e 20 0a 43 30 30 30 48 20 28 34 38 4b 29 20 69 73 20 73 74 61 74 69 63 20 52 41 4d 20 61 6e ┆an C000H (48K) is static RAM an┆
0x22e0…2300 64 20 68 61 73 20 6e 6f 20 72 65 66 72 65 73 68 20 63 6f 75 6e 74 69 6e 67 2e 0d 0a 0d 0a 84 a1 ┆d has no refresh counting. ┆
0x2300…2320 50 6f 73 73 69 62 6c 65 20 6d 65 73 73 61 67 65 73 20 61 72 65 3a 0d 0a 0d 0a 09 3c 4f 4b 3e 0d ┆Possible messages are: <OK> ┆
0x2320…2340 0a 0d 0a 09 3c 64 61 74 61 20 6d 6f 64 69 66 69 65 64 20 69 6e 20 62 79 74 65 20 78 78 20 78 78 ┆ <data modified in byte xx xx┆
0x2340…2360 20 65 78 70 3a 20 78 78 20 72 65 63 3a 20 78 78 3e 0d 0a 0d 0a 0d 0a a1 34 2e 31 09 42 61 74 74 ┆ exp: xx rec: xx> 4.1 Batt┆
0x2360…2380 65 72 79 20 74 65 73 74 0d 0a 0d 0a 84 57 68 65 6e 20 74 68 65 20 72 65 66 72 65 73 68 20 63 6f ┆ery test When the refresh co┆
0x2380…23a0 75 6e 74 69 6e 67 20 69 73 20 74 65 73 74 65 64 2c 20 74 68 65 20 74 65 73 74 20 63 68 65 63 6b ┆unting is tested, the test check┆
0x23a0…23c0 73 20 34 20 62 79 74 65 73 20 69 6e 20 0a 74 68 65 20 4e 56 4d 2d 61 72 65 61 2e 20 49 66 20 74 ┆s 4 bytes in the NVM-area. If t┆
0x23c0…23e0 68 65 65 73 65 20 34 20 62 79 74 65 73 20 64 6f 65 73 20 6e 6f 74 20 6d 61 74 63 68 20 61 20 74 ┆heese 4 bytes does not match a t┆
0x23e0…2400 65 73 74 70 61 74 74 65 72 6e 20 28 30 30 20 0a 46 46 20 30 30 20 46 46 29 2c 20 74 68 65 20 62 ┆estpattern (00 FF 00 FF), the b┆
0x2400…2420 (18,) 79 74 65 73 20 77 69 6c 6c 20 62 65 20 69 6e 69 74 69 61 74 65 64 20 74 6f 20 74 68 69 73 20 74 ┆ytes will be initiated to this t┆
0x2420…2440 65 73 74 70 61 74 74 65 72 6e 2c 20 61 6e 64 20 0a 74 68 65 20 74 65 78 74 20 22 62 61 74 74 65 ┆estpattern, and the text "batte┆
0x2440…2460 72 79 20 74 65 73 74 20 69 6e 69 74 69 61 74 65 64 22 20 77 69 6c 6c 20 62 65 20 77 72 69 74 74 ┆ry test initiated" will be writt┆
0x2460…2480 65 6e 2e 20 54 6f 20 63 68 65 63 6b 20 74 68 65 20 0a 62 61 74 74 65 72 79 20 63 69 72 63 75 69 ┆en. To check the battery circui┆
0x2480…24a0 74 20 74 75 72 6e 20 6f 66 66 20 61 6e 64 20 6f 6e 20 74 68 65 20 70 6f 77 65 72 20 61 6e 64 20 ┆t turn off and on the power and ┆
0x24a0…24c0 72 65 73 74 61 72 74 20 74 68 65 20 0a 74 65 73 74 73 79 74 65 6d 2e 20 57 68 65 6e 20 70 65 72 ┆restart the testsytem. When per┆
0x24c0…24e0 66 6f 72 6d 69 6e 67 20 74 68 65 20 72 65 66 72 65 73 68 20 74 65 73 74 2c 20 74 68 65 20 74 65 ┆forming the refresh test, the te┆
0x24e0…2500 78 74 20 22 62 61 74 74 65 72 79 20 0a 74 65 73 74 20 69 6e 69 74 69 61 74 65 64 22 20 6d 75 73 ┆xt "battery test initiated" mus┆
0x2500…2520 74 20 6e 6f 74 20 61 70 70 65 61 72 2e 20 a1 4e 6f 74 65 20 74 68 61 74 20 74 68 65 20 74 65 73 ┆t not appear. Note that the tes┆
0x2520…2540 74 20 6d 75 73 74 20 62 65 20 0a 19 80 80 84 73 74 61 72 74 65 64 20 77 69 74 68 20 74 68 65 20 ┆t must be started with the ┆
0x2540…2560 74 65 73 74 63 61 62 6c 65 20 4b 42 4c 20 37 32 31 20 69 6e 20 74 68 65 20 70 72 69 6e 74 65 72 ┆testcable KBL 721 in the printer┆
0x2560…2580 63 6f 6e 6e 65 63 74 6f 72 2c 20 69 66 20 0a 19 80 80 84 74 68 69 73 20 70 61 72 74 20 6f 66 20 ┆connector, if this part of ┆
0x2580…259f 74 68 65 20 74 65 73 74 20 73 68 61 6c 6c 20 61 63 74 20 63 6f 72 72 65 63 74 2e 0d 0a 0d 0a ┆the test shall act correct. ┆
0x259f…25a2 FormFeed {
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0x25a2…25c0 0a a1 35 2e 09 4b 45 59 42 4f 41 52 44 20 54 45 53 54 e1 0d 0a 0d 0a 84 54 68 65 20 6b 65 ┆ 5. KEYBOARD TEST The ke┆
0x25c0…25e0 79 62 6f 61 72 64 20 63 6f 6e 74 61 69 6e 73 20 61 20 63 68 65 63 6b 73 75 6d 20 74 65 73 74 20 ┆yboard contains a checksum test ┆
0x25e0…2600 6f 66 20 74 68 65 20 20 6b 65 79 62 6f 61 72 64 2d 50 52 4f 4d 2c 20 61 20 52 41 4d 20 0a 74 65 ┆of the keyboard-PROM, a RAM te┆
0x2600…2620 (19,) 73 74 20 6f 66 20 6b 65 79 62 6f 61 72 64 2d 43 50 55 20 61 6e 64 20 61 20 73 63 61 6e 20 74 65 ┆st of keyboard-CPU and a scan te┆
0x2620…2640 73 74 20 6f 66 20 74 68 65 20 6b 65 79 62 6f 61 72 64 2d 20 6d 61 74 72 69 78 2e 20 0a 54 68 65 ┆st of the keyboard- matrix. The┆
0x2640…2660 65 73 65 20 74 68 72 65 65 20 74 65 73 74 73 20 63 61 6e 20 62 65 20 61 63 74 69 76 61 74 65 64 ┆ese three tests can be activated┆
0x2660…2680 20 62 79 20 77 72 69 74 69 6e 67 20 73 6f 6d 65 20 73 70 65 63 69 66 69 63 61 6c 6c 79 20 0a 63 ┆ by writing some specifically c┆
0x2680…26a0 6f 64 65 73 20 28 6b 65 79 62 6f 61 72 64 2d 50 52 4f 4d 20 74 65 73 74 3a 20 31 38 36 2c 20 6b ┆odes (keyboard-PROM test: 186, k┆
0x26a0…26c0 65 79 62 6f 61 72 64 2d 52 41 4d 20 74 65 73 74 3a 20 31 38 34 20 61 6e 64 20 0a 6b 65 79 62 6f ┆eyboard-RAM test: 184 and keybo┆
0x26c0…26e0 61 72 64 20 73 63 61 6e 20 74 65 73 74 3a 20 31 38 38 29 20 74 6f 20 74 68 65 20 6b 65 79 62 6f ┆ard scan test: 188) to the keybo┆
0x26e0…2700 61 72 64 2e 20 54 68 65 20 6b 65 79 62 6f 61 72 64 20 77 69 6c 6c 20 0a 72 65 73 70 6f 6e 64 20 ┆ard. The keyboard will respond ┆
0x2700…2720 77 69 74 68 20 4f 4b 20 28 74 68 65 20 73 61 6d 65 20 63 6f 64 65 29 20 6f 72 20 6e 6f 74 20 4f ┆with OK (the same code) or not O┆
0x2720…2740 4b 20 28 74 68 65 20 63 6f 64 65 20 2b 20 31 29 2e 0d 0a 0d 0a a1 50 6f 73 73 69 62 6c 65 20 6d ┆K (the code + 1). Possible m┆
0x2740…2760 65 73 73 61 67 65 73 20 61 72 65 3a 0d 0a 0d 0a 09 3c 4f 4b 3e 0d 0a 0d 0a 09 3c 72 6f 6d 65 72 ┆essages are: <OK> <romer┆
0x2760…2780 72 6f 72 3e 0d 0a 0d 0a 09 3c 72 61 6d 65 72 72 6f 72 3e 0d 0a 0d 0a 09 3c 73 63 61 6e 65 72 72 ┆ror> <ramerror> <scanerr┆
0x2780…2789 6f 72 3e 0d 0a 0d 0a 0d 0a ┆or> ┆
0x2789…278c FormFeed {
0x2789…278c 0c 81 f0 ┆ ┆
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0x278c…27a0 0a a1 36 2e 09 53 49 4f 20 54 45 53 54 0d 0a 0d 0a 84 49 66 ┆ 6. SIO TEST If┆
0x27a0…27c0 20 74 68 65 20 53 49 4f 2d 74 65 73 74 20 70 6c 75 67 20 28 43 42 4c 20 39 39 38 29 20 69 73 20 ┆ the SIO-test plug (CBL 998) is ┆
0x27c0…27e0 69 6e 73 65 72 74 65 64 20 69 6e 20 74 68 65 20 56 2e 32 34 20 0a 63 6f 6e 6e 65 63 74 69 6f 6e ┆inserted in the V.24 connection┆
0x27e0…2800 2c 20 74 68 65 20 53 49 4f 20 74 65 73 74 20 69 73 20 70 65 72 66 6f 72 6d 65 64 2e 0d 0a 0d 0a ┆, the SIO test is performed. ┆
0x2800…2820 (20,) 84 54 68 65 20 53 49 4f 20 74 65 73 74 20 69 73 20 74 65 73 74 69 6e 67 20 74 68 65 20 6d 6f 64 ┆ The SIO test is testing the mod┆
0x2820…2840 65 6d 20 73 69 67 6e 61 6c 73 20 61 6e 64 20 64 61 74 61 20 74 72 61 6e 73 70 6f 72 74 73 20 6f ┆em signals and data transports o┆
0x2840…2860 6e 20 0a 53 49 4f 20 63 68 61 6e 6e 65 6c 20 41 2e 0d 0a 0d 0a 84 43 68 61 6e 6e 65 6c 20 42 20 ┆n SIO channel A. Channel B ┆
0x2860…2880 73 65 65 20 52 43 43 49 52 43 55 49 54 20 49 20 74 65 73 74 2e 0a 0d 0a 0d 0a a1 36 2e 31 09 4d ┆see RCCIRCUIT I test. 6.1 M┆
0x2880…28a0 6f 64 65 6d 20 53 69 67 6e 61 6c 20 52 65 73 70 6f 6e 73 65 0d 0a 0d 0a 84 54 68 65 20 72 65 73 ┆odem Signal Response The res┆
0x28a0…28c0 70 6f 6e 73 65 73 20 6f 66 20 44 54 52 20 61 6e 64 20 52 54 53 20 61 72 65 20 74 65 73 74 65 64 ┆ponses of DTR and RTS are tested┆
0x28c0…28e0 20 6f 6e 20 74 68 65 20 44 43 44 20 61 6e 64 20 43 54 53 20 70 69 6e 73 2e 20 0a 54 65 73 74 20 ┆ on the DCD and CTS pins. Test ┆
0x28e0…2900 70 6c 75 67 20 61 73 20 73 68 6f 77 6e 20 69 6e 20 66 69 67 2e 20 34 20 6d 75 73 74 20 62 65 20 ┆plug as shown in fig. 4 must be ┆
0x2900…2920 69 6e 73 74 61 6c 6c 65 64 20 6f 6e 20 74 68 65 20 20 56 2e 32 34 20 0a 63 6f 6e 6e 65 63 74 69 ┆installed on the V.24 connecti┆
0x2920…2940 6f 6e 20 6f 66 20 74 68 65 20 74 65 72 6d 69 6e 61 6c 2e 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d ┆on of the terminal. ┆
0x2940…2960 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 06 46 69 67 75 72 65 20 34 ┆ Figure 4┆
0x2960…2980 3a 20 43 42 4c 20 39 39 38 0d 0a 0d 0a 84 49 66 20 61 6e 20 65 72 72 6f 72 20 6f 63 63 75 72 73 ┆: CBL 998 If an error occurs┆
0x2980…29a0 20 6f 6e 20 74 68 65 20 6d 6f 64 65 6d 20 73 69 67 6e 61 6c 73 20 43 54 53 20 6f 72 20 44 43 44 ┆ on the modem signals CTS or DCD┆
0x29a0…29c0 20 74 68 65 20 72 65 63 65 69 76 65 64 20 0a 68 65 78 2e 20 76 61 6c 75 65 20 73 68 6f 75 6c 64 ┆ the received hex. value should┆
0x29c0…29e0 20 62 65 20 69 6e 74 65 72 70 72 65 74 65 64 20 61 73 20 73 68 6f 77 6e 20 69 6e 20 66 69 67 2e ┆ be interpreted as shown in fig.┆
0x29e0…29e6 20 35 0d 0a 0d 0a ┆ 5 ┆
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0x29e6…29e9 0c 83 c8 ┆ ┆
0x29e6…29e9 }
0x29e9…2a00 0a 84 a1 45 72 72 6f 72 20 6d 65 73 73 61 67 65 73 20 66 72 6f 6d 20 ┆ Error messages from ┆
0x2a00…2a20 (21,) 74 68 69 73 20 70 61 72 74 20 6f 66 20 74 68 65 20 74 65 73 74 3a 0d 0a 0d 0a 09 43 54 53 20 6f ┆this part of the test: CTS o┆
0x2a20…2a40 72 20 44 43 44 20 65 72 72 6f 72 2c 20 65 78 70 3a 20 3c 78 78 3e 20 72 65 63 3a 20 3c 78 78 3e ┆r DCD error, exp: <xx> rec: <xx>┆
0x2a40…2a60 0d 0a 0d 0a 52 65 63 65 69 76 65 64 20 76 61 6c 75 65 20 64 69 66 66 65 72 73 20 66 72 6f 6d 20 ┆ Received value differs from ┆
0x2a60…2a80 65 78 70 65 63 74 65 64 3b 20 63 66 2e 20 66 69 67 2e 20 35 2e 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d ┆expected; cf. fig. 5. ┆
0x2a80…2aa0 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 0d 0a 06 46 69 67 75 ┆ Figu┆
0x2aa0…2ac0 72 65 20 35 3a 20 4d 6f 64 65 6d 20 73 69 67 6e 61 6c 20 72 65 73 70 6f 6e 73 65 2e 0d 0a 0d 0a ┆re 5: Modem signal response. ┆
0x2ac0…2ae0 0d 0a a1 36 2e 32 09 53 49 4f 20 43 68 61 6e 6e 65 6c 20 54 65 73 74 0d 0a 0d 0a 84 57 68 65 6e ┆ 6.2 SIO Channel Test When┆
0x2ae0…2b00 20 74 68 65 20 6d 6f 64 65 6d 20 73 69 67 6e 61 6c 20 72 65 73 70 6f 6e 73 65 73 20 68 61 76 65 ┆ the modem signal responses have┆
0x2b00…2b20 20 62 65 65 6e 20 63 68 65 63 6b 65 64 2c 20 74 68 65 20 53 49 4f 20 0a 63 68 61 6e 6e 65 6c 20 ┆ been checked, the SIO channel ┆
0x2b20…2b40 41 20 69 73 20 69 6e 69 74 69 61 74 65 64 2e 0d 0a 0d 0a 84 54 68 65 20 53 49 4f 20 63 68 61 6e ┆A is initiated. The SIO chan┆
0x2b40…2b60 6e 65 6c 20 69 73 20 69 6e 69 74 69 61 74 65 64 20 74 6f 20 31 39 32 30 30 20 62 70 73 2e 20 42 ┆nel is initiated to 19200 bps. B┆
0x2b60…2b80 61 75 64 20 72 61 74 65 20 67 65 6e 65 72 61 74 6f 72 20 69 73 20 0a 74 68 65 20 43 54 43 2e 0d ┆aud rate generator is the CTC. ┆
0x2b80…2b83 0a 0d 0a ┆ ┆
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0x2b86…2ba0 0a 84 41 20 74 69 6d 65 72 20 69 6e 74 65 72 72 75 70 74 20 67 65 6e 65 72 61 ┆ A timer interrupt genera┆
0x2ba0…2bc0 74 65 64 20 61 70 70 72 6f 78 2e 20 31 37 36 30 20 74 69 6d 65 73 2f 73 20 74 72 61 6e 73 6d 69 ┆ted approx. 1760 times/s transmi┆
0x2bc0…2be0 74 73 20 74 68 65 20 0a 64 61 74 61 20 66 72 6f 6d 20 74 68 65 20 74 72 61 6e 73 6d 69 74 20 62 ┆ts the data from the transmit b┆
0x2be0…2c00 75 66 66 65 72 2e 20 0d 0a 0d 0a 84 54 68 65 20 63 68 61 6e 6e 65 6c 20 74 72 61 6e 73 6d 69 74 ┆uffer. The channel transmit┆
0x2c00…2c20 (22,) 20 61 20 64 61 74 61 62 75 66 66 65 72 20 6f 66 20 31 20 6b 20 62 79 74 65 73 20 63 6f 6e 73 69 ┆ a databuffer of 1 k bytes consi┆
0x2c20…2c40 73 74 69 6e 67 20 6f 66 20 61 20 0a 63 6f 75 6e 74 69 6e 67 20 70 61 74 74 65 72 6e 20 28 30 30 ┆sting of a counting pattern (00┆
0x2c40…2c60 20 46 46 20 46 45 20 46 44 20 65 74 63 2e 29 2e 20 54 68 65 20 74 65 73 74 20 6c 6f 6f 70 20 77 ┆ FF FE FD etc.). The test loop w┆
0x2c60…2c80 69 6c 6c 20 63 68 65 63 6b 20 74 68 65 20 0a 72 65 63 65 69 76 65 64 20 62 75 66 66 65 72 2c 20 ┆ill check the received buffer, ┆
0x2c80…2ca0 61 73 20 73 6f 6f 6e 20 61 73 20 74 68 65 20 70 61 74 74 65 72 6e 20 68 61 76 65 20 62 65 65 6e ┆as soon as the pattern have been┆
0x2ca0…2cc0 20 74 72 61 6e 73 66 65 72 65 64 2e 20 49 74 20 0a 61 6c 73 6f 20 6d 6f 6e 69 74 6f 72 73 20 74 ┆ transfered. It also monitors t┆
0x2cc0…2ce0 68 65 20 63 68 61 6e 6e 65 6c 20 66 6f 72 20 74 69 6d 65 6f 75 74 2e 0d 0a 0d 0a a1 45 72 72 6f ┆he channel for timeout. Erro┆
0x2ce0…2d00 72 20 6d 65 73 73 61 67 65 73 20 66 72 6f 6d 20 74 68 65 20 53 49 4f 20 63 68 61 6e 6e 65 6c 20 ┆r messages from the SIO channel ┆
0x2d00…2d20 74 65 73 74 3a 0d 0a 0d 0a 09 84 3c 69 6c 6c 65 67 61 6c 20 69 6e 74 65 72 72 75 70 74 2c 20 70 ┆test: <illegal interrupt, p┆
0x2d20…2d40 6f 72 74 3a 20 3c 78 78 3e 3e 0d 0a 0d 0a 84 41 6e 20 69 6e 74 65 72 72 75 70 74 20 68 61 73 20 ┆ort: <xx>> An interrupt has ┆
0x2d40…2d60 6f 63 63 75 72 65 64 20 66 72 6f 6d 20 61 20 64 65 76 69 63 65 20 74 68 61 74 20 77 61 73 20 6e ┆occured from a device that was n┆
0x2d60…2d80 6f 74 20 69 6e 74 65 6e 64 65 64 20 74 6f 20 0a 69 6e 74 65 72 72 75 70 74 2c 20 6f 72 20 74 68 ┆ot intended to interrupt, or th┆
0x2d80…2da0 65 20 53 49 4f 20 68 61 73 20 67 69 76 65 6e 20 61 20 73 74 61 74 75 73 20 69 6e 74 65 72 72 75 ┆e SIO has given a status interru┆
0x2da0…2dc0 70 74 20 28 61 6e 79 20 63 68 61 6e 67 65 20 6f 6e 20 0a 74 68 65 20 6d 6f 64 65 6d 20 73 69 67 ┆pt (any change on the modem sig┆
0x2dc0…2de0 6e 61 6c 73 20 64 75 72 69 6e 67 20 64 61 74 61 20 74 72 61 6e 73 66 65 72 20 77 69 6c 6c 20 72 ┆nals during data transfer will r┆
0x2de0…2e00 65 73 70 6f 6e 64 20 77 69 74 68 20 74 68 69 73 20 0a 6d 65 73 73 61 67 65 29 2e 0d 0a 0d 0a 09 ┆espond with this message). ┆
0x2e00…2e20 (23,) 3c 70 61 72 69 74 79 20 65 72 72 6f 72 3e 0d 0a 0d 0a 41 20 73 70 65 63 69 61 6c 20 72 65 63 65 ┆<parity error> A special rece┆
0x2e20…2e40 69 76 65 20 69 6e 74 65 72 72 75 70 74 20 77 69 74 68 20 70 61 72 69 74 79 20 62 69 74 20 68 61 ┆ive interrupt with parity bit ha┆
0x2e40…2e60 73 20 6f 63 63 75 72 65 64 2e 0d 0a 0d 0a 09 3c 64 61 74 61 20 65 72 72 6f 72 2c 20 62 79 74 65 ┆s occured. <data error, byte┆
0x2e60…2e80 20 6e 6f 3a 20 3c 78 78 20 78 78 3e 20 65 78 70 3a 20 3c 78 78 3e 20 72 65 63 3a 20 3c 78 78 3e ┆ no: <xx xx> exp: <xx> rec: <xx>┆
0x2e80…2ea0 3e 0d 0a 0d 0a 54 68 65 20 72 65 63 65 69 76 65 64 20 62 75 66 66 65 72 20 64 6f 65 73 20 6e 6f ┆> The received buffer does no┆
0x2ea0…2ec0 74 20 63 6f 6e 74 61 69 6e 20 74 68 65 20 65 78 70 65 63 74 65 64 20 70 61 74 74 65 72 6e 2e 0d ┆t contain the expected pattern. ┆
0x2ec0…2eda 0a 0d 0a 09 3c 72 65 63 65 69 76 65 72 20 6f 76 65 72 72 75 6e 3e 0d 0a 0d 0a ┆ <receiver overrun> ┆
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0x2edd…2ee0 0a a1 37 ┆ 7┆
0x2ee0…2f00 2e 09 52 43 43 49 52 43 55 49 54 20 49 20 54 45 53 54 0d 0a 0d 0a 84 42 65 66 6f 72 65 20 74 68 ┆. RCCIRCUIT I TEST Before th┆
0x2f00…2f20 65 20 74 65 73 74 20 73 74 61 72 74 73 2c 20 69 74 20 69 73 20 74 65 73 74 65 64 2c 20 69 66 20 ┆e test starts, it is tested, if ┆
0x2f20…2f40 43 69 72 63 75 69 74 20 31 20 69 73 20 69 6e 73 74 61 6c 6c 65 64 2e 0d 0a 0d 0a 84 54 68 65 20 ┆Circuit 1 is installed. The ┆
0x2f40…2f60 53 49 4f 20 63 68 61 6e 6e 65 6c 20 42 20 69 73 20 69 6e 69 74 69 61 74 65 64 20 74 6f 20 66 75 ┆SIO channel B is initiated to fu┆
0x2f60…2f80 6c 6c 20 64 75 70 6c 65 78 20 61 6e 64 20 74 68 65 20 44 4d 41 20 69 73 20 0a 69 6e 69 74 69 61 ┆ll duplex and the DMA is initia┆
0x2f80…2fa0 74 65 64 20 74 6f 20 72 65 63 65 69 76 65 20 31 4b 20 62 79 74 65 73 20 66 72 6f 6d 20 74 68 65 ┆ted to receive 1K bytes from the┆
0x2fa0…2fc0 20 53 49 4f 2e 0d 0a 0d 0a 84 41 20 74 69 6d 65 72 20 69 6e 74 65 72 72 75 70 74 20 67 65 6e 65 ┆ SIO. A timer interrupt gene┆
0x2fc0…2fe0 72 61 74 65 64 20 61 70 70 72 6f 78 2e 20 31 37 36 30 20 74 69 6d 65 73 2f 73 20 74 72 61 6e 73 ┆rated approx. 1760 times/s trans┆
0x2fe0…3000 6d 69 74 73 20 74 68 65 20 0a 64 61 74 61 20 66 72 6f 6d 20 74 68 65 20 74 72 61 6e 73 6d 69 74 ┆mits the data from the transmit┆
0x3000…3020 (24,) 20 62 75 66 66 65 72 2e 20 0d 0a 0d 0a 84 54 68 65 20 63 68 61 6e 6e 65 6c 20 74 72 61 6e 73 6d ┆ buffer. The channel transm┆
0x3020…3040 69 74 20 61 20 64 61 74 61 62 75 66 66 65 72 20 6f 66 20 31 20 6b 20 62 79 74 65 73 20 63 6f 6e ┆it a databuffer of 1 k bytes con┆
0x3040…3060 73 69 73 74 69 6e 67 20 6f 66 20 61 20 0a 63 6f 75 6e 74 69 6e 67 20 70 61 74 74 65 72 6e 20 28 ┆sisting of a counting pattern (┆
0x3060…3080 30 30 20 46 46 20 46 45 20 46 44 20 65 74 63 2e 29 2e 20 54 68 65 20 74 65 73 74 20 6c 6f 6f 70 ┆00 FF FE FD etc.). The test loop┆
0x3080…30a0 20 77 69 6c 6c 20 63 68 65 63 6b 20 74 68 65 20 0a 72 65 63 65 69 76 65 64 20 62 75 66 66 65 72 ┆ will check the received buffer┆
0x30a0…30c0 20 61 73 20 73 6f 6f 6e 20 61 73 20 74 68 65 20 70 61 74 74 65 72 6e 20 68 61 76 65 20 62 65 65 ┆ as soon as the pattern have bee┆
0x30c0…30e0 6e 20 74 72 61 6e 73 66 65 72 65 64 2e 20 49 74 20 0a 61 6c 73 6f 20 6d 6f 6e 69 74 6f 72 73 20 ┆n transfered. It also monitors ┆
0x30e0…3100 74 68 65 20 63 68 61 6e 6e 65 6c 20 66 6f 72 20 74 69 6d 65 6f 75 74 2e 0d 0a 0d 0a 84 a1 50 6f ┆the channel for timeout. Po┆
0x3100…3120 73 73 69 62 6c 65 20 6d 65 73 73 61 67 65 73 20 61 72 65 3a 0d 0a 0d 0a 09 3c 4f 4b 3e 0d 0a 0d ┆ssible messages are: <OK> ┆
0x3120…3140 0a 09 3c 54 49 4d 45 4f 55 54 3e 0d 0a 0d 0a 54 68 65 20 64 61 74 61 20 68 61 73 20 6e 6f 74 20 ┆ <TIMEOUT> The data has not ┆
0x3140…3160 62 65 65 6e 20 74 72 61 6e 73 6d 69 74 74 65 64 20 63 6f 6d 70 6c 65 74 65 6c 79 2e 0d 0a 0d 0a ┆been transmitted completely. ┆
0x3160…3180 09 3c 64 61 74 61 20 65 72 72 6f 72 2c 20 62 79 74 65 20 6e 6f 3a 20 3c 78 78 20 78 78 3e 20 65 ┆ <data error, byte no: <xx xx> e┆
0x3180…31a0 78 70 3a 20 3c 78 78 3e 20 72 65 63 3a 20 3c 78 78 3e 3e 0d 0a 0d 0a 54 68 65 20 72 65 63 65 69 ┆xp: <xx> rec: <xx>> The recei┆
0x31a0…31c0 76 65 64 20 62 75 66 66 65 72 20 64 6f 65 73 20 6e 6f 74 20 63 6f 6e 74 61 69 6e 20 74 68 65 20 ┆ved buffer does not contain the ┆
0x31c0…31d5 65 78 70 65 63 74 65 64 20 70 61 74 74 65 72 6e 2e 0d 0a 0d 0a ┆expected pattern. ┆
0x31d5…31d8 FormFeed {
0x31d5…31d8 0c 82 c4 ┆ ┆
0x31d5…31d8 }
0x31d8…31e0 0a a1 38 2e 09 43 54 43 ┆ 8. CTC┆
0x31e0…3200 20 54 45 53 54 0d 0a 0d 0a 84 54 68 69 73 20 70 72 6f 67 72 61 6d 20 74 65 73 74 73 20 74 68 65 ┆ TEST This program tests the┆
0x3200…3220 (25,) 20 63 6f 75 6e 74 65 72 2f 74 69 6d 65 72 20 63 69 72 63 75 69 74 2c 20 77 68 69 63 68 20 69 73 ┆ counter/timer circuit, which is┆
0x3220…3240 20 75 73 65 64 20 66 6f 72 20 0a 62 61 75 64 20 72 61 74 65 20 67 65 6e 65 72 61 74 6f 72 20 61 ┆ used for baud rate generator a┆
0x3240…3260 6e 64 20 61 73 20 69 6e 74 65 72 72 75 70 74 20 63 69 72 63 75 69 74 20 66 6f 72 20 74 68 65 20 ┆nd as interrupt circuit for the ┆
0x3260…3280 43 52 54 20 61 6e 64 20 74 68 65 20 0a 6b 65 79 62 6f 61 72 64 2e 0d 0a 0d 0a 84 84 49 74 20 69 ┆CRT and the keyboard. It i┆
0x3280…32a0 73 20 74 65 73 74 65 64 2c 20 74 68 61 74 20 74 68 65 20 63 69 72 63 75 69 74 20 77 69 6c 6c 20 ┆s tested, that the circuit will ┆
0x32a0…32c0 67 65 6e 65 72 61 74 65 20 69 6e 74 65 72 72 75 70 74 73 2c 20 61 6e 64 20 74 68 61 74 20 0a 74 ┆generate interrupts, and that t┆
0x32c0…32e0 68 65 20 76 65 63 74 6f 72 20 28 69 6e 74 65 72 72 75 70 74 20 61 64 64 72 65 73 73 29 20 69 73 ┆he vector (interrupt address) is┆
0x32e0…3300 20 63 6f 72 72 65 63 74 2e 0d 0a 0d 0a 84 54 68 65 20 66 6f 75 72 20 20 63 68 61 6e 6e 65 6c 73 ┆ correct. The four channels┆
0x3300…3320 20 30 2c 20 31 2c 20 32 2c 20 61 6e 64 20 33 20 61 72 65 20 74 65 73 74 65 64 2e 20 49 66 20 74 ┆ 0, 1, 2, and 3 are tested. If t┆
0x3320…3340 77 6f 20 43 54 43 27 73 20 61 72 65 20 0a 69 6e 73 74 61 6c 6c 65 64 20 61 6c 73 6f 20 74 68 65 ┆wo CTC's are installed also the┆
0x3340…3360 20 63 68 61 6e 6e 65 6c 73 20 34 2c 20 35 2c 20 36 20 61 6e 64 20 37 20 61 72 65 20 74 65 73 74 ┆ channels 4, 5, 6 and 7 are test┆
0x3360…3380 65 64 2e 20 54 68 65 20 0a 63 68 61 6e 6e 65 6c 73 20 61 72 65 20 74 65 73 74 65 64 20 69 6e 20 ┆ed. The channels are tested in ┆
0x3380…33a0 74 68 65 20 74 69 6d 65 72 20 6d 6f 64 65 2c 20 61 6e 64 20 74 68 65 20 74 69 6d 69 6e 67 20 73 ┆the timer mode, and the timing s┆
0x33a0…33c0 74 61 72 74 73 20 0a 61 75 74 6f 6d 61 74 69 63 61 6c 6c 79 2e 20 54 68 65 20 63 68 61 6e 6e 65 ┆tarts automatically. The channe┆
0x33c0…33e0 6c 20 75 6e 64 65 72 20 74 65 73 74 20 73 68 6f 75 6c 64 20 62 65 20 67 69 76 69 6e 67 20 69 6e ┆l under test should be giving in┆
0x33e0…3400 74 65 72 72 75 70 74 20 0a 61 66 74 65 72 20 61 70 70 72 6f 78 2e 20 34 32 33 20 20 6d 69 6b 72 ┆terrupt after approx. 423 mikr┆
0x3400…3420 (26,) 6f 20 73 2e 20 0d 0a 0d 0a 84 54 68 65 20 74 65 73 74 20 69 73 20 62 61 73 65 64 20 6f 6e 20 61 ┆o s. The test is based on a┆
0x3420…3440 20 74 69 6d 65 6f 75 74 20 6c 6f 6f 70 2c 20 73 6f 20 69 74 20 69 73 20 63 68 65 63 6b 65 64 20 ┆ timeout loop, so it is checked ┆
0x3440…3460 69 66 20 74 68 65 20 0a 69 6e 74 65 72 72 75 70 74 20 77 61 73 20 72 65 63 65 69 76 65 64 20 77 ┆if the interrupt was received w┆
0x3460…3480 69 74 68 69 6e 20 61 20 73 70 65 63 69 66 69 65 64 20 74 69 6d 65 20 28 33 6f 6f 20 6d 73 2e 29 ┆ithin a specified time (3oo ms.)┆
0x3480…34a0 2e 20 49 74 20 69 73 20 0a 61 6c 73 6f 20 63 68 65 63 6b 65 64 20 74 68 61 74 20 6f 6e 6c 79 20 ┆. It is also checked that only ┆
0x34a0…34c0 74 68 65 20 73 70 65 63 69 66 69 65 64 20 63 68 61 6e 6e 65 6c 20 69 6e 74 65 72 72 75 70 74 73 ┆the specified channel interrupts┆
0x34c0…34e0 2e 0d 0a 0d 0a 84 a1 50 6f 73 73 69 62 6c 65 20 6d 65 73 73 61 67 65 73 20 61 72 65 3a 0d 0a 0d ┆. Possible messages are: ┆
0x34e0…3500 0a 09 3c 4f 4b 3e 0d 0a 0d 0a 09 84 3c 69 6c 6c 65 67 61 6c 20 69 6e 74 65 72 72 75 70 74 2c 20 ┆ <OK> <illegal interrupt, ┆
0x3500…3520 70 6f 72 74 3a 20 78 78 3e 0d 0a 84 6d 65 61 6e 69 6e 67 20 74 68 61 74 20 61 6e 6f 74 68 65 72 ┆port: xx> meaning that another┆
0x3520…3540 20 63 68 61 6e 6e 65 6c 20 74 68 61 6e 20 74 68 65 20 73 70 65 63 69 66 69 65 64 20 68 61 73 20 ┆ channel than the specified has ┆
0x3540…3560 69 6e 74 65 72 72 75 70 74 65 64 2e 0d 0a 0d 0a 09 84 3c 6e 6f 20 69 6e 74 65 72 72 75 70 74 2c ┆interrupted. <no interrupt,┆
0x3560…3580 20 63 68 3a 3e 0d 0a 84 6d 65 61 6e 69 6e 67 20 74 68 61 74 20 74 68 65 20 74 65 73 74 20 68 61 ┆ ch:> meaning that the test ha┆
0x3580…35a0 73 20 74 69 6d 65 64 20 6f 75 74 20 62 65 66 6f 72 65 20 69 6e 74 65 72 72 75 70 74 20 77 61 73 ┆s timed out before interrupt was┆
0x35a0…35b0 20 0a 72 65 63 65 69 76 65 64 2e 0d 0a 0d 0a 0a ┆ received. ┆
0x35b0…35b3 FormFeed {
0x35b0…35b3 0c 82 f4 ┆ ┆
0x35b0…35b3 }
0x35b3…35c0 0a a1 39 2e 09 50 41 52 41 4c 4c 45 4c ┆ 9. PARALLEL┆
0x35c0…35e0 20 50 4f 52 54 20 54 45 53 54 e1 0d 0a 0d 0a 84 54 68 69 73 20 74 65 73 74 20 69 73 20 61 20 71 ┆ PORT TEST This test is a q┆
0x35e0…3600 75 69 63 6b 20 74 65 73 74 20 6f 66 20 74 68 65 20 74 68 72 65 65 20 6f 75 74 70 75 74 20 73 69 ┆uick test of the three output si┆
0x3600…3620 (27,) 67 6e 61 6c 73 20 28 73 74 72 6f 62 65 2c 20 0a 69 6e 69 74 20 61 6e 64 20 73 65 6c 65 63 74 29 ┆gnals (strobe, init and select)┆
0x3620…3640 20 66 72 6f 6d 20 74 68 65 20 63 70 75 20 74 6f 20 74 68 65 20 70 6f 72 74 20 31 39 48 20 72 6f ┆ from the cpu to the port 19H ro┆
0x3640…3660 75 74 65 64 20 62 61 63 6b 20 74 6f 20 70 6f 72 74 20 0a 31 39 48 2e 20 41 6c 6c 20 65 69 67 68 ┆uted back to port 19H. All eigh┆
0x3660…3680 74 20 63 6f 6d 62 69 6e 61 74 69 6f 6e 73 20 61 72 65 20 74 65 73 74 65 64 2e 0d 0a 0d 0a a1 50 ┆t combinations are tested. P┆
0x3680…36a0 6f 73 73 69 62 6c 65 20 6d 65 73 73 61 67 65 20 61 72 65 3a 0d 0a 0d 0a 09 3c 4f 4b 3e 0d 0a 0d ┆ossible message are: <OK> ┆
0x36a0…36c0 0a 09 3c 64 61 74 61 20 65 72 72 6f 72 20 65 78 70 20 78 78 20 72 65 63 20 78 78 3e 0d 0a 0d 0a ┆ <data error exp xx rec xx> ┆
0x36c0…36c2 0d 0a ┆ ┆
0x36c2…36c5 FormFeed {
0x36c2…36c5 0c 81 9c ┆ ┆
0x36c2…36c5 }
0x36c5…36e0 0a a1 31 30 2e 09 44 4d 41 20 54 65 73 74 0d 0a 0d 0a 84 41 74 20 66 69 72 73 74 ┆ 10. DMA Test At first┆
0x36e0…3700 20 69 74 20 69 73 20 74 65 73 74 65 64 20 69 66 20 44 4d 41 20 69 73 20 69 6e 73 74 61 6c 6c 65 ┆ it is tested if DMA is installe┆
0x3700…3720 64 2c 20 62 65 66 6f 72 65 20 74 68 65 20 74 65 73 74 20 0a 73 74 61 72 74 73 2e 0d 0a 0d 0a 84 ┆d, before the test starts. ┆
0x3720…3740 54 68 65 20 44 4d 41 20 74 65 73 74 20 69 73 20 74 65 73 74 65 64 20 62 79 20 61 20 6d 65 6d 6f ┆The DMA test is tested by a memo┆
0x3740…3760 72 79 20 74 6f 20 6d 65 6d 6f 72 79 20 74 72 61 6e 73 70 6f 72 74 2e 20 0d 0a 0d 0a 84 54 68 65 ┆ry to memory transport. The┆
0x3760…3780 20 74 72 61 6e 73 6d 69 74 74 65 64 20 70 61 74 74 65 72 6e 20 69 73 20 61 20 62 75 66 66 65 72 ┆ transmitted pattern is a buffer┆
0x3780…37a0 20 6f 66 20 31 20 6b 20 63 6f 6e 74 61 69 6e 69 6e 67 20 61 20 63 6f 75 6e 74 69 6e 67 20 0a 70 ┆ of 1 k containing a counting p┆
0x37a0…37c0 61 74 74 65 72 6e 2e 20 54 68 65 20 70 61 74 74 65 72 6e 20 69 73 20 61 73 20 66 6f 6c 6c 6f 77 ┆attern. The pattern is as follow┆
0x37c0…37e0 73 3a 20 30 30 20 46 46 20 46 45 20 46 44 20 65 74 63 2e 20 72 65 70 65 61 74 65 64 20 34 20 0a ┆s: 00 FF FE FD etc. repeated 4 ┆
0x37e0…3800 74 69 6d 65 73 2e 0d 0a 0d 0a 84 57 68 65 6e 20 74 68 65 20 74 72 61 6e 73 70 6f 72 74 20 69 73 ┆times. When the transport is┆
0x3800…3820 (28,) 20 66 69 6e 69 73 68 65 64 2c 20 74 68 65 20 72 65 63 65 69 76 69 6e 67 20 62 75 66 66 65 72 20 ┆ finished, the receiving buffer ┆
0x3820…3840 69 73 20 63 68 65 63 6b 65 64 20 0a 61 67 61 69 6e 73 74 20 74 68 65 20 74 72 61 6e 73 6d 69 74 ┆is checked against the transmit┆
0x3840…3860 74 65 64 20 62 75 66 66 65 72 20 62 79 74 65 20 62 79 20 62 79 74 65 2e 0d 0a 0d 0a 84 49 66 20 ┆ted buffer byte by byte. If ┆
0x3860…3880 74 68 65 20 74 72 61 6e 73 70 6f 72 74 20 69 73 20 63 6f 72 72 65 63 74 20 69 74 20 69 73 20 74 ┆the transport is correct it is t┆
0x3880…38a0 65 73 74 65 64 20 69 66 20 74 68 65 20 44 4d 41 20 63 61 6e 20 72 65 73 70 6f 6e 64 20 0a 77 69 ┆ested if the DMA can respond wi┆
0x38a0…38c0 74 68 20 61 6e 20 69 6e 74 65 72 72 75 70 74 20 61 66 74 65 72 20 65 6e 64 20 6f 66 20 62 6c 6f ┆th an interrupt after end of blo┆
0x38c0…38e0 63 6b 20 69 73 20 72 65 61 63 68 65 64 2e 0d 0a 0d 0a 84 a1 50 6f 73 73 69 62 6c 65 20 6d 65 73 ┆ck is reached. Possible mes┆
0x38e0…3900 73 61 67 65 73 20 61 72 65 3a 0d 0a 0d 0a 09 84 3c 4f 4b 3e 0d 0a 0d 0a 09 3c 6e 6f 74 20 69 6e ┆sages are: <OK> <not in┆
0x3900…3920 73 74 61 6c 6c 65 64 3e 0d 0a 0d 0a 09 77 68 65 6e 20 74 65 73 74 69 6e 67 20 74 72 61 6e 73 66 ┆stalled> when testing transf┆
0x3920…3940 65 72 3a 0d 0a 0d 0a 09 09 3c 45 6e 64 20 6f 66 20 42 6c 6f 63 6b 20 74 69 6d 65 6f 75 74 20 32 ┆er: <End of Block timeout 2┆
0x3940…3960 30 30 20 6d 73 3e 0d 0a 09 09 3c 64 61 74 61 20 65 72 72 6f 72 2c 20 62 79 74 65 20 6e 6f 3a 20 ┆00 ms> <data error, byte no: ┆
0x3960…3980 78 78 20 78 78 20 65 78 70 3a 20 78 78 20 72 65 63 3a 20 78 78 3e 0d 0a 0d 0a 09 77 68 65 6e 20 ┆xx xx exp: xx rec: xx> when ┆
0x3980…39a0 74 65 73 74 69 6e 67 20 69 6e 74 65 72 72 75 70 74 3a 0d 0a 0d 0a 09 09 3c 74 69 6d 65 6f 75 74 ┆testing interrupt: <timeout┆
0x39a0…39c0 3e 0d 0a 0d 0a 09 09 3c 84 64 61 74 61 20 65 72 72 6f 72 2c 20 62 79 74 65 20 6e 6f 3a 20 78 78 ┆> < data error, byte no: xx┆
0x39c0…39e0 20 78 78 20 65 78 70 3a 20 78 78 20 72 65 63 3a 20 78 78 20 69 6e 20 0a 19 8f 80 80 69 6e 74 65 ┆ xx exp: xx rec: xx in inte┆
0x39e0…3a00 72 72 75 70 74 3e 0d 0a 0d 0a 84 41 6c 6c 20 6e 75 6d 62 65 72 73 20 61 72 65 20 69 6e 20 68 65 ┆rrupt> All numbers are in he┆
0x3a00…3a20 (29,) 78 61 64 65 63 69 6d 61 6c 20 6e 6f 74 61 74 69 6f 6e 2e 20 22 45 6e 64 20 6f 66 20 42 6c 6f 63 ┆xadecimal notation. "End of Bloc┆
0x3a20…3a40 6b 20 74 69 6d 65 6f 75 74 20 0a 32 30 30 20 6d 73 22 20 73 68 6f 77 73 20 74 68 61 74 20 74 68 ┆k timeout 200 ms" shows that th┆
0x3a40…3a60 65 20 65 6e 64 20 6f 66 20 62 6c 6f 63 6b 20 62 69 74 20 69 6e 20 74 68 65 20 44 4d 41 20 73 74 ┆e end of block bit in the DMA st┆
0x3a60…3a80 61 74 75 73 20 0a 72 65 67 69 73 74 65 72 20 68 61 73 20 6e 6f 74 20 62 65 65 6e 20 73 65 74 20 ┆atus register has not been set ┆
0x3a80…3aa0 77 69 74 68 69 6e 20 32 30 30 20 6d 73 2c 20 61 6e 64 20 74 68 65 20 74 72 61 6e 73 70 6f 72 74 ┆within 200 ms, and the transport┆
0x3aa0…3ac0 20 69 73 20 0a 74 68 65 72 65 66 6f 72 65 20 6e 6f 74 20 73 75 63 63 65 73 66 75 6c 2e 0d 0a 0d ┆ is therefore not succesful. ┆
0x3ac0…3ac2 0a 0a ┆ ┆
0x3ac2…3ac5 FormFeed {
0x3ac2…3ac5 0c 83 ec ┆ ┆
0x3ac2…3ac5 }
0x3ac5…3ae0 0a a1 31 31 2e 09 43 52 54 20 54 45 53 54 0d 0a 0d 0a 54 68 69 73 20 69 73 20 61 ┆ 11. CRT TEST This is a┆
0x3ae0…3b00 20 76 69 73 75 61 6c 20 74 65 73 74 2e 0d 0a 0d 0a 84 49 74 20 69 73 20 70 6f 73 73 69 62 6c 79 ┆ visual test. It is possibly┆
0x3b00…3b20 20 74 6f 20 73 74 6f 70 20 74 68 65 20 74 65 73 74 20 62 79 20 70 72 65 73 73 69 6e 67 20 74 68 ┆ to stop the test by pressing th┆
0x3b20…3b40 65 20 22 48 22 20 6b 65 79 2e 20 54 6f 20 0a 63 6f 6e 74 69 6e 75 65 20 70 72 65 73 73 20 74 68 ┆e "H" key. To continue press th┆
0x3b40…3b60 65 20 22 52 45 54 55 52 4e 22 20 4b 45 59 2e 0d 0a 0d 0a 54 68 65 20 66 6f 6c 6c 6f 77 69 6e 67 ┆e "RETURN" KEY. The following┆
0x3b60…3b80 20 73 68 6f 75 6c 64 20 61 70 70 65 61 72 20 6f 6e 20 74 68 65 20 73 63 72 65 65 6e 2e 0d 0a 0d ┆ should appear on the screen. ┆
0x3b80…3ba0 0a 54 68 65 20 63 68 61 72 61 63 74 65 72 2d 50 52 4f 4d 20 69 73 20 77 72 69 74 74 65 6e 2e 0d ┆ The character-PROM is written. ┆
0x3ba0…3bc0 0a 0d 0a 84 46 69 65 6c 64 20 61 74 74 72 69 62 75 74 65 73 20 74 65 73 74 2e 20 54 68 65 20 66 ┆ Field attributes test. The f┆
0x3bc0…3be0 69 65 6c 64 20 61 74 74 72 69 62 75 74 65 73 20 61 72 65 20 74 65 73 74 65 64 20 6f 6e 20 74 68 ┆ield attributes are tested on th┆
0x3be0…3c00 65 20 0a 63 68 61 72 61 63 74 65 72 2d 50 52 4f 4d 2e 20 54 68 65 20 32 35 20 6c 69 6e 65 73 20 ┆e character-PROM. The 25 lines ┆
0x3c00…3c20 (30,) 61 70 70 65 61 72 20 61 73 20 66 6f 6c 6c 6f 77 73 3a 0d 0a 0d 0a 09 20 20 20 84 61 3a 20 35 20 ┆appear as follows: a: 5 ┆
0x3c20…3c40 6c 69 6e 65 73 20 77 69 74 68 20 68 69 67 68 6c 69 67 68 74 0d 0a 20 20 20 20 20 20 20 62 3a 20 ┆lines with highlight b: ┆
0x3c40…3c60 34 20 6c 69 6e 65 73 20 77 69 74 68 20 72 65 76 65 72 73 65 20 76 69 64 65 6f 2b 68 69 67 68 6c ┆4 lines with reverse video+highl┆
0x3c60…3c80 69 67 68 74 0d 0a 20 20 20 20 20 20 20 63 3a 20 34 20 6c 69 6e 65 73 20 77 69 74 68 20 72 65 76 ┆ight c: 4 lines with rev┆
0x3c80…3ca0 65 72 73 65 20 76 69 64 65 6f 0d 0a 20 20 20 20 20 20 20 64 3a 20 34 20 6c 69 6e 65 73 20 77 69 ┆erse video d: 4 lines wi┆
0x3ca0…3cc0 74 68 20 69 6e 76 69 73 69 62 6c 65 0d 0a 20 20 20 20 20 20 20 65 3a 20 34 20 6c 69 6e 65 73 20 ┆th invisible e: 4 lines ┆
0x3cc0…3ce0 77 69 74 68 20 75 6e 64 65 72 6c 69 6e 65 0d 0a 20 20 20 20 20 20 20 66 3a 20 34 20 6c 69 6e 65 ┆with underline f: 4 line┆
0x3ce0…3d00 73 20 77 69 74 68 20 62 6c 69 6e 6b 0d 0a 0d 0a 84 54 68 65 20 73 63 72 65 65 6e 20 69 73 20 20 ┆s with blink The screen is ┆
0x3d00…3d20 66 69 6c 6c 65 64 20 77 69 74 68 20 22 48 22 2e 20 54 6f 20 61 64 6a 75 73 74 20 74 68 65 20 73 ┆filled with "H". To adjust the s┆
0x3d20…3d40 63 72 65 65 6e 20 22 48 22 20 20 20 20 20 20 20 20 0a 69 73 20 6f 66 74 65 6e 20 75 73 65 64 2e ┆creen "H" is often used.┆
0x3d40…3d60 0d 0a 0d 0a 84 54 68 65 20 63 6f 6e 74 72 61 73 74 20 61 6e 64 20 62 72 69 67 74 68 6e 65 73 73 ┆ The contrast and brigthness┆
0x3d60…3d80 20 61 72 65 20 74 65 73 74 65 64 2e 20 46 69 72 73 74 20 74 68 65 20 63 6f 6e 74 72 61 73 74 20 ┆ are tested. First the contrast ┆
0x3d80…3da0 61 6e 64 20 0a 74 68 65 6e 20 74 68 65 20 62 72 69 67 74 6e 65 73 73 20 61 72 65 20 74 65 73 74 ┆and then the brigtness are test┆
0x3da0…3dc0 65 64 2e 20 46 6f 72 20 62 6f 74 68 2c 20 66 69 72 73 74 20 6d 61 78 69 6d 75 6d 2c 20 74 68 65 ┆ed. For both, first maximum, the┆
0x3dc0…3de0 6e 20 0a 6d 69 6e 69 6d 75 6d 20 61 6e 64 20 66 69 6e 61 6c 6c 79 20 6e 6f 72 6d 61 6c 6c 79 20 ┆n minimum and finally normally ┆
0x3de0…3e00 73 68 6f 75 6c 64 20 61 70 70 65 61 72 2e 0d 0a 0d 0a 84 49 66 20 6e 6f 74 20 61 20 70 61 70 65 ┆should appear. If not a pape┆
0x3e00…3e20 (31,) 72 77 68 69 74 65 20 6d 6f 6e 69 74 6f 72 20 74 68 65 6e 20 74 68 65 20 74 65 73 74 20 65 6e 64 ┆rwhite monitor then the test end┆
0x3e20…3e40 73 20 75 70 20 77 69 74 68 20 74 68 65 20 31 33 32 20 0a 63 68 61 72 61 63 74 65 72 20 73 65 74 ┆s up with the 132 character set┆
0x3e40…3e52 20 77 72 69 74 74 65 6e 2e 0d 0a 8c 82 e8 0a a1 0d 0a ┆ written. ┆
0x3e52…3e55 FormFeed {
0x3e52…3e55 0c 80 8c ┆ ┆
0x3e52…3e55 }
0x3e55…3e60 0a 1a 1a 20 1a 1a 20 69 73 20 61 ┆ is a┆
0x3e60…3e80 20 74 65 73 74 2c 20 77 68 69 63 68 20 76 65 72 69 66 69 65 73 20 74 68 65 20 0a 66 75 6e 63 74 ┆ test, which verifies the funct┆