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DataMuseum.dkPresents historical artifacts from the history of: Rational R1000/400 DFS Tapes |
This is an automatic "excavation" of a thematic subset of
See our Wiki for more about Rational R1000/400 DFS Tapes Excavated with: AutoArchaeologist - Free & Open Source Software. |
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Length: 528384 (0x81000)
Types: M200_UCODE
Names: »M207_53.M200_UCODE«
└─⟦bc1274df5⟧ Bits:30000750 8mm tape, Rational 1000, DFS backup from PAM's R1000
└─⟦this⟧ »M207_53.M200_UCODE«
0100 ; -------------------------------------------------------------------------------------- 0100 ; no details_5e1032 0100 ; Initial Register File (adr, typ, val, frame:offset) where non-zero 0100 ; 000 TR00:00 0000000000000100 VR00:00 0000000008000000 0100 ; 001 TR00:01 00000000c0000000 VR00:01 0000000048000000 0100 ; 002 TR00:02 0000000068000060 VR00:02 0000000088000000 0100 ; 003 TR00:03 00000000a8000060 VR00:03 0000000000000000 0100 ; 004 TR00:04 0000000000000058 VR00:04 0000000000000000 0100 ; 005 TR00:05 0000000000000005 VR00:05 0000000000000000 0100 ; 006 TR00:06 0000000000000000 VR00:06 0000000000000000 0100 ; 007 TR00:07 0000000000000000 VR00:07 0000000000000000 0100 ; 008 TR00:08 0000000000000000 VR00:08 0000000000000000 0100 ; 009 TR00:09 0000000000000000 VR00:09 0000000000000000 0100 ; 00a TR00:0a 0000000000000000 VR00:0a 0000000000000000 0100 ; 00b TR00:0b 0000000000000000 VR00:0b 0000000000000000 0100 ; 00c TR00:0c 0000000000000000 VR00:0c 0000000000000000 0100 ; 00d TR00:0d 0000000000000000 VR00:0d 0000000000000000 0100 ; 00e TR00:0e 0000000000000000 VR00:0e 0000000000000000 0100 ; 00f TR00:0f 0000000000000000 VR00:0f 0000000000000000 0100 ; 010 TR00:10 0000000000000000 VR00:10 0000000000000000 0100 ; 011 TR00:11 0000000000000000 VR00:11 0000000000000000 0100 ; 012 TR00:12 0000000000000000 VR00:12 0000000000000000 0100 ; 013 TR00:13 0000000000000000 VR00:13 0000000000000000 0100 ; 014 TR00:14 0000000000000000 VR00:14 0000000000000000 0100 ; 015 TR00:15 0000000000000000 VR00:15 0000000000000000 0100 ; 016 TR00:16 0000000000000000 VR00:16 0000000000000000 0100 ; 017 TR00:17 0000000000000000 VR00:17 0000000000000000 0100 ; 018 TR00:18 0000000000000000 VR00:18 0000000000000000 0100 ; 019 TR00:19 0000000000000000 VR00:19 0000000000000000 0100 ; 01a TR00:1a 0000000000000000 VR00:1a 0000000000000000 0100 ; 01b TR00:1b 0000000000000000 VR00:1b 0000000000000000 0100 ; 01c TR00:1c 0000000000000000 VR00:1c 0000000000000000 0100 ; 01d TR00:1d 0000000000000000 VR00:1d 0000000000000000 0100 ; 01e TR00:1e 0000000000000000 VR00:1e 0000000000000000 0100 ; 01f TR00:1f 0000000000000000 VR00:1f 0000000000000000 0100 ; 020 TR01:00 ffffffffffffff00 VR01:00 0000000000000000 0100 ; 021 TR01:01 0000000080000000 VR01:01 0000000000000000 0100 ; 022 TR01:02 0000000040000000 VR01:02 0000000000000000 0100 ; 023 TR01:03 0000000020000000 VR01:03 0000000000000000 0100 ; 024 TR01:04 0000000000000000 VR01:04 0000000000000000 0100 ; 025 TR01:05 0000000000000000 VR01:05 0000000000000000 0100 ; 026 TR01:06 0000000000000000 VR01:06 0000000000000000 0100 ; 027 TR01:07 0000000000000000 VR01:07 0000000000000000 0100 ; 028 TR01:08 0000000000000000 VR01:08 0000000000000000 0100 ; 029 TR01:09 0000000000000000 VR01:09 0000000000000000 0100 ; 02a TR01:0a 0000000000000000 VR01:0a 0000000000000000 0100 ; 02b TR01:0b 0000000000000000 VR01:0b 0000000000000000 0100 ; 02c TR01:0c 0000000000000000 VR01:0c 0000000000000000 0100 ; 02d TR01:0d 0000000000000000 VR01:0d 0000000000000000 0100 ; 02e TR01:0e 0000000000000000 VR01:0e 0000000000000000 0100 ; 02f TR01:0f 0000000000000000 VR01:0f 0000000000000000 0100 ; 030 TR01:10 0000000000000000 VR01:10 0000000000000000 0100 ; 031 TR01:11 0000000000000000 VR01:11 0000000000000000 0100 ; 032 TR01:12 0000000000000000 VR01:12 0000000000000000 0100 ; 033 TR01:13 0000000000000000 VR01:13 0000000000000000 0100 ; 034 TR01:14 0000000000000000 VR01:14 0000000000000000 0100 ; 035 TR01:15 0000000000000000 VR01:15 0000000000000000 0100 ; 036 TR01:16 0000000000000000 VR01:16 0000000000000000 0100 ; 037 TR01:17 0000000000000000 VR01:17 0000000000000000 0100 ; 038 TR01:18 0000000000000000 VR01:18 0000000000000000 0100 ; 039 TR01:19 0000000000000000 VR01:19 0000000000000000 0100 ; 03a TR01:1a 0000000000000000 VR01:1a 0000000000000000 0100 ; 03b TR01:1b 0000000000000000 VR01:1b 0000000000000000 0100 ; 03c TR01:1c 0000000000000000 VR01:1c 0000000000000000 0100 ; 03d TR01:1d 0000000000000000 VR01:1d 0000000000000000 0100 ; 03e TR01:1e 0000000000000000 VR01:1e 0000000000000000 0100 ; 03f TR01:1f 0000000000000000 VR01:1f 0000000000000000 0100 ; 040 TR02:00 0000000000000001 VR02:00 0000000000000010 0100 ; 041 TR02:01 000000000000003f VR02:01 0000000000000000 0100 ; 042 TR02:02 0000000000000000 VR02:02 0000000000000000 0100 ; 043 TR02:03 0000000000000021 VR02:03 0000000000000000 0100 ; 044 TR02:04 0000000000000029 VR02:04 0000000000000000 0100 ; 045 TR02:05 0000000000000000 VR02:05 0000000000000000 0100 ; 046 TR02:06 0000000000000300 VR02:06 0000000000000000 0100 ; 047 TR02:07 0000000010000000 VR02:07 0000000000000000 0100 ; 048 TR02:08 0000000018000000 VR02:08 0000000000000000 0100 ; 049 TR02:09 0000000020000000 VR02:09 0000000000000000 0100 ; 04a TR02:0a 0000000000000009 VR02:0a 0000000000000000 0100 ; 04b TR02:0b ffffffffffffff80 VR02:0b 0000000000000000 0100 ; 04c TR02:0c 000007c000000000 VR02:0c 0000000000000000 0100 ; 04d TR02:0d 0000000000000029 VR02:0d 0400000000000000 0100 ; 04e TR02:0e 0000000000000021 VR02:0e ff00000000000000 0100 ; 04f TR02:0f 0000000000000000 VR02:0f 0000000000000000 0100 ; 050 TR02:10 0000000040000000 VR02:10 ffffffffffffffff 0100 ; 051 TR02:11 0000000000000008 VR02:11 0000000000000001 0100 ; 052 TR02:12 0000000000000000 VR02:12 0000000000000040 0100 ; 053 TR02:13 0000000000000400 VR02:13 0000000000001fff 0100 ; 054 TR02:14 0000001000000000 VR02:14 0000000010000000 0100 ; 055 TR02:15 0000000008000000 VR02:15 0000000020000000 0100 ; 056 TR02:16 000000000000007e VR02:16 0000000030000000 0100 ; 057 TR02:17 0000800000000000 VR02:17 00000000f8000080 0100 ; 058 TR02:18 0000000000000000 VR02:18 000000000000007f 0100 ; 059 TR02:19 000000000000007f VR02:19 0000000000000000 0100 ; 05a TR02:1a 000000000000003f VR02:1a 0000000000000002 0100 ; 05b TR02:1b 0000000000000000 VR02:1b 00000000ffffffff 0100 ; 05c TR02:1c 0000000008000000 VR02:1c 0000000000000000 0100 ; 05d TR02:1d 00000000f8000000 VR02:1d 0000000000000010 0100 ; 05e TR02:1e 0000000007ffff80 VR02:1e 0000000007ffff80 0100 ; 05f TR02:1f 0000000000000180 VR02:1f 0000000000000060 0100 ; 060 TR03:00 0000000000000000 VR03:00 0000000000000000 0100 ; 061 TR03:01 0000000000000000 VR03:01 0000000000000000 0100 ; 062 TR03:02 0000000000000000 VR03:02 0000000000000000 0100 ; 063 TR03:03 0000000000000000 VR03:03 0000000000000000 0100 ; 064 TR03:04 0000000000000000 VR03:04 0000000000000000 0100 ; 065 TR03:05 0000000000000000 VR03:05 0000000000000000 0100 ; 066 TR03:06 0000000000000000 VR03:06 0000000000000000 0100 ; 067 TR03:07 0000000000000000 VR03:07 0000000000000000 0100 ; 068 TR03:08 0000000000000000 VR03:08 0000000000000000 0100 ; 069 TR03:09 0000000000000000 VR03:09 0000000000000000 0100 ; 06a TR03:0a 0000000000000000 VR03:0a 0000000000000000 0100 ; 06b TR03:0b 0000000000000000 VR03:0b 0000000000000000 0100 ; 06c TR03:0c 0000000000000000 VR03:0c 0000000000000000 0100 ; 06d TR03:0d 0000000000000000 VR03:0d 0000000000000000 0100 ; 06e TR03:0e 0000000000000000 VR03:0e 0000000000000000 0100 ; 06f TR03:0f 0000000000000000 VR03:0f 0000000000000000 0100 ; 070 TR03:10 0000000000000000 VR03:10 0000000000000004 0100 ; 071 TR03:11 0000000000000000 VR03:11 0000000000000000 0100 ; 072 TR03:12 0000000000000000 VR03:12 0000000000000000 0100 ; 073 TR03:13 0000000000000000 VR03:13 0000000000000000 0100 ; 074 TR03:14 0000000000000000 VR03:14 0000000000000000 0100 ; 075 TR03:15 0000000000000000 VR03:15 0000000000000000 0100 ; 076 TR03:16 0000000000000000 VR03:16 0000000000000000 0100 ; 077 TR03:17 0000000000000000 VR03:17 0bad0bad0bad0bad 0100 ; 078 TR03:18 0404000100000000 VR03:18 0000000000000000 0100 ; 079 TR03:19 0000000000000000 VR03:19 0000000000000000 0100 ; 07a TR03:1a 0000000000000000 VR03:1a 0000000000000000 0100 ; 07b TR03:1b 0000000000000000 VR03:1b 0000200000000000 0100 ; 07c TR03:1c 0000000000000000 VR03:1c 0000000000000000 0100 ; 07d TR03:1d 0000000000000000 VR03:1d 0000000000000000 0100 ; 07e TR03:1e 0000000000000000 VR03:1e 0000000000000004 0100 ; 07f TR03:1f 0000000000000000 VR03:1f 0000000000000000 0100 ; 080 TR04:00 0000000000000000 VR04:00 0000000000000000 0100 ; 081 TR04:01 0000000000000000 VR04:01 0000000000000001 0100 ; 082 TR04:02 0000000000000000 VR04:02 0000000000000000 0100 ; 083 TR04:03 0000000000000000 VR04:03 0000000000000000 0100 ; 084 TR04:04 0000000000000000 VR04:04 0000000000000000 0100 ; 085 TR04:05 0000000000000000 VR04:05 0000000000000000 0100 ; 086 TR04:06 0000000000000000 VR04:06 0000000000000000 0100 ; 087 TR04:07 0000000000000000 VR04:07 0000000000000000 0100 ; 088 TR04:08 0000000000000000 VR04:08 0000000000000000 0100 ; 089 TR04:09 0000000000000000 VR04:09 0000000000000000 0100 ; 08a TR04:0a 0000000000000028 VR04:0a 0000000000000000 0100 ; 08b TR04:0b 0000000000000000 VR04:0b 0000000000000000 0100 ; 08c TR04:0c 0000000000000000 VR04:0c 0000000000000000 0100 ; 08d TR04:0d 0000000000000180 VR04:0d 0000000000000080 0100 ; 08e TR04:0e 0000000000000000 VR04:0e 0000000000000100 0100 ; 08f TR04:0f 0000000000000000 VR04:0f 0000000000000180 0100 ; 090 TR04:10 0000000000000000 VR04:10 0000000000000500 0100 ; 091 TR04:11 0000000000000000 VR04:11 0000000000001f80 0100 ; 092 TR04:12 0000000000000000 VR04:12 000ffcf00000a000 0100 ; 093 TR04:13 0000000000000000 VR04:13 0000000000200000 0100 ; 094 TR04:14 0000000000000000 VR04:14 0000000000000000 0100 ; 095 TR04:15 0000000000000000 VR04:15 0000000000000000 0100 ; 096 TR04:16 0000000000000000 VR04:16 0000000000000000 0100 ; 097 TR04:17 0000000000000000 VR04:17 0000000000000000 0100 ; 098 TR04:18 0000000000000000 VR04:18 0000000000000000 0100 ; 099 TR04:19 0000000000000000 VR04:19 0000000000000000 0100 ; 09a TR04:1a 0000000000000000 VR04:1a 0000000000000000 0100 ; 09b TR04:1b 0000000000000000 VR04:1b 000000000000a000 0100 ; 09c TR04:1c 0000000000000000 VR04:1c 0000040000000000 0100 ; 09d TR04:1d 0000000000000000 VR04:1d 0000000000000000 0100 ; 09e TR04:1e 0000000000000000 VR04:1e 0000000000000000 0100 ; 09f TR04:1f 0000000000000000 VR04:1f 0000000000000000 0100 ; 0a0 TR05:00 0000000000000001 VR05:00 0000000000000001 0100 ; 0a1 TR05:01 0000000000000004 VR05:01 0000000000000003 0100 ; 0a2 TR05:02 0000004000000000 VR05:02 0000000000000005 0100 ; 0a3 TR05:03 0000000000000006 VR05:03 0000000000000006 0100 ; 0a4 TR05:04 000000000000000a VR05:04 0000000000000007 0100 ; 0a5 TR05:05 000000000000000e VR05:05 0000000000000008 0100 ; 0a6 TR05:06 000000000000000f VR05:06 0000000000000009 0100 ; 0a7 TR05:07 0000000000000013 VR05:07 000000000000000a 0100 ; 0a8 TR05:08 0000000000000014 VR05:08 000000000000000b 0100 ; 0a9 TR05:09 0000000000000016 VR05:09 000000000000000c 0100 ; 0aa TR05:0a 0000000000000026 VR05:0a 000000000000000d 0100 ; 0ab TR05:0b 0000000000000036 VR05:0b 000000000000000e 0100 ; 0ac TR05:0c 0000000000000039 VR05:0c 0000000000002300 0100 ; 0ad TR05:0d 0000000000000040 VR05:0d 0000000000000020 0100 ; 0ae TR05:0e 0000000000000046 VR05:0e 0000000000000025 0100 ; 0af TR05:0f 000000000000005f VR05:0f 0000000000000031 0100 ; 0b0 TR05:10 0000000000000060 VR05:10 000000000000003f 0100 ; 0b1 TR05:11 000000f000000000 VR05:11 00000000fff90000 0100 ; 0b2 TR05:12 000000000000007b VR05:12 0000000000000480 0100 ; 0b3 TR05:13 0000000000000680 VR05:13 000000000000006c 0100 ; 0b4 TR05:14 000000000000009e VR05:14 0000000000000074 0100 ; 0b5 TR05:15 0000000000000118 VR05:15 000000000000007c 0100 ; 0b6 TR05:16 0000000000000158 VR05:16 00000000000000ff 0100 ; 0b7 TR05:17 0000000000000200 VR05:17 0000000000000076 0100 ; 0b8 TR05:18 0000000000000300 VR05:18 0000000000000200 0100 ; 0b9 TR05:19 0000000000000380 VR05:19 0000000000000580 0100 ; 0ba TR05:1a 0000000000000800 VR05:1a 00000000000003ff 0100 ; 0bb TR05:1b 0000000000001f80 VR05:1b 0000000000000400 0100 ; 0bc TR05:1c 0000000007ff8000 VR05:1c 0000000000002400 0100 ; 0bd TR05:1d 0000000008000008 VR05:1d 0000010000000000 0100 ; 0be TR05:1e 0000000008000046 VR05:1e 000000000000ffff 0100 ; 0bf TR05:1f 0000000000000047 VR05:1f 5f5f5f5f5f5f5f5f 0100 ; 0c0 TR06:00 000000000800009e VR06:00 0000000040000000 0100 ; 0c1 TR06:01 0000000020000060 VR06:01 000000000000000f 0100 ; 0c2 TR06:02 00000000f6000000 VR06:02 0000000080000000 0100 ; 0c3 TR06:03 0d04000f00000001 VR06:03 0002000000000000 0100 ; 0c4 TR06:04 0000000080000118 VR06:04 fffffeff00000000 0100 ; 0c5 TR06:05 0000000080000158 VR06:05 00000000000000f0 0100 ; 0c6 TR06:06 0000000088000000 VR06:06 0000000000008000 0100 ; 0c7 TR06:07 fffffffffffffe80 VR06:07 00000000c0000000 0100 ; 0c8 TR06:08 0000000000000580 VR06:08 0000000100000001 0100 ; 0c9 TR06:09 0000000000000064 VR06:09 0000004000000040 0100 ; 0ca TR06:0a 0000000000000015 VR06:0a 0000004100000041 0100 ; 0cb TR06:0b 0000000007ffe000 VR06:0b 0000007fffffffff 0100 ; 0cc TR06:0c 000000000800006c VR06:0c 000000000004c4b4 0100 ; 0cd TR06:0d 00000000000002a0 VR06:0d 0000000000000028 0100 ; 0ce TR06:0e 00000000ffff0000 VR06:0e 0004000000000000 0100 ; 0cf TR06:0f 0000000f00000000 VR06:0f 0000000000000032 0100 ; 0d0 TR06:10 ffffffffc0000000 VR06:10 00ffffff0000000f 0100 ; 0d1 TR06:11 ff00000000000000 VR06:11 0200000000000000 0100 ; 0d2 TR06:12 00000000e0000176 VR06:12 8000000000000000 0100 ; 0d3 TR06:13 ffff000000000000 VR06:13 8200000000000000 0100 ; 0d4 TR06:14 00000000000000c0 VR06:14 0000000000000041 0100 ; 0d5 TR06:15 ffffffffffff0000 VR06:15 00000000000002a0 0100 ; 0d6 TR06:16 fffffffffffffe00 VR06:16 000000007fffffff 0100 ; 0d7 TR06:17 000000000000000d VR06:17 ffffffff80000000 0100 ; 0d8 TR06:18 0000000000000076 VR06:18 0000000000000027 0100 ; 0d9 TR06:19 00000000d0000000 VR06:19 00000000000010c0 0100 ; 0da TR06:1a 0000000008000000 VR06:1a 0000000000000042 0100 ; 0db TR06:1b 000000000000002e VR06:1b 00000000000000fe 0100 ; 0dc TR06:1c fffffffffffffd00 VR06:1c 0000000000001008 0100 ; 0dd TR06:1d 0000000000000039 VR06:1d 0000000100000000 0100 ; 0de TR06:1e 00000000c0000116 VR06:1e 0000000200000000 0100 ; 0df TR06:1f 0000000000002000 VR06:1f 0000000000002000 0100 ; 0e0 TR07:00 0000000000000280 VR07:00 ffffffffffffff80 0100 ; 0e1 TR07:01 0000003000000000 VR07:01 000fffff00000000 0100 ; 0e2 TR07:02 ffff00000000000e VR07:02 0100000000000000 0100 ; 0e3 TR07:03 0000000060000000 VR07:03 0000000000000011 0100 ; 0e4 TR07:04 000000000000016c VR07:04 000000000000fff0 0100 ; 0e5 TR07:05 00ff000000000000 VR07:05 0000ffffffffffff 0100 ; 0e6 TR07:06 0001000000000000 VR07:06 000000000000004e 0100 ; 0e7 TR07:07 0000005000000000 VR07:07 0000000000000f80 0100 ; 0e8 TR07:08 00000000f0000000 VR07:08 ffffffff00000000 0100 ; 0e9 TR07:09 0000000048000000 VR07:09 7fffffffffffffff 0100 ; 0ea TR07:0a 0000000030000000 VR07:0a 0000000000000026 0100 ; 0eb TR07:0b 0000000088000011 VR07:0b 0000000000000036 0100 ; 0ec TR07:0c 00000000a8000071 VR07:0c 0000008000000040 0100 ; 0ed TR07:0d 0000000000000174 VR07:0d 0000000000000280 0100 ; 0ee TR07:0e 0000000080000029 VR07:0e 0000000000000380 0100 ; 0ef TR07:0f 0000007f00000000 VR07:0f 0000000000000021 0100 ; 0f0 TR07:10 0100000000000000 VR07:10 0000000000000016 0100 ; 0f1 TR07:11 0200000000000000 VR07:11 00000000ffff00ff 0100 ; 0f2 TR07:12 fec7000000000000 VR07:12 0000000000000012 0100 ; 0f3 TR07:13 0000000000001001 VR07:13 0000000000000043 0100 ; 0f4 TR07:14 000000000ff00000 VR07:14 00000000000000a0 0100 ; 0f5 TR07:15 00000000ffffffff VR07:15 ffffffffffffff00 0100 ; 0f6 TR07:16 0000037000000000 VR07:16 0000800000000000 0100 ; 0f7 TR07:17 000000000000003e VR07:17 0000005500000000 0100 ; 0f8 TR07:18 0000040400000050 VR07:18 8000005500000000 0100 ; 0f9 TR07:19 0000000040000020 VR07:19 0000000000000038 0100 ; 0fa TR07:1a 000000000000004e VR07:1a 0000000088000011 0100 ; 0fb TR07:1b 00000000000000ff VR07:1b ffffff8000000000 0100 ; 0fc TR07:1c 00000001ffffffff VR07:1c 0000008000000000 0100 ; 0fd TR07:1d 00000000f800007f VR07:1d 0000007f00000000 0100 ; 0fe TR07:1e 0000000080000010 VR07:1e 0000000000000045 0100 ; 0ff TR07:1f 0000000000000081 VR07:1f 0000000000000044 0100 ; 100 TR08:00 ffffffffffffffff VR08:00 00fe007f00000000 0100 ; 101 TR08:01 0000000060000060 VR08:01 00000000003fffff 0100 ; 102 TR08:02 0000000000000044 VR08:02 0001000000000000 0100 ; 103 TR08:03 ffffffffffffffe0 VR08:03 000000000000004c 0100 ; 104 TR08:04 000ffc000000a000 VR08:04 0000000000000013 0100 ; 105 TR08:05 0000008000000000 VR08:05 0000000000000030 0100 ; 106 TR08:06 000007c008000000 VR08:06 00000000000005ff 0100 ; 107 TR08:07 ffffffffe0000000 VR08:07 00ff000000000000 0100 ; 108 TR08:08 fffffffffffffecc VR08:08 1000000000000000 0100 ; 109 TR08:09 000000000800014c VR08:09 0000001000000000 0100 ; 10a TR08:0a 0000000007ffbf00 VR08:0a 00008000ffffffff 0100 ; 10b TR08:0b 8000000000000000 VR08:0b 0000808000000000 0100 ; 10c TR08:0c 2000000000000000 VR08:0c 00000000000000e0 0100 ; 10d TR08:0d 0000000000000050 VR08:0d 00000000000000e1 0100 ; 10e TR08:0e 000000003800001f VR08:0e 00000000000000e2 0100 ; 10f TR08:0f 0000000100000000 VR08:0f 00000000000000e3 0100 ; 110 TR08:10 fffff83ff7ffffff VR08:10 00000000000000e4 0100 ; 111 TR08:11 0000000000000054 VR08:11 0000000000000061 0100 ; 112 TR08:12 000000000000017c VR08:12 0000000000000062 0100 ; 113 TR08:13 1020a040101011c0 VR08:13 0000000000000063 0100 ; 114 TR08:14 000000000000001c VR08:14 0000000000000065 0100 ; 115 TR08:15 000000000000001b VR08:15 000000000000002f 0100 ; 116 TR08:16 0000000080000008 VR08:16 000000000000004f 0100 ; 117 TR08:17 0000000000004000 VR08:17 000000000000005f 0100 ; 118 TR08:18 0000000088000008 VR08:18 000000000000fe00 0100 ; 119 TR08:19 0000060000000000 VR08:19 fffe010000000080 0100 ; 11a TR08:1a 00000000a0000068 VR08:1a 0000000000002710 0100 ; 11b TR08:1b 0000000020000068 VR08:1b 0001ff8000000000 0100 ; 11c TR08:1c 0010000000000000 VR08:1c 0000000000000049 0100 ; 11d TR08:1d 000000000000001f VR08:1d 0408000000000000 0100 ; 11e TR08:1e 7ff0000000000000 VR08:1e 8204000000000000 0100 ; 11f TR08:1f 3ff0000000000000 VR08:1f 00000000000000d0 0100 ; 120 TR09:00 7fe0000000000000 VR09:00 000000000000007b 0100 ; 121 TR09:01 00000000000003ff VR09:01 00f0000000000000 0100 ; 122 TR09:02 00000000000007ff VR09:02 0000000000000300 0100 ; 123 TR09:03 ffffffffffffffcd VR09:03 0000000000000034 0100 ; 124 TR09:04 00000000e0000060 VR09:04 000000000000fc00 0100 ; 125 TR09:05 00000000e0000020 VR09:05 fff9000000000000 0100 ; 126 TR09:06 000000000000031f VR09:06 0000000000000070 0100 ; 127 TR09:07 00000000000000a0 VR09:07 1819113111161715 0100 ; 128 TR09:08 00000000e0000000 VR09:08 0000000000000014 0100 ; 129 TR09:09 0000000040000029 VR09:09 0000000008000100 0100 ; 12a TR09:0a 000000000fffff80 VR09:0a 0000000028000160 0100 ; 12b TR09:0b 00000000000000ad VR09:0b 00000000000002d0 0100 ; 12c TR09:0c 00000000e0000040 VR09:0c bff0000000000000 0100 ; 12d TR09:0d 000000000000004c VR09:0d 0006000000000000 0100 ; 12e TR09:0e 0000000020000040 VR09:0e 0000000000e00000 0100 ; 12f TR09:0f 8000000080000000 VR09:0f 0000000007ffff00 0100 ; 130 TR09:10 0000000008000025 VR09:10 0000000000000081 0100 ; 131 TR09:11 0000000020000020 VR09:11 0000000000000052 0100 ; 132 TR09:12 fffff83fffffffff VR09:12 0000000000000320 0100 ; 133 TR09:13 00000000f4000004 VR09:13 0000000000000050 0100 ; 134 TR09:14 0000000000000500 VR09:14 000000000000031f 0100 ; 135 TR09:15 fffffffffffffd80 VR09:15 000000ff00000000 0100 ; 136 TR09:16 0000000001800000 VR09:16 00000fffffffffff 0100 ; 137 TR09:17 ffffffff7fffff88 VR09:17 fffeffffffffffff 0100 ; 138 TR09:18 0000024000000000 VR09:18 fffffffffffeffff 0100 ; 139 TR09:19 0d01000100000001 VR09:19 0000000000000088 0100 ; 13a TR09:1a fffff83fe7ffffff VR09:1a 0000000000520000 0100 ; 13b TR09:1b 0000200000000000 VR09:1b 0000000000000082 0100 ; 13c TR09:1c 0000180000000000 VR09:1c 0000000000000046 0100 ; 13d TR09:1d 00001fc000000000 VR09:1d 0000000001ffe000 0100 ; 13e TR09:1e 0000000000020000 VR09:1e 0000000000000048 0100 ; 13f TR09:1f 0000000007ffff00 VR09:1f 0000000000000051 0100 ; 140 TR0a:00 0000000088000000 VR0a:00 0000000000000000 0100 ; 141 TR0a:01 0000000000000000 VR0a:01 0000000000000000 0100 ; 142 TR0a:02 0000000000000000 VR0a:02 0000000000000000 0100 ; 143 TR0a:03 0000000000000000 VR0a:03 0000000000000000 0100 ; 144 TR0a:04 0000000000000000 VR0a:04 0000000000000000 0100 ; 145 TR0a:05 0000000000000000 VR0a:05 0000000000000000 0100 ; 146 TR0a:06 0000000000000000 VR0a:06 0000000000000000 0100 ; 147 TR0a:07 0000000000000000 VR0a:07 0000000000000000 0100 ; 148 TR0a:08 0000000000000000 VR0a:08 0000000000000000 0100 ; 149 TR0a:09 0000000000000000 VR0a:09 0000000000000000 0100 ; 14a TR0a:0a 0000000000000000 VR0a:0a 0000000000000000 0100 ; 14b TR0a:0b 0000000000000000 VR0a:0b 0000000000000000 0100 ; 14c TR0a:0c 0000000000000000 VR0a:0c 0000000000000000 0100 ; 14d TR0a:0d 0000000000000000 VR0a:0d 0000000000000000 0100 ; 14e TR0a:0e 0000000000000000 VR0a:0e 0000000000000000 0100 ; 14f TR0a:0f 0000000000000000 VR0a:0f 0000000000000000 0100 ; 150 TR0a:10 0000000000000000 VR0a:10 0000000000000000 0100 ; 151 TR0a:11 0000000000000000 VR0a:11 0000000000000000 0100 ; 152 TR0a:12 0000000000000000 VR0a:12 0000000000000000 0100 ; 153 TR0a:13 0000000000000000 VR0a:13 0000000000000000 0100 ; 154 TR0a:14 0000000000000000 VR0a:14 0000000000000000 0100 ; 155 TR0a:15 0000000000000000 VR0a:15 0000000000000000 0100 ; 156 TR0a:16 0000000000000000 VR0a:16 0000000000000000 0100 ; 157 TR0a:17 0000000000000000 VR0a:17 0000000000000000 0100 ; 158 TR0a:18 0000000000000000 VR0a:18 0000000000000000 0100 ; 159 TR0a:19 0000000000000000 VR0a:19 0000000000000000 0100 ; 15a TR0a:1a 0000000000000000 VR0a:1a 0000000000000000 0100 ; 15b TR0a:1b 0000000000000000 VR0a:1b 0000000000000000 0100 ; 15c TR0a:1c 0000000000000000 VR0a:1c 0000000000000000 0100 ; 15d TR0a:1d 0000000000000000 VR0a:1d 0000000000000000 0100 ; 15e TR0a:1e 0000000000000000 VR0a:1e 0000000000000000 0100 ; 15f TR0a:1f 0000000000000000 VR0a:1f 0000000000000000 0100 ; 160 TR0b:00 ffffffffffffffff VR0b:00 ffffffffffffffff 0100 ; 161 TR0b:01 ffffffffffffffff VR0b:01 ffffffffffffffff 0100 ; 162 TR0b:02 ffffffffffffffff VR0b:02 ffffffffffffffff 0100 ; 163 TR0b:03 ffffffffffffffff VR0b:03 ffffffffffffffff 0100 ; 164 TR0b:04 ffffffffffffffff VR0b:04 ffffffffffffffff 0100 ; 165 TR0b:05 ffffffffffffffff VR0b:05 ffffffffffffffff 0100 ; 166 TR0b:06 ffffffffffffffff VR0b:06 ffffffffffffffff 0100 ; 167 TR0b:07 ffffffffffffffff VR0b:07 ffffffffffffffff 0100 ; 168 TR0b:08 ffffffffffffffff VR0b:08 ffffffffffffffff 0100 ; 169 TR0b:09 ffffffffffffffff VR0b:09 ffffffffffffffff 0100 ; 16a TR0b:0a ffffffffffffffff VR0b:0a ffffffffffffffff 0100 ; 16b TR0b:0b ffffffffffffffff VR0b:0b ffffffffffffffff 0100 ; 16c TR0b:0c ffffffffffffffff VR0b:0c ffffffffffffffff 0100 ; 16d TR0b:0d ffffffffffffffff VR0b:0d ffffffffffffffff 0100 ; 16e TR0b:0e ffffffffffffffff VR0b:0e ffffffffffffffff 0100 ; 16f TR0b:0f ffffffffffffffff VR0b:0f ffffffffffffffff 0100 ; 170 TR0b:10 ffffffffffffffff VR0b:10 ffffffffffffffff 0100 ; 171 TR0b:11 ffffffffffffffff VR0b:11 ffffffffffffffff 0100 ; 172 TR0b:12 ffffffffffffffff VR0b:12 ffffffffffffffff 0100 ; 173 TR0b:13 ffffffffffffffff VR0b:13 ffffffffffffffff 0100 ; 174 TR0b:14 ffffffffffffffff VR0b:14 ffffffffffffffff 0100 ; 175 TR0b:15 ffffffffffffffff VR0b:15 ffffffffffffffff 0100 ; 176 TR0b:16 ffffffffffffffff VR0b:16 ffffffffffffffff 0100 ; 177 TR0b:17 ffffffffffffffff VR0b:17 ffffffffffffffff 0100 ; 178 TR0b:18 ffffffffffffffff VR0b:18 ffffffffffffffff 0100 ; 179 TR0b:19 ffffffffffffffff VR0b:19 ffffffffffffffff 0100 ; 17a TR0b:1a ffffffffffffffff VR0b:1a ffffffffffffffff 0100 ; 17b TR0b:1b ffffffffffffffff VR0b:1b ffffffffffffffff 0100 ; 17c TR0b:1c ffffffffffffffff VR0b:1c ffffffffffffffff 0100 ; 17d TR0b:1d ffffffffffffffff VR0b:1d ffffffffffffffff 0100 ; 17e TR0b:1e ffffffffffffffff VR0b:1e ffffffffffffffff 0100 ; 17f TR0b:1f ffffffffffffffff VR0b:1f ffffffffffffffff 0100 ; 180 TR0c:00 0000000000000100 VR0c:00 0000000000000000 0100 ; 181 TR0c:01 0000000008000000 VR0c:01 0000000000000000 0100 ; 182 TR0c:02 0000000000000000 VR0c:02 000413ff00000000 0100 ; 183 TR0c:03 0000000000000000 VR0c:03 0000000000000000 0100 ; 184 TR0c:04 0000000000000000 VR0c:04 0000000000000000 0100 ; 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0000000000000c33 0100 ; 239 TR11:19 0000000080000038 VR11:19 0000000000000433 0100 ; 23a TR11:1a ffffffffffffffbf VR11:1a 0080000000000000 0100 ; 23b TR11:1b 00000000000003fe VR11:1b 0000000000000066 0100 ; 23c TR11:1c 0000024008000000 VR11:1c 0000000000000068 0100 ; 23d TR11:1d 000013ff00000000 VR11:1d 0000000000ffe000 0100 ; 23e TR11:1e 00000000000005ff VR11:1e 0000000000000029 0100 ; 23f TR11:1f 0500000000000000 VR11:1f 000000000000006b 0100 ; 240 TR12:00 0600000000000000 VR12:00 0000000007fff007 0100 ; 241 TR12:01 0c00000000000000 VR12:01 0000000000002800 0100 ; 242 TR12:02 0f00000000000000 VR12:02 0000000000002c00 0100 ; 243 TR12:03 cfcf000000000000 VR12:03 0000000000000083 0100 ; 244 TR12:04 0000100000000000 VR12:04 0000000000000084 0100 ; 245 TR12:05 0000000007ffe600 VR12:05 0000000000000085 0100 ; 246 TR12:06 000000009d000000 VR12:06 0000000000000160 0100 ; 247 TR12:07 ffffffff07ffff91 VR12:07 0000000000000140 0100 ; 248 TR12:08 0000000000000049 VR12:08 0000000007fff001 0100 ; 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0000000000000000 0100 ; 2cc TR16:0c 0000000000000000 VR16:0c 0000000000000000 0100 ; 2cd TR16:0d 0000000000000000 VR16:0d 0000000000000000 0100 ; 2ce TR16:0e 0000000000000000 VR16:0e 0000000000000000 0100 ; 2cf TR16:0f 0000000000000000 VR16:0f 0000000000000000 0100 ; 2d0 TR16:10 0000000000000000 VR16:10 0000000000000000 0100 ; 2d1 TR16:11 0000000000000000 VR16:11 0000000000000000 0100 ; 2d2 TR16:12 0000000000000000 VR16:12 0000000000000000 0100 ; 2d3 TR16:13 0000000000000000 VR16:13 0000000000000000 0100 ; 2d4 TR16:14 0000000000000000 VR16:14 0000000000000000 0100 ; 2d5 TR16:15 0000000000000000 VR16:15 0000000000000000 0100 ; 2d6 TR16:16 0000000000000000 VR16:16 0000000000000000 0100 ; 2d7 TR16:17 0000000000000000 VR16:17 0000000000000000 0100 ; 2d8 TR16:18 0000000000000000 VR16:18 0000000000000000 0100 ; 2d9 TR16:19 0000000000000000 VR16:19 0000000000000000 0100 ; 2da TR16:1a 0000000000000000 VR16:1a 0000000000000000 0100 ; 2db TR16:1b 0000000000000000 VR16:1b 0000000000000000 0100 ; 2dc TR16:1c 0000000000000000 VR16:1c 0000000000000000 0100 ; 2dd TR16:1d 0000000000000000 VR16:1d 0000000000000000 0100 ; 2de TR16:1e 0000000000000000 VR16:1e 0000000000000000 0100 ; 2df TR16:1f 0000000000000000 VR16:1f 0000000000000000 0100 ; 2e0 TR17:00 0000000000000000 VR17:00 0000000000000000 0100 ; 2e1 TR17:01 0000000000000000 VR17:01 0000000000000000 0100 ; 2e2 TR17:02 0000000000000000 VR17:02 0000000000000000 0100 ; 2e3 TR17:03 0000000000000000 VR17:03 0000000000000000 0100 ; 2e4 TR17:04 0000000000000000 VR17:04 0000000000000000 0100 ; 2e5 TR17:05 0000000000000000 VR17:05 0000000000000000 0100 ; 2e6 TR17:06 0000000000000000 VR17:06 0000000000000000 0100 ; 2e7 TR17:07 0000000000000000 VR17:07 0000000000000000 0100 ; 2e8 TR17:08 0000000000000000 VR17:08 0000000000000000 0100 ; 2e9 TR17:09 0000000000000000 VR17:09 0000000000000000 0100 ; 2ea TR17:0a 0000000000000000 VR17:0a 0000000000000000 0100 ; 2eb TR17:0b 0000000000000000 VR17:0b 0000000000000000 0100 ; 2ec TR17:0c 0000000000000000 VR17:0c 0000000000000000 0100 ; 2ed TR17:0d 0000000000000000 VR17:0d 0000000000000000 0100 ; 2ee TR17:0e 0000000000000000 VR17:0e 0000000000000000 0100 ; 2ef TR17:0f 0000000000000000 VR17:0f 0000000000000000 0100 ; 2f0 TR17:10 0000000000000000 VR17:10 0000000000000000 0100 ; 2f1 TR17:11 0000000000000000 VR17:11 0000000000000000 0100 ; 2f2 TR17:12 0000000000000000 VR17:12 0000000000000000 0100 ; 2f3 TR17:13 0000000000000000 VR17:13 0000000000000000 0100 ; 2f4 TR17:14 ffffffffffff0000 VR17:14 0000000007fffd80 0100 ; 2f5 TR17:15 0000000000000600 VR17:15 000ffcf00000a000 0100 ; 2f6 TR17:16 0000000000000180 VR17:16 0000000000000180 0100 ; 2f7 TR17:17 0000000000000100 VR17:17 0000000000000600 0100 ; 2f8 TR17:18 0000000000000500 VR17:18 0000000649534e00 0100 ; 2f9 TR17:19 fd00000000000000 VR17:19 0000000000098969 0100 ; 2fa TR17:1a fe00000000000000 VR17:1a ffff000000000000 0100 ; 2fb TR17:1b 8f8f000000000000 VR17:1b 000000000000ff00 0100 ; 2fc TR17:1c 4f4f000000000000 VR17:1c 0003ffffffffffff 0100 ; 2fd TR17:1d 0000000000000000 VR17:1d 0000000000000000 0100 ; 2fe TR17:1e 0000000080000000 VR17:1e 0000000000000500 0100 ; 2ff TR17:1f 0000000000000000 VR17:1f 0000000000000000 0100 ; 300 TR18:00 0000000080000000 VR18:00 0000000000000000 0100 ; 301 TR18:01 0000000000000000 VR18:01 0000000000000000 0100 ; 302 TR18:02 0000000000000000 VR18:02 0000000000000000 0100 ; 303 TR18:03 0000000000000000 VR18:03 0000000000000000 0100 ; 304 TR18:04 0000000000000000 VR18:04 0000000000000000 0100 ; 305 TR18:05 0000000000000000 VR18:05 0000000000000000 0100 ; 306 TR18:06 0000000000000000 VR18:06 0000000000000000 0100 ; 307 TR18:07 0000000000000000 VR18:07 0000000000000000 0100 ; 308 TR18:08 0000000000000000 VR18:08 0000000000000000 0100 ; 309 TR18:09 0000000000000000 VR18:09 0000000000000000 0100 ; 30a TR18:0a 0000000000000000 VR18:0a 0000000000000000 0100 ; 30b TR18:0b 0000000000000000 VR18:0b 0000000000000000 0100 ; 30c TR18:0c 0000000000000000 VR18:0c 0000000000000000 0100 ; 30d TR18:0d 0000000000000000 VR18:0d 0000000000000000 0100 ; 30e TR18:0e 0000000000000000 VR18:0e 0000000000000000 0100 ; 30f TR18:0f 0000000000000000 VR18:0f 0000000000000000 0100 ; 310 TR18:10 0000000000000000 VR18:10 0000000000000000 0100 ; 311 TR18:11 0000000000000000 VR18:11 0000000000000000 0100 ; 312 TR18:12 0000000007ffe700 VR18:12 0000000000000000 0100 ; 313 TR18:13 0000000000000000 VR18:13 0000000000000000 0100 ; 314 TR18:14 0000000000000000 VR18:14 0000000000000000 0100 ; 315 TR18:15 0000000000000000 VR18:15 0000000000000000 0100 ; 316 TR18:16 0000000000000000 VR18:16 0000000000000000 0100 ; 317 TR18:17 0000000000000000 VR18:17 0000000000000000 0100 ; 318 TR18:18 0000000000000000 VR18:18 0000000000000000 0100 ; 319 TR18:19 0000000000000000 VR18:19 0000000000000000 0100 ; 31a TR18:1a 0000000000000000 VR18:1a 0000000000000000 0100 ; 31b TR18:1b 0000000000000000 VR18:1b 0000000000000000 0100 ; 31c TR18:1c 0000000000000000 VR18:1c 0000000000000000 0100 ; 31d TR18:1d 0000000000000000 VR18:1d 0000000000000000 0100 ; 31e TR18:1e 0000000000000000 VR18:1e 0000000000000000 0100 ; 31f TR18:1f 0000000000000000 VR18:1f 0000000000000000 0100 ; 320 TR19:00 0000000000000000 VR19:00 0000000000000000 0100 ; 321 TR19:01 0000000000000000 VR19:01 0000000000000000 0100 ; 322 TR19:02 0000000000000000 VR19:02 0000000000000000 0100 ; 323 TR19:03 0000000000000000 VR19:03 0000000000000000 0100 ; 324 TR19:04 0000000000000000 VR19:04 0000000000000000 0100 ; 325 TR19:05 0000000000000000 VR19:05 0000000000000000 0100 ; 326 TR19:06 0000000000000000 VR19:06 0000000000000000 0100 ; 327 TR19:07 0000000000000000 VR19:07 0000000000000000 0100 ; 328 TR19:08 0000000000000000 VR19:08 0000000000000008 0100 ; 329 TR19:09 0000000000000000 VR19:09 0000000000000000 0100 ; 32a TR19:0a 0000000000000000 VR19:0a 0000000000000000 0100 ; 32b TR19:0b 0000000000000000 VR19:0b 0000000000000000 0100 ; 32c TR19:0c 0000000000000000 VR19:0c 0000000000000000 0100 ; 32d TR19:0d 0000000000000000 VR19:0d 0000000000000000 0100 ; 32e TR19:0e 0000000000000000 VR19:0e 0000000000000000 0100 ; 32f TR19:0f 0000000000000000 VR19:0f 0000000000000000 0100 ; 330 TR19:10 0000000000000000 VR19:10 0000000000000000 0100 ; 331 TR19:11 0000000000000000 VR19:11 0000000000000000 0100 ; 332 TR19:12 0000000000000000 VR19:12 0000000000000000 0100 ; 333 TR19:13 0000000000000000 VR19:13 0000000000000000 0100 ; 334 TR19:14 0000000000000000 VR19:14 0000000000000000 0100 ; 335 TR19:15 0000000000000000 VR19:15 0000000000000000 0100 ; 336 TR19:16 0000000000000000 VR19:16 0000000000000000 0100 ; 337 TR19:17 0000000000000000 VR19:17 0000000000000000 0100 ; 338 TR19:18 0000000000000000 VR19:18 0000000000000000 0100 ; 339 TR19:19 0000000000000000 VR19:19 0000000000000000 0100 ; 33a TR19:1a 0000000000000000 VR19:1a 0000000000000000 0100 ; 33b TR19:1b 0000000000000000 VR19:1b 0000000000000000 0100 ; 33c TR19:1c 0000000000000000 VR19:1c 0000000000000000 0100 ; 33d TR19:1d 0000000000000000 VR19:1d 0000000000000000 0100 ; 33e TR19:1e 0000000000000000 VR19:1e 0000000000000000 0100 ; 33f TR19:1f 0000000000000000 VR19:1f 0000000000000000 0100 ; 340 TR1a:00 0000000000000000 VR1a:00 0000000000000000 0100 ; 341 TR1a:01 0000000000000000 VR1a:01 0000000000000000 0100 ; 342 TR1a:02 0000000000000000 VR1a:02 0000000000000000 0100 ; 343 TR1a:03 0000000000000000 VR1a:03 0000000000000000 0100 ; 344 TR1a:04 0000000000000000 VR1a:04 0000000000000000 0100 ; 345 TR1a:05 0000000000000000 VR1a:05 0000000000000000 0100 ; 346 TR1a:06 0000000000000000 VR1a:06 0000000000000000 0100 ; 347 TR1a:07 0000000000000000 VR1a:07 0000000000000000 0100 ; 348 TR1a:08 0000000000000000 VR1a:08 0000000000000000 0100 ; 349 TR1a:09 0000000000000000 VR1a:09 0000000000000000 0100 ; 34a TR1a:0a 0000000000000000 VR1a:0a 0000000000000000 0100 ; 34b TR1a:0b 0000000000000000 VR1a:0b 0000000000000000 0100 ; 34c TR1a:0c 0000000000000000 VR1a:0c 0000000000000000 0100 ; 34d TR1a:0d 0000000000000000 VR1a:0d 0000000000000000 0100 ; 34e TR1a:0e 0000000000000000 VR1a:0e 0000000000000000 0100 ; 34f TR1a:0f 0000000000000000 VR1a:0f 0000000000000000 0100 ; 350 TR1a:10 0000000000000000 VR1a:10 0000000000000000 0100 ; 351 TR1a:11 0000000000000000 VR1a:11 0000000000000000 0100 ; 352 TR1a:12 0000000000000000 VR1a:12 0000000000000000 0100 ; 353 TR1a:13 0000000000000000 VR1a:13 0000000000000000 0100 ; 354 TR1a:14 0000000000000000 VR1a:14 0000000000000000 0100 ; 355 TR1a:15 0000000000000000 VR1a:15 0000000000000000 0100 ; 356 TR1a:16 0000000000000000 VR1a:16 0000000000000000 0100 ; 357 TR1a:17 0000000000000000 VR1a:17 0000000000000000 0100 ; 358 TR1a:18 0000000000000000 VR1a:18 0000000000000000 0100 ; 359 TR1a:19 0000000000000000 VR1a:19 0000000000000000 0100 ; 35a TR1a:1a 0000000000000000 VR1a:1a 0000000000000000 0100 ; 35b TR1a:1b 0000000000000000 VR1a:1b 0000000000000000 0100 ; 35c TR1a:1c 0000000000000000 VR1a:1c 0000000000000000 0100 ; 35d TR1a:1d 0000000000000000 VR1a:1d 0000000000000000 0100 ; 35e TR1a:1e 0000000000000000 VR1a:1e 0000000000000000 0100 ; 35f TR1a:1f 0000000000000000 VR1a:1f 0000000000000000 0100 ; 360 TR1b:00 0000000000000000 VR1b:00 0000000000000000 0100 ; 361 TR1b:01 0000000000000000 VR1b:01 0000000000000000 0100 ; 362 TR1b:02 0000000000000000 VR1b:02 0000000000000000 0100 ; 363 TR1b:03 0000000000000000 VR1b:03 0000000000000000 0100 ; 364 TR1b:04 000000000000005d VR1b:04 000000000000005d 0100 ; 365 TR1b:05 0000000000000000 VR1b:05 0000000000000000 0100 ; 366 TR1b:06 0000000000000000 VR1b:06 0000000000000000 0100 ; 367 TR1b:07 0000000000000000 VR1b:07 0000000000000000 0100 ; 368 TR1b:08 0000000000000000 VR1b:08 0000000000000000 0100 ; 369 TR1b:09 0000000000000000 VR1b:09 0000000000000000 0100 ; 36a TR1b:0a 0000000000000000 VR1b:0a 0000000000000000 0100 ; 36b TR1b:0b 0000000000000000 VR1b:0b 0000000000000080 0100 ; 36c TR1b:0c 0000000000000000 VR1b:0c 0000000000000100 0100 ; 36d TR1b:0d 0000000000000080 VR1b:0d 000000000000001f 0100 ; 36e TR1b:0e ffff000040000000 VR1b:0e 0000000000000000 0100 ; 36f TR1b:0f 0000000000007f80 VR1b:0f ffffffffffff0000 0100 ; 370 TR1b:10 000000000000007f VR1b:10 0000000000000001 0100 ; 371 TR1b:11 000000008000003f VR1b:11 fffff00000000000 0100 ; 372 TR1b:12 000000000000003f VR1b:12 0000000000000000 0100 ; 373 TR1b:13 fffe000000000601 VR1b:13 0000000000000001 0100 ; 374 TR1b:14 fffe000040000601 VR1b:14 0000000000000000 0100 ; 375 TR1b:15 000000000000003f VR1b:15 0000000000000001 0100 ; 376 TR1b:16 0000000000000021 VR1b:16 0000000000000000 0100 ; 377 TR1b:17 0000000000000029 VR1b:17 0000000000000000 0100 ; 378 TR1b:18 0000000000000011 VR1b:18 0000000000000000 0100 ; 379 TR1b:19 0000000000000019 VR1b:19 0000000000000000 0100 ; 37a TR1b:1a 0000000000001fc1 VR1b:1a ffff000000000000 0100 ; 37b TR1b:1b 000000000000003f VR1b:1b 0000000000000000 0100 ; 37c TR1b:1c 0000000000000049 VR1b:1c 0000000000000000 0100 ; 37d TR1b:1d 0000000000000076 VR1b:1d 0000000000000000 0100 ; 37e TR1b:1e 0000000000000009 VR1b:1e 0000000000000000 0100 ; 37f TR1b:1f 0000000000000000 VR1b:1f 0000000000000000 0100 ; 380 TR1c:00 0000000080000000 VR1c:00 0000000000000000 0100 ; 381 TR1c:01 0000000000000000 VR1c:01 0000000000000000 0100 ; 382 TR1c:02 0000000000000000 VR1c:02 0000000000000000 0100 ; 383 TR1c:03 0000000000000000 VR1c:03 0000000000000000 0100 ; 384 TR1c:04 0000000000000000 VR1c:04 0000000000000000 0100 ; 385 TR1c:05 0000000000000000 VR1c:05 0000000000000000 0100 ; 386 TR1c:06 0000000000000000 VR1c:06 0000000000000000 0100 ; 387 TR1c:07 0000000000000000 VR1c:07 0000000000000000 0100 ; 388 TR1c:08 0000000000000000 VR1c:08 0000000000000000 0100 ; 389 TR1c:09 0000000000000000 VR1c:09 0000000000000000 0100 ; 38a TR1c:0a 0000000000000000 VR1c:0a 0000000000000000 0100 ; 38b TR1c:0b 0000000000000000 VR1c:0b 0000000000000000 0100 ; 38c TR1c:0c 0000000000000000 VR1c:0c 0000000000000000 0100 ; 38d TR1c:0d 0000000000000000 VR1c:0d 0000000000000000 0100 ; 38e TR1c:0e 0000000000000000 VR1c:0e 0000000000000000 0100 ; 38f TR1c:0f 0000000000000000 VR1c:0f 0000000000000000 0100 ; 390 TR1c:10 0000000000000000 VR1c:10 0000000000000000 0100 ; 391 TR1c:11 0000000000000000 VR1c:11 0000000000000000 0100 ; 392 TR1c:12 0000000000000000 VR1c:12 0000000000000000 0100 ; 393 TR1c:13 0000000000000000 VR1c:13 0000000000000000 0100 ; 394 TR1c:14 0000000000000000 VR1c:14 0000000000000000 0100 ; 395 TR1c:15 0000000000000000 VR1c:15 0000000000000000 0100 ; 396 TR1c:16 0000000000000000 VR1c:16 0000000000000000 0100 ; 397 TR1c:17 0000000000000000 VR1c:17 0000000000000000 0100 ; 398 TR1c:18 0000000000000000 VR1c:18 0000000000000000 0100 ; 399 TR1c:19 0000000000000000 VR1c:19 0000000000000000 0100 ; 39a TR1c:1a 0000000000000000 VR1c:1a 0000000000000000 0100 ; 39b TR1c:1b 0000000000000000 VR1c:1b 0000000000000000 0100 ; 39c TR1c:1c 0000000000000000 VR1c:1c 0000000000000000 0100 ; 39d TR1c:1d 0000000000000000 VR1c:1d 0000000000000000 0100 ; 39e TR1c:1e 0000000000000000 VR1c:1e 0000000000000000 0100 ; 39f TR1c:1f 0000000000000000 VR1c:1f 0000000000000000 0100 ; 3a0 TR1d:00 0000000000000001 VR1d:00 0000000000000000 0100 ; 3a1 TR1d:01 ffffffffffffffff VR1d:01 0000000000000000 0100 ; 3a2 TR1d:02 0000000000000000 VR1d:02 0000000000000000 0100 ; 3a3 TR1d:03 0000000000000000 VR1d:03 0000000000000000 0100 ; 3a4 TR1d:04 0000000000000000 VR1d:04 0000040000000000 0100 ; 3a5 TR1d:05 0000000000000000 VR1d:05 0000000000000000 0100 ; 3a6 TR1d:06 0000000000000000 VR1d:06 0000000000000000 0100 ; 3a7 TR1d:07 0000000000000000 VR1d:07 0000000000000000 0100 ; 3a8 TR1d:08 0000000000000000 VR1d:08 0000000000000000 0100 ; 3a9 TR1d:09 0000000000000000 VR1d:09 0000000000000000 0100 ; 3aa TR1d:0a 0000000000000000 VR1d:0a 0000000000000000 0100 ; 3ab TR1d:0b 0000000000000000 VR1d:0b 0000000000000000 0100 ; 3ac TR1d:0c 0000000000000000 VR1d:0c 000ffff00000bf80 0100 ; 3ad TR1d:0d 0000000000000068 VR1d:0d 0000000000000000 0100 ; 3ae TR1d:0e 0000000000000000 VR1d:0e 0000000000000000 0100 ; 3af TR1d:0f 0000000000000000 VR1d:0f 0000000000000000 0100 ; 3b0 TR1d:10 0000000000000000 VR1d:10 0000000000000000 0100 ; 3b1 TR1d:11 00000000000001f4 VR1d:11 0000000000000000 0100 ; 3b2 TR1d:12 0000000000000000 VR1d:12 fffffffffffffff0 0100 ; 3b3 TR1d:13 0000000000000000 VR1d:13 0000000000000000 0100 ; 3b4 TR1d:14 0000000000000000 VR1d:14 0000000000000000 0100 ; 3b5 TR1d:15 0000000000000000 VR1d:15 0000000000000000 0100 ; 3b6 TR1d:16 0000000000000000 VR1d:16 0000000000000000 0100 ; 3b7 TR1d:17 0000000000000000 VR1d:17 0000000000000000 0100 ; 3b8 TR1d:18 0000000000000000 VR1d:18 0000000000000000 0100 ; 3b9 TR1d:19 0000000000000000 VR1d:19 0000000000000000 0100 ; 3ba TR1d:1a 0000000000000000 VR1d:1a 0000000000000000 0100 ; 3bb TR1d:1b 0000000000000000 VR1d:1b 0000000000000000 0100 ; 3bc TR1d:1c 0000000000000000 VR1d:1c 0000000000000000 0100 ; 3bd TR1d:1d 0000000000000000 VR1d:1d 0000000000000000 0100 ; 3be TR1d:1e 0000000000000000 VR1d:1e 0000000000000000 0100 ; 3bf TR1d:1f 0000000000000000 VR1d:1f 0000000000000000 0100 ; 3c0 TR1e:00 0000000020000000 VR1e:00 0000000000000000 0100 ; 3c1 TR1e:01 0000000000000000 VR1e:01 0000000000000000 0100 ; 3c2 TR1e:02 0000000000000000 VR1e:02 0000000000000000 0100 ; 3c3 TR1e:03 0000000000000000 VR1e:03 0000000000000000 0100 ; 3c4 TR1e:04 0000000000000000 VR1e:04 0000000000000000 0100 ; 3c5 TR1e:05 0000000000000000 VR1e:05 0000000000000000 0100 ; 3c6 TR1e:06 0000000000000000 VR1e:06 0000000000000000 0100 ; 3c7 TR1e:07 0000000000000000 VR1e:07 0000000000000000 0100 ; 3c8 TR1e:08 0000000000000000 VR1e:08 0000000000000000 0100 ; 3c9 TR1e:09 0000000000000000 VR1e:09 0000000000000000 0100 ; 3ca TR1e:0a 0000000000000000 VR1e:0a 0000000000000000 0100 ; 3cb TR1e:0b 0000000000000000 VR1e:0b 0000000000000000 0100 ; 3cc TR1e:0c 0000000000000000 VR1e:0c 0000000000000000 0100 ; 3cd TR1e:0d 0000000000000000 VR1e:0d 0000000000000000 0100 ; 3ce TR1e:0e 0000000000000000 VR1e:0e 0000000000000000 0100 ; 3cf TR1e:0f 00000000c0000003 VR1e:0f 0000000000000000 0100 ; 3d0 TR1e:10 0000000000000030 VR1e:10 0000000000000000 0100 ; 3d1 TR1e:11 000000008000000d VR1e:11 0000000000000000 0100 ; 3d2 TR1e:12 0000000000000003 VR1e:12 0000000000000000 0100 ; 3d3 TR1e:13 0000000080000005 VR1e:13 0000000000000000 0100 ; 3d4 TR1e:14 00000000c0000002 VR1e:14 0000000000000000 0100 ; 3d5 TR1e:15 00000000c0000001 VR1e:15 0000000000000000 0100 ; 3d6 TR1e:16 00000000c0000000 VR1e:16 0000000000000000 0100 ; 3d7 TR1e:17 0000000000000002 VR1e:17 0000000000000000 0100 ; 3d8 TR1e:18 0000000000000020 VR1e:18 0000000000000000 0100 ; 3d9 TR1e:19 0000000000000010 VR1e:19 0000000000000000 0100 ; 3da TR1e:1a 0000000000000000 VR1e:1a 0000000000000000 0100 ; 3db TR1e:1b 0000000040000002 VR1e:1b 0000000000000000 0100 ; 3dc TR1e:1c 0000000080000009 VR1e:1c 0000000000000002 0100 ; 3dd TR1e:1d 0000000080000001 VR1e:1d 0000000000000001 0100 ; 3de TR1e:1e 0000000007ffff80 VR1e:1e 0000000000000000 0100 ; 3df TR1e:1f ffffffff07ffff80 VR1e:1f ffffffff07ffff80 0100 ; 3e0 TCSA0 00c80000ba716456 VCSA0 00cf0035444a4c00 0100 ; 3e1 TCSA1 0000000000000000 VCSA1 0000000000000000 0100 ; 3e2 TCSA2 0000000000000000 VCSA2 0000000000000000 0100 ; 3e3 TCSA3 0000000000000000 VCSA3 0000000000000000 0100 ; 3e4 TCSA4 0000000000000000 VCSA4 0000000000000000 0100 ; 3e5 TCSA5 0000000000000000 VCSA5 0000000000000000 0100 ; 3e6 TCSA6 0000000000000000 VCSA6 0000000000000000 0100 ; 3e7 TCSA7 0000000000000000 VCSA7 0000000000000000 0100 ; 3e8 TCSA8 0000000000000000 VCSA8 0000000000000000 0100 ; 3e9 TCSA9 0000000000000000 VCSA9 0000000000000000 0100 ; 3ea TCSAa 0000000000000000 VCSAa 0000000000000000 0100 ; 3eb TCSAb 0000000000000000 VCSAb 0000000000000000 0100 ; 3ec TCSAc 0000000000000000 VCSAc 0000000000000000 0100 ; 3ed TCSAd 0000000000000000 VCSAd 0000000000000000 0100 ; 3ee TCSAe 0000000000000000 VCSAe 0000000000000000 0100 ; 3ef TCSAf 0000000000000000 VCSAf 0000000000000000 0100 ; 3f0 TGP0 0000000000000000 VGP0 0000000000000000 0100 ; 3f1 TGP1 0000000000000000 VGP1 0000000000000000 0100 ; 3f2 TGP2 0000000000000000 VGP2 0000000000000000 0100 ; 3f3 TGP3 0000000000000000 VGP3 0000000000000000 0100 ; 3f4 TGP4 0000000000000000 VGP4 0000000000000000 0100 ; 3f5 TGP5 0000000000000000 VGP5 0000000000000000 0100 ; 3f6 TGP6 0000000000000000 VGP6 0000000000000000 0100 ; 3f7 TGP7 0000000000000000 VGP7 0000000000000000 0100 ; 3f8 TGP8 0000000000000000 VGP8 0000000000000000 0100 ; 3f9 TGP9 0000000000000000 VGP9 0000000000000000 0100 ; 3fa TGPa 0000000000000000 VGPa 0000000000000000 0100 ; 3fb TGPb 0000000000000000 VGPb 0000000000000000 0100 ; 3fc TGPc 0000000000000000 VGPc 0000000000000000 0100 ; 3fd TGPd 0000000000000000 VGPd 0000000000000000 0100 ; 3fe TGPe 0000000000000000 VGPe 0000000000000000 0100 ; 3ff TGPf 0000000000000000 VGPf 0000000000000000 0100 ; 0100 ; Defaults not shown: 0100 ; =================== 0100 ; dispatch_csa_free 0 0100 ; dispatch_ibuff_fill 0 0100 ; dispatch_ignore 0 0100 ; dispatch_mem_strt 4 MEMORY NOT STARTED 0100 ; dispatch_uses_tos 0 0100 ; fiu_fill_mode_src 1 0100 ; fiu_len_fill_lit 7f zero-fill 0x3f 0100 ; fiu_len_fill_reg_ctl 3 len=unchanged, fill=unchanged 0100 ; fiu_length_src 1 length_literal 0100 ; fiu_load_mdr 0 load_mdr 0100 ; fiu_load_oreg 0 load_oreg 0100 ; fiu_load_tar 0 load_tar 0100 ; fiu_load_var 0 load_var 0100 ; fiu_mem_start 19 nop_0x19 0100 ; fiu_offs_lit 00 0100 ; fiu_offset_src 1 offset_literal 0100 ; fiu_op_sel 0 extract 0100 ; fiu_oreg_src 1 merge data register 0100 ; fiu_rdata_src 1 mdr 0100 ; fiu_tivi_src 0 tar_var 0100 ; fiu_vmux_sel 2 VI 0100 ; ioc_adrbs 0 fiu 0100 ; ioc_fiubs 3 seq 0100 ; ioc_load_wdr 1 0100 ; ioc_random 0 noop 0100 ; ioc_tvbs 0 typ+val 0100 ; seq_b_timing 2 Late Condition, Hint True (or unconditional branch) 0100 ; seq_br_type 6 Continue 0100 ; seq_branch_adr 0000 0100 ; seq_cond_sel 46 SEQ.previously_latched_cond 0100 ; seq_en_micro 1 0100 ; seq_int_reads 3 TOP OF THE MICRO STACK 0100 ; seq_latch 0 0100 ; seq_lex_adr 0 0100 ; seq_random 00 ? 0100 ; typ_a_adr 00 GP00 0100 ; typ_alu_func 1f ZEROS 0100 ; typ_b_adr 00 GP00 0100 ; typ_c_adr 29 WRITE_DISABLE 0100 ; typ_c_lit 3 0100 ; typ_c_mux_sel 1 WDR 0100 ; typ_c_source 1 MUX 0100 ; typ_csa_cntl 6 NOP 0100 ; typ_frame 0 0100 ; typ_mar_cntl 0 NOP 0100 ; typ_priv_check 7 NOP 0100 ; typ_rand f INC_DEC_128 0100 ; val_a_adr 00 GP00 0100 ; val_alu_func 1f ZEROS 0100 ; val_b_adr 00 GP00 0100 ; val_c_adr 29 WRITE_DISABLE 0100 ; val_c_mux_sel 3 WDR 0100 ; val_c_source 1 MUX 0100 ; val_frame 0 0100 ; val_m_a_src 3 Bits 48…63 0100 ; val_m_b_src 3 Bits 48…63 0100 ; val_rand 0 NO_OP 0100 ; 0100 ; Early macro event: ME_STOP_MACH 0100 ; -------------------------------------------------------------------------------------- 0100 ME_STOP_MACH: 0100 0100 <halt> ; Flow R 0101 0101 seq_en_micro 0 0102 0102 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0103 0103 <halt> ; Flow R 0104 0104 <halt> ; Flow R 0105 0105 <halt> ; Flow R 0106 0106 <halt> ; Flow R 0107 0107 <halt> ; Flow R 0108 ; -------------------------------------------------------------------------------------- 0108 ; Early macro event: ME_GP_TIME 0108 ; -------------------------------------------------------------------------------------- 0108 ME_GP_TIME: 0108 0108 seq_br_type 7 Unconditional Call; Flow C 0x5db seq_branch_adr 05db 0x05db seq_en_micro 0 0109 0109 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 010a 010a <halt> ; Flow R 010b 010b <halt> ; Flow R 010c 010c <halt> ; Flow R 010d 010d <halt> ; Flow R 010e 010e <halt> ; Flow R 010f 010f <halt> ; Flow R 0110 ; -------------------------------------------------------------------------------------- 0110 ; Early macro event: ME_SL_TIME 0110 ; -------------------------------------------------------------------------------------- 0110 ME_SL_TIME: 0110 0110 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0x763 fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random d disable slice timer ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0763 0x0763 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 0111 0111 fiu_tivi_src 2 tar_fiu; Flow J cc=True 0x765 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0765 0x0765 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2d TR13:0d typ_frame 13 val_a_adr 21 VR02:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0112 0112 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_frame 4 0113 0113 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x760 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_random 6 load slice timer seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0760 0x0760 seq_en_micro 0 typ_b_adr 32 TR07:12 typ_frame 7 val_a_adr 2f VR02:0f val_frame 2 0114 0114 fiu_len_fill_lit 78 zero-fill 0x38 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 0115 0115 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x73a seq_br_type 1 Branch True seq_branch_adr 073a 0x073a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0116 0116 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0117 0117 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x73c fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 073c 0x073c seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_b_adr 0f GP0f val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0118 ; -------------------------------------------------------------------------------------- 0118 ; Early macro event: ME_SPARE1 0118 ; -------------------------------------------------------------------------------------- 0118 ME_SPARE1: 0118 0118 <halt> ; Flow R 0119 0119 <halt> ; Flow R 011a 011a <halt> ; Flow R 011b 011b <halt> ; Flow R 011c 011c <halt> ; Flow R 011d 011d <halt> ; Flow R 011e 011e <halt> ; Flow R 011f 011f <halt> ; Flow R 0120 ; -------------------------------------------------------------------------------------- 0120 ; Early macro event: ME_PACKET 0120 ; -------------------------------------------------------------------------------------- 0120 ME_PACKET: 0120 0120 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_random 5 read response fifo ioc_tvbs 4 ioc+ioc seq_en_micro 0 0121 0121 ioc_fiubs 0 fiu ioc_random 15 clear transfer parity error ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_a_adr 34 VR03:14 val_b_adr 16 CSA/VAL_BUS val_frame 3 val_rand c START_MULTIPLY 0122 0122 ioc_load_wdr 0 ; Flow C cc=False 0x20c ioc_random 13 set cpu running seq_br_type 4 Call False seq_branch_adr 020c 0x020c seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 33 TR03:13 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0b GP0b typ_frame 3 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 35 VR03:15 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 3 0123 0123 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_en_micro 0 val_a_adr 0b GP0b val_m_a_src 2 Bits 32…47 0124 0124 ioc_random 1c read ioc memory and increment address seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 36 VR03:16 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 3 0125 0125 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 0b GP0b 0126 0126 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x819 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_br_type 3 Unconditional Branch seq_branch_adr 0819 0x0819 seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 0127 0127 seq_br_type 3 Unconditional Branch; Flow J 0x8f6 seq_branch_adr 08f6 0x08f6 seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 7 INC_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 0128 ; -------------------------------------------------------------------------------------- 0128 ; Early macro event: ME_STATUS 0128 ; -------------------------------------------------------------------------------------- 0128 ME_STATUS: 0128 0128 <halt> ; Flow R 0129 0129 <halt> ; Flow R 012a 012a <halt> ; Flow R 012b 012b <halt> ; Flow R 012c 012c <halt> ; Flow R 012d 012d <halt> ; Flow R 012e 012e <halt> ; Flow R 012f 012f <halt> ; Flow R 0130 ; -------------------------------------------------------------------------------------- 0130 ; Early macro event: ME_SPARE0 0130 ; -------------------------------------------------------------------------------------- 0130 ME_SPARE0: 0130 0130 <halt> ; Flow R 0131 0131 <halt> ; Flow R 0132 0132 <halt> ; Flow R 0133 0133 <halt> ; Flow R 0134 0134 <halt> ; Flow R 0135 0135 <halt> ; Flow R 0136 0136 <halt> ; Flow R 0137 0137 <halt> ; Flow R 0138 ; -------------------------------------------------------------------------------------- 0138 ; Early macro event: ME_REFRESH 0138 ; -------------------------------------------------------------------------------------- 0138 ME_REFRESH: 0138 0138 fiu_mem_start d start_physical_rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 20 VR1d:00 val_alu_func 0 PASS_A val_c_adr 1e VR1d:01 val_c_source 0 FIU_BUS val_frame 1d 0139 0139 fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x2a95 fiu_tivi_src c mar_0xc seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2a95 0x2a95 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 34 TR0d:14 typ_alu_func 0 PASS_A typ_frame d val_a_adr 34 VR0d:14 val_alu_func 1c DEC_A val_c_adr 0b VR0d:14 val_c_mux_sel 2 ALU val_frame d 013a 013a ioc_tvbs 3 fiu+fiu; Flow C 0xbab seq_br_type 7 Unconditional Call seq_branch_adr 0bab 0x0bab seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0e TR0d:11 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0e VR0d:11 val_c_mux_sel 2 ALU val_frame d 013b 013b fiu_load_tar 1 hold_tar; Flow J cc=True 0x13e fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 013e 0x013e seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_b_adr 31 TR0d:11 typ_frame d val_a_adr 34 VR0d:14 val_alu_func 7 INC_A val_b_adr 31 VR0d:11 val_frame d 013c 013c fiu_len_fill_reg_ctl 2 ; Flow R cc=True fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 013d 0x013d seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_alu_func 13 ONES typ_b_adr 21 TR1d:01 typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR1d:01 val_alu_func 0 PASS_A val_frame 1d 013d 013d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 013e 013e fiu_mem_start d start_physical_rd; Flow J 0x2a96 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a96 0x2a96 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 0 PASS_A val_frame 1d 013f 013f <halt> ; Flow R 0140 ; -------------------------------------------------------------------------------------- 0140 ; Late macro event: ML_IBUF_empty 0140 ; -------------------------------------------------------------------------------------- 0140 ML_IBUF_empty: 0140 0140 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_cond_sel 55 SEQ.E_MACRO_PEND seq_int_reads 0 TYP VAL BUS seq_random 28 Load_ibuff+Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0141 0141 seq_br_type 7 Unconditional Call; Flow C 0x367b seq_branch_adr 367b 0x367b seq_en_micro 0 0142 0142 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0143 0143 seq_en_micro 0 0144 0144 seq_en_micro 0 0145 ; -------------------------------------------------------------------------------------- 0145 ; Micro event: UE_MACHINE_STARTUP 0145 ; -------------------------------------------------------------------------------------- 0145 UE_MACHINE_STARTUP: 0145 0145 seq_br_type 3 Unconditional Branch; Flow J 0x2aed seq_branch_adr 2aed 0x2aed seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 09 TR04:16 typ_c_mux_sel 0 ALU typ_frame 4 val_alu_func 0 PASS_A val_c_adr 09 VR04:16 val_c_mux_sel 2 ALU val_frame 4 0146 0146 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 0147 0147 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 0148 ; -------------------------------------------------------------------------------------- 0148 ; Late macro event: ML_break_class 0148 ; -------------------------------------------------------------------------------------- 0148 ML_break_class: 0148 0148 fiu_load_tar 1 hold_tar; Flow C cc=True 0x2d85 fiu_load_var 1 hold_var fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2d85 0x2d85 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 30 TR00:10 val_a_adr 24 VR07:04 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 0149 0149 ioc_tvbs 5 seq+seq; Flow J cc=True 0x14a ; Flow J cc=#0x0 0x2d97 seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 2d97 0x2d97 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 30 TR00:10 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 32 VR1d:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 1d 014a 014a ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 014b 014b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2d84 seq_br_type 1 Branch True seq_branch_adr 2d84 0x2d84 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3c TR05:1c typ_frame 5 014c 014c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 014d 014d fiu_mem_start 4 continue; Flow J cc=True 0x170 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0170 ML_CSA_Underflow seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 2a TR06:0a typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 29 VR05:09 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 014e 014e fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_a_adr 2a VR12:0a val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 12 014f 014f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2d6c fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d6c 0x2d6c typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 0150 ; -------------------------------------------------------------------------------------- 0150 ; Late macro event: ML_pullup 0150 ; -------------------------------------------------------------------------------------- 0150 ML_pullup: 0150 0150 <halt> ; Flow R 0151 0151 <halt> ; Flow R 0152 0152 <halt> ; Flow R 0153 0153 <halt> ; Flow R 0154 0154 <halt> ; Flow R 0155 0155 <halt> ; Flow R 0156 0156 <halt> ; Flow R 0157 0157 <halt> ; Flow R 0158 ; -------------------------------------------------------------------------------------- 0158 ; Late macro event: ML_TOS_INVLD 0158 ; -------------------------------------------------------------------------------------- 0158 ML_TOS_INVLD: 0158 0158 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0159 0159 <halt> ; Flow R 015a 015a <halt> ; Flow R 015b 015b <halt> ; Flow R 015c 015c <halt> ; Flow R 015d 015d <halt> ; Flow R 015e 015e <halt> ; Flow R 015f 015f <halt> ; Flow R 0160 ; -------------------------------------------------------------------------------------- 0160 ; Late macro event: ML_Resolve Reference 0160 ; -------------------------------------------------------------------------------------- 0160 ML_Resolve Reference: 0160 0160 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x165 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0165 0x0165 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? typ_a_adr 26 TR02:06 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR1d:13 val_frame 1d 0161 0161 fiu_tivi_src c mar_0xc ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 3e ? typ_a_adr 26 TR02:06 typ_b_adr 2f TR02:0f typ_c_adr 10 TR02:0f typ_frame 2 val_a_adr 34 VR1d:14 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0b VR1d:14 val_c_source 0 FIU_BUS val_frame 1d 0162 0162 fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0163 0x0163 seq_cond_sel 4a SEQ.ME_resolve_ref seq_latch 1 seq_random 04 Load_save_offset+? typ_a_adr 26 TR02:06 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 19 TR02:06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR1d:13 val_c_mux_sel 2 ALU val_frame 1d val_rand a PASS_B_HIGH 0163 0163 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? val_a_adr 33 VR1d:13 val_frame 1d 0164 0164 fiu_len_fill_lit 43 zero-fill 0x3; Flow R cc=True ; Flow J cc=False 0x2a8e fiu_mem_start 2 start-rd fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2a8e 0x2a8e seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0165 0165 fiu_len_fill_lit 43 zero-fill 0x3; Flow R cc=True ; Flow J cc=False 0x2a8e fiu_mem_start 2 start-rd fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type c Dispatch True seq_branch_adr 2a8e 0x2a8e seq_cond_sel 4a SEQ.ME_resolve_ref seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0166 0166 <halt> ; Flow R 0167 0167 <halt> ; Flow R 0168 ; -------------------------------------------------------------------------------------- 0168 ; Late macro event: ML_SEQ_STOP 0168 ; -------------------------------------------------------------------------------------- 0168 ML_SEQ_STOP: 0168 0168 <halt> ; Flow R 0169 0169 <halt> ; Flow R 016a 016a <halt> ; Flow R 016b 016b <halt> ; Flow R 016c 016c <halt> ; Flow R 016d 016d <halt> ; Flow R 016e 016e <halt> ; Flow R 016f 016f <halt> ; Flow R 0170 ; -------------------------------------------------------------------------------------- 0170 ; Late macro event: ML_CSA_Underflow 0170 ; -------------------------------------------------------------------------------------- 0170 ML_CSA_Underflow: 0170 0170 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0171 0171 fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 26 TR02:06 typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 5 DEC_A_MINUS_B val_b_adr 25 VR05:05 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 0172 0172 fiu_mem_start 3 start-wr; Flow J cc=True 0x176 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0176 0x0176 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 33 VR1d:13 val_frame 1d val_rand 2 DEC_LOOP_COUNTER 0173 0173 fiu_mem_start 4 continue; Flow J cc=False 0x173 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0173 0x0173 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 14 BOT - 1 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 0174 0174 ioc_load_wdr 0 typ_b_adr 14 BOT - 1 val_b_adr 14 BOT - 1 0175 0175 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0176 0176 fiu_mem_start 4 continue; Flow J 0x173 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 0173 0x0173 seq_lex_adr 2 seq_random 0b ? typ_b_adr 14 BOT - 1 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 0177 0177 <halt> ; Flow R 0178 ; -------------------------------------------------------------------------------------- 0178 ; Late macro event: ML_CSA_overflow 0178 ; -------------------------------------------------------------------------------------- 0178 ML_CSA_overflow: 0178 0178 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 0179 0179 fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 26 TR02:06 typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 3e VR03:1e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 3 017a 017a fiu_mem_start 2 start-rd; Flow J cc=True 0x17e fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 017e 0x017e seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 3e ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 33 VR1d:13 val_frame 1d val_rand 2 DEC_LOOP_COUNTER 017b 017b seq_b_timing 0 Early Condition; Flow J cc=True 0x17d seq_br_type 1 Branch True seq_branch_adr 017d 0x017d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 10 TOP 017c 017c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x17b fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 017b 0x017b typ_alu_func 0 PASS_A typ_c_adr 2b BOT - 1 typ_c_source 0 FIU_BUS typ_csa_cntl 4 DEC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2b BOT - 1 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 017d 017d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2b BOT - 1 typ_c_mux_sel 0 ALU typ_csa_cntl 4 DEC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2b BOT - 1 val_c_mux_sel 2 ALU 017e 017e seq_br_type 3 Unconditional Branch; Flow J 0x17c seq_branch_adr 017c 0x017c seq_lex_adr 2 seq_random 0b ? typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 017f 017f <halt> ; Flow R 0180 ; -------------------------------------------------------------------------------------- 0180 ; Micro event: UE_MEM_EXP 0180 ; -------------------------------------------------------------------------------------- 0180 UE_MEM_EXP: 0180 0180 ioc_tvbs 3 fiu+fiu; Flow J cc=False 0xf1e seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0f1e 0x0f1e seq_cond_sel 6d MAR_MODIFIED seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR0d:02 val_c_mux_sel 2 ALU val_frame d 0181 0181 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 29 TR12:09 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0182 0182 fiu_tivi_src 8 type_var; Flow J 0xf1e ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0f1e 0x0f1e seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0183 0183 <halt> ; Flow R 0184 0184 <halt> ; Flow R 0185 0185 <halt> ; Flow R 0186 0186 <halt> ; Flow R 0187 0187 <halt> ; Flow R 0188 ; -------------------------------------------------------------------------------------- 0188 ; Micro event: UE_ECC 0188 ; -------------------------------------------------------------------------------------- 0188 UE_ECC: 0188 0188 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2ac6 seq_br_type 1 Branch True seq_branch_adr 2ac6 0x2ac6 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 0 PASS_A typ_c_adr 19 TR1d:06 typ_frame 1d val_c_adr 19 VR1d:06 val_frame 1d 0189 0189 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2ae9 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ae9 0x2ae9 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 13 TR1d:0c typ_c_source 0 FIU_BUS typ_frame 1d val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 018a 018a fiu_len_fill_reg_ctl 1 len=literal, fill=literal; Flow J cc=True 0x2abb fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2abb 0x2abb seq_cond_sel 63 CSA_HIT seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1a TR1d:05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1d typ_rand c WRITE_OUTER_FRAME val_a_adr 2a VR1d:0a val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR1d:05 val_c_mux_sel 2 ALU val_frame 1d 018b 018b fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0x2abd fiu_load_oreg 1 hold_oreg fiu_offs_lit 73 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 3 tar_frame ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2abd 0x2abd seq_cond_sel 7a IOC.CHECKBIT_ERROR~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 018c 018c fiu_len_fill_lit 00 sign-fill 0x0; Flow J cc=False 0x2abd fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2abd 0x2abd seq_cond_sel 78 IOC.MULTIBIT_ERROR seq_en_micro 0 typ_c_adr 14 TR1d:0b typ_c_source 0 FIU_BUS typ_frame 1d 018d 018d seq_br_type 7 Unconditional Call; Flow C 0x20e seq_branch_adr 020e 0x020e seq_en_micro 0 018e 018e ioc_tvbs 5 seq+seq seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 3d VR12:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 018f 018f fiu_mem_start c start_if_incmplt; Flow R ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 6c INCOMPLETE_MEMORY_CYCLE seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 7 INC_A typ_b_adr 28 TR1d:08 typ_c_adr 15 TR1d:0a typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl 1 RESTORE_RDR val_b_adr 28 VR1d:08 val_frame 1d 0190 ; -------------------------------------------------------------------------------------- 0190 ; Micro event: UE_BKPT 0190 ; -------------------------------------------------------------------------------------- 0190 UE_BKPT: 0190 0190 <halt> ; Flow R 0191 0191 <halt> ; Flow R 0192 0192 <halt> ; Flow R 0193 0193 <halt> ; Flow R 0194 0194 <halt> ; Flow R 0195 0195 <halt> ; Flow R 0196 0196 <halt> ; Flow R 0197 0197 <halt> ; Flow R 0198 ; -------------------------------------------------------------------------------------- 0198 ; Micro event: UE_CHK_EXIT 0198 ; -------------------------------------------------------------------------------------- 0198 UE_CHK_EXIT: 0198 0198 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_random 6a ? typ_a_adr 36 TR09:16 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0199 0199 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 019a 019a seq_br_type 7 Unconditional Call; Flow C 0x32df seq_branch_adr 32df 0x32df seq_en_micro 0 seq_lex_adr 3 seq_random 6a ? 019b 019b <halt> ; Flow R 019c 019c <halt> ; Flow R 019d 019d <halt> ; Flow R 019e 019e <halt> ; Flow R 019f 019f <halt> ; Flow R 01a0 ; -------------------------------------------------------------------------------------- 01a0 ; Micro event: UE_FIELD_ERROR 01a0 ; -------------------------------------------------------------------------------------- 01a0 UE_FIELD_ERROR: 01a0 01a0 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 01a1 01a1 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 36 TR09:16 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 01a2 01a2 fiu_tivi_src 8 type_var; Flow C 0x32e0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32e0 0x32e0 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 01a3 01a3 <halt> ; Flow R 01a4 01a4 <halt> ; Flow R 01a5 01a5 <halt> ; Flow R 01a6 01a6 <halt> ; Flow R 01a7 01a7 <halt> ; Flow R 01a8 ; -------------------------------------------------------------------------------------- 01a8 ; Micro event: UE_CLASS 01a8 ; -------------------------------------------------------------------------------------- 01a8 UE_CLASS: 01a8 01a8 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 36 TR09:16 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 01a9 01a9 fiu_tivi_src 8 type_var; Flow C 0x32d7 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 32d7 0x32d7 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 01aa 01aa <halt> ; Flow R 01ab 01ab <halt> ; Flow R 01ac 01ac <halt> ; Flow R 01ad 01ad <halt> ; Flow R 01ae 01ae <halt> ; Flow R 01af 01af <halt> ; Flow R 01b0 ; -------------------------------------------------------------------------------------- 01b0 ; Micro event: UE_BIN_EQ 01b0 ; -------------------------------------------------------------------------------------- 01b0 UE_BIN_EQ: 01b0 01b0 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 01b1 01b1 <halt> ; Flow R 01b2 01b2 <halt> ; Flow R 01b3 01b3 <halt> ; Flow R 01b4 01b4 <halt> ; Flow R 01b5 01b5 <halt> ; Flow R 01b6 01b6 <halt> ; Flow R 01b7 01b7 <halt> ; Flow R 01b8 ; -------------------------------------------------------------------------------------- 01b8 ; Micro event: UE_BIN_OP 01b8 ; -------------------------------------------------------------------------------------- 01b8 UE_BIN_OP: 01b8 01b8 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 01b9 01b9 <halt> ; Flow R 01ba 01ba <halt> ; Flow R 01bb 01bb <halt> ; Flow R 01bc 01bc <halt> ; Flow R 01bd 01bd <halt> ; Flow R 01be 01be <halt> ; Flow R 01bf 01bf <halt> ; Flow R 01c0 ; -------------------------------------------------------------------------------------- 01c0 ; Micro event: UE_TOS_OP 01c0 ; -------------------------------------------------------------------------------------- 01c0 UE_TOS_OP: 01c0 01c0 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 01c1 01c1 <halt> ; Flow R 01c2 01c2 <halt> ; Flow R 01c3 01c3 <halt> ; Flow R 01c4 01c4 <halt> ; Flow R 01c5 01c5 <halt> ; Flow R 01c6 01c6 <halt> ; Flow R 01c7 01c7 <halt> ; Flow R 01c8 ; -------------------------------------------------------------------------------------- 01c8 ; Micro event: UE_TOSI_OP 01c8 ; -------------------------------------------------------------------------------------- 01c8 UE_TOSI_OP: 01c8 01c8 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 01c9 01c9 <halt> ; Flow R 01ca 01ca <halt> ; Flow R 01cb 01cb <halt> ; Flow R 01cc 01cc <halt> ; Flow R 01cd 01cd <halt> ; Flow R 01ce 01ce <halt> ; Flow R 01cf 01cf <halt> ; Flow R 01d0 ; -------------------------------------------------------------------------------------- 01d0 ; Micro event: UE_PAGE_X 01d0 ; -------------------------------------------------------------------------------------- 01d0 UE_PAGE_X: 01d0 01d0 fiu_tivi_src c mar_0xc; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 27 VR07:07 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 7 01d1 01d1 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 1 RESTORE_RDR val_b_adr 16 CSA/VAL_BUS 01d2 01d2 fiu_mem_start c start_if_incmplt; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 6e INCOMPLETE_MEMORY_CYCLE_FOR_PAGE_CROSSING seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 01d3 01d3 <halt> ; Flow R 01d4 01d4 <halt> ; Flow R 01d5 01d5 <halt> ; Flow R 01d6 01d6 <halt> ; Flow R 01d7 01d7 <halt> ; Flow R 01d8 ; -------------------------------------------------------------------------------------- 01d8 ; Micro event: UE_CHK_SYS 01d8 ; -------------------------------------------------------------------------------------- 01d8 UE_CHK_SYS: 01d8 01d8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 01d9 01d9 <halt> ; Flow R 01da 01da <halt> ; Flow R 01db 01db <halt> ; Flow R 01dc 01dc <halt> ; Flow R 01dd 01dd <halt> ; Flow R 01de 01de <halt> ; Flow R 01df 01df <halt> ; Flow R 01e0 ; -------------------------------------------------------------------------------------- 01e0 ; Micro event: UE_NEW_PAK 01e0 ; -------------------------------------------------------------------------------------- 01e0 UE_NEW_PAK: 01e0 01e0 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_random 6a ? typ_a_adr 36 TR09:16 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 01e1 01e1 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_b_adr 0f GP0f typ_mar_cntl 4 RESTORE_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 01e2 01e2 seq_br_type 7 Unconditional Call; Flow C 0x32df seq_branch_adr 32df 0x32df seq_en_micro 0 seq_lex_adr 3 seq_random 6a ? 01e3 01e3 <halt> ; Flow R 01e4 01e4 <halt> ; Flow R 01e5 01e5 <halt> ; Flow R 01e6 01e6 <halt> ; Flow R 01e7 01e7 <halt> ; Flow R 01e8 ; -------------------------------------------------------------------------------------- 01e8 ; Micro event: UE_NEW_STS 01e8 ; -------------------------------------------------------------------------------------- 01e8 UE_NEW_STS: 01e8 01e8 <halt> ; Flow R 01e9 01e9 <halt> ; Flow R 01ea 01ea <halt> ; Flow R 01eb 01eb <halt> ; Flow R 01ec 01ec <halt> ; Flow R 01ed 01ed <halt> ; Flow R 01ee 01ee <halt> ; Flow R 01ef 01ef <halt> ; Flow R 01f0 ; -------------------------------------------------------------------------------------- 01f0 ; Micro event: UE_XFER_CP 01f0 ; -------------------------------------------------------------------------------------- 01f0 UE_XFER_CP: 01f0 01f0 <halt> ; Flow R 01f1 01f1 <halt> ; Flow R 01f2 01f2 <halt> ; Flow R 01f3 01f3 <halt> ; Flow R 01f4 01f4 <halt> ; Flow R 01f5 01f5 <halt> ; Flow R 01f6 01f6 <halt> ; Flow R 01f7 01f7 <halt> ; Flow R 01f8 ; -------------------------------------------------------------------------------------- 01f8 ; 0x0020-0x0030 Illegal - 01f8 ; 0x0037-0x0038 Illegal - 01f8 ; 0x003f-0x0040 Illegal - 01f8 ; 0x0047-0x0048 Illegal - 01f8 ; 0x004f-0x0050 Illegal - 01f8 ; 0x0057-0x0058 Illegal - 01f8 ; 0x005f-0x0067 Illegal - 01f8 ; 0x0077-0x007f Illegal - 01f8 ; 0x0083-0x0086 Illegal - 01f8 ; 0x0094 Illegal - 01f8 ; 0x00ae-0x00b2 Illegal - 01f8 ; 0x00c0-0x00c3 Illegal - 01f8 ; 0x00df Illegal - 01f8 ; 0x0102-0x0105 Illegal - 01f8 ; 0x0108 Illegal - 01f8 ; 0x0113 Illegal - 01f8 ; 0x0130-0x0131 Illegal - 01f8 ; 0x0134-0x0135 Illegal - 01f8 ; 0x0138-0x013b Illegal - 01f8 ; 0x0150-0x015a Illegal - 01f8 ; 0x0170-0x0176 Illegal - 01f8 ; 0x0180-0x0188 Illegal - 01f8 ; 0x018c Illegal - 01f8 ; 0x0190-0x019a Illegal - 01f8 ; 0x01a0-0x01a2 Illegal - 01f8 ; 0x01b0-0x01bd Illegal - 01f8 ; 0x01c8-0x01c9 Illegal - 01f8 ; 0x01e0-0x01ea Illegal - 01f8 ; 0x01f0-0x01f2 Illegal - 01f8 ; 0x0200-0x0204 Illegal - 01f8 ; 0x0207 Illegal - 01f8 ; 0x0280-0x0298 Illegal - 01f8 ; 0x02a1 Illegal - 01f8 ; 0x02a3 Illegal - 01f8 ; 0x02a6-0x02a7 Illegal - 01f8 ; 0x02ac-0x02bd Illegal - 01f8 ; 0x02c0-0x02c5 Illegal - 01f8 ; 0x02c8 Illegal - 01f8 ; 0x02ca Illegal - 01f8 ; 0x02cc-0x02cd Illegal - 01f8 ; 0x02d0-0x02fa Illegal - 01f8 ; 0x0300-0x0302 Illegal - 01f8 ; 0x0308-0x0310 Illegal - 01f8 ; 0x0313-0x0314 Illegal - 01f8 ; 0x0317 Illegal - 01f8 ; 0x031a Illegal - 01f8 ; 0x031f Illegal - 01f8 ; 0x0323 Illegal - 01f8 ; 0x0329 Illegal - 01f8 ; 0x032c Illegal - 01f8 ; 0x032f-0x0332 Illegal - 01f8 ; 0x0338-0x033f Illegal - 01f8 ; 0x0344-0x0345 Illegal - 01f8 ; 0x034a Illegal - 01f8 ; 0x034d Illegal - 01f8 ; 0x0352 Illegal - 01f8 ; 0x0357 Illegal - 01f8 ; 0x035a Illegal - 01f8 ; 0x035f-0x0369 Illegal - 01f8 ; 0x0370-0x0373 Illegal - 01f8 ; 0x0375-0x0376 Illegal - 01f8 ; 0x0379 Illegal - 01f8 ; 0x037c Illegal - 01f8 ; 0x037f-0x0383 Illegal - 01f8 ; 0x0388-0x038b Illegal - 01f8 ; 0x0390-0x0394 Illegal - 01f8 ; 0x03aa Illegal - 01f8 ; 0x03af-0x03b4 Illegal - 01f8 ; 0x03c0-0x03c3 Illegal - 01f8 ; 0x03c8-0x03cb Illegal - 01f8 ; 0x03d0 Illegal - 01f8 ; 0x03d7 Illegal - 01f8 ; 0x03e2 Illegal - 01f8 ; 0x03e7 Illegal - 01f8 ; 0x03f4 Illegal - 01f8 ; 0x03ff Illegal - 01f8 ; 0x1e00-0x1fff Illegal - 01f8 ; 0x3100-0x33ff Illegal - 01f8 ; 0x3500-0x35ff Illegal - 01f8 ; 0x3900-0x3bff Illegal - 01f8 ; 0x3d00-0x3dff Illegal - 01f8 ; 0x4000-0x40ff Illegal - 01f8 ; -------------------------------------------------------------------------------------- 01f8 MACRO_Illegal_-: 01f8 01f8 dispatch_brk_class 0 ; Flow C 0x32dd dispatch_csa_valid 0 dispatch_uadr 01f8 seq_br_type 7 Unconditional Call seq_branch_adr 32dd 0x32dd seq_random 05 ? 01f9 01f9 ioc_random 14 clear cpu running; Flow R seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_random 01 Halt+? 01fa 01fa <halt> ; Flow R 01fb 01fb <halt> ; Flow R 01fc 01fc <halt> ; Flow R 01fd 01fd <halt> ; Flow R 01fe 01fe <halt> ; Flow R 01ff 01ff <halt> ; Flow R 0200 0200 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0200 0x0200 seq_en_micro 0 seq_random 01 Halt+? 0201 0201 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0201 0x0201 seq_en_micro 0 seq_random 01 Halt+? 0202 0202 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0202 0x0202 seq_en_micro 0 seq_random 01 Halt+? 0203 0203 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0203 0x0203 seq_en_micro 0 seq_random 01 Halt+? 0204 0204 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0204 0x0204 seq_en_micro 0 seq_random 01 Halt+? 0205 0205 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0205 0x0205 seq_en_micro 0 seq_random 01 Halt+? 0206 0206 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0206 0x0206 seq_en_micro 0 seq_random 01 Halt+? 0207 0207 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0207 0x0207 seq_en_micro 0 seq_random 01 Halt+? 0208 0208 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0208 0x0208 seq_en_micro 0 seq_random 01 Halt+? 0209 0209 ioc_random 14 clear cpu running; Flow R seq_br_type 3 Unconditional Branch seq_branch_adr 0209 0x0209 seq_en_micro 0 seq_random 01 Halt+? 020a ; -------------------------------------------------------------------------------------- 020a ; Comes from: 020a ; 058e C False from color 0x058d 020a ; 0bc7 C False from color 0x0bab 020a ; 0bd3 C from color 0x0bab 020a ; 0bf9 C False from color 0x0bab 020a ; 0c05 C from color 0x0bab 020a ; 22fe C from color 0x0000 020a ; 2af5 C False from color 0x2aef 020a ; 2b05 C False from color 0x2aef 020a ; 2b08 C False from color 0x2aef 020a ; 2b10 C True from color 0x2b0d 020a ; 2b16 C True from color 0x2b0d 020a ; 334b C from color 0x0921 020a ; 334e C from color 0x0921 020a ; 335d C from color 0x0921 020a ; 3367 C False from color 0x0921 020a ; 3369 C False from color 0x0921 020a ; 337e C from color MACRO_Action_Accept_Activation 020a ; 3381 C from color MACRO_Action_Accept_Activation 020a ; 3385 C from color MACRO_Action_Accept_Activation 020a ; 3392 C from color 0x2f17 020a ; 3394 C from color 0x2f17 020a ; 36c4 C False from color 0x05a7 020a ; 36d0 C from color 0x36d0 020a ; 36d1 C from color 0x36d0 020a ; 36d8 C from color 0x05a7 020a ; 36db C False from color 0x05a7 020a ; 36de C False from color 0x05a7 020a ; 36e2 C False from color 0x05a7 020a ; 36e5 C True from color 0x05a7 020a ; 36ed C from color 0x05a7 020a ; 36fb C from color 0x05a7 020a ; -------------------------------------------------------------------------------------- 020a 020a ioc_random 14 clear cpu running; Flow J 0x200 seq_br_type 3 Unconditional Branch seq_branch_adr 0200 0x0200 seq_en_micro 0 020b ; -------------------------------------------------------------------------------------- 020b ; Comes from: 020b ; 081b C False from color ME_PACKET 020b ; 083c C False from color ME_PACKET 020b ; 0854 C False from color 0x0820 020b ; -------------------------------------------------------------------------------------- 020b 020b ioc_random 14 clear cpu running; Flow J 0x201 seq_br_type 3 Unconditional Branch seq_branch_adr 0201 0x0201 seq_en_micro 0 020c ; -------------------------------------------------------------------------------------- 020c ; Comes from: 020c ; 0122 C False from color ME_PACKET 020c ; 081e C from color ME_PACKET 020c ; 0827 C False from color ME_PACKET 020c ; 0847 C True from color 0x0820 020c ; 0848 C True from color 0x0820 020c ; 0849 C True from color 0x0820 020c ; 0872 C True from color 0x0821 020c ; -------------------------------------------------------------------------------------- 020c 020c ioc_random 14 clear cpu running; Flow J 0x202 seq_br_type 3 Unconditional Branch seq_branch_adr 0202 0x0202 seq_en_micro 0 020d ; -------------------------------------------------------------------------------------- 020d ; Comes from: 020d ; 01b0 C from color UE_BIN_EQ 020d ; 01b8 C from color UE_BIN_OP 020d ; 01c0 C from color UE_TOS_OP 020d ; 01c8 C from color UE_TOSI_OP 020d ; 06bc C from color 0x062d 020d ; 06c4 C False from color 0x06c3 020d ; 06c9 C from color 0x06b7 020d ; 06cc C False from color 0x06cb 020d ; 06dc C False from color 0x06dc 020d ; 08be C False from color 0x0127 020d ; 08d2 C True from color 0x0127 020d ; 08e6 C True from color 0x08e6 020d ; 08e7 C True from color 0x08e6 020d ; 08eb C True from color 0x08e6 020d ; 08ee C True from color 0x08e6 020d ; 08f1 C True from color 0x08e6 020d ; 08f4 C True from color 0x08e6 020d ; 098e C from color 0x098e 020d ; 09b0 C from color 0x09b0 020d ; 09c0 C from color 0x09c0 020d ; 0a7e C from color 0x0a7e 020d ; 0a92 C from color 0x0a92 020d ; 0aa6 C from color 0x0a35 020d ; 0d85 C False from color 0x0000 020d ; 0f20 C True from color 0x0000 020d ; 0f24 C True from color 0x0000 020d ; 0f26 C from color 0x0000 020d ; 0f27 C from color 0x0000 020d ; 0f39 C False from color 0x0000 020d ; 194d C from color 0x194d 020d ; 194e C from color 0x194d 020d ; 194f C from color 0x194d 020d ; 1950 C from color 0x194d 020d ; 1954 C from color 0x1954 020d ; 1958 C from color 0x1958 020d ; 195c C from color 0x195c 020d ; 2aa2 C True from color ME_REFRESH 020d ; 2aa4 C True from color ME_REFRESH 020d ; 2aa6 C True from color ME_REFRESH 020d ; 2aa8 C True from color ME_REFRESH 020d ; 2aaa C True from color ME_REFRESH 020d ; 2aad C True from color ME_REFRESH 020d ; 2aec C from color 0x0127 020d ; 34d2 C from color 0x34cd 020d ; 398b C False from color 0x0000 020d ; 3a2d C False from color 0x3a2b 020d ; 3a3c C False from color 0x0000 020d ; 3b94 C from color 0x3b8f 020d ; -------------------------------------------------------------------------------------- 020d 020d ioc_random 14 clear cpu running; Flow J 0x203 seq_br_type 3 Unconditional Branch seq_branch_adr 0203 0x0203 seq_en_micro 0 020e ; -------------------------------------------------------------------------------------- 020e ; Comes from: 020e ; 018d C from color 0x0127 020e ; -------------------------------------------------------------------------------------- 020e 020e ioc_random 14 clear cpu running; Flow J 0x204 seq_br_type 3 Unconditional Branch seq_branch_adr 0204 0x0204 seq_en_micro 0 020f 020f ioc_random 14 clear cpu running; Flow J 0x205 seq_br_type 3 Unconditional Branch seq_branch_adr 0205 0x0205 seq_en_micro 0 0210 ; -------------------------------------------------------------------------------------- 0210 ; Comes from: 0210 ; 0116 C from color 0x0000 0210 ; 01d0 C from color UE_PAGE_X 0210 ; 01d8 C from color UE_CHK_SYS 0210 ; 026a C from color 0x026a 0210 ; 0299 C from color 0x0299 0210 ; 029d C from color 0x0000 0210 ; 02b6 C from color 0x0000 0210 ; 02d5 C from color 0x02ca 0210 ; 02ea C from color 0x0000 0210 ; 0311 C from color 0x0000 0210 ; 0315 C from color 0x0000 0210 ; 0316 C from color 0x0000 0210 ; 0326 C from color MACRO_Action_Set_Priority 0210 ; 0329 C from color 0x0329 0210 ; 032a C from color 0x032a 0210 ; 032b C from color 0x032b 0210 ; 032e C from color 0x032c 0210 ; 0330 C from color 0x032f 0210 ; 0337 C from color 0x0335 0210 ; 0339 C from color 0x0338 0210 ; 033b C from color 0x033a 0210 ; 033c C from color 0x033c 0210 ; 033d C from color 0x033d 0210 ; 0382 C from color 0x0380 0210 ; 0385 C from color 0x0383 0210 ; 0393 C from color 0x0000 0210 ; 039a C from color 0x0398 0210 ; 03ac C from color 0x0398 0210 ; 03ad C from color 0x03ad 0210 ; 03b0 C from color 0x03ae 0210 ; 03be C from color 0x0000 0210 ; 03d3 C from color 0x03d1 0210 ; 03ef C from color 0x0000 0210 ; 03f8 C from color 0x03f8 0210 ; 0420 C from color 0x0000 0210 ; 0424 C from color 0x0421 0210 ; 042a C from color 0x0000 0210 ; 0447 C from color 0x0000 0210 ; 0468 C from color 0x0000 0210 ; 047f C from color 0x0000 0210 ; 0499 C from color 0x0496 0210 ; 049e C from color 0x0000 0210 ; 04af C from color 0x04ae 0210 ; 04b2 C from color 0x04b2 0210 ; 04bc C from color 0x04bb 0210 ; 04bd C from color 0x04bd 0210 ; 04be C from color 0x04be 0210 ; 04c2 C from color 0x04c2 0210 ; 04c3 C from color 0x04c3 0210 ; 04c4 C from color 0x04c4 0210 ; 04f5 C from color 0x04f5 0210 ; 04f7 C from color 0x04f7 0210 ; 04f8 C from color 0x04f8 0210 ; 04f9 C from color 0x04f9 0210 ; 0516 C from color 0x0515 0210 ; 0518 C from color 0x0518 0210 ; 0519 C from color 0x0519 0210 ; 0556 C from color 0x0550 0210 ; 0564 C from color 0x0564 0210 ; 0566 C from color 0x0565 0210 ; 0571 C from color 0x056d 0210 ; 0572 C from color 0x0572 0210 ; 0575 C from color 0x0573 0210 ; 0577 C from color 0x0576 0210 ; 057b C from color 0x0573 0210 ; 057e C from color 0x0573 0210 ; 0581 C from color 0x0573 0210 ; 0583 C from color 0x0582 0210 ; 0585 C from color 0x0584 0210 ; 0587 C from color 0x0586 0210 ; 058c C from color 0x0573 0210 ; 05a9 C from color 0x05a7 0210 ; 05ae C from color 0x05a7 0210 ; 05b2 C from color 0x05b0 0210 ; 05b3 C from color 0x05b3 0210 ; 05b4 C from color 0x05b4 0210 ; 05c6 C from color 0x05a7 0210 ; 05d1 C from color 0x05d0 0210 ; 05d5 C from color 0x05a7 0210 ; 05d7 C from color 0x05d6 0210 ; 05e8 C from color 0x05db 0210 ; 05ea C from color 0x05e9 0210 ; 05eb C from color 0x05eb 0210 ; 05f8 C from color 0x05ec 0210 ; 05f9 C from color 0x05f9 0210 ; 05fa C from color 0x05fa 0210 ; 0605 C from color 0x05fb 0210 ; 060f C from color 0x0000 0210 ; 0616 C from color 0x0000 0210 ; 061a C from color 0x0000 0210 ; 061f C from color 0x0000 0210 ; 0624 C from color 0x05fb 0210 ; 062c C from color 0x062a 0210 ; 062e C from color 0x062e 0210 ; 0644 C from color 0x0000 0210 ; 0663 C from color 0x0000 0210 ; 0667 C from color 0x0664 0210 ; 0668 C from color 0x0668 0210 ; 0669 C from color 0x0669 0210 ; 0682 C from color 0x066a 0210 ; 0683 C from color 0x0683 0210 ; 0685 C from color 0x0684 0210 ; 0694 C from color 0x0693 0210 ; 06b5 C from color 0x0000 0210 ; 06b9 C from color 0x06b7 0210 ; 06be C from color 0x062d 0210 ; 06c2 C from color 0x06b7 0210 ; 06c6 C from color 0x06c3 0210 ; 06ca C from color 0x06b7 0210 ; 06d1 C from color 0x06ce 0210 ; 06da C from color 0x06d8 0210 ; 06db C from color 0x06db 0210 ; 06e3 C from color 0x06ce 0210 ; 06e7 C from color 0x06e6 0210 ; 06fb C from color 0x06d2 0210 ; 06fc C from color 0x06fc 0210 ; 0700 C from color 0x06fd 0210 ; 0716 C from color 0x0000 0210 ; 071b C from color 0x0719 0210 ; 071f C from color 0x071c 0210 ; 073a C from color 0x0000 0210 ; 073c C from color 0x0117 0210 ; 073d C from color 0x073d 0210 ; 0745 C from color 0x0000 0210 ; 0758 C from color 0x0203 0210 ; 0773 C from color 0x0773 0210 ; 079e C from color 0x0799 0210 ; 07a2 C from color 0x0799 0210 ; 07b3 C from color 0x07b1 0210 ; 07b8 C from color 0x07b5 0210 ; 07bf C from color 0x07b9 0210 ; 07c0 C from color 0x07c0 0210 ; 07c2 C from color 0x07c1 0210 ; 07c3 C from color 0x07c3 0210 ; 07d9 C from color 0x07c4 0210 ; 07ee C from color 0x07e8 0210 ; 0806 C from color 0x07ef 0210 ; 0807 C from color 0x0807 0210 ; 0984 C from color 0x0984 0210 ; 0994 C from color 0x0994 0210 ; 09a6 C from color 0x09a6 0210 ; 09b6 C from color 0x09b6 0210 ; 09c8 C from color MACRO_Execute_Any,Address 0210 ; 0a2a C from color 0x0a2a 0210 ; 0a3c C from color 0x0a3c 0210 ; 0a54 C from color 0x0a54 0210 ; 0a55 C from color 0x0a55 0210 ; 0a56 C from color 0x0a56 0210 ; 0a65 C from color 0x0a65 0210 ; 0a66 C from color 0x0a66 0210 ; 0a67 C from color 0x0a67 0210 ; 0a74 C from color 0x0a74 0210 ; 0a88 C from color 0x0a88 0210 ; 0a9c C from color 0x0a9c 0210 ; 0abf C from color 0x0abf 0210 ; 0ac0 C from color 0x0ac0 0210 ; 0ac1 C from color 0x0ac1 0210 ; 0ac5 C from color 0x0ac5 0210 ; 0ac7 C from color 0x0ac7 0210 ; 0dec C from color 0x0de2 0210 ; 0e36 C from color 0x0000 0210 ; 0e3d C from color 0x0000 0210 ; 0e4a C from color 0x0000 0210 ; 0edd C from color 0x0000 0210 ; 0ee8 C from color 0x0000 0210 ; 0eec C from color 0x0000 0210 ; 0f02 C from color 0x0000 0210 ; 0f08 C from color 0x0f07 0210 ; 0f32 C from color 0x0f30 0210 ; 0f35 C from color 0x0f33 0210 ; 0f40 C from color 0x0000 0210 ; 0f47 C from color 0x0f47 0210 ; 0f4b C from color 0x0f29 0210 ; 0f4c C from color 0x0f4c 0210 ; 0f56 C from color 0x0f29 0210 ; 0f5e C from color 0x0f29 0210 ; 0f5f C from color 0x0f5f 0210 ; 0f68 C from color 0x0f29 0210 ; 0f69 C from color 0x0f69 0210 ; 0f6c C from color 0x0f29 0210 ; 0f71 C from color 0x0f29 0210 ; 0f72 C from color 0x0f29 0210 ; 0f8c C from color 0x0f29 0210 ; 0f98 C from color 0x0f95 0210 ; 0f9d C from color 0x0f93 0210 ; 0fad C from color 0x0f29 0210 ; 0fb8 C from color 0x0f29 0210 ; 0fe3 C from color 0x0f29 0210 ; 0fe9 C from color 0x0fe9 0210 ; 0fee C from color 0x0fea 0210 ; 0ff0 C from color 0x0fef 0210 ; 0ffd C from color 0x0ffd 0210 ; 1020 C from color 0x1004 0210 ; 1032 C from color 0x1004 0210 ; 1048 C from color 0x1004 0210 ; 1084 C from color 0x1004 0210 ; 1085 C from color 0x1004 0210 ; 108c C from color 0x108c 0210 ; 108d C from color 0x1086 0210 ; 1099 C from color 0x1095 0210 ; 109b C from color 0x0ff8 0210 ; 10a2 C from color 0x109e 0210 ; 10a5 C from color 0x109e 0210 ; 10a9 C from color 0x109e 0210 ; 10ec C from color 0x10ec 0210 ; 10ed C from color 0x10ed 0210 ; 10ee C from color 0x10ee 0210 ; 10f2 C from color 0x10f2 0210 ; 10f3 C from color 0x10f3 0210 ; 10f4 C from color 0x10f4 0210 ; 1105 C from color 0x1104 0210 ; 1132 C from color 0x1132 0210 ; 1136 C from color 0x1136 0210 ; 113a C from color 0x113a 0210 ; 113e C from color 0x113e 0210 ; 1143 C from color 0x1142 0210 ; 1144 C from color 0x1144 0210 ; 1145 C from color 0x1145 0210 ; 1149 C from color 0x1149 0210 ; 114a C from color 0x114a 0210 ; 114b C from color 0x114b 0210 ; 1178 C from color 0x113f 0210 ; 1227 C from color 0x1222 0210 ; 1228 C from color 0x1228 0210 ; 1229 C from color 0x1229 0210 ; 122d C from color 0x122d 0210 ; 122e C from color 0x122e 0210 ; 122f C from color 0x122f 0210 ; 1285 C from color 0x1280 0210 ; 1286 C from color 0x1286 0210 ; 1287 C from color 0x1287 0210 ; 128b C from color 0x128b 0210 ; 128c C from color 0x128c 0210 ; 128d C from color 0x128d 0210 ; 1659 C from color MACRO_Execute_Variant_Record,Field_Write,Fixed,Indirect,fieldnum 0210 ; 166b C from color MACRO_Execute_Variant_Record,Field_Write,Variant,Indirect,fieldnum 0210 ; 167d C from color MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 0210 ; 168f C from color MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum 0210 ; 17b8 C from color MACRO_Execute_Variant_Record,Structure_Query 0210 ; 17ba C from color 0x17b9 0210 ; 17c1 C from color MACRO_Execute_Variant_Record,Structure_Query 0210 ; 17c5 C from color MACRO_Execute_Variant_Record,Structure_Query 0210 ; 1b51 C from color MACRO_Execute_Access,Deallocate 0210 ; 1cc7 C from color 0x1cc6 0210 ; 1cc8 C from color 0x1cc8 0210 ; 1cd9 C from color 0x1cd9 0210 ; 1cda C from color 0x1cda 0210 ; 1cdb C from color 0x1cdb 0210 ; 1d3f C from color 0x1d3f 0210 ; 1d60 C from color 0x1d5e 0210 ; 1d62 C from color 0x1d61 0210 ; 1d64 C from color 0x1d63 0210 ; 1d65 C from color 0x1d65 0210 ; 1d68 C from color 0x1d68 0210 ; 1d6a C from color 0x1d6a 0210 ; 1d6c C from color 0x1d6c 0210 ; 1d6d C from color 0x1d6d 0210 ; 1d6f C from color 0x1d6e 0210 ; 1d70 C from color 0x1d70 0210 ; 1d71 C from color 0x1d71 0210 ; 1d72 C from color 0x1d72 0210 ; 1d74 C from color 0x1d74 0210 ; 1d76 C from color 0x1d76 0210 ; 1d7d C from color 0x1d7c 0210 ; 1d7e C from color 0x1d7e 0210 ; 1d7f C from color 0x1d7f 0210 ; 1d83 C from color 0x1d83 0210 ; 1d84 C from color 0x1d84 0210 ; 1d85 C from color 0x1d85 0210 ; 1ec2 C from color 0x1ec1 0210 ; 1ec3 C from color 0x1ec3 0210 ; 1ef3 C from color 0x1ef3 0210 ; 1f96 C from color 0x1f96 0210 ; 1f98 C from color 0x1f98 0210 ; 1f99 C from color 0x1f99 0210 ; 1f9a C from color 0x1f9a 0210 ; 2014 C from color MACRO_Complete_Type_Array,By_Constraining 0210 ; 2063 C from color 0x2057 0210 ; 20a3 C from color 0x20a3 0210 ; 20a4 C from color 0x20a4 0210 ; 20a5 C from color 0x20a5 0210 ; 20a9 C from color 0x20a9 0210 ; 20aa C from color 0x20aa 0210 ; 20ab C from color 0x20ab 0210 ; 20dc C from color 0x20dc 0210 ; 20dd C from color 0x20dd 0210 ; 20de C from color 0x20de 0210 ; 20e2 C from color 0x20e2 0210 ; 20e3 C from color 0x20e3 0210 ; 20e4 C from color 0x20e4 0210 ; 21b0 C from color MACRO_Declare_Type_Array,Constrained 0210 ; 220c C from color 0x2035 0210 ; 2223 C from color 0x2223 0210 ; 2225 C from color 0x2225 0210 ; 2226 C from color 0x2226 0210 ; 2227 C from color 0x2227 0210 ; 2342 C from color 0x2342 0210 ; 2376 C from color 0x2374 0210 ; 23c0 C from color 0x23c0 0210 ; 247a C from color 0x243b 0210 ; 24c3 C from color 0x24ba 0210 ; 258d C from color 0x2569 0210 ; 259a C from color 0x259a 0210 ; 259b C from color 0x259b 0210 ; 25c0 C from color 0x25a7 0210 ; 269b C from color MACRO_Declare_Type_Variant_Record,Defined 0210 ; 26b9 C from color 0x26b6 0210 ; 26ba C from color 0x26ba 0210 ; 26bf C from color 0x26bb 0210 ; 26ce C from color MACRO_Declare_Type_Variant_Record,Defined 0210 ; 26f3 C from color 0x26f3 0210 ; 26f4 C from color 0x26f4 0210 ; 26f5 C from color 0x26f5 0210 ; 26f9 C from color 0x26f9 0210 ; 26fa C from color 0x26fa 0210 ; 26fb C from color 0x26fb 0210 ; 2714 C from color 0x2712 0210 ; 2716 C from color 0x2716 0210 ; 2717 C from color 0x2717 0210 ; 2718 C from color 0x2718 0210 ; 2813 C from color 0x0000 0210 ; 295e C from color 0x0000 0210 ; 2a94 C from color ML_Resolve Reference 0210 ; 2ac3 C from color 0x0127 0210 ; 2ac5 C from color 0x0127 0210 ; 2ac6 C from color 0x0127 0210 ; 2acb C from color 0x0127 0210 ; 2b38 C from color 0x2b38 0210 ; 2b39 C from color 0x2b39 0210 ; 2b3a C from color 0x2b3a 0210 ; 2b3b C from color 0x2b3b 0210 ; 2b3c C from color 0x2b3c 0210 ; 2b3f C from color 0x2b3f 0210 ; 2b40 C from color 0x2b40 0210 ; 2b41 C from color 0x2b41 0210 ; 2b4e C from color 0x2b4e 0210 ; 2b4f C from color 0x2b4f 0210 ; 2b50 C from color 0x2b50 0210 ; 2b54 C from color 0x2b54 0210 ; 2b55 C from color 0x2b55 0210 ; 2b56 C from color 0x2b56 0210 ; 2b96 C from color MACRO_Complete_Type_Task,By_Renaming 0210 ; 2ba0 C from color MACRO_Action_Load_Dynamic 0210 ; 2ba3 C from color 0x2ba3 0210 ; 2c58 C from color 0x0000 0210 ; 2c72 C from color 0x2c6d 0210 ; 2c7f C from color 0x2c7f 0210 ; 2c82 C from color 0x2c82 0210 ; 2c8a C from color MACRO_Execute_Immediate_Reference_Lex_1,uimmediate 0210 ; 2cb1 C from color MACRO_Execute_Select,Member_Write,fieldnum 0210 ; 2cb6 C from color 0x2cb6 0210 ; 2cb8 C from color 0x2cb7 0210 ; 2d07 C from color 0x2d07 0210 ; 2d0d C from color 0x2d0b 0210 ; 2d45 C from color 0x2d44 0210 ; 2d74 C from color ML_break_class 0210 ; 2d77 C from color 0x2d75 0210 ; 2d87 C from color 0x2d85 0210 ; 2e20 C from color 0x0000 0210 ; 2e26 C from color 0x2e22 0210 ; 2e59 C from color 0x0000 0210 ; 2ee2 C from color 0x2ee2 0210 ; 2ef8 C from color 0x0000 0210 ; 2f2a C from color 0x2f17 0210 ; 2f45 C from color 0x2ef9 0210 ; 2f5a C from color 0x06b7 0210 ; 2f6e C from color 0x2ef9 0210 ; 2f94 C from color 0x0000 0210 ; 2fb1 C from color 0x2fa5 0210 ; 2fc7 C from color 0x0000 0210 ; 32c8 C from color 0x32c8 0210 ; 32fa C from color 0x0000 0210 ; 3310 C from color 0x0000 0210 ; 33a9 C from color 0x33a5 0210 ; 33ae C from color 0x33a5 0210 ; 33b4 C from color 0x0000 0210 ; 33b9 C from color 0x0000 0210 ; 33bd C from color 0x33a5 0210 ; 33c5 C from color 0x0000 0210 ; 33c6 C from color 0x33c6 0210 ; 33cb C from color 0x33c7 0210 ; 33ce C from color 0x33c7 0210 ; 33d0 C from color 0x33c7 0210 ; 33d3 C from color 0x33c7 0210 ; 33d4 C from color 0x33d4 0210 ; 33ea C from color 0x33c7 0210 ; 33eb C from color 0x33eb 0210 ; 33ec C from color 0x0000 0210 ; 33fb C from color 0x0f36 0210 ; 33fd C from color 0x33fc 0210 ; 3418 C from color 0x3411 0210 ; 3423 C from color 0x3411 0210 ; 3426 C from color 0x3411 0210 ; 3440 C from color 0x22fd 0210 ; 3441 C from color 0x3441 0210 ; 3442 C from color 0x3442 0210 ; 3443 C from color 0x3443 0210 ; 3444 C from color 0x3444 0210 ; 344f C from color 0x0b53 0210 ; 3482 C from color 0x02c9 0210 ; 3484 C from color 0x0ff8 0210 ; 349c C from color 0x0000 0210 ; 349d C from color 0x349d 0210 ; 34a0 C from color 0x0000 0210 ; 34a1 C from color 0x34a1 0210 ; 34a3 C from color 0x34a2 0210 ; 34a4 C from color 0x34a4 0210 ; 34a5 C from color 0x34a5 0210 ; 34ae C from color 0x34ad 0210 ; 34af C from color 0x34af 0210 ; 34b0 C from color 0x34b0 0210 ; 34b1 C from color 0x34b1 0210 ; 34c1 C from color 0x34bf 0210 ; 34c2 C from color 0x34c2 0210 ; 34c7 C from color 0x34c5 0210 ; 34e6 C from color 0x0000 0210 ; 34f6 C from color 0x0000 0210 ; 3501 C from color 0x0f36 0210 ; 3503 C from color 0x3502 0210 ; 3506 C from color 0x3505 0210 ; 350c C from color 0x0000 0210 ; 350d C from color 0x350d 0210 ; 350f C from color 0x350e 0210 ; 351b C from color 0x3511 0210 ; 351e C from color 0x3511 0210 ; 3521 C from color 0x3511 0210 ; 3560 C from color 0x0000 0210 ; 356c C from color 0x0000 0210 ; 3576 C from color 0x0000 0210 ; 3578 C from color 0x0000 0210 ; 3579 C from color 0x3579 0210 ; 3582 C from color 0x0000 0210 ; 3584 C from color 0x0000 0210 ; 3585 C from color 0x3585 0210 ; 35c1 C from color 0x0000 0210 ; 35d0 C from color 0x0000 0210 ; 35d2 C from color 0x35d2 0210 ; 3649 C from color 0x108b 0210 ; 364c C from color 0x364a 0210 ; 366b C from color 0x365e 0210 ; 366c C from color 0x366c 0210 ; 368d C from color 0x3689 0210 ; 368f C from color 0x368e 0210 ; 3693 C from color 0x3690 0210 ; 371d C from color 0x371b 0210 ; 371e C from color 0x371e 0210 ; 3723 C from color 0x0000 0210 ; 372a C from color 0x372a 0210 ; 372b C from color 0x372b 0210 ; 372c C from color 0x372c 0210 ; 3736 C from color 0x3727 0210 ; 3748 C from color 0x0000 0210 ; 374c C from color 0x0000 0210 ; 3750 C from color 0x374d 0210 ; 3753 C from color 0x0000 0210 ; 3756 C from color 0x3756 0210 ; 3757 C from color 0x3757 0210 ; 3758 C from color 0x3758 0210 ; 3759 C from color 0x3759 0210 ; 375a C from color 0x375a 0210 ; 3760 C from color 0x0000 0210 ; 3769 C from color 0x3767 0210 ; 376d C from color 0x376a 0210 ; 3776 C from color 0x3772 0210 ; 3789 C from color 0x3772 0210 ; 3796 C from color 0x3796 0210 ; 3797 C from color 0x3797 0210 ; 3798 C from color 0x3798 0210 ; 379a C from color 0x379a 0210 ; 379e C from color 0x379e 0210 ; 379f C from color 0x3767 0210 ; 37a5 C from color 0x0000 0210 ; 37ad C from color 0x3799 0210 ; 37ae C from color 0x37ae 0210 ; 37b7 C from color 0x3799 0210 ; 37b9 C from color 0x0000 0210 ; 37bf C from color 0x0000 0210 ; 37c4 C from color 0x37c0 0210 ; 37c6 C from color 0x37c5 0210 ; 37cd C from color 0x37c7 0210 ; 37dc C from color 0x0000 0210 ; 37f5 C from color 0x0000 0210 ; 380f C from color MACRO_Execute_Select,Rendezvous 0210 ; 382f C from color 0x3810 0210 ; 3835 C from color 0x3833 0210 ; 383e C from color 0x3832 0210 ; 384d C from color 0x3833 0210 ; 3856 C from color 0x3833 0210 ; 386d C from color 0x0000 0210 ; 38b5 C from color 0x38ae 0210 ; 38ce C from color 0x2aef 0210 ; 38f3 C from color 0x38e7 0210 ; 38f6 C from color 0x38f4 0210 ; 3909 C from color 0x38fc 0210 ; 394e C from color 0x0000 0210 ; 3954 C from color 0x0000 0210 ; 396e C from color 0x03fa 0210 ; 397e C from color 0x0913 0210 ; 3984 C from color 0x0000 0210 ; 398c C from color 0x0000 0210 ; 39a2 C from color 0x03fa 0210 ; 39a3 C from color 0x39a3 0210 ; 39a4 C from color 0x39a4 0210 ; 39a5 C from color 0x39a5 0210 ; 39b4 C from color 0x39a6 0210 ; 39bd C from color 0x39a8 0210 ; 39df C from color 0x0000 0210 ; 39e1 C from color 0x0000 0210 ; 39e5 C from color 0x39e2 0210 ; 39f2 C from color 0x0000 0210 ; 3a1d C from color 0x0000 0210 ; 3a25 C from color 0x0000 0210 ; 3a2a C from color 0x0000 0210 ; 3a2e C from color 0x3a2b 0210 ; 3a38 C from color 0x0000 0210 ; 3a3d C from color 0x0000 0210 ; 3a5b C from color 0x03fa 0210 ; 3a6a C from color 0x3a69 0210 ; 3a78 C from color 0x0000 0210 ; 3a81 C from color 0x0000 0210 ; 3aa3 C from color 0x0000 0210 ; 3ab5 C from color 0x3ab5 0210 ; 3ab6 C from color 0x3ab6 0210 ; 3ab9 C from color 0x3ab9 0210 ; 3aba C from color 0x3aba 0210 ; 3abc C from color 0x3abc 0210 ; 3abd C from color 0x3abd 0210 ; 3abe C from color 0x3abe 0210 ; 3abf C from color 0x3abf 0210 ; 3ac5 C from color 0x3ac5 0210 ; 3ac6 C from color 0x3ac6 0210 ; 3ac7 C from color 0x3ac7 0210 ; 3ae1 C from color 0x0000 0210 ; 3ae5 C from color 0x0000 0210 ; 3af1 C from color 0x0000 0210 ; 3b13 C from color 0x0000 0210 ; 3b1a C from color 0x0000 0210 ; 3b1b C from color 0x03fa 0210 ; 3b7f C from color 0x0000 0210 ; 3b83 C from color 0x3b82 0210 ; 3b88 C from color 0x0200 0210 ; 3b8a C from color 0x3b89 0210 ; 3b8e C from color 0x0f29 0210 ; 3b97 C from color 0x3b97 0210 ; 3baf C from color 0x3bad 0210 ; 3bb1 C from color 0x3b7d 0210 ; 3bb4 C from color 0x3bad 0210 ; 3bbe C from color 0x3bbd 0210 ; 3bc4 C from color 0x3bbf 0210 ; -------------------------------------------------------------------------------------- 0210 0210 ioc_random 14 clear cpu running; Flow J 0x206 seq_br_type 3 Unconditional Branch seq_branch_adr 0206 0x0206 seq_en_micro 0 0211 ; -------------------------------------------------------------------------------------- 0211 ; Comes from: 0211 ; 03ae C True from color 0x03ae 0211 ; 06d6 C True from color 0x06d2 0211 ; 077c C False from color 0x0767 0211 ; 0783 C from color 0x0767 0211 ; 0825 C True from color ME_PACKET 0211 ; 082d C False from color ME_PACKET 0211 ; 082e C True from color ME_PACKET 0211 ; 0831 C from color ME_PACKET 0211 ; 0833 C from color ME_PACKET 0211 ; 0838 C False from color ME_PACKET 0211 ; 084b C False from color 0x0820 0211 ; 0878 C True from color 0x0821 0211 ; 0b56 C True from color 0x0b53 0211 ; 0b72 C False from color 0x0b72 0211 ; 0b76 C False from color 0x0b74 0211 ; 0b7a C False from color 0x0b78 0211 ; 0f03 C False from color 0x0203 0211 ; 0ff3 C from color 0x0fef 0211 ; 10bc C from color 0x0f29 0211 ; 3641 C True from color 0x108b 0211 ; 3648 C True from color 0x108b 0211 ; 364a C True from color 0x364a 0211 ; 3655 C True from color 0x108b 0211 ; 374d C False from color 0x374d 0211 ; 374f C True from color 0x374d 0211 ; 37b4 C True from color 0x3799 0211 ; 37b5 C False from color 0x3799 0211 ; 37b6 C False from color 0x3799 0211 ; 37cc C False from color 0x37c7 0211 ; 3b8d C True from color 0x0f29 0211 ; -------------------------------------------------------------------------------------- 0211 0211 ioc_random 14 clear cpu running; Flow J 0x207 seq_br_type 3 Unconditional Branch seq_branch_adr 0207 0x0207 seq_en_micro 0 0212 ; -------------------------------------------------------------------------------------- 0212 ; Comes from: 0212 ; 0eff C from color 0x0000 0212 ; -------------------------------------------------------------------------------------- 0212 0212 ioc_random 14 clear cpu running; Flow J 0x208 seq_br_type 3 Unconditional Branch seq_branch_adr 0208 0x0208 seq_en_micro 0 0213 ; -------------------------------------------------------------------------------------- 0213 ; Comes from: 0213 ; 0efe C from color 0x0000 0213 ; -------------------------------------------------------------------------------------- 0213 0213 ioc_random 14 clear cpu running; Flow J 0x209 seq_br_type 3 Unconditional Branch seq_branch_adr 0209 0x0209 seq_en_micro 0 0214 ; -------------------------------------------------------------------------------------- 0214 ; 0x00bf Action Accept_Activation 0214 ; -------------------------------------------------------------------------------------- 0214 MACRO_Action_Accept_Activation: 0214 0214 dispatch_brk_class 3 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0214 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 37 GP08 val_c_mux_sel 2 ALU 0215 0215 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32d4 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d4 0x32d4 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0216 0216 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x217 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 0219 0x0219 typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0217 0217 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32d4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d4 0x32d4 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0218 0218 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3949 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3949 0x3949 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0219 0219 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 021a 021a seq_br_type 2 Push (branch address); Flow J 0x21b seq_branch_adr 0228 0x0228 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 021b 021b fiu_mem_start 2 start-rd; Flow J cc=False 0x220 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0220 0x0220 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 021c 021c <default> 021d 021d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 021e 021e ioc_load_wdr 0 typ_b_adr 02 GP02 val_b_adr 01 GP01 021f 021f fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x221 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0221 0x0221 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0220 0220 fiu_load_tar 1 hold_tar; Flow R cc=True fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 0221 0x0221 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 0221 0221 ioc_tvbs 2 fiu+val; Flow C cc=False 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0222 0222 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0223 0223 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 0224 0224 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a9 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0225 0225 ioc_load_wdr 0 typ_b_adr 02 GP02 val_b_adr 01 GP01 val_c_adr 3c GP03 0226 0226 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 23 TR01:03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 0 PASS_A 0227 0227 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 03 GP03 val_b_adr 03 GP03 0228 0228 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0229 0229 <halt> ; Flow R 022a ; -------------------------------------------------------------------------------------- 022a ; 0x00bc Action Signal_Activated 022a ; -------------------------------------------------------------------------------------- 022a MACRO_Action_Signal_Activated: 022a 022a dispatch_brk_class 3 ; Flow C 0x33af dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 022a seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af 022b 022b fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 37 GP08 val_c_mux_sel 2 ALU 022c 022c fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32d4 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d4 0x32d4 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 022d 022d fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 022e 022e ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 022f 022f ioc_tvbs 1 typ+fiu; Flow C cc=True 0x398d seq_br_type 5 Call True seq_branch_adr 398d 0x398d seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0230 0230 seq_br_type 7 Unconditional Call; Flow C 0x32d4 seq_branch_adr 32d4 0x32d4 typ_a_adr 20 TR02:00 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0231 0231 <halt> ; Flow R 0232 ; -------------------------------------------------------------------------------------- 0232 ; 0x00be Action Activate_Tasks 0232 ; -------------------------------------------------------------------------------------- 0232 MACRO_Action_Activate_Tasks: 0232 0232 dispatch_brk_class 3 ; Flow C cc=True 0x26c dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0232 seq_br_type 5 Call True seq_branch_adr 026c 0x026c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 0233 0233 seq_br_type 7 Unconditional Call; Flow C 0x33af seq_branch_adr 33af 0x33af 0234 0234 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2f VR07:0f val_frame 7 0235 0235 ioc_load_wdr 0 ; Flow J cc=False 0x526 ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0526 MACRO_Action_Idle seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0236 0236 fiu_mem_start 2 start-rd; Flow C 0x336f ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 336f 0x336f seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 0237 0237 seq_br_type 7 Unconditional Call; Flow C 0x23a seq_branch_adr 023a 0x023a seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 0238 0238 seq_br_type 2 Push (branch address); Flow J 0x239 seq_branch_adr 0238 0x0238 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 35 TR07:15 typ_frame 7 0239 0239 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x337a fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 337a 0x337a typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 023a 023a fiu_load_var 1 hold_var; Flow C cc=True 0x245 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0245 0x0245 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 023b 023b typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 023c 023c fiu_mem_start 8 start_wr_if_false ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 023d 023d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x397f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 397f 0x397f seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 22 TR05:02 typ_b_adr 03 GP03 typ_frame 5 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 023e 023e ioc_tvbs 2 fiu+val; Flow J cc=True 0x242 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0242 0x0242 typ_a_adr 20 TR02:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 023f 023f seq_br_type 2 Push (branch address); Flow J 0x240 seq_branch_adr 0242 0x0242 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0240 0240 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x33a3 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0241 0241 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 0242 0242 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x244 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0244 0x0244 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 23 TR02:03 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0243 0243 ioc_tvbs 2 fiu+val; Flow C 0x32d4 seq_br_type 7 Unconditional Call seq_branch_adr 32d4 0x32d4 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0244 0244 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 0245 ; -------------------------------------------------------------------------------------- 0245 ; Comes from: 0245 ; 023a C True from color 0x0000 0245 ; 0253 C True from color 0x0000 0245 ; 02d1 C True from color 0x02ca 0245 ; -------------------------------------------------------------------------------------- 0245 0245 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 0246 0246 fiu_mem_start 2 start-rd; Flow R seq_br_type a Unconditional Return 0247 0247 <halt> ; Flow R 0248 ; -------------------------------------------------------------------------------------- 0248 ; 0x00bd Action Activate_Heap_Tasks 0248 ; -------------------------------------------------------------------------------------- 0248 MACRO_Action_Activate_Heap_Tasks: 0248 0248 dispatch_brk_class 3 ; Flow C cc=True 0x26c dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0248 seq_br_type 5 Call True seq_branch_adr 026c 0x026c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0249 0249 seq_br_type 7 Unconditional Call; Flow C 0x33af seq_branch_adr 33af 0x33af 024a 024a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 0 PASS_A typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 38 VR05:18 val_frame 5 024b 024b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x25f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 025f 0x025f seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 024c 024c fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 024d 024d ioc_load_wdr 0 typ_b_adr 2e TR02:0e typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 024e 024e fiu_mem_start 2 start-rd; Flow C 0x3377 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3377 0x3377 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 024f 024f seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x260 seq_br_type f Unconditional Case Call seq_branch_adr 0260 0x0260 seq_en_micro 0 0250 0250 seq_br_type 2 Push (branch address); Flow J 0x251 seq_branch_adr 0250 0x0250 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 35 TR07:15 typ_frame 7 0251 0251 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x337a fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 337a 0x337a seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 0252 0252 fiu_tivi_src c mar_0xc; Flow C cc=False 0x266 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0266 0x0266 seq_random 02 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 0253 0253 fiu_mem_start 2 start-rd; Flow C cc=True 0x245 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0245 0x0245 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0254 0254 ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0255 0255 fiu_mem_start 8 start_wr_if_false ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0256 0256 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x397f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 397f 0x397f seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 22 TR05:02 typ_b_adr 02 GP02 typ_frame 5 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0257 0257 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x258 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 025d 0x025d seq_int_reads 5 RESOLVE RAM typ_a_adr 22 TR02:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3c TR02:1c typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 0258 0258 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu typ_a_adr 20 TR02:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0259 0259 ioc_load_wdr 0 typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 025a 025a seq_b_timing 1 Latch Condition; Flow J cc=True 0x25d seq_br_type 1 Branch True seq_branch_adr 025d 0x025d typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 025b 025b fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x33a3 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 025c 025c seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 025d 025d typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 025e 025e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d4 seq_br_type 5 Call True seq_branch_adr 32d4 0x32d4 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 23 TR02:03 typ_frame 2 025f 025f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0260 0260 seq_br_type 3 Unconditional Branch; Flow J 0x264 seq_branch_adr 0264 0x0264 0261 0261 seq_br_type 3 Unconditional Branch; Flow J 0x252 seq_branch_adr 0252 0x0252 0262 0262 seq_br_type 3 Unconditional Branch; Flow J 0x264 seq_branch_adr 0264 0x0264 0263 0263 seq_br_type 3 Unconditional Branch; Flow J 0x264 seq_branch_adr 0264 0x0264 0264 0264 seq_b_timing 1 Latch Condition; Flow J cc=True 0x252 seq_br_type 1 Branch True seq_branch_adr 0252 0x0252 0265 0265 seq_br_type 7 Unconditional Call; Flow C 0x32d4 seq_branch_adr 32d4 0x32d4 0266 0266 seq_br_type 7 Unconditional Call; Flow C 0x35cc seq_branch_adr 35cc 0x35cc 0267 0267 seq_b_timing 1 Latch Condition; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 0268 0x0268 seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_a_adr 2e TR02:0e typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 0268 0268 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x269 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 026a 0x026a typ_a_adr 20 TR02:00 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 22 VR05:02 val_frame 5 0269 0269 ioc_tvbs 2 fiu+val; Flow J 0x25b seq_br_type 3 Unconditional Branch seq_branch_adr 025b 0x025b typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 026a 026a seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 20 TR02:00 typ_frame 2 026b 026b seq_br_type 3 Unconditional Branch; Flow J 0x268 seq_branch_adr 0268 0x0268 typ_a_adr 2e TR02:0e typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 026c ; -------------------------------------------------------------------------------------- 026c ; Comes from: 026c ; 0232 C True from color 0x0000 026c ; 0248 C True from color 0x0000 026c ; -------------------------------------------------------------------------------------- 026c 026c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x336f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 336f 0x336f seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 026d 026d fiu_load_var 1 hold_var; Flow R cc=True fiu_mem_start 6 start_rd_if_false fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 026e 0x026e typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 22 VR09:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 9 val_rand a PASS_B_HIGH 026e 026e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x274 seq_br_type 5 Call True seq_branch_adr 0274 0x0274 seq_cond_sel 67 REFRESH_MACRO_EVENT 026f 026f fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0270 0270 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x277 fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0277 0x0277 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0271 0271 seq_br_type 2 Push (branch address); Flow J 0x272 seq_branch_adr 026d 0x026d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 35 TR07:15 typ_frame 7 0272 0272 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x337a fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 337a 0x337a typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 0273 0273 seq_br_type a Unconditional Return; Flow R 0274 ; -------------------------------------------------------------------------------------- 0274 ; Comes from: 0274 ; 026e C True from color MACRO_Action_Accept_Activation 0274 ; -------------------------------------------------------------------------------------- 0274 0274 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 0275 0275 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 05 GP05 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0276 0276 seq_br_type a Unconditional Return; Flow R 0277 0277 ioc_fiubs 1 val ; Flow J 0x221 seq_br_type 3 Unconditional Branch seq_branch_adr 0221 0x0221 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 0278 ; -------------------------------------------------------------------------------------- 0278 ; 0x00bb Action Signal_Completion,>R 0278 ; -------------------------------------------------------------------------------------- 0278 MACRO_Action_Signal_Completion,>R: 0278 0278 dispatch_brk_class 3 ; Flow C 0x33af dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0278 seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 0279 0279 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x2ab fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 02ab 0x02ab seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 20 TR02:00 typ_frame 2 027a 027a ioc_tvbs 1 typ+fiu; Flow J cc=True 0x291 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0291 0x0291 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 027b 027b fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x2a1 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 02a1 0x02a1 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 027c 027c fiu_mem_start 2 start-rd; Flow C 0x34ad ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 34ad 0x34ad seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 027d 027d fiu_mem_start 11 start_tag_query; Flow C cc=True 0x34c5 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 5 Call True seq_branch_adr 34c5 0x34c5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR06:0b typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 20 VR02:00 val_frame 2 027e 027e seq_br_type 1 Branch True; Flow J cc=True 0x2b4 seq_branch_adr 02b4 0x02b4 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 027f 027f fiu_mem_start 2 start-rd; Flow J 0x280 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0282 0x0282 seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0280 0280 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0281 0281 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x39d7 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 39d7 0x39d7 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0282 0282 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x2af fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 02af 0x02af seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 22 TR02:02 typ_frame 2 0283 0283 fiu_mem_start 2 start-rd; Flow C 0x339b ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 339b 0x339b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 0284 0284 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x2c0 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 02c0 0x02c0 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 2e TR11:0e typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_frame 11 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0285 0285 fiu_mem_start 2 start-rd; Flow J cc=True 0x29e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 029e 0x029e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 0 PASS_A 0286 0286 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0287 0287 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28f seq_br_type 1 Branch True seq_branch_adr 028f 0x028f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 08 GP08 typ_rand 6 CHECK_CLASS_A_??_B 0288 0288 seq_br_type 7 Unconditional Call; Flow C 0x3a51 seq_branch_adr 3a51 0x3a51 0289 0289 typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 2b TR02:0b typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 028a 028a fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 23 VR05:03 val_frame 5 028b 028b fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x28c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0299 0x0299 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 028c 028c fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x28d fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 028d 028d ioc_tvbs 1 typ+fiu; Flow C 0x33a3 seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 028e 028e ioc_adrbs 2 typ ; Flow J 0x3ba5 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3ba5 0x3ba5 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 028f 028f ioc_adrbs 2 typ ; Flow C 0x3ba5 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3ba5 0x3ba5 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0290 0290 seq_br_type 3 Unconditional Branch; Flow J 0x2b4 seq_branch_adr 02b4 0x02b4 seq_cond_sel 26 TYP.TRUE (early) seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0291 0291 ioc_adrbs 2 typ ; Flow C 0x3ba5 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3ba5 0x3ba5 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0292 0292 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0293 0293 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR05:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0294 0294 ioc_load_wdr 0 ; Flow J cc=True 0x296 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0296 0x0296 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_b_adr 05 GP05 val_frame 8 0295 0295 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 0 PASS_A 0296 0296 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_frame 2 0297 0297 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x371 seq_br_type 1 Branch True seq_branch_adr 0371 0x0371 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0298 0298 seq_br_type 3 Unconditional Branch; Flow J 0x371 seq_branch_adr 0371 0x0371 typ_a_adr 20 TR02:00 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0299 0299 fiu_len_fill_lit 41 zero-fill 0x1; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 22 TR02:02 typ_frame 2 029a 029a fiu_mem_start 2 start-rd; Flow C 0x339b ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 339b 0x339b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 029b 029b ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x289 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0289 0x0289 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 029c 029c seq_br_type 1 Branch True; Flow J cc=True 0x27f seq_branch_adr 027f 0x027f seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 2e TR11:0e typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_frame 11 029d 029d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 029e 029e fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x29f fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 0282 0x0282 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 24 VR05:04 val_frame 5 029f 029f fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2a0 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02a0 02a0 ioc_tvbs 2 fiu+val; Flow J 0x33a3 seq_br_type 3 Unconditional Branch seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02a1 02a1 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_a_adr 20 TR02:00 typ_alu_func 1 A_PLUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 02a2 02a2 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2d VR07:0d val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 7 val_rand a PASS_B_HIGH 02a3 02a3 ioc_load_wdr 0 ; Flow C cc=True 0x2e1 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 02e1 0x02e1 typ_alu_func 1a PASS_B typ_b_adr 2d TR02:0d typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 02a4 02a4 seq_br_type 1 Branch True; Flow J cc=True 0x2b4 seq_branch_adr 02b4 0x02b4 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 02a5 02a5 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 02a6 02a6 ioc_load_wdr 0 typ_b_adr 2e TR07:0e typ_frame 7 val_b_adr 39 VR02:19 val_frame 2 02a7 02a7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2c0 seq_br_type 1 Branch True seq_branch_adr 02c0 0x02c0 typ_c_adr 1b TR02:04 typ_frame 2 02a8 02a8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 02a9 02a9 seq_br_type 2 Push (branch address); Flow J 0x2aa seq_branch_adr 02af 0x02af 02aa 02aa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x39d2 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 39d2 0x39d2 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02ab 02ab seq_br_type 7 Unconditional Call; Flow C 0x2ad seq_branch_adr 02ad 0x02ad typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02ac 02ac seq_br_type 3 Unconditional Branch; Flow J 0x278 seq_branch_adr 0278 MACRO_Action_Signal_Completion,>R 02ad 02ad fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT 02ae 02ae fiu_mem_start 3 start-wr; Flow J 0x3b7e fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b7e 0x3b7e seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 23 TR11:03 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 02af 02af seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2ad seq_br_type 5 Call True seq_branch_adr 02ad 0x02ad seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02b0 02b0 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 2a VR05:0a val_frame 5 02b1 02b1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 02b2 02b2 ioc_load_wdr 0 ; Flow J 0x2b3 ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 02b3 02b3 fiu_mem_start 2 start-rd; Flow J 0x3496 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3496 0x3496 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 02b4 02b4 ioc_adrbs 3 seq seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 02b5 02b5 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 02b6 02b6 ioc_tvbs 5 seq+seq; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 04 GP04 typ_b_adr 16 CSA/VAL_BUS 02b7 02b7 fiu_mem_start 2 start-rd; Flow C 0x339b seq_br_type 7 Unconditional Call seq_branch_adr 339b 0x339b 02b8 02b8 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2bd seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 02bd 0x02bd seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 2b TR02:0b typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 02b9 02b9 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 23 VR05:03 val_frame 5 02ba 02ba fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2bb fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 02b4 0x02b4 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 02bb 02bb fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2bc fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02bc 02bc ioc_tvbs 1 typ+fiu; Flow J 0x33a3 seq_br_type 3 Unconditional Branch seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 02bd 02bd typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 02be 02be seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2a5 seq_br_type 1 Branch True seq_branch_adr 02a5 0x02a5 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02bf 02bf seq_br_type 3 Unconditional Branch; Flow J 0x27f seq_branch_adr 027f 0x027f 02c0 02c0 fiu_mem_start 2 start-rd; Flow C 0x3377 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3377 0x3377 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 02c1 02c1 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x2c7 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 02c7 0x02c7 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02c2 02c2 ioc_fiubs 2 typ ; Flow J 0x2c3 seq_br_type 3 Unconditional Branch seq_branch_adr 02c3 0x02c3 typ_a_adr 02 GP02 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02c3 02c3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2ce fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 02ce 0x02ce seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 02c4 02c4 fiu_load_oreg 1 hold_oreg; Flow C 0x338c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 338c 0x338c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 23 VR02:03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 02c5 02c5 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x2c7 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 02c7 0x02c7 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02c6 02c6 ioc_fiubs 2 typ ; Flow J 0x2c3 seq_br_type 3 Unconditional Branch seq_branch_adr 02c3 0x02c3 typ_a_adr 02 GP02 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02c7 ; -------------------------------------------------------------------------------------- 02c7 ; Comes from: 02c7 ; 02c1 C #0x0 from color 0x0000 02c7 ; 02c5 C #0x0 from color 0x02c2 02c7 ; -------------------------------------------------------------------------------------- 02c7 02c7 seq_br_type 3 Unconditional Branch; Flow J 0x2cb seq_branch_adr 02cb 0x02cb 02c8 02c8 seq_br_type 3 Unconditional Branch; Flow J 0x2cb seq_branch_adr 02cb 0x02cb 02c9 02c9 fiu_mem_start 2 start-rd; Flow J 0x3487 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3487 0x3487 typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 02ca 02ca fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2d1 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 02d1 0x02d1 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 02cb 02cb seq_br_type 2 Push (branch address); Flow J 0x2cc seq_branch_adr 02c3 0x02c3 02cc 02cc fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x2ab4 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 02 GP02 02cd 02cd ioc_fiubs 0 fiu ; Flow J 0x3a10 seq_br_type 3 Unconditional Branch seq_branch_adr 3a10 0x3a10 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02ce 02ce seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 02cf 02cf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2a8 seq_br_type 1 Branch True seq_branch_adr 02a8 0x02a8 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02d0 02d0 seq_br_type 3 Unconditional Branch; Flow J 0x2af seq_branch_adr 02af 0x02af 02d1 02d1 fiu_mem_start 2 start-rd; Flow C cc=True 0x245 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0245 0x0245 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02d2 02d2 ioc_fiubs 2 typ typ_a_adr 02 GP02 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02d3 02d3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02d4 02d4 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 02d5 0x02d5 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 21 VR13:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 02d5 02d5 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 02d6 02d6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2df seq_br_type 1 Branch True seq_branch_adr 02df 0x02df seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 24 VR02:04 val_frame 2 02d7 02d7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_frame 2 02d8 02d8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2da seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 02da 0x02da seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 02d9 02d9 fiu_fill_mode_src 0 ; Flow J 0x2dc fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 02dc 0x02dc typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02da 02da fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 02db 02db fiu_fill_mode_src 0 ; Flow J 0x2dc fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 02dc 0x02dc typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02dc 02dc ioc_fiubs 2 typ ; Flow J 0x2dd seq_br_type 2 Push (branch address) seq_branch_adr 02d6 0x02d6 typ_a_adr 02 GP02 val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 02dd 02dd fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x2ab4 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 23 VR02:03 val_frame 2 02de 02de ioc_fiubs 0 fiu ; Flow J 0x3a10 seq_br_type 3 Unconditional Branch seq_branch_adr 3a10 0x3a10 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 02df 02df seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 02e0 02e0 seq_br_type 3 Unconditional Branch; Flow J 0x2c3 seq_branch_adr 02c3 0x02c3 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 02e1 02e1 ioc_tvbs 2 fiu+val; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 02e2 0x02e2 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 02e2 02e2 fiu_mem_start 2 start-rd; Flow J 0x2e3 ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 0309 0x0309 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 2 val_rand a PASS_B_HIGH 02e3 02e3 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_random 06 Pop_stack+? val_c_adr 3c GP03 val_c_source 0 FIU_BUS 02e4 02e4 seq_br_type 4 Call False; Flow C cc=False 0x305 seq_branch_adr 0305 0x0305 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 02e5 02e5 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x302 fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0302 0x0302 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 1 INC_LOOP_COUNTER val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 02e6 02e6 seq_br_type 0 Branch False; Flow J cc=False 0x304 seq_branch_adr 0304 0x0304 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 02e7 02e7 seq_br_type 4 Call False; Flow C cc=False 0x305 seq_branch_adr 0305 0x0305 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 02e8 02e8 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=False 0x2eb fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 02eb 0x02eb seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 02e9 02e9 ioc_fiubs 0 fiu ; Flow J cc=False 0x300 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0300 0x0300 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x33) Mark_Word_Flag Auxiliary_Mark Activation_Link Accept_Link Activation_State typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 13 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 02ea 02ea seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 02eb 02eb fiu_mem_start 2 start-rd; Flow C 0x34f0 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f0 0x34f0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 02ec 02ec fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x300 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0300 0x0300 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 02ed 02ed <default> 02ee 02ee fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x300 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0300 0x0300 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 02ef 02ef ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2f6 seq_br_type 1 Branch True seq_branch_adr 02f6 0x02f6 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 26 VR05:06 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 02f0 02f0 seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 02f1 02f1 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2f5 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 02f5 0x02f5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 02f2 02f2 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val val_a_adr 25 VR05:05 val_frame 5 02f3 02f3 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 02f4 02f4 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 02f5 02f5 fiu_load_var 1 hold_var; Flow J 0x2eb fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 02eb 0x02eb val_a_adr 05 GP05 02f6 02f6 ioc_fiubs 0 fiu ; Flow J cc=True 0x2fb ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 02fb 0x02fb seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 25 VR05:05 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 02f7 02f7 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 02f8 02f8 ioc_load_wdr 0 typ_b_adr 04 GP04 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 04 GP04 02f9 02f9 fiu_mem_start 3 start-wr; Flow J 0x2fa ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 0300 0x0300 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 38 VR05:18 val_alu_func 0 PASS_A val_frame 5 val_rand a PASS_B_HIGH 02fa 02fa ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x6b4 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 06b4 0x06b4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 2e TR02:0e typ_frame 2 val_b_adr 03 GP03 02fb 02fb fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x300 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0300 0x0300 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 02fc 02fc fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 14 ZEROS 02fd 02fd fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x2f7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 02f7 0x02f7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 02fe 02fe fiu_mem_start 3 start-wr; Flow C 0x332e ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e 02ff 02ff seq_br_type 3 Unconditional Branch; Flow J 0x2f7 seq_branch_adr 02f7 0x02f7 0300 0300 ioc_adrbs 1 val typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0301 0301 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x2e6 fiu_mem_start 2 start-rd fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 02e6 0x02e6 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 0302 0302 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0303 0303 fiu_mem_start 2 start-rd; Flow J 0x2e6 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 02e6 0x02e6 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 01 GP01 val_alu_func 0 PASS_A 0304 0304 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0305 0305 seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0306 0306 seq_br_type 1 Branch True; Flow J cc=True 0x308 seq_branch_adr 0308 0x0308 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0307 0307 seq_br_type 3 Unconditional Branch; Flow J 0x304 seq_branch_adr 0304 0x0304 seq_en_micro 0 seq_random 06 Pop_stack+? 0308 0308 fiu_mem_start 2 start-rd; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0309 0x0309 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 0309 0309 seq_br_type 7 Unconditional Call; Flow C 0x32d5 seq_branch_adr 32d5 0x32d5 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 030a ; -------------------------------------------------------------------------------------- 030a ; 0x00b7 Action Make_Self 030a ; -------------------------------------------------------------------------------------- 030a MACRO_Action_Make_Self: 030a 030a dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 030a fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 030b 030b seq_br_type 3 Unconditional Branch; Flow J 0x314 seq_branch_adr 0314 0x0314 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 030c ; -------------------------------------------------------------------------------------- 030c ; 0x00b6 Action Make_Scope 030c ; -------------------------------------------------------------------------------------- 030c MACRO_Action_Make_Scope: 030c 030c dispatch_brk_class 8 ; Flow J 0x312 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 030c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0312 0x0312 seq_int_reads 5 RESOLVE RAM seq_lex_adr 3 typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 030d 030d <halt> ; Flow R 030e ; -------------------------------------------------------------------------------------- 030e ; 0x00b5 Action Make_Parent 030e ; -------------------------------------------------------------------------------------- 030e MACRO_Action_Make_Parent: 030e 030e dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 030e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2e VR04:0e val_frame 4 030f 030f ioc_tvbs 2 fiu+val typ_a_adr 38 TR1b:18 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1b 0310 0310 fiu_mem_start 2 start-rd; Flow J cc=True 0x312 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0312 0x0312 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 16 CSA/VAL_BUS 0311 0311 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0312 0312 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 5 typ_rand c WRITE_OUTER_FRAME 0313 0313 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 0314 0314 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x316 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0316 0x0316 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_latch 1 typ_a_adr 27 TR12:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 16 CSA/VAL_BUS 0315 0315 fiu_mem_start 2 start-rd; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 28 TR12:08 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0316 0316 fiu_mem_start 2 start-rd; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2a TR02:0a typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0317 0317 <halt> ; Flow R 0318 ; -------------------------------------------------------------------------------------- 0318 ; 0x00b4 Action Name_Partner 0318 ; -------------------------------------------------------------------------------------- 0318 MACRO_Action_Name_Partner: 0318 0318 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0318 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM 0319 0319 ioc_fiubs 0 fiu ; Flow J cc=False 0x320 seq_br_type 0 Branch False seq_branch_adr 0320 0x0320 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 031a 031a fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_frame 7 031b 031b fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 031c 031c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 031d 031d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x321 seq_br_type 1 Branch True seq_branch_adr 0321 0x0321 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B 031e 031e fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x31a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 031a 0x031a seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 031f 031f ioc_tvbs 1 typ+fiu; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0320 0320 fiu_mem_start 2 start-rd; Flow J 0x31d ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 031d 0x031d typ_a_adr 39 TR02:19 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0321 0321 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0322 ; -------------------------------------------------------------------------------------- 0322 ; 0x00b8 Action Set_Priority 0322 ; -------------------------------------------------------------------------------------- 0322 MACRO_Action_Set_Priority: 0322 0322 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0322 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 21 VR06:01 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 6 0323 0323 fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=True 0x327 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0327 0x0327 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 23 TR05:03 typ_frame 5 val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 4 0324 0324 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0325 0325 seq_en_micro 0 0326 0326 fiu_len_fill_lit 42 zero-fill 0x2; Flow C 0x210 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0327 0327 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 03 GP03 val_b_adr 01 GP01 0328 0328 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x329e fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR05:02 val_frame 5 0329 0329 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 78 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_b_adr 16 CSA/VAL_BUS 032a 032a ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 032b 032b seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 032c 032c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 032d 032d fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR02:00 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 2 032e 032e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 032f 032f ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 0330 0330 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0331 0331 seq_br_type 7 Unconditional Call; Flow C 0x33a3 seq_branch_adr 33a3 0x33a3 seq_en_micro 0 0332 0332 ioc_adrbs 3 seq ; Flow C 0x6c0 seq_br_type 7 Unconditional Call seq_branch_adr 06c0 0x06c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0333 0333 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0334 0334 ioc_fiubs 1 val ; Flow C 0x329e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR06:01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 6 0335 0335 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0336 0336 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 0337 0337 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0338 0338 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 0339 0339 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3d VR02:1d val_alu_func 1b A_OR_B val_b_adr 20 VR02:00 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 033a 033a fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_offs_lit 7b fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 01 GP01 033b 033b fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 7b fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 033c 033c ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 033d 033d seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 033e 033e seq_br_type 7 Unconditional Call; Flow C 0x33a3 seq_branch_adr 33a3 0x33a3 seq_en_micro 0 033f 033f ioc_adrbs 3 seq ; Flow C 0x6c0 seq_br_type 7 Unconditional Call seq_branch_adr 06c0 0x06c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0340 0340 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0341 0341 <halt> ; Flow R 0342 ; -------------------------------------------------------------------------------------- 0342 ; 0x00b3 Action Increase_Priority 0342 ; -------------------------------------------------------------------------------------- 0342 MACRO_Action_Increase_Priority: 0342 0342 dispatch_brk_class 4 ; Flow C 0x329c dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0342 seq_br_type 7 Unconditional Call seq_branch_adr 329c 0x329c 0343 0343 <halt> ; Flow R 0344 ; -------------------------------------------------------------------------------------- 0344 ; 0x00b9 Action Get_Priority 0344 ; -------------------------------------------------------------------------------------- 0344 MACRO_Action_Get_Priority: 0344 0344 dispatch_brk_class 8 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0344 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 0345 0345 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0346 0346 fiu_load_tar 1 hold_tar; Flow C 0x32f5 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 32f5 0x32f5 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR05:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0347 0347 ioc_load_wdr 0 ; Flow J cc=True 0x526 ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0526 MACRO_Action_Idle seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_frame 8 0348 0348 fiu_mem_start 3 start-wr; Flow J 0x332e ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 332e 0x332e typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 0349 0349 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 034a 034a fiu_load_tar 1 hold_tar; Flow C 0x32f5 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32f5 0x32f5 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 8 034b 034b ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 2e VR04:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 034c 034c fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 38 VR05:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 034d 034d ioc_fiubs 2 typ ; Flow J cc=True 0x526 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0526 MACRO_Action_Idle seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 3b TR02:1b typ_frame 2 val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_c_adr 37 GP08 val_c_source 0 FIU_BUS val_frame 8 034e 034e fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3a6e ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 3a6e 0x3a6e seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 034f 034f fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0350 0350 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0351 0351 ioc_tvbs 5 seq+seq; Flow J cc=False 0x366 seq_br_type 0 Branch False seq_branch_adr 0366 0x0366 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0352 0352 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x354 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0354 0x0354 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 30 VR11:10 val_frame 11 val_rand 9 PASS_A_HIGH 0353 0353 seq_br_type 1 Branch True; Flow J cc=True 0x359 seq_branch_adr 0359 0x0359 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3d GP02 val_c_adr 3d GP02 0354 0354 seq_b_timing 0 Early Condition; Flow J cc=True 0x367 seq_br_type 1 Branch True seq_branch_adr 0367 0x0367 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 0355 0355 fiu_mem_start 2 start-rd; Flow C 0x34f0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f0 0x34f0 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_rand a PASS_B_HIGH 0356 0356 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0357 0x0357 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0357 0357 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 0358 0358 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x359 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0359 0x0359 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0359 0359 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x365 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0365 0x0365 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 23 TR01:03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 02 GP02 typ_frame 1 val_a_adr 2a VR05:0a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 035a 035a fiu_load_tar 1 hold_tar; Flow C cc=True 0x35d fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 035d 0x035d seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 21 VR06:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 6 035b 035b fiu_mem_start 3 start-wr; Flow J 0x35c ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 069b 0x069b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 035c 035c ioc_load_wdr 0 ; Flow J 0x6b4 seq_br_type 3 Unconditional Branch seq_branch_adr 06b4 0x06b4 typ_b_adr 01 GP01 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 035d 035d fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x363 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0363 0x0363 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 3d VR02:1d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 035e 035e seq_br_type 0 Branch False; Flow J cc=False 0x367 seq_branch_adr 0367 0x0367 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_frame 2 035f 035f seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 seq_en_micro 0 0360 0360 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0361 0361 seq_b_timing 1 Latch Condition; Flow J cc=False 0x352 seq_br_type 0 Branch False seq_branch_adr 0352 0x0352 typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0362 0362 ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0363 0363 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 31 TR12:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0364 0364 ioc_load_wdr 0 ; Flow J 0x365 seq_br_type 3 Unconditional Branch seq_branch_adr 0365 0x0365 typ_b_adr 02 GP02 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 0365 0365 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0366 0366 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x36b fiu_load_tar 1 hold_tar fiu_offs_lit 11 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 036b 0x036b typ_a_adr 20 TR05:00 typ_b_adr 03 GP03 typ_frame 5 0367 0367 seq_br_type 2 Push (branch address); Flow J 0x368 seq_branch_adr 069b 0x069b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 19 0368 0368 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x211 seq_br_type 1 Branch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 2e TR12:0e typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 24 VR04:04 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0369 0369 fiu_mem_start 2 start-rd; Flow J 0x3743 ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3743 0x3743 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 37 GP08 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 036a 036a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 11 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_b_adr 20 TR02:00 typ_frame 2 036b 036b fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 036c 036c seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 036d 036d seq_br_type 7 Unconditional Call; Flow C 0x33af seq_branch_adr 33af 0x33af typ_a_adr 2e TR02:0e typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 036e 036e fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x36f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 11 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A 036f 036f ioc_tvbs 1 typ+fiu; Flow J cc=True 0x372 seq_br_type 1 Branch True seq_branch_adr 0372 0x0372 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 31 TR12:11 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0370 0370 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 0371 0371 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x372 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 1a PASS_B typ_b_adr 2e TR02:0e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0372 0372 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x374 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0374 0x0374 seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR06:01 val_frame 6 0373 0373 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x33a3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 0374 0374 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 val_a_adr 3d VR02:1d val_frame 2 0375 0375 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x33a3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 0376 0376 ioc_tvbs 5 seq+seq; Flow J 0x56b seq_br_type 3 Unconditional Branch seq_branch_adr 056b 0x056b seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 0377 0377 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR02:18 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0378 0378 fiu_mem_start 2 start-rd; Flow C 0x34f0 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f0 0x34f0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0379 0379 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x37e ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 037e 0x037e typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A 037a 037a <default> 037b 037b fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 037c 037c ioc_tvbs 1 typ+fiu; Flow J cc=True 0x37f seq_br_type 1 Branch True seq_branch_adr 037f 0x037f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 21 VR06:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 6 037d 037d ioc_tvbs 1 typ+fiu; Flow J cc=True 0x37f seq_br_type 1 Branch True seq_branch_adr 037f 0x037f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3d VR02:1d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 037e 037e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 037f 037f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x37e fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 037e 0x037e typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 2f TOP val_c_source 0 FIU_BUS 0380 ; -------------------------------------------------------------------------------------- 0380 ; Comes from: 0380 ; 372d C from color 0x0000 0380 ; 372f C from color 0x0000 0380 ; 3731 C from color 0x3727 0380 ; -------------------------------------------------------------------------------------- 0380 0380 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 04 GP04 val_frame 4 val_rand a PASS_B_HIGH 0381 0381 ioc_load_wdr 0 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 0382 0382 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 0383 0383 ioc_fiubs 1 val typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 0384 0384 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1e typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0385 0385 fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0386 0386 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu typ_b_adr 02 GP02 val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 0387 0387 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x393 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0393 0x0393 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0388 0388 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 0389 0389 seq_br_type 3 Unconditional Branch; Flow J 0x38a seq_branch_adr 038a 0x038a typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 038a 038a fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x38e fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 038e 0x038e seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 3d TR06:1d typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 038b 038b seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 038c 038c fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 038d 038d ioc_fiubs 0 fiu seq_en_micro 0 038e 038e fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=#0x0 0x396 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0396 0x0396 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 038f 038f fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x395 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0395 0x0395 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0390 0390 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x38a seq_br_type 1 Branch True seq_branch_adr 038a 0x038a seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0391 0391 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 0392 0392 seq_br_type 3 Unconditional Branch; Flow J 0x38a seq_branch_adr 038a 0x038a typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 0393 0393 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 0394 0394 seq_br_type 3 Unconditional Branch; Flow J 0x38a seq_branch_adr 038a 0x038a typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 0395 0395 seq_br_type 3 Unconditional Branch; Flow J 0x42f seq_branch_adr 042f 0x042f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0396 ; -------------------------------------------------------------------------------------- 0396 ; Comes from: 0396 ; 038e C #0x0 from color 0x0000 0396 ; -------------------------------------------------------------------------------------- 0396 0396 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return typ_b_adr 30 TR07:10 typ_frame 7 val_b_adr 22 VR07:02 val_frame 7 0397 0397 fiu_load_tar 1 hold_tar; Flow J 0x39b fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 039b 0x039b typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_b_adr 30 TR07:10 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 22 VR07:02 val_frame 7 0398 0398 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x39a fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 8 Return True seq_branch_adr 039a 0x039a seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 31 TR07:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 0399 0399 fiu_load_tar 1 hold_tar; Flow J cc=True 0x3a2 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 03a2 0x03a2 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 30 TR07:10 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 039a 039a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 039b 039b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 09 GP09 typ_b_adr 02 GP02 val_b_adr 02 GP02 039c 039c fiu_mem_start 8 start_wr_if_false; Flow R cc=True ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 039d 0x039d seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 09 GP09 typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 039d 039d fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_tivi_src 8 type_var seq_random 06 Pop_stack+? typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 039e 039e <default> 039f 039f fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03a0 03a0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 03a1 03a1 fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_br_type a Unconditional Return 03a2 03a2 seq_b_timing 1 Latch Condition; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 03a3 0x03a3 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 03a3 03a3 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x3ab fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 03ab 0x03ab seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame e typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS 03a4 03a4 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x3aa fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 03aa 0x03aa seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 09 GP09 typ_alu_func 1a PASS_B typ_b_adr 06 GP06 val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 03a5 03a5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_load_wdr 0 seq_random 06 Pop_stack+? typ_a_adr 02 GP02 typ_b_adr 02 GP02 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 02 GP02 03a6 03a6 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 03a7 03a7 <default> 03a8 03a8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03a9 03a9 fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_br_type a Unconditional Return 03aa 03aa fiu_load_var 1 hold_var; Flow R fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return val_b_adr 31 VR06:11 val_frame 6 03ab 03ab ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32e2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32e2 0x32e2 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1e 03ac 03ac seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 03ad ; -------------------------------------------------------------------------------------- 03ad ; Comes from: 03ad ; 375b C from color 0x0000 03ad ; 375d C from color 0x0000 03ad ; -------------------------------------------------------------------------------------- 03ad 03ad fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 03ae 03ae ioc_fiubs 1 val ; Flow C cc=True 0x211 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 03af 03af ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1e typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 03b0 03b0 fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 03b1 03b1 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu typ_b_adr 02 GP02 val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 03b2 03b2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3be fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 03be 0x03be seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 03b3 03b3 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 03b4 03b4 seq_br_type 3 Unconditional Branch; Flow J 0x3b5 seq_branch_adr 03b5 0x03b5 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 03b5 03b5 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x3b9 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 03b9 0x03b9 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 3d TR06:1d typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 03b6 03b6 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 03b7 03b7 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 03b8 03b8 ioc_fiubs 0 fiu seq_en_micro 0 03b9 03b9 fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=#0x0 0x3c0 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 03c0 0x03c0 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 03ba 03ba fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x470 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0470 0x0470 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 03bb 03bb ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x3b5 seq_br_type 1 Branch True seq_branch_adr 03b5 0x03b5 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 03bc 03bc fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 03bd 03bd seq_br_type 3 Unconditional Branch; Flow J 0x3b5 seq_branch_adr 03b5 0x03b5 typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 03be 03be fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 03bf 03bf seq_br_type 3 Unconditional Branch; Flow J 0x3b5 seq_branch_adr 03b5 0x03b5 typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 03c0 ; -------------------------------------------------------------------------------------- 03c0 ; Comes from: 03c0 ; 03b9 C #0x0 from color 0x0000 03c0 ; -------------------------------------------------------------------------------------- 03c0 03c0 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return typ_b_adr 30 TR07:10 typ_frame 7 val_b_adr 22 VR07:02 val_frame 7 03c1 03c1 fiu_load_tar 1 hold_tar; Flow J 0x3c4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 03c4 0x03c4 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_b_adr 30 TR07:10 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 22 VR07:02 val_frame 7 03c2 03c2 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x39a fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 8 Return True seq_branch_adr 039a 0x039a seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 31 TR07:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 03c3 03c3 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x39a fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 8 Return True seq_branch_adr 039a 0x039a seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 31 TR07:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 03c4 03c4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 09 GP09 typ_b_adr 02 GP02 val_b_adr 02 GP02 03c5 03c5 fiu_mem_start 8 start_wr_if_false; Flow R cc=True ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 03c6 0x03c6 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 09 GP09 typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 03c6 03c6 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_tivi_src 8 type_var seq_random 06 Pop_stack+? typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 03c7 03c7 <default> 03c8 03c8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03c9 03c9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 03ca 03ca fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_br_type a Unconditional Return 03cb 03cb fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x42f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 042f 0x042f seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 3a GP05 03cc 03cc seq_b_timing 1 Latch Condition; Flow C cc=True 0x3cf seq_br_type 5 Call True seq_branch_adr 03cf 0x03cf typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 03cd 03cd fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=False 0x3d1 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 03d1 0x03d1 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2c TR05:0c typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 03ce 03ce ioc_fiubs 2 typ ; Flow J 0x3d8 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 03d8 0x03d8 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03cf 03cf ioc_fiubs 2 typ typ_a_adr 32 TR02:12 typ_frame 2 val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03d0 03d0 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x42f seq_branch_adr 042f 0x042f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 05 GP05 val_alu_func 0 PASS_A 03d1 ; -------------------------------------------------------------------------------------- 03d1 ; Comes from: 03d1 ; 03cd C False from color 0x0000 03d1 ; -------------------------------------------------------------------------------------- 03d1 03d1 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 03d2 03d2 ioc_load_wdr 0 typ_b_adr 03 GP03 03d3 03d3 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A 03d4 03d4 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 2c TR05:0c typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 03d5 03d5 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 03d6 03d6 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 03d7 0x03d7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 37 TR02:17 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 03d7 03d7 seq_br_type a Unconditional Return; Flow R typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 03d8 03d8 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 03d9 03d9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 typ_a_adr 2f TR06:0f typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 6 03da 03da fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2f TR05:0f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 03db 03db fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x409 fiu_load_tar 1 hold_tar fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 0409 0x0409 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 03dc 03dc fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x408 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0408 0x0408 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 03dd 03dd ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 03de 03de fiu_load_tar 1 hold_tar; Flow J cc=False 0x3e1 fiu_mem_start 8 start_wr_if_false fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 03e1 0x03e1 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 03df 03df seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 03e0 03e0 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 03e1 03e1 ioc_tvbs 2 fiu+val; Flow J cc=True 0x40c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 040c 0x040c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame f val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 03e2 03e2 fiu_mem_start 6 start_rd_if_false ioc_adrbs 2 typ seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 03e3 03e3 seq_b_timing 0 Early Condition; Flow J cc=False 0x3de seq_br_type 0 Branch False seq_branch_adr 03de 0x03de seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 03e4 03e4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 02 GP02 03e5 03e5 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_csa_cntl 7 FINISH_POP_DOWN 03e6 03e6 seq_br_type 7 Unconditional Call; Flow C 0x33a3 seq_branch_adr 33a3 0x33a3 seq_en_micro 0 val_a_adr 2f VR02:0f val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 03e7 03e7 fiu_mem_start 2 start-rd; Flow C 0x34dc ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34dc 0x34dc typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 03e8 03e8 fiu_mem_start 2 start-rd; Flow C 0x33c4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 33c4 0x33c4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 03e9 03e9 seq_b_timing 1 Latch Condition; Flow J cc=False 0x3ec seq_br_type 0 Branch False seq_branch_adr 03ec 0x03ec seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 03ea 03ea seq_br_type 7 Unconditional Call; Flow C 0x33ec seq_branch_adr 33ec 0x33ec 03eb 03eb seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 03ec 03ec fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 2e Load_save_offset+Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 03ed 03ed fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 2e TOP + 1 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 05 GP05 03ee 03ee fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED seq_random 33 ? typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 03ef 03ef fiu_len_fill_lit 4b zero-fill 0xb; Flow C 0x210 fiu_offs_lit 54 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 6 CONTROL TOP seq_random 3e ? typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03f0 03f0 seq_br_type 7 Unconditional Call; Flow C 0x410 seq_branch_adr 0410 0x0410 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 03f1 03f1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_random 39 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 03f2 03f2 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x3fe fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 0 Branch False seq_branch_adr 03fe 0x03fe seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 20 TR02:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR02:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 val_frame 2 03f3 03f3 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x400 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0400 0x0400 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 05 GP05 03f4 03f4 fiu_load_tar 1 hold_tar; Flow R cc=False fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 03f5 0x03f5 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 03f5 03f5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x40a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 040a 0x040a seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 03f6 03f6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x3f8 seq_br_type f Unconditional Case Call seq_branch_adr 03f8 0x03f8 seq_en_micro 0 03f7 03f7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 03f8 ; -------------------------------------------------------------------------------------- 03f8 ; Comes from: 03f8 ; 03f6 C #0x0 from color 0x03f0 03f8 ; -------------------------------------------------------------------------------------- 03f8 03f8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 03f9 03f9 seq_br_type 3 Unconditional Branch; Flow J 0x3fc seq_branch_adr 03fc 0x03fc seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 03fa 03fa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3a51 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3a51 0x3a51 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03fb 03fb fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3a51 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 3a51 0x3a51 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 03fc 03fc seq_br_type 1 Branch True; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 03fd 03fd seq_br_type 3 Unconditional Branch; Flow J 0x32de seq_branch_adr 32de 0x32de 03fe 03fe fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3ff fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 03f4 0x03f4 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 03ff 03ff ioc_tvbs 2 fiu+val; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0400 0x0400 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2f TR12:0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 12 0400 0400 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0401 0401 ioc_load_wdr 0 ; Flow J 0x405 seq_br_type 3 Unconditional Branch seq_branch_adr 0405 0x0405 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0402 0402 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 0403 0403 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x405 seq_br_type 0 Branch False seq_branch_adr 0405 0x0405 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 0404 0404 fiu_load_tar 1 hold_tar; Flow R cc=False ; Flow J cc=True 0x3f5 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 03f5 0x03f5 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0405 0405 ioc_adrbs 3 seq ; Flow C 0x34cd seq_br_type 7 Unconditional Call seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 0406 0406 ioc_fiubs 2 typ ; Flow J cc=True 0x402 seq_br_type 1 Branch True seq_branch_adr 0402 0x0402 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 38 TR07:18 typ_frame 7 val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0407 0407 seq_br_type 3 Unconditional Branch; Flow J 0x402 seq_branch_adr 0402 0x0402 seq_int_reads 0 TYP VAL BUS seq_random 59 ? val_b_adr 03 GP03 0408 0408 ioc_tvbs 2 fiu+val; Flow J 0x3e4 seq_br_type 3 Unconditional Branch seq_branch_adr 03e4 0x03e4 seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 0409 ; -------------------------------------------------------------------------------------- 0409 ; Comes from: 0409 ; 03db C True from color 0x0000 0409 ; -------------------------------------------------------------------------------------- 0409 0409 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 2f TR11:0f typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 11 040a ; -------------------------------------------------------------------------------------- 040a ; Comes from: 040a ; 03f5 C True from color 0x03f0 040a ; -------------------------------------------------------------------------------------- 040a 040a seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 040b 0x040b seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 040b 040b seq_br_type a Unconditional Return; Flow R typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU 040c 040c fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_load_wdr 0 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand 1 INC_LOOP_COUNTER 040d 040d typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2f TR05:0f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_rand 2 DEC_LOOP_COUNTER 040e 040e fiu_mem_start 8 start_wr_if_false; Flow J cc=False 0x40d ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 040d 0x040d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 040f 040f seq_br_type 3 Unconditional Branch; Flow J 0x3e6 seq_branch_adr 03e6 0x03e6 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 0410 ; -------------------------------------------------------------------------------------- 0410 ; Comes from: 0410 ; 03f0 C from color 0x03f0 0410 ; -------------------------------------------------------------------------------------- 0410 0410 ioc_adrbs 2 typ ; Flow C 0x3ba5 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3ba5 0x3ba5 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0411 0411 seq_br_type a Unconditional Return; Flow R typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0412 0412 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 05 GP05 val_b_adr 08 GP08 0413 0413 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x414 fiu_mem_start 3 start-wr fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0417 0x0417 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 26 TR08:06 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 0414 0414 ioc_load_wdr 0 ; Flow J cc=True 0x416 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0416 0x0416 typ_a_adr 2f TR06:0f typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 6 0415 0415 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True ; Flow J cc=False 0x211 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 8 Return True seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 02 ? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 0416 0416 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True ; Flow J cc=False 0x211 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 8 Return True seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 02 ? typ_a_adr 2f TR11:0f typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 11 val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 0417 0417 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x42c fiu_load_tar 1 hold_tar fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 042c 0x042c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 0418 0418 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 0419 0419 seq_br_type 3 Unconditional Branch; Flow J 0x41b seq_branch_adr 041b 0x041b typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 26 TR09:06 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 34 VR09:14 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 9 041a 041a seq_br_type 0 Branch False; Flow J cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 041b 041b fiu_mem_start 3 start-wr; Flow C cc=True 0x211 ioc_adrbs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 13 LOOP_REG typ_frame f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 13 LOOP_REG 041c 041c ioc_tvbs 2 fiu+val; Flow J cc=True 0x41a seq_br_type 1 Branch True seq_branch_adr 041a 0x041a seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 32 VR09:12 val_frame 9 val_rand 2 DEC_LOOP_COUNTER 041d 041d seq_br_type 0 Branch False; Flow J cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2f TR05:0f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 05 GP05 val_alu_func 1e A_AND_B val_b_adr 21 VR06:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 041e 041e fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 041f 041f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0420 0420 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 38 TR12:18 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0421 0421 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 0422 0422 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 02 GP02 0423 0423 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_a_adr 05 GP05 val_b_adr 08 GP08 0424 0424 fiu_len_fill_lit 4b zero-fill 0xb; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 05 GP05 typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT 0425 0425 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 08 GP08 typ_b_adr 04 GP04 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0426 0426 seq_br_type 2 Push (branch address); Flow J 0x427 seq_branch_adr 042d 0x042d val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0427 0427 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x6b4 seq_br_type 0 Branch False seq_branch_adr 06b4 0x06b4 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 1a PASS_B typ_b_adr 09 GP09 val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0428 0428 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x211 seq_br_type 1 Branch True seq_branch_adr 0211 0x0211 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 0429 0429 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 7 val_rand a PASS_B_HIGH 042a 042a seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 2f TR11:0f typ_frame 11 042b 042b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3a51 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3a51 0x3a51 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 042c 042c ioc_tvbs 2 fiu+val; Flow J 0x41d seq_br_type 3 Unconditional Branch seq_branch_adr 041d 0x041d typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 042d 042d seq_br_type 5 Call True; Flow C cc=True 0x69b seq_branch_adr 069b 0x069b seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 042e 042e seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 042f 042f fiu_mem_start 2 start-rd; Flow C cc=False 0x49e ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 049e 0x049e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 0430 0430 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x46a seq_br_type 1 Branch True seq_branch_adr 046a 0x046a seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 08 GP08 0431 0431 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x432 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 044b 0x044b seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_a_adr 33 TR06:13 typ_alu_func 1e A_AND_B typ_b_adr 08 GP08 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand c WRITE_OUTER_FRAME val_a_adr 2b VR05:0b val_frame 5 0432 0432 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_alu_func 1e A_AND_B typ_b_adr 21 TR07:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 0433 0433 fiu_tivi_src c mar_0xc; Flow J cc=True 0x436 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0436 0x0436 0434 0434 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x49a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 049a 0x049a seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame e val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0435 0435 fiu_mem_start 2 start-rd; Flow J 0x43c ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 043c 0x043c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 0436 0436 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 1 RESTORE_RDR val_b_adr 16 CSA/VAL_BUS 0437 0437 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x49a fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 049a 0x049a seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0438 0438 fiu_len_fill_lit 58 zero-fill 0x18; Flow J cc=True 0x49c fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 049c 0x049c seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS val_a_adr 22 VR06:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0439 0439 fiu_len_fill_lit 66 zero-fill 0x26 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 043a 043a fiu_mem_start 2 start-rd; Flow J cc=False 0x43c ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 043c 0x043c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 043b 043b seq_br_type 3 Unconditional Branch; Flow J 0x49c seq_branch_adr 049c 0x049c seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 043c 043c fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x46e fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 046e 0x046e seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR07:01 typ_frame 7 val_a_adr 20 VR02:00 val_frame 2 043d 043d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame e typ_rand 1 INC_LOOP_COUNTER val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 043e 043e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_a_adr 22 TR07:02 typ_alu_func 1e A_AND_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 6 A_MINUS_B val_b_adr 3d VR06:1d val_frame 6 043f 043f fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x493 fiu_load_tar 1 hold_tar fiu_offs_lit 3d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0493 0x0493 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 val_b_adr 22 VR05:02 val_frame 5 0440 0440 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x22f7 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 22f7 0x22f7 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0441 0441 ioc_fiubs 1 val ; Flow C 0x22f7 seq_br_type 7 Unconditional Call seq_branch_adr 22f7 0x22f7 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 0442 0442 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 0443 0443 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ 0444 0444 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE 0445 0445 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 03 GP03 0446 0446 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0447 0447 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 04 GP04 typ_c_lit 2 typ_frame 12 val_b_adr 04 GP04 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0448 0448 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 1 val seq_random 02 ? typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_rand 2 DEC_LOOP_COUNTER 0449 0449 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 044a 044a seq_br_type 3 Unconditional Branch; Flow J 0x450 seq_branch_adr 0450 0x0450 044b 044b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 044c 044c fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 3d VR06:1d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 val_rand a PASS_B_HIGH 044d 044d fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 01 GP01 044e 044e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_b_adr 04 GP04 044f 044f ioc_tvbs 1 typ+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0450 0450 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x456 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0456 0x0456 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0451 0451 <default> 0452 0452 ioc_load_wdr 0 ; Flow J cc=True 0x4a7 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 04a7 0x04a7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame f val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 0453 0453 fiu_mem_start 3 start-wr; Flow C cc=True 0x460 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0460 0x0460 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 0 NO_OP 0454 0454 <default> 0455 0455 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x451 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0451 0x0451 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 0456 0456 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP 0457 0457 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_a_adr 02 GP02 typ_b_adr 03 GP03 typ_csa_cntl 7 FINISH_POP_DOWN 0458 0458 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 2 fiu+val typ_a_adr 26 TR07:06 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl c LOAD_MAR_QUEUE val_alu_func 1a PASS_B val_b_adr 03 GP03 0459 0459 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 02 GP02 val_a_adr 01 GP01 val_b_adr 02 GP02 045a 045a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 22 TR01:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 045b 045b ioc_load_wdr 0 ; Flow J 0x45c seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 05 GP05 045c 045c fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val val_b_adr 3e VR11:1e val_frame 11 045d 045d fiu_mem_start 3 start-wr; Flow J cc=True 0x461 ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0461 0x0461 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 045e 045e ioc_load_wdr 0 ; Flow C 0x33a3 seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_b_adr 24 TR02:04 typ_frame 2 val_b_adr 09 GP09 045f 045f fiu_mem_start 2 start-rd; Flow J 0x4a0 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0460 ; -------------------------------------------------------------------------------------- 0460 ; Comes from: 0460 ; 0453 C True from color 0x0000 0460 ; -------------------------------------------------------------------------------------- 0460 0460 seq_br_type 3 Unconditional Branch; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 0461 0461 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR02:04 typ_frame 2 val_b_adr 09 GP09 0462 0462 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ typ_a_adr 2a TR02:0a typ_b_adr 20 TR02:00 typ_frame 2 0463 0463 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x33a3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 0464 0464 fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR02:04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0465 0465 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A 0466 0466 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x469 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 0469 0x0469 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 07 GP07 typ_c_adr 1d TR17:02 typ_c_mux_sel 0 ALU typ_frame 17 val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 1d VR17:02 val_c_mux_sel 2 ALU val_frame 17 0467 0467 ioc_fiubs 1 val ; Flow C 0x56b ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 056b 0x056b typ_a_adr 3e TR17:1e typ_alu_func 0 PASS_A typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 0468 0468 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 0469 ; -------------------------------------------------------------------------------------- 0469 ; Comes from: 0469 ; 0466 C True from color 0x0000 0469 ; -------------------------------------------------------------------------------------- 0469 0469 seq_br_type a Unconditional Return; Flow R typ_a_adr 22 TR17:02 typ_alu_func 1b A_OR_B typ_b_adr 3e TR17:1e typ_c_adr 1d TR17:02 typ_c_mux_sel 0 ALU typ_frame 17 046a 046a fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_random 02 ? typ_a_adr 20 TR05:00 typ_csa_cntl 1 START_POP_DOWN typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 046b 046b fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 046c 046c fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 046d 046d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 046e 046e fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 046f 046f seq_br_type 7 Unconditional Call; Flow C 0x32d5 seq_branch_adr 32d5 0x32d5 0470 0470 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x211 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0211 0x0211 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 33 TR06:13 typ_alu_func 1e A_AND_B typ_b_adr 08 GP08 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand c WRITE_OUTER_FRAME val_a_adr 2b VR05:0b val_frame 5 0471 0471 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x472 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 0483 0x0483 typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 0472 0472 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 0473 0473 fiu_mem_start 2 start-rd; Flow J cc=False 0x4a6 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 04a6 0x04a6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B 0474 0474 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0475 0475 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x4a6 fiu_load_mdr 1 hold_mdr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 04a6 0x04a6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 0476 0476 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_a_adr 22 TR07:02 typ_alu_func 1e A_AND_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 6 A_MINUS_B val_b_adr 3d VR06:1d val_frame 6 0477 0477 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x493 fiu_load_tar 1 hold_tar fiu_offs_lit 3d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0493 0x0493 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 val_b_adr 22 VR05:02 val_frame 5 0478 0478 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x22f7 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 22f7 0x22f7 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0479 0479 ioc_fiubs 1 val ; Flow C 0x22f7 seq_br_type 7 Unconditional Call seq_branch_adr 22f7 0x22f7 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 047a 047a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 047b 047b fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 typ_b_adr 2e TR11:0e typ_frame 11 val_b_adr 39 VR02:19 val_frame 2 047c 047c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x4a6 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 04a6 0x04a6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE 047d 047d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 03 GP03 047e 047e fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x4a6 fiu_load_tar 1 hold_tar fiu_mem_start 7 start_wr_if_true fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 04a6 0x04a6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 047f 047f fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key seq_en_micro 0 typ_b_adr 04 GP04 typ_c_adr 28 LOOP_COUNTER typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 12 val_b_adr 04 GP04 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0480 0480 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 seq_random 02 ? typ_mar_cntl b LOAD_MAR_DATA typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 1a PASS_B val_b_adr 01 GP01 val_rand 2 DEC_LOOP_COUNTER 0481 0481 ioc_fiubs 1 val ; Flow J cc=False 0x489 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0489 0x0489 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 0482 0482 seq_br_type 3 Unconditional Branch; Flow J 0x48d seq_branch_adr 048d 0x048d 0483 0483 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 0484 0484 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 3d VR06:1d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 val_rand a PASS_B_HIGH 0485 0485 seq_en_micro 0 0486 0486 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 0487 0487 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_b_adr 04 GP04 0488 0488 ioc_fiubs 0 fiu ; Flow J cc=True 0x48d ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 048d 0x048d seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0489 0489 seq_br_type 3 Unconditional Branch; Flow J 0x48b seq_branch_adr 048b 0x048b typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 26 TR09:06 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 34 VR09:14 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 9 048a 048a <default> 048b 048b fiu_mem_start 3 start-wr; Flow C cc=True 0x211 ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 13 LOOP_REG typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame f typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 0 NO_OP val_b_adr 13 LOOP_REG 048c 048c seq_br_type 1 Branch True; Flow J cc=True 0x48a seq_branch_adr 048a 0x048a seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 32 VR09:12 val_frame 9 val_rand 2 DEC_LOOP_COUNTER 048d 048d fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 26 TR07:06 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl c LOAD_MAR_QUEUE val_alu_func 1a PASS_B val_b_adr 03 GP03 048e 048e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 02 GP02 val_a_adr 20 VR02:00 val_b_adr 02 GP02 val_frame 2 048f 048f fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 32 TR11:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 0490 0490 ioc_load_wdr 0 typ_b_adr 05 GP05 val_b_adr 05 GP05 0491 0491 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0492 0x0492 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0492 0492 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 0493 0493 fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 0494 0494 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0495 0495 seq_br_type 4 Call False; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 01 GP01 typ_frame e 0496 0496 typ_a_adr 25 TR07:05 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 0497 0497 typ_a_adr 25 TR07:05 typ_alu_func 1e A_AND_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 7 0498 0498 seq_br_type 5 Call True; Flow C cc=True 0x32de seq_branch_adr 32de 0x32de seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 09 GP09 0499 0499 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 049a 049a fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 049b 049b seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 049c 049c fiu_mem_start 2 start-rd; Flow C 0x4a0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 04a0 0x04a0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 049d 049d seq_br_type 7 Unconditional Call; Flow C 0x32a6 seq_branch_adr 32a6 0x32a6 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 049e 049e fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 049f 049f ioc_load_wdr 0 ; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 04a0 04a0 <default> 04a1 04a1 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 04a2 04a2 fiu_mem_start 3 start-wr typ_a_adr 37 TR02:17 typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 04a3 04a3 ioc_load_wdr 0 04a4 04a4 fiu_tivi_src c mar_0xc; Flow C 0x3ba5 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3ba5 0x3ba5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 04a5 04a5 seq_br_type a Unconditional Return; Flow R 04a6 04a6 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 04a7 04a7 seq_br_type 7 Unconditional Call; Flow C 0x49a seq_branch_adr 049a 0x049a 04a8 ; -------------------------------------------------------------------------------------- 04a8 ; 0x03c7 Complete_Type Access,By_Defining 04a8 ; -------------------------------------------------------------------------------------- 04a8 MACRO_Complete_Type_Access,By_Defining: 04a8 04a8 dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 04a8 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 04a9 04a9 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 04aa 04aa fiu_load_tar 1 hold_tar; Flow C cc=False 0x32d9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 3d TR07:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR09:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 9 04ab 04ab fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x4ac fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 32d9 0x32d9 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 2a TR09:0a typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3a GP05 val_c_source 0 FIU_BUS 04ac 04ac fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32a9 fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 04ad 04ad fiu_len_fill_lit 41 zero-fill 0x1; Flow C 0x32d7 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3f GP00 04ae 04ae fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x4af ; Flow J cc=#0x0 0x4af fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 04af 0x04af seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 04af 04af seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04b0 04b0 fiu_load_tar 1 hold_tar; Flow J 0x4b3 fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 04b3 0x04b3 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 04b1 04b1 fiu_load_var 1 hold_var; Flow J 0x4cc fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 04cc 0x04cc typ_a_adr 20 TR08:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 04b2 04b2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04b3 04b3 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x4b4 ; Flow J cc=#0x0 0x4b8 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 04b8 0x04b8 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 04b4 04b4 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 04b5 04b5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32d7 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_random 02 ? typ_a_adr 1e TOP - 2 typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 04b6 04b6 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 04b7 04b7 ioc_load_wdr 0 ; Flow J 0x526 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle typ_csa_cntl 3 POP_CSA val_b_adr 39 VR02:19 val_frame 2 04b8 04b8 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04b9 04b9 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04ba 04ba ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04bb 04bb seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 04bc 04bc seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04bd 04bd seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04be 04be seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04bf 04bf seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 04c0 04c0 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04c1 04c1 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04c2 04c2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04c3 04c3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04c4 04c4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04c5 04c5 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x4cb seq_br_type 8 Return True seq_branch_adr 04cb 0x04cb seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1e TOP - 2 04c6 04c6 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x4cb seq_br_type 8 Return True seq_branch_adr 04cb 0x04cb seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1e TOP - 2 04c7 04c7 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x4cb seq_br_type 8 Return True seq_branch_adr 04cb 0x04cb seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1e TOP - 2 04c8 04c8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 0 PASS_A 04c9 04c9 fiu_fill_mode_src 0 ; Flow C 0x352d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 352d 0x352d seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 val_b_adr 30 VR02:10 val_frame 2 04ca 04ca ioc_load_wdr 0 ; Flow J 0x4d0 seq_br_type 3 Unconditional Branch seq_branch_adr 04d0 0x04d0 seq_random 02 ? typ_b_adr 1e TOP - 2 04cb 04cb ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x4c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 04c8 0x04c8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 04cc 04cc fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x4cf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 04cf 0x04cf seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1e TOP - 2 typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 05 GP05 04cd 04cd fiu_fill_mode_src 0 ; Flow C 0x352d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 352d 0x352d seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 04ce 04ce ioc_load_wdr 0 ; Flow J 0x4d0 seq_br_type 3 Unconditional Branch seq_branch_adr 04d0 0x04d0 seq_random 02 ? typ_b_adr 1e TOP - 2 04cf ; -------------------------------------------------------------------------------------- 04cf ; Comes from: 04cf ; 04cc C True from color 0x04b0 04cf ; -------------------------------------------------------------------------------------- 04cf 04cf seq_br_type a Unconditional Return; Flow R typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 04d0 04d0 fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x4d4 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 04d4 0x04d4 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 04d1 04d1 fiu_mem_start a start_continue_if_false; Flow C 0x32d7 ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 04d2 04d2 ioc_load_wdr 0 typ_b_adr 02 GP02 typ_csa_cntl 3 POP_CSA val_b_adr 02 GP02 04d3 04d3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 04d4 04d4 seq_br_type 3 Unconditional Branch; Flow J 0x4d0 seq_branch_adr 04d0 0x04d0 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 04d5 04d5 <halt> ; Flow R 04d6 ; -------------------------------------------------------------------------------------- 04d6 ; 0x03c6 Complete_Type Access,By_Renaming 04d6 ; -------------------------------------------------------------------------------------- 04d6 MACRO_Complete_Type_Access,By_Renaming: 04d6 04d6 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 04d6 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 04d7 04d7 ioc_fiubs 0 fiu ; Flow C cc=True 0x32db ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 04d8 04d8 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32d9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 04d9 04d9 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 04da 04da fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x50b fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 050b 0x050b seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 04db 04db fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 04dc 04dc fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 04dd 04dd fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 04de 04de fiu_load_tar 1 hold_tar; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 04df 04df fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32d9 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 04e0 04e0 fiu_mem_start 3 start-wr; Flow C cc=True 0x32d9 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 35 VR07:15 val_c_adr 3b GP04 val_frame 7 04e1 04e1 fiu_mem_start 4 continue ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 04e2 04e2 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 04e3 04e3 ioc_load_wdr 0 ; Flow J 0x526 seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA val_b_adr 04 GP04 04e4 ; -------------------------------------------------------------------------------------- 04e4 ; 0x03c5 Complete_Type Access,By_Constraining 04e4 ; -------------------------------------------------------------------------------------- 04e4 MACRO_Complete_Type_Access,By_Constraining: 04e4 04e4 dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 04e4 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 04e5 04e5 ioc_fiubs 0 fiu ; Flow C cc=True 0x32db ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 04e6 04e6 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32d9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 04e7 04e7 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 04e8 04e8 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x50b fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 050b 0x050b seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 04e9 04e9 fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 04ea 04ea fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 04eb 04eb fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 04ec 04ec fiu_load_tar 1 hold_tar; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 04ed 04ed fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32d9 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 04ee 04ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 val_c_adr 3e GP01 04ef 04ef fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x32d9 fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_a_adr 01 GP01 typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_frame b typ_rand 9 PASS_A_HIGH 04f0 04f0 ioc_fiubs 0 fiu ; Flow C cc=#0x0 0x4f5 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 04f5 0x04f5 seq_en_micro 0 typ_a_adr 1e TOP - 2 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 04f1 04f1 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 35 VR07:15 val_frame 7 04f2 04f2 fiu_mem_start 4 continue ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 04f3 04f3 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 04f4 04f4 ioc_load_wdr 0 ; Flow J 0x526 seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 04f5 ; -------------------------------------------------------------------------------------- 04f5 ; Comes from: 04f5 ; 04f0 C #0x0 from color 0x0000 04f5 ; -------------------------------------------------------------------------------------- 04f5 04f5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04f6 04f6 fiu_mem_start 2 start-rd; Flow J 0x4fd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 04fd 0x04fd typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 04f7 04f7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04f8 04f8 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04f9 04f9 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 04fa 04fa seq_br_type 3 Unconditional Branch; Flow J 0x501 seq_branch_adr 0501 0x0501 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 04fb 04fb seq_br_type 3 Unconditional Branch; Flow J 0x501 seq_branch_adr 0501 0x0501 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 04fc 04fc fiu_mem_start 2 start-rd; Flow J 0x509 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0509 0x0509 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 04fd 04fd <default> 04fe 04fe fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32d9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1e TOP - 2 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 04ff 04ff ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32d9 seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0500 0500 fiu_mem_start 2 start-rd; Flow J 0x3274 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3274 0x3274 typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0501 0501 seq_b_timing 1 Latch Condition; Flow C cc=False 0x32d9 seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 0502 0502 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0503 0x0503 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1e TOP - 2 typ_b_adr 01 GP01 0503 0503 fiu_mem_start 2 start-rd; Flow C 0x3274 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3274 0x3274 typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0504 0504 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 0505 0505 typ_a_adr 1e TOP - 2 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 0506 0506 seq_br_type 7 Unconditional Call; Flow C 0x2292 seq_branch_adr 2292 0x2292 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 0507 0507 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0508 0x0508 typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 0508 0508 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 0509 0509 <default> 050a 050a fiu_len_fill_lit 45 zero-fill 0x5; Flow J 0x501 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0501 0x0501 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 050b 050b fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 050c 050c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32db seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 050d 050d seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 050e ; -------------------------------------------------------------------------------------- 050e ; 0x03c4 Complete_Type Access,By_Component_Completion 050e ; -------------------------------------------------------------------------------------- 050e MACRO_Complete_Type_Access,By_Component_Completion: 050e 050e dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 050e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 050f 050f fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0510 0510 fiu_load_tar 1 hold_tar; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0511 0511 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x4d3 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 04d3 0x04d3 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 0512 0512 fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 39 GP06 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 0513 0513 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32a9 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0514 0514 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x516 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0516 0x0516 seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 0515 0515 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 0516 ; -------------------------------------------------------------------------------------- 0516 ; Comes from: 0516 ; 0514 C #0x0 from color 0x0000 0516 ; -------------------------------------------------------------------------------------- 0516 0516 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0517 0517 ioc_tvbs 1 typ+fiu; Flow J 0x51a seq_br_type 3 Unconditional Branch seq_branch_adr 051a 0x051a val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0518 0518 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0519 0519 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 051a 051a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x51f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 051f 0x051f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 02 GP02 typ_b_adr 10 TOP val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 05 GP05 051b 051b fiu_fill_mode_src 0 ; Flow C 0x352d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 352d 0x352d seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 val_b_adr 30 VR02:10 val_frame 2 051c 051c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x526 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0526 MACRO_Action_Idle seq_random 02 ? typ_a_adr 02 GP02 typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA 051d 051d fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3b fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_frame 2 051e 051e ioc_load_wdr 0 ; Flow J 0x526 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle val_b_adr 02 GP02 051f 051f fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 0520 0520 fiu_mem_start 3 start-wr; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 0521 0521 ioc_load_wdr 0 ; Flow J 0x526 seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle seq_random 02 ? typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA val_b_adr 06 GP06 0522 ; -------------------------------------------------------------------------------------- 0522 ; 0x0000 Action Illegal,>R 0522 ; -------------------------------------------------------------------------------------- 0522 MACRO_Action_Illegal,>R: 0522 0522 dispatch_brk_class 0 ; Flow C cc=True 0x68d dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0522 seq_br_type 5 Call True seq_branch_adr 068d 0x068d seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 0523 0523 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x32dd seq_br_type 1 Branch True seq_branch_adr 32dd 0x32dd seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 20 VR02:00 val_alu_func 6 A_MINUS_B val_b_adr 3d VR02:1d val_frame 2 0524 0524 seq_br_type 3 Unconditional Branch; Flow J 0x526 seq_branch_adr 0526 MACRO_Action_Idle seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0525 0525 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 typ_csa_cntl 2 PUSH_CSA 0526 ; -------------------------------------------------------------------------------------- 0526 ; 0x0008 Action Idle 0526 ; -------------------------------------------------------------------------------------- 0526 MACRO_Action_Idle: 0526 0526 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0526 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0527 0527 <halt> ; Flow R 0528 ; -------------------------------------------------------------------------------------- 0528 ; 0x00c4 Action Make_Default 0528 ; -------------------------------------------------------------------------------------- 0528 MACRO_Action_Make_Default: 0528 0528 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0528 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 37 TR07:17 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0529 ; -------------------------------------------------------------------------------------- 0529 ; Comes from: 0529 ; 052d C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 052f C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 0531 C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 0533 C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 0535 C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 0537 C True from color MACRO_Pop_Control_Pop_Count_7 0529 ; 053a C from color MACRO_Pop_Control_Pop_Count_7 0529 ; -------------------------------------------------------------------------------------- 0529 0529 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 052a 0x052a seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 11 TOP + 1 typ_frame a 052a 052a seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 052b 0x052b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 10 052b 052b seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x525 seq_br_type 9 Return False seq_branch_adr 0525 0x0525 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18) Select_Var Default_Var Exception_Var seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 18 052c ; -------------------------------------------------------------------------------------- 052c ; 0x00d7 Pop_Control Pop_Count_7 052c ; -------------------------------------------------------------------------------------- 052c MACRO_Pop_Control_Pop_Count_7: 052c 052c dispatch_brk_class 3 ; Flow J cc=False 0x52e dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 052c seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 052e MACRO_Pop_Control_Pop_Count_6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 052d 052d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 052e ; -------------------------------------------------------------------------------------- 052e ; 0x00d6 Pop_Control Pop_Count_6 052e ; -------------------------------------------------------------------------------------- 052e MACRO_Pop_Control_Pop_Count_6: 052e 052e dispatch_brk_class 3 ; Flow J cc=False 0x530 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 052e seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0530 MACRO_Pop_Control_Pop_Count_5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 052f 052f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0530 ; -------------------------------------------------------------------------------------- 0530 ; 0x00d5 Pop_Control Pop_Count_5 0530 ; -------------------------------------------------------------------------------------- 0530 MACRO_Pop_Control_Pop_Count_5: 0530 0530 dispatch_brk_class 3 ; Flow J cc=False 0x532 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 0530 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0532 MACRO_Pop_Control_Pop_Count_4 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 0531 0531 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0532 ; -------------------------------------------------------------------------------------- 0532 ; 0x00d4 Pop_Control Pop_Count_4 0532 ; -------------------------------------------------------------------------------------- 0532 MACRO_Pop_Control_Pop_Count_4: 0532 0532 dispatch_brk_class 3 ; Flow J cc=False 0x534 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 0532 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0534 MACRO_Pop_Control_Pop_Count_3 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 0533 0533 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0534 ; -------------------------------------------------------------------------------------- 0534 ; 0x00d3 Pop_Control Pop_Count_3 0534 ; -------------------------------------------------------------------------------------- 0534 MACRO_Pop_Control_Pop_Count_3: 0534 0534 dispatch_brk_class 3 ; Flow J cc=False 0x536 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 0534 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0536 MACRO_Pop_Control_Pop_Count_2 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 0535 0535 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x529 seq_br_type 5 Call True seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0536 ; -------------------------------------------------------------------------------------- 0536 ; 0x00d2 Pop_Control Pop_Count_2 0536 ; -------------------------------------------------------------------------------------- 0536 MACRO_Pop_Control_Pop_Count_2: 0536 0536 dispatch_brk_class 3 ; Flow J cc=False 0x538 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0536 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0538 MACRO_Pop_Control_Pop_Count_1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 0537 0537 seq_br_type 5 Call True; Flow C cc=True 0x529 seq_branch_adr 0529 0x0529 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 11 0538 ; -------------------------------------------------------------------------------------- 0538 ; 0x00d1 Pop_Control Pop_Count_1 0538 ; -------------------------------------------------------------------------------------- 0538 MACRO_Pop_Control_Pop_Count_1: 0538 0538 dispatch_brk_class 3 ; Flow R cc=False dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0538 fiu_mem_start 2 start-rd fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0539 0x0539 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0539 0539 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 053a 0x053a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 11 TOP + 1 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL 053a 053a seq_br_type 7 Unconditional Call; Flow C 0x529 seq_branch_adr 0529 0x0529 053b 053b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 053c ; -------------------------------------------------------------------------------------- 053c ; 0x00d0 Action Swap_Control 053c ; -------------------------------------------------------------------------------------- 053c MACRO_Action_Swap_Control: 053c 053c dispatch_brk_class 3 ; Flow J cc=True 0x53f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 053c ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 053f 0x053f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 053d 053d fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 053e 0x053e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 053e 053e typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 053f 053f seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 typ_c_adr 2f TOP val_c_adr 2f TOP 0540 ; -------------------------------------------------------------------------------------- 0540 ; 0x00cd Action Spare6_Action 0540 ; -------------------------------------------------------------------------------------- 0540 MACRO_Action_Spare6_Action: 0540 0540 dispatch_brk_class 3 ; Flow C 0x32d7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0540 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_b_adr 10 TOP typ_frame 1 val_b_adr 10 TOP 0541 0541 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0542 0x0542 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0542 0542 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 typ_c_adr 2f TOP typ_csa_cntl 2 PUSH_CSA val_c_adr 2f TOP 0543 0543 <halt> ; Flow R 0544 ; -------------------------------------------------------------------------------------- 0544 ; 0x00cf Action Mark_Auxiliary 0544 ; -------------------------------------------------------------------------------------- 0544 MACRO_Action_Mark_Auxiliary: 0544 0544 dispatch_brk_class 3 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 0544 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 1 val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR02:16 val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0545 0545 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu typ_alu_func 1b A_OR_B typ_b_adr 21 TR02:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0546 0546 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x54c fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 21 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 054c 0x054c seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 10 NOT_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0547 0547 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_alu_func 19 X_XOR_B typ_b_adr 31 TR11:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 11 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 2f TOP val_c_mux_sel 2 ALU 0548 0548 fiu_len_fill_lit 40 zero-fill 0x0; Flow R cc=False fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0549 0x0549 seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_frame 2 0549 0549 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 22 TR02:02 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 054a 054a fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 22 TR02:02 typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 054b 054b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 054c 054c seq_br_type 3 Unconditional Branch; Flow J 0x548 seq_branch_adr 0548 0x0548 typ_alu_func 19 X_XOR_B typ_b_adr 39 TR07:19 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 054d 054d <halt> ; Flow R 054e ; -------------------------------------------------------------------------------------- 054e ; 0x00ce Action Pop_Auxiliary 054e ; -------------------------------------------------------------------------------------- 054e MACRO_Action_Pop_Auxiliary: 054e 054e dispatch_brk_class 3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 054e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 1 val seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 054f 054f seq_b_timing 3 Late Condition, Hint False; Flow C 0x32d7 seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x62) Auxiliary_Mark typ_a_adr 3a TR02:1a typ_alu_func 1b A_OR_B typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 2 0550 0550 fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x555 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0555 0x0555 typ_a_adr 22 TR01:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0551 0551 ioc_load_wdr 0 ; Flow J cc=True 0x552 ; Flow J cc=#0x0 0x552 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0552 0x0552 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_random 02 ? typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0552 0552 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0553 0553 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR02:11 val_frame 2 0554 0554 ioc_load_wdr 0 ; Flow J 0x552 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0552 0x0552 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 0555 0555 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0556 0x0556 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0556 0556 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0557 0557 <halt> ; Flow R 0558 ; -------------------------------------------------------------------------------------- 0558 ; 0x00c9 Action Pop_Auxiliary_Loop 0558 ; -------------------------------------------------------------------------------------- 0558 MACRO_Action_Pop_Auxiliary_Loop: 0558 0558 dispatch_brk_class 3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0558 fiu_len_fill_lit 64 zero-fill 0x24 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 10 TOP typ_frame 1f typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS 0559 0559 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 3a TR02:1a typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 055a ; -------------------------------------------------------------------------------------- 055a ; 0x00c8 Action Pop_Auxiliary_Range 055a ; -------------------------------------------------------------------------------------- 055a MACRO_Action_Pop_Auxiliary_Range: 055a 055a dispatch_brk_class 3 ; Flow C 0x32d7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 055a fiu_load_oreg 1 hold_oreg fiu_offs_lit 3f ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 34 VR06:14 val_frame 6 055b 055b fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 055c 0x055c seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 1f TOP - 1 typ_c_adr 2c LOOP_REG typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 055c 055c typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU 055d 055d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 055e ; -------------------------------------------------------------------------------------- 055e ; 0x00ba Action Initiate_Delay 055e ; -------------------------------------------------------------------------------------- 055e MACRO_Action_Initiate_Delay: 055e 055e dispatch_brk_class 3 ; Flow J cc=False 0x563 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 055e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type 0 Branch False seq_branch_adr 0563 0x0563 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_random 1d ? typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 055f 055f seq_br_type 7 Unconditional Call; Flow C 0x33af seq_branch_adr 33af 0x33af seq_random 05 ? 0560 0560 ioc_tvbs 5 seq+seq; Flow C 0x56b seq_br_type 7 Unconditional Call seq_branch_adr 056b 0x056b seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 0 PASS_A val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 0561 0561 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x562 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 28 VR05:08 val_frame 5 0562 0562 ioc_tvbs 2 fiu+val; Flow J 0x33a3 seq_br_type 3 Unconditional Branch seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0563 0563 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x526 seq_br_type 3 Unconditional Branch seq_branch_adr 0526 MACRO_Action_Idle seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 0564 ; -------------------------------------------------------------------------------------- 0564 ; Comes from: 0564 ; 0591 C from color 0x0590 0564 ; 05c2 C from color 0x05a7 0564 ; 05e7 C True from color 0x05db 0564 ; -------------------------------------------------------------------------------------- 0564 0564 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 38 TR17:18 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0565 0565 seq_en_micro 0 0566 0566 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_b_adr 16 CSA/VAL_BUS 0567 0567 fiu_len_fill_lit 71 zero-fill 0x31; Flow C 0x3683 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3683 0x3683 seq_en_micro 0 val_c_adr 00 VR17:1f val_c_source 0 FIU_BUS val_frame 17 0568 0568 fiu_load_var 1 hold_var; Flow C 0x2ab4 fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_b_adr 39 VR03:19 val_frame 3 0569 0569 ioc_tvbs 1 typ+fiu; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 056a 0x056a seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_a_adr 3f VR17:1f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 056a 056a seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 056b 056b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x599 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0599 0x0599 seq_en_micro 0 typ_c_adr 18 TR17:07 typ_c_source 0 FIU_BUS typ_frame 17 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 18 VR17:07 val_c_mux_sel 2 ALU val_frame 17 056c 056c fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x2ab4 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 21 TR17:01 typ_frame 17 056d 056d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 056e 056e fiu_len_fill_lit 71 zero-fill 0x31 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 07 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 38 TR17:18 typ_alu_func 0 PASS_A typ_b_adr 21 TR17:01 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 23 VR17:03 val_frame 17 056f 056f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 07 fiu_rdata_src 0 rotator seq_en_micro 0 0570 0570 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=False 0x62e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 062e 0x062e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0571 0571 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 0572 0572 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 35 TR17:15 typ_alu_func 0 PASS_A typ_b_adr 21 TR17:01 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0573 0573 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 22 TR17:02 typ_frame 17 val_b_adr 22 VR17:02 val_frame 17 0574 0574 seq_br_type 0 Branch False; Flow J cc=False 0x58c seq_branch_adr 058c 0x058c seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR17:00 typ_frame 17 0575 0575 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 38 TR17:18 typ_alu_func 0 PASS_A typ_b_adr 20 TR17:00 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0576 0576 seq_en_micro 0 0577 0577 fiu_len_fill_lit 71 zero-fill 0x31; Flow C 0x210 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_b_adr 16 CSA/VAL_BUS 0578 0578 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x58c seq_br_type 0 Branch False seq_branch_adr 058c 0x058c seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 val_a_adr 23 VR17:03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 17 0579 0579 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 057a 057a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_frame 17 057b 057b ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 38 TR17:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR17:04 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 057c 057c fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x581 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 0581 0x0581 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 24 TR17:04 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL 057d 057d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x596 seq_br_type 1 Branch True seq_branch_adr 0596 0x0596 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 057e 057e fiu_len_fill_lit 71 zero-fill 0x31; Flow C 0x210 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_b_adr 16 CSA/VAL_BUS 057f 057f fiu_mem_start 2 start-rd; Flow J cc=False 0x581 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0581 0x0581 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 24 TR17:04 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 23 VR17:03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 17 0580 0580 fiu_load_tar 1 hold_tar; Flow J 0x57b fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 057b 0x057b seq_en_micro 0 typ_b_adr 24 TR17:04 typ_frame 17 0581 0581 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 3f TR02:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0582 0582 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 21 TR17:01 typ_frame 17 0583 0583 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0584 0584 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0585 0585 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR17:01 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0586 0586 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 24 TR17:04 typ_frame 17 0587 0587 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0588 0588 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0589 0589 ioc_tvbs 5 seq+seq; Flow C cc=False 0x594 seq_br_type 4 Call False seq_branch_adr 0594 0x0594 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR17:01 typ_b_adr 16 CSA/VAL_BUS typ_frame 17 058a 058a fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 27 TR17:07 typ_frame 17 val_b_adr 27 VR17:07 val_frame 17 058b ; -------------------------------------------------------------------------------------- 058b ; Comes from: 058b ; 36bf C from color 0x0200 058b ; -------------------------------------------------------------------------------------- 058b 058b seq_br_type 1 Branch True; Flow J cc=True 0x575 seq_branch_adr 0575 0x0575 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR17:00 typ_frame 17 058c 058c fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR17:01 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 058d 058d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_frame 17 058e 058e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x20a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 058f 058f ioc_fiubs 2 typ ; Flow C 0x2ab4 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 21 TR17:01 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME 0590 0590 ioc_tvbs 5 seq+seq; Flow C cc=False 0x594 seq_br_type 4 Call False seq_branch_adr 0594 0x0594 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR17:01 typ_b_adr 16 CSA/VAL_BUS typ_frame 17 0591 0591 seq_br_type 7 Unconditional Call; Flow C 0x564 seq_branch_adr 0564 0x0564 seq_en_micro 0 0592 0592 seq_br_type 7 Unconditional Call; Flow C 0x5dd seq_branch_adr 05dd 0x05dd seq_en_micro 0 0593 0593 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 27 TR17:07 typ_frame 17 val_b_adr 27 VR17:07 val_frame 17 0594 ; -------------------------------------------------------------------------------------- 0594 ; Comes from: 0594 ; 0589 C False from color 0x0588 0594 ; 0590 C False from color 0x0590 0594 ; -------------------------------------------------------------------------------------- 0594 0594 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 0595 0595 ioc_tvbs 3 fiu+fiu; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0596 0596 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0597 0597 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 24 TR17:04 typ_alu_func 0 PASS_A typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL 0598 0598 seq_br_type 3 Unconditional Branch; Flow J 0x57e seq_branch_adr 057e 0x057e seq_en_micro 0 0599 ; -------------------------------------------------------------------------------------- 0599 ; Comes from: 0599 ; 056b C from color 0x0000 0599 ; -------------------------------------------------------------------------------------- 0599 0599 ioc_fiubs 1 val ; Flow C cc=True 0x5a4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 05a4 0x05a4 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 21 VR17:01 val_alu_func 1e A_AND_B val_b_adr 3a VR17:1a val_c_adr 1c VR17:03 val_c_source 0 FIU_BUS val_frame 17 059a 059a seq_en_micro 0 val_a_adr 23 VR17:03 val_b_adr 39 VR17:19 val_frame 17 val_rand c START_MULTIPLY 059b 059b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 1c VR17:03 val_c_mux_sel 1 ALU >> 16 val_frame 17 val_m_b_src 2 Bits 32…47 059c 059c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_m_a_src 2 Bits 32…47 059d 059d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 059e 059e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_m_a_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 059f 059f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 05a0 05a0 seq_br_type 7 Unconditional Call; Flow C 0x3683 seq_branch_adr 3683 0x3683 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 23 VR17:03 val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 val_rand e PRODUCT_LEFT_32 05a1 05a1 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 39 VR03:19 val_frame 3 05a2 05a2 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 23 VR17:03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 05a3 05a3 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x5a6 seq_branch_adr 05a6 0x05a6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 23 VR17:03 val_alu_func 1d A_AND_NOT_B val_b_adr 3c VR17:1c val_frame 17 05a4 05a4 fiu_vmux_sel 1 fill value; Flow R cc=True ioc_fiubs 0 fiu seq_br_type 8 Return True seq_branch_adr 05a5 0x05a5 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 21 VR17:01 val_c_adr 1c VR17:03 val_c_source 0 FIU_BUS val_frame 17 05a5 05a5 seq_en_micro 0 seq_random 06 Pop_stack+? 05a6 05a6 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3c VR17:1c val_alu_func 0 PASS_A val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 05a7 ; -------------------------------------------------------------------------------------- 05a7 ; Comes from: 05a7 ; 02f0 C from color 0x0000 05a7 ; 035f C from color 0x0000 05a7 ; 3733 C from color 0x3727 05a7 ; 375e C from color 0x0000 05a7 ; 38e8 C from color 0x38e7 05a7 ; 3ad3 C from color 0x0000 05a7 ; 3afd C from color 0x0000 05a7 ; 3b01 C from color 0x0000 05a7 ; -------------------------------------------------------------------------------------- 05a7 05a7 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 1c TR17:03 typ_c_source 0 FIU_BUS typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 05a8 05a8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 05a9 05a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP 05aa 05aa fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x5bb fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 05bb 0x05bb seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3b TR09:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 05ab 05ab fiu_mem_start 3 start-wr; Flow C 0x3b82 ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b82 0x3b82 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 11 val_rand a PASS_B_HIGH 05ac 05ac seq_br_type 2 Push (branch address); Flow J 0x5ad seq_branch_adr 05b8 0x05b8 seq_en_micro 0 05ad 05ad seq_br_type 7 Unconditional Call; Flow C 0x7b6 seq_branch_adr 07b6 0x07b6 seq_en_micro 0 05ae 05ae seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 27 VR04:07 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 05af 05af ioc_fiubs 2 typ ; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 05b0 05b0 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 28 TR05:08 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 4 val_rand a PASS_B_HIGH 05b1 05b1 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 1 ALU >> 16 val_frame 19 05b2 05b2 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 39 TR09:19 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 20 VR19:00 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 1 ALU >> 16 val_frame 19 05b3 05b3 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 05b4 05b4 ioc_adrbs 2 typ ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 05b5 05b5 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 05b6 05b6 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 45 Load_current_name+? typ_b_adr 32 TR02:12 typ_frame 2 05b7 05b7 fiu_mem_start 2 start-rd; Flow J 0x3743 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3743 0x3743 seq_en_micro 0 seq_random 0a ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 05b8 05b8 ioc_adrbs 1 val ; Flow C 0x34cd seq_br_type 7 Unconditional Call seq_branch_adr 34cd 0x34cd seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 06 GP06 val_frame 4 val_rand a PASS_B_HIGH 05b9 05b9 fiu_mem_start 2 start-rd; Flow J cc=False 0x5da ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 05da 0x05da seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 06 GP06 val_frame 4 val_rand a PASS_B_HIGH 05ba 05ba ioc_fiubs 1 val ; Flow J 0x5a9 seq_br_type 3 Unconditional Branch seq_branch_adr 05a9 0x05a9 seq_en_micro 0 typ_c_adr 1c TR17:03 typ_c_source 0 FIU_BUS typ_frame 17 val_a_adr 06 GP06 05bb 05bb seq_br_type 0 Branch False; Flow J cc=False 0x5da seq_branch_adr 05da 0x05da seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR17:00 typ_frame 17 05bc 05bc fiu_mem_start 11 start_tag_query ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 20 TR17:00 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 05bd 05bd seq_en_micro 0 05be 05be fiu_tivi_src 3 tar_frame; Flow C cc=False 0x62e ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 062e 0x062e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 35 VR17:15 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 19 VR17:06 val_c_mux_sel 2 ALU val_frame 17 05bf 05bf fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 26 VR17:06 val_alu_func 1 A_PLUS_B val_b_adr 36 VR17:16 val_frame 17 05c0 05c0 seq_br_type 1 Branch True; Flow J cc=True 0x5c8 seq_branch_adr 05c8 0x05c8 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 20 TR17:00 typ_b_adr 23 TR17:03 typ_frame 17 05c1 05c1 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x5c5 seq_br_type 0 Branch False seq_branch_adr 05c5 0x05c5 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 05c2 05c2 seq_br_type 7 Unconditional Call; Flow C 0x564 seq_branch_adr 0564 0x0564 seq_en_micro 0 05c3 05c3 seq_br_type 7 Unconditional Call; Flow C 0x5dd seq_branch_adr 05dd 0x05dd seq_en_micro 0 05c4 05c4 seq_br_type 3 Unconditional Branch; Flow J 0x5d2 seq_branch_adr 05d2 0x05d2 seq_en_micro 0 05c5 05c5 seq_br_type 1 Branch True; Flow J cc=True 0x5d2 seq_branch_adr 05d2 0x05d2 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 05c6 05c6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 05c7 05c7 fiu_mem_start 11 start_tag_query; Flow J 0x5bd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 05bd 0x05bd seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 20 TR17:00 typ_c_adr 1c TR17:03 typ_c_source 0 FIU_BUS typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 23 VR04:03 val_frame 4 05c8 05c8 ioc_load_wdr 0 ; Flow C 0x2ab4 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 36 TR17:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR17:04 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 05c9 05c9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x5da fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 05da 0x05da seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 24 TR17:04 typ_frame 17 val_a_adr 26 VR17:06 val_frame 17 05ca 05ca fiu_mem_start 11 start_tag_query; Flow C 0x5d0 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 05d0 0x05d0 seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 24 TR17:04 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 05cb 05cb fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 26 VR17:06 val_alu_func 1 A_PLUS_B val_b_adr 36 VR17:16 val_frame 17 05cc 05cc seq_br_type 1 Branch True; Flow J cc=True 0x5c8 seq_branch_adr 05c8 0x05c8 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 23 TR17:03 typ_b_adr 24 TR17:04 typ_frame 17 05cd 05cd fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 1a TR17:05 typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME val_c_adr 1a VR17:05 val_frame 17 05ce 05ce fiu_mem_start e start_physical_wr ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3f TR02:1f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl f LOAD_MAR_RESERVED 05cf 05cf ioc_load_wdr 0 ; Flow J 0x5d2 seq_br_type 3 Unconditional Branch seq_branch_adr 05d2 0x05d2 seq_en_micro 0 typ_b_adr 25 TR17:05 typ_frame 17 val_b_adr 25 VR17:05 val_frame 17 05d0 ; -------------------------------------------------------------------------------------- 05d0 ; Comes from: 05d0 ; 05ca C from color 0x05a7 05d0 ; 05d2 C from color 0x05a7 05d0 ; -------------------------------------------------------------------------------------- 05d0 05d0 seq_en_micro 0 05d1 05d1 fiu_tivi_src 3 tar_frame; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 35 VR17:15 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 19 VR17:06 val_c_mux_sel 2 ALU val_frame 17 05d2 05d2 fiu_mem_start 11 start_tag_query; Flow C 0x5d0 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 05d0 0x05d0 seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 23 TR17:03 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 05d3 05d3 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 26 VR17:06 val_alu_func 1 A_PLUS_B val_b_adr 3e VR17:1e val_frame 17 05d4 05d4 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 13 ONES typ_b_adr 23 TR17:03 typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 26 VR17:06 val_alu_func 1 A_PLUS_B val_b_adr 37 VR17:17 val_c_adr 19 VR17:06 val_c_mux_sel 2 ALU val_frame 17 05d5 05d5 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 05d6 05d6 fiu_len_fill_lit 71 zero-fill 0x31 fiu_mem_start d start_physical_rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 26 VR17:06 val_alu_func 0 PASS_A val_c_adr 1e VR17:01 val_c_source 0 FIU_BUS val_frame 17 05d7 05d7 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 21 TR17:01 typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 05d8 05d8 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR17:02 typ_c_mux_sel 0 ALU typ_frame 17 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR17:02 val_c_mux_sel 2 ALU val_frame 17 05d9 05d9 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 05da 05da fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 05 ? typ_b_adr 04 GP04 val_b_adr 04 GP04 05db ; -------------------------------------------------------------------------------------- 05db ; Comes from: 05db ; 0108 C from color ME_GP_TIME 05db ; -------------------------------------------------------------------------------------- 05db 05db seq_br_type 0 Branch False; Flow J cc=False 0x5e4 seq_branch_adr 05e4 0x05e4 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR17:00 typ_frame 17 05dc 05dc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5e5 seq_br_type 1 Branch True seq_branch_adr 05e5 0x05e5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3f VR17:1f val_alu_func 0 PASS_A val_frame 17 05dd ; -------------------------------------------------------------------------------------- 05dd ; Comes from: 05dd ; 0592 C from color 0x0590 05dd ; 05c3 C from color 0x05a7 05dd ; -------------------------------------------------------------------------------------- 05dd 05dd seq_br_type 1 Branch True; Flow J cc=True 0x5df seq_branch_adr 05df 0x05df seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 val_a_adr 3f VR17:1f val_alu_func 5 DEC_A_MINUS_B val_b_adr 3b VR17:1b val_frame 17 05de 05de fiu_load_var 1 hold_var; Flow J 0x5e0 fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 05e0 0x05e0 seq_en_micro 0 val_b_adr 3f VR17:1f val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 05df 05df fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_a_adr 3f VR17:1f val_alu_func 6 A_MINUS_B val_b_adr 3b VR17:1b val_c_adr 00 VR17:1f val_c_mux_sel 2 ALU val_frame 17 05e0 05e0 ioc_random e enable delay timer; Flow J cc=True 0x5e2 ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 05e2 0x05e2 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 05e1 05e1 fiu_load_var 1 hold_var; Flow J 0x367d fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 367d 0x367d seq_en_micro 0 val_b_adr 3c VR12:1c val_frame 12 05e2 05e2 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 15 NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR17:03 val_c_mux_sel 2 ALU val_frame 17 05e3 05e3 fiu_load_var 1 hold_var; Flow J 0x367d fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 367d 0x367d seq_en_micro 0 val_b_adr 23 VR17:03 val_frame 17 05e4 05e4 fiu_load_var 1 hold_var; Flow J 0x367d fiu_tivi_src 1 tar_val ioc_random f disable delay timer seq_br_type 3 Unconditional Branch seq_branch_adr 367d 0x367d seq_en_micro 0 val_b_adr 3c VR12:1c val_frame 12 05e5 05e5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 20 TR17:00 typ_alu_func 1a PASS_B typ_b_adr 36 TR17:16 typ_c_adr 1c TR17:03 typ_c_mux_sel 0 ALU typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 05e6 05e6 seq_en_micro 0 05e7 05e7 ioc_fiubs 2 typ ; Flow C cc=True 0x564 ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 0564 0x0564 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand c WRITE_OUTER_FRAME 05e8 05e8 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 23 TR17:03 typ_alu_func 1a PASS_B typ_b_adr 38 TR17:18 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 05e9 05e9 seq_en_micro 0 05ea 05ea ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 val_b_adr 16 CSA/VAL_BUS 05eb 05eb fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 23 TR17:03 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 17 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 05ec 05ec fiu_len_fill_lit 60 zero-fill 0x20 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 21 TR17:01 typ_alu_func 0 PASS_A typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand c WRITE_OUTER_FRAME val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 05ed 05ed seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x5f6 seq_br_type 1 Branch True seq_branch_adr 05f6 0x05f6 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 21 TR17:01 typ_frame 17 05ee 05ee fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 37 TR17:17 typ_alu_func 0 PASS_A typ_b_adr 23 TR17:03 typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 05ef 05ef seq_en_micro 0 05f0 05f0 fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x62e ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 062e 0x062e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 05f1 05f1 ioc_load_wdr 0 ; Flow C 0x62a seq_br_type 7 Unconditional Call seq_branch_adr 062a 0x062a seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 03 GP03 05f2 05f2 seq_br_type 5 Call True; Flow C cc=True 0x69b seq_branch_adr 069b 0x069b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 05f3 05f3 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 05f4 05f4 seq_b_timing 1 Latch Condition; Flow J cc=True 0x5f6 seq_br_type 1 Branch True seq_branch_adr 05f6 0x05f6 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 24 TR17:04 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT 05f5 05f5 seq_br_type 3 Unconditional Branch; Flow J 0x5ee seq_branch_adr 05ee 0x05ee seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 05f6 05f6 fiu_mem_start 2 start-rd; Flow J 0x5f7 ioc_adrbs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 05ff 0x05ff seq_en_micro 0 seq_random 02 ? typ_a_adr 23 TR17:03 typ_alu_func 1a PASS_B typ_b_adr 37 TR17:17 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 05f7 05f7 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 05f8 05f8 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 05f9 05f9 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 26 VR05:06 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 05fa 05fa ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 03 GP03 typ_frame 1 val_b_adr 03 GP03 05fb 05fb fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 05fc 05fc ioc_load_wdr 0 ; Flow C 0x62a seq_br_type 7 Unconditional Call seq_branch_adr 062a 0x062a seq_en_micro 0 typ_b_adr 2e TR02:0e typ_frame 2 val_b_adr 0f GP0f 05fd 05fd seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x69b seq_br_type 4 Call False seq_branch_adr 069b 0x069b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 05fe 05fe seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 05ff 05ff fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR17:15 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0600 0600 seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0601 0601 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x62e fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 062e 0x062e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0602 0602 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 0603 0603 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 04 GP04 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0604 0604 fiu_mem_start 3 start-wr; Flow J cc=True 0x623 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0623 0x0623 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0605 0605 ioc_fiubs 2 typ ; Flow C 0x210 ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0606 0606 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x621 seq_br_type 1 Branch True seq_branch_adr 0621 0x0621 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 21 TR07:01 typ_frame 7 val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 35 VR02:15 val_frame 2 0607 0607 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 0 PASS_A 0608 0608 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 0609 0609 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 060a 060a fiu_mem_start 2 start-rd; Flow J 0x60b ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 060b 0x060b seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 060b 060b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 03 GP03 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 060c 060c fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x611 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 79 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0611 0x0611 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl 1 RESTORE_RDR typ_rand 1 INC_LOOP_COUNTER val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 060d 060d fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x613 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0613 0x0613 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 060e 060e ioc_tvbs 2 fiu+val; Flow J cc=True 0x617 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0617 0x0617 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 060f 060f fiu_mem_start 3 start-wr; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_frame 2 0610 0610 ioc_load_wdr 0 ; Flow J 0x61b seq_br_type 3 Unconditional Branch seq_branch_adr 061b 0x061b seq_en_micro 0 0611 0611 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_en_micro 0 val_b_adr 39 VR02:19 val_frame 2 0612 0612 ioc_load_wdr 0 ; Flow J 0x61b ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 061b 0x061b seq_en_micro 0 val_b_adr 39 VR02:19 val_frame 2 0613 0613 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 0614 0614 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_en_micro 0 0615 0615 ioc_load_wdr 0 ; Flow J cc=False 0x61b ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 061b 0x061b seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0616 0616 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0617 0617 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 0618 0618 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_en_micro 0 0619 0619 ioc_load_wdr 0 ; Flow J cc=False 0x61b ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 061b 0x061b seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_frame 2 061a 061a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 061b 061b fiu_mem_start 2 start-rd; Flow C 0x2aef ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2aef 0x2aef seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_rand a PASS_B_HIGH 061c 061c fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 4 val_rand a PASS_B_HIGH 061d 061d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x627 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0627 0x0627 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 37 TR02:17 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 061e 061e fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 35 TR12:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 061f 061f ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f 0620 0620 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 7 INC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0621 0621 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x622 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 25 VR05:05 val_frame 5 0622 0622 ioc_tvbs 2 fiu+val; Flow J 0x33a3 seq_br_type 3 Unconditional Branch seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0623 0623 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 04 GP04 0624 0624 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f 0625 0625 fiu_mem_start 3 start-wr; Flow C 0x3b7e ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b7e 0x3b7e seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 23 TR11:03 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0626 0626 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x603 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0603 0x0603 seq_en_micro 0 typ_b_adr 04 GP04 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0627 ; -------------------------------------------------------------------------------------- 0627 ; Comes from: 0627 ; 061d C True from color 0x0000 0627 ; -------------------------------------------------------------------------------------- 0627 0627 ioc_adrbs 1 val ; Flow C 0x3ba5 seq_br_type 7 Unconditional Call seq_branch_adr 3ba5 0x3ba5 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_rand a PASS_B_HIGH 0628 0628 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0629 0629 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 062a ; -------------------------------------------------------------------------------------- 062a ; Comes from: 062a ; 05f1 C from color 0x05ec 062a ; 05fc C from color 0x05fb 062a ; -------------------------------------------------------------------------------------- 062a 062a fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR11:10 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 11 val_rand a PASS_B_HIGH 062b 062b seq_en_micro 0 062c 062c seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 062d 062d seq_br_type 3 Unconditional Branch; Flow J 0x6bd seq_branch_adr 06bd 0x06bd seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 062e ; -------------------------------------------------------------------------------------- 062e ; Comes from: 062e ; 0570 C False from color 0x056d 062e ; 05be C False from color 0x05a7 062e ; 05f0 C False from color 0x05ec 062e ; 0601 C False from color 0x05fb 062e ; -------------------------------------------------------------------------------------- 062e 062e seq_br_type 3 Unconditional Branch; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 062f 062f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x632 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 0632 0x0632 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0630 0630 ioc_fiubs 0 fiu typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0631 0631 seq_br_type 3 Unconditional Branch; Flow J 0x632 seq_branch_adr 0632 0x0632 typ_a_adr 29 TR02:09 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0632 0632 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 0633 0633 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x634 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0637 0x0637 seq_int_reads 6 CONTROL TOP 0634 0634 fiu_mem_start 2 start-rd; Flow C 0x3372 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3372 0x3372 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 0635 0635 fiu_load_var 1 hold_var; Flow J cc=True 0x636 ; Flow J cc=#0x0 0x63c fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 063c 0x063c seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0636 0636 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x652 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0652 0x0652 seq_int_reads 6 CONTROL TOP seq_random 06 Pop_stack+? 0637 0637 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 0638 0638 seq_br_type 2 Push (branch address); Flow J 0x639 seq_branch_adr 0637 0x0637 0639 0639 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x652 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0652 0x0652 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP val_a_adr 23 VR02:03 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 063a 063a fiu_load_oreg 1 hold_oreg; Flow C 0x338c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 338c 0x338c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 23 VR02:03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 063b 063b fiu_load_var 1 hold_var; Flow J cc=True 0x63c ; Flow J cc=#0x0 0x63c fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 063c 0x063c seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 063c 063c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x650 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0650 0x0650 seq_int_reads 6 CONTROL TOP val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 063d 063d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x650 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0650 0x0650 seq_int_reads 6 CONTROL TOP val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 063e 063e ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 063f 063f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x640 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0640 0x0640 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 0640 0640 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 0641 0641 ioc_fiubs 2 typ val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0642 0642 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x637 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0637 0x0637 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0643 0643 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0644 0x0644 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2c TR08:0c typ_frame 8 val_a_adr 21 VR13:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 0644 0644 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 42 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 6 0645 0645 ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0646 0646 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x637 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0637 0x0637 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_frame 2 0647 0647 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP 0648 0648 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA 0649 0649 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x64b fiu_mem_start a start_continue_if_false fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 064b 0x064b seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 6 CONTROL TOP typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 064a 064a fiu_fill_mode_src 0 ; Flow J 0x64d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 064d 0x064d val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 064b 064b fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 064c 064c fiu_fill_mode_src 0 ; Flow J 0x64d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 064d 0x064d val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 064d 064d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x64e fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0646 0x0646 val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 064e 064e fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq val_a_adr 23 VR02:03 val_frame 2 064f 064f ioc_fiubs 0 fiu ; Flow C 0x3a72 seq_br_type 7 Unconditional Call seq_branch_adr 3a72 0x3a72 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0650 0650 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 5 seq+seq 0651 0651 ioc_fiubs 0 fiu ; Flow J 0x3a72 seq_br_type 3 Unconditional Branch seq_branch_adr 3a72 0x3a72 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0652 0652 ioc_tvbs 1 typ+fiu val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 0653 0653 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 0654 0654 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x656 seq_br_type 1 Branch True seq_branch_adr 0656 0x0656 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 21 TR01:01 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_frame 2 0655 0655 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x632 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0632 0x0632 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0656 0656 ioc_fiubs 2 typ ; Flow J cc=False 0x661 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 0661 0x0661 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 24 TR02:04 typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0657 0657 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x3b0d seq_br_type 4 Call False seq_branch_adr 3b0d 0x3b0d seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 24 TR02:04 typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 09 GP09 val_alu_func 0 PASS_A 0658 0658 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x65c fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 065c 0x065c seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 24 TR02:04 typ_frame 2 val_b_adr 25 VR05:05 val_frame 5 0659 0659 ioc_tvbs 2 fiu+val; Flow J 0x65a seq_br_type 2 Push (branch address) seq_branch_adr 0661 0x0661 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 065a 065a fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x33a3 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 065b 065b seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 065c 065c fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_frame 2 065d 065d ioc_tvbs 1 typ+fiu; Flow J cc=False 0x661 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0661 0x0661 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 29 VR05:09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 065e 065e seq_br_type 2 Push (branch address); Flow J 0x65f seq_branch_adr 0661 0x0661 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 065f 065f fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x33a3 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 0660 0660 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 0661 0661 seq_br_type 7 Unconditional Call; Flow C 0x32e3 seq_branch_adr 32e3 0x32e3 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0662 0662 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3a GP05 val_c_source 0 FIU_BUS 0663 0663 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0664 0664 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 04 GP04 typ_b_adr 29 TR09:09 typ_frame 9 val_b_adr 39 VR02:19 val_frame 2 0665 0665 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 0 fiu typ_b_adr 04 GP04 typ_c_lit 2 typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 04 GP04 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 0666 0666 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 0667 0667 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0668 0668 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 val_a_adr 04 GP04 val_b_adr 0f GP0f 0669 0669 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 066a 066a fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x68a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 068a 0x068a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 066b 066b ioc_tvbs 1 typ+fiu; Flow J cc=True 0x68a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 068a 0x068a seq_cond_sel 08 VAL.ALU_CARRY(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 066c 066c fiu_load_tar 1 hold_tar; Flow J cc=False 0x68a fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 068a 0x068a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 066d 066d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x68a fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 068a 0x068a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 03 GP03 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 066e 066e seq_br_type 0 Branch False; Flow J cc=False 0x68a seq_branch_adr 068a 0x068a seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 066f 066f fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x674 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 79 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0674 0x0674 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl 1 RESTORE_RDR typ_rand 1 INC_LOOP_COUNTER val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 0670 0670 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x676 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0676 0x0676 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 0671 0671 ioc_tvbs 2 fiu+val; Flow J cc=True 0x67a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 067a 0x067a seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 0672 0672 fiu_mem_start 3 start-wr; Flow J cc=True 0x68a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 068a 0x068a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_frame 2 0673 0673 ioc_load_wdr 0 ; Flow J 0x67e seq_br_type 3 Unconditional Branch seq_branch_adr 067e 0x067e seq_random 02 ? 0674 0674 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val val_b_adr 39 VR02:19 val_frame 2 0675 0675 ioc_load_wdr 0 ; Flow J 0x67e ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 067e 0x067e val_b_adr 39 VR02:19 val_frame 2 0676 0676 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 01 GP01 0677 0677 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val 0678 0678 ioc_load_wdr 0 ; Flow J cc=False 0x67e ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 067e 0x067e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0679 0679 seq_br_type 3 Unconditional Branch; Flow J 0x68a seq_branch_adr 068a 0x068a seq_en_micro 0 067a 067a fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 01 GP01 067b 067b fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ 067c 067c ioc_load_wdr 0 ; Flow J cc=False 0x67e ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 067e 0x067e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_frame 2 067d 067d seq_br_type 3 Unconditional Branch; Flow J 0x68a seq_branch_adr 068a 0x068a seq_en_micro 0 067e 067e fiu_mem_start 2 start-rd; Flow C 0x2aef ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2aef 0x2aef typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_rand a PASS_B_HIGH 067f 067f fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 4 val_rand a PASS_B_HIGH 0680 0680 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x687 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0687 0x0687 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 37 TR02:17 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 0681 0681 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 35 TR12:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0682 0682 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f 0683 0683 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0684 0684 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x685 fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 2 Push (branch address) seq_branch_adr 0662 0x0662 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 0685 0685 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 val_b_adr 0f GP0f 0686 0686 fiu_mem_start 3 start-wr; Flow J 0x3b7e ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b7e 0x3b7e seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 23 TR11:03 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0687 ; -------------------------------------------------------------------------------------- 0687 ; Comes from: 0687 ; 0680 C True from color 0x066a 0687 ; -------------------------------------------------------------------------------------- 0687 0687 ioc_adrbs 1 val ; Flow C 0x3ba5 seq_br_type 7 Unconditional Call seq_branch_adr 3ba5 0x3ba5 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_rand a PASS_B_HIGH 0688 0688 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0689 0689 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 068a 068a fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 068b 068b fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 068c 068c seq_br_type 3 Unconditional Branch; Flow J 0x680 seq_branch_adr 0680 0x0680 068d ; -------------------------------------------------------------------------------------- 068d ; Comes from: 068d ; 0333 C from color 0x0331 068d ; 0340 C from color 0x033e 068d ; 05f3 C from color 0x05ec 068d ; 05fe C from color 0x05fb 068d ; 39e2 C False from color 0x39e2 068d ; 39e4 C False from color 0x39e2 068d ; 3b9f C from color 0x0bab 068d ; -------------------------------------------------------------------------------------- 068d 068d seq_br_type 7 Unconditional Call; Flow C 0x6a3 seq_branch_adr 06a3 0x06a3 seq_en_micro 0 typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 068e 068e seq_b_timing 1 Latch Condition; Flow C cc=True 0x722 seq_br_type 5 Call True seq_branch_adr 0722 0x0722 seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT 068f 068f ioc_adrbs 2 typ ioc_random 14 clear cpu running seq_en_micro 0 typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 0690 0690 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0691 0691 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0692 0692 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0693 0693 fiu_mem_start 2 start-rd; Flow C 0x7b4 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0694 0694 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0695 0695 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0696 0696 ioc_fiubs 1 val seq_en_micro 0 0697 0697 ioc_tvbs 1 typ+fiu; Flow C cc=#0x0 0x6a3 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 06a3 0x06a3 seq_en_micro 0 typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 3f VR02:1f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0698 0698 seq_b_timing 1 Latch Condition; Flow C cc=False 0x72b seq_br_type 4 Call False seq_branch_adr 072b 0x072b seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 0699 0699 ioc_fiubs 1 val ; Flow C 0x6b7 seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 069a 069a seq_br_type 7 Unconditional Call; Flow C 0x722 seq_branch_adr 0722 0x0722 seq_en_micro 0 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 069b ; -------------------------------------------------------------------------------------- 069b ; Comes from: 069b ; 042d C True from color 0x0000 069b ; 05f2 C True from color 0x05ec 069b ; 05fd C False from color 0x05fb 069b ; 394d C True from color 0x0000 069b ; 397d C True from color 0x0913 069b ; 3b16 C from color 0x0000 069b ; -------------------------------------------------------------------------------------- 069b 069b seq_br_type 7 Unconditional Call; Flow C 0x33af seq_branch_adr 33af 0x33af seq_en_micro 0 069c 069c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 6 A_MINUS_B val_b_adr 20 VR02:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 069d 069d fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x69e fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 06a1 0x06a1 seq_en_micro 0 069e 069e ioc_tvbs 1 typ+fiu; Flow C cc=#0x0 0x6a3 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 06a3 0x06a3 seq_en_micro 0 typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 3f VR02:1f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 069f 069f seq_b_timing 1 Latch Condition; Flow J cc=True 0x33a3 seq_br_type 1 Branch True seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 06a0 06a0 seq_br_type 3 Unconditional Branch; Flow J 0x72e seq_branch_adr 072e 0x072e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 06a1 06a1 ioc_adrbs 3 seq ; Flow C 0x6b7 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 06a2 06a2 seq_br_type 7 Unconditional Call; Flow C 0x722 seq_branch_adr 0722 0x0722 seq_en_micro 0 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 06a3 ; -------------------------------------------------------------------------------------- 06a3 ; Comes from: 06a3 ; 068d C from color 0x0000 06a3 ; 0697 C #0x0 from color 0x0695 06a3 ; 069e C #0x0 from color 0x0698 06a3 ; -------------------------------------------------------------------------------------- 06a3 06a3 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a4 0x06a4 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a4 06a4 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a5 0x06a5 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a5 06a5 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a6 0x06a6 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a6 06a6 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a7 0x06a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a7 06a7 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a8 0x06a8 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a8 06a8 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06a9 0x06a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06a9 06a9 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06aa 0x06aa seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06aa 06aa seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06ab 0x06ab seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06ab 06ab seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06ac 0x06ac seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06ac 06ac seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06ad 0x06ad seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06ad 06ad seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06ae 0x06ae seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06ae 06ae seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06af 0x06af seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06af 06af seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06b0 0x06b0 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06b0 06b0 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06b1 0x06b1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06b1 06b1 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06b2 0x06b2 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06b2 06b2 seq_br_type a Unconditional Return; Flow R seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B 06b3 06b3 seq_br_type a Unconditional Return; Flow R seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 seq_latch 1 06b4 ; -------------------------------------------------------------------------------------- 06b4 ; Comes from: 06b4 ; 3694 C from color 0x3690 06b4 ; 36b0 C from color 0x0200 06b4 ; 39af C from color 0x39a6 06b4 ; 39c8 C from color 0x39bf 06b4 ; 3a5c C from color 0x3a5c 06b4 ; -------------------------------------------------------------------------------------- 06b4 06b4 fiu_mem_start 2 start-rd; Flow C 0x7b4 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06b5 06b5 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 06b6 06b6 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 06b7 ; -------------------------------------------------------------------------------------- 06b7 ; Comes from: 06b7 ; 0699 C from color 0x0698 06b7 ; 06a1 C from color 0x06a1 06b7 ; 377e C from color 0x0000 06b7 ; 378e C from color 0x0000 06b7 ; 37bb C from color 0x0000 06b7 ; 39ac C from color 0x39a6 06b7 ; 3bb6 C from color 0x3bad 06b7 ; -------------------------------------------------------------------------------------- 06b7 06b7 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06b8 06b8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x6ca fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 06ca 0x06ca seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_b_adr 13 LOOP_REG typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 06b9 06b9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 06ba 06ba ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 val_a_adr 2a VR04:0a val_alu_func 7 INC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06bb 06bb fiu_tivi_src c mar_0xc; Flow R cc=True ioc_fiubs 0 fiu seq_br_type 8 Return True seq_branch_adr 06bc 0x06bc seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 06bc 06bc seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 06bd ; -------------------------------------------------------------------------------------- 06bd ; Comes from: 06bd ; 2f2d C from color 0x2f17 06bd ; 2f31 C from color 0x2f17 06bd ; 3a4b C from color 0x0000 06bd ; -------------------------------------------------------------------------------------- 06bd 06bd fiu_mem_start 2 start-rd; Flow C 0x7b4 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06be 06be fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 06bf 06bf seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 06c0 ; -------------------------------------------------------------------------------------- 06c0 ; Comes from: 06c0 ; 0332 C from color 0x0331 06c0 ; 033f C from color 0x033e 06c0 ; 074d C from color 0x0203 06c0 ; 075e C from color 0x0000 06c0 ; -------------------------------------------------------------------------------------- 06c0 06c0 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06c1 06c1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x6ca fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 06ca 0x06ca seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 32 TR02:12 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 13 LOOP_REG val_c_adr 30 GP0f val_c_source 0 FIU_BUS 06c2 06c2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 06c3 06c3 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 7 INC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06c4 06c4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x20d fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 13 LOOP_REG val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 06c5 06c5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 06c6 06c6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 06c7 06c7 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 06c8 06c8 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 06c9 0x06c9 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 06c9 06c9 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 06ca 06ca fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU val_b_adr 16 CSA/VAL_BUS 06cb 06cb ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 06cc 06cc fiu_tivi_src c mar_0xc; Flow C cc=False 0x20d ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 06cd 06cd seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 2a VR04:0a val_alu_func 7 INC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06ce 06ce seq_en_micro 0 06cf ; -------------------------------------------------------------------------------------- 06cf ; Comes from: 06cf ; 373b C from color 0x0000 06cf ; 38f0 C from color 0x38e7 06cf ; 38ff C from color 0x38e7 06cf ; 3ad0 C from color 0x0000 06cf ; 3afb C from color 0x0000 06cf ; -------------------------------------------------------------------------------------- 06cf 06cf fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 1a TR04:05 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 06d0 06d0 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 25 TR04:05 typ_frame 4 val_c_adr 39 GP06 val_c_source 0 FIU_BUS 06d1 06d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP 06d2 06d2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x6e8 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 06e8 0x06e8 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3b TR09:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 06d3 06d3 fiu_mem_start 3 start-wr; Flow C 0x3b82 ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b82 0x3b82 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 11 val_rand a PASS_B_HIGH 06d4 06d4 seq_br_type 2 Push (branch address); Flow J 0x6d5 seq_branch_adr 06e0 0x06e0 seq_en_micro 0 06d5 06d5 seq_br_type 7 Unconditional Call; Flow C 0x7b6 seq_branch_adr 07b6 0x07b6 seq_en_micro 0 06d6 06d6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x211 seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 28 VR04:08 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 06d7 06d7 ioc_fiubs 2 typ ; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 06d8 06d8 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 28 TR05:08 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 4 val_rand a PASS_B_HIGH 06d9 06d9 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 1 ALU >> 16 val_frame 19 06da 06da fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 39 TR09:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 20 VR19:00 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 1 ALU >> 16 val_frame 19 06db 06db ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 06dc 06dc ioc_adrbs 2 typ ; Flow C cc=False 0x20d seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 06dd 06dd seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 06de 06de seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 45 Load_current_name+? typ_b_adr 32 TR02:12 typ_frame 2 06df 06df fiu_mem_start 2 start-rd; Flow J 0x3743 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3743 0x3743 seq_en_micro 0 seq_random 0a ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 06e0 06e0 ioc_adrbs 1 val ; Flow C 0x34cd seq_br_type 7 Unconditional Call seq_branch_adr 34cd 0x34cd seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 06 GP06 val_rand a PASS_B_HIGH 06e1 06e1 fiu_mem_start 2 start-rd; Flow J cc=False 0x6e5 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 06e5 0x06e5 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 06 GP06 val_frame 4 val_rand a PASS_B_HIGH 06e2 06e2 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 1a TR04:05 typ_c_source 0 FIU_BUS typ_frame 4 val_a_adr 06 GP06 06e3 06e3 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 06e4 06e4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x6d1 seq_br_type 1 Branch True seq_branch_adr 06d1 0x06d1 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3d TR09:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 06e5 06e5 seq_br_type a Unconditional Return; Flow R seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 05 ? 06e6 ; -------------------------------------------------------------------------------------- 06e6 ; Comes from: 06e6 ; 06e8 C from color 0x06d2 06e6 ; 06ed C from color 0x06d2 06e6 ; 0702 C from color 0x0000 06e6 ; -------------------------------------------------------------------------------------- 06e6 06e6 seq_en_micro 0 06e7 06e7 fiu_tivi_src 3 tar_frame; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 06e8 06e8 fiu_mem_start 11 start_tag_query; Flow C 0x6e6 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 06e6 0x06e6 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 1a TR04:05 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 06e9 06e9 fiu_mem_start d start_physical_rd; Flow C 0x7b4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 06ea 06ea fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 02 VR04:1d val_c_mux_sel 2 ALU val_frame 4 06eb 06eb seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 06ec ; -------------------------------------------------------------------------------------- 06ec ; Comes from: 06ec ; 36c8 C from color 0x05a7 06ec ; -------------------------------------------------------------------------------------- 06ec 06ec seq_br_type 0 Branch False; Flow J cc=False 0x6f8 seq_branch_adr 06f8 0x06f8 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_b_adr 32 TR02:12 typ_frame 2 06ed 06ed fiu_mem_start 11 start_tag_query; Flow C 0x6e6 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 06e6 0x06e6 seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 06ee 06ee fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_frame 4 06ef 06ef ioc_fiubs 2 typ ; Flow J cc=False 0x6f5 seq_br_type 0 Branch False seq_branch_adr 06f5 0x06f5 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_b_adr 25 TR04:05 typ_c_adr 19 TR04:06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 4 typ_rand c WRITE_OUTER_FRAME 06f0 06f0 seq_br_type 7 Unconditional Call; Flow C 0x70b seq_branch_adr 070b 0x070b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 06f1 06f1 seq_b_timing 1 Latch Condition; Flow J cc=False 0x6f8 seq_br_type 0 Branch False seq_branch_adr 06f8 0x06f8 seq_en_micro 0 06f2 06f2 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 06f3 0x06f3 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 2c TR04:0c typ_frame 4 val_a_adr 2a VR04:0a val_alu_func 1c DEC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06f3 06f3 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 06f4 06f4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_en_micro 0 val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 06f5 06f5 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 06f6 0x06f6 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 1c DEC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06f6 06f6 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 06f7 06f7 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU 06f8 06f8 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x6fc fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 06fc 0x06fc seq_en_micro 0 typ_b_adr 25 TR04:05 typ_frame 4 06f9 06f9 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 06fa 0x06fa seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 3c VR04:1c val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 06fa 06fa fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x6fc fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 06fc 0x06fc seq_en_micro 0 val_a_adr 3d VR04:1d val_frame 4 06fb 06fb seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_en_micro 0 06fc ; -------------------------------------------------------------------------------------- 06fc ; Comes from: 06fc ; 06f8 C from color 0x06d2 06fc ; 06fa C from color 0x06d2 06fc ; -------------------------------------------------------------------------------------- 06fc 06fc seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 06fd 06fd fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 3b VR04:1b val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 06fe 06fe fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 06ff 06ff seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 0700 0700 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 19 TR04:06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 4 typ_rand c WRITE_OUTER_FRAME 0701 0701 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0702 0x0702 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 26 TR04:06 typ_alu_func 0 PASS_A typ_frame 4 0702 0702 fiu_mem_start 11 start_tag_query; Flow C 0x6e6 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 06e6 0x06e6 seq_en_micro 0 typ_a_adr 26 TR04:06 typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 0703 0703 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_frame 4 0704 0704 seq_br_type 0 Branch False; Flow J cc=False 0x706 seq_branch_adr 0706 0x0706 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 26 TR04:06 typ_b_adr 25 TR04:05 typ_c_adr 05 TR04:1a typ_frame 4 val_c_adr 05 VR04:1a val_frame 4 0705 0705 seq_br_type 3 Unconditional Branch; Flow J 0x70b seq_branch_adr 070b 0x070b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 0706 0706 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0707 0707 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 0708 0708 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 3a TR04:1a typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR04:19 val_alu_func 0 PASS_A val_b_adr 3a VR04:1a val_frame 4 0709 0709 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 070a 070a seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 070b ; -------------------------------------------------------------------------------------- 070b ; Comes from: 070b ; 06f0 C from color 0x06d2 070b ; -------------------------------------------------------------------------------------- 070b 070b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 11 start_tag_query fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 26 TR04:06 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 070c 070c fiu_load_var 1 hold_var; Flow J cc=False 0x710 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0710 0x0710 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 14 ZEROS typ_c_adr 19 TR04:06 typ_frame 4 typ_rand c WRITE_OUTER_FRAME val_b_adr 29 VR04:09 val_frame 4 070d 070d seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 070e 070e fiu_mem_start 11 start_tag_query ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 26 TR04:06 typ_alu_func 0 PASS_A typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL 070f 070f seq_en_micro 0 0710 0710 fiu_tivi_src 3 tar_frame; Flow J cc=False 0x716 ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0716 0x0716 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 0711 0711 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_frame 4 0712 0712 ioc_fiubs 0 fiu ; Flow J cc=True 0x70b seq_br_type 1 Branch True seq_branch_adr 070b 0x070b seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 25 TR04:05 typ_b_adr 26 TR04:06 typ_c_adr 1b TR04:04 typ_c_source 0 FIU_BUS typ_frame 4 0713 0713 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 13 TR04:0c typ_c_source 0 FIU_BUS typ_frame 4 typ_rand c WRITE_OUTER_FRAME val_c_adr 13 VR04:0c val_frame 4 0714 0714 fiu_mem_start e start_physical_wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 24 TR04:04 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR04:0d typ_frame 4 typ_mar_cntl f LOAD_MAR_RESERVED 0715 0715 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 2c TR04:0c typ_frame 4 val_b_adr 2c VR04:0c val_frame 4 0716 0716 seq_br_type 8 Return True; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 26 TR04:06 typ_alu_func 0 PASS_A typ_frame 4 0717 0717 ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 0718 0718 fiu_len_fill_lit 7a zero-fill 0x3a; Flow C 0x2ab4 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 04 GP04 val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 3b VR04:1b val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 0719 0719 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 071a 071a seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 1 A_PLUS_B val_b_adr 3c VR04:1c val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 071b 071b fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 30 GP0f val_c_source 0 FIU_BUS 071c 071c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0f GP0f 071d 071d fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 05 TR04:1a typ_frame 4 val_c_adr 05 VR04:1a val_frame 4 071e 071e ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 071f 071f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 0e GP0e val_a_adr 14 ZEROS 0720 0720 seq_br_type 7 Unconditional Call; Flow C 0x707 seq_branch_adr 0707 0x0707 seq_en_micro 0 0721 0721 seq_br_type 3 Unconditional Branch; Flow J 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0722 ; -------------------------------------------------------------------------------------- 0722 ; Comes from: 0722 ; 069a C from color 0x0698 0722 ; 06a2 C from color 0x06a1 0722 ; 074e C from color 0x0203 0722 ; -------------------------------------------------------------------------------------- 0722 0722 fiu_mem_start 2 start-rd; Flow C 0x33c4 ioc_adrbs 2 typ ioc_random 13 set cpu running seq_br_type 7 Unconditional Call seq_branch_adr 33c4 0x33c4 seq_en_micro 0 typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0723 0723 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x727 seq_br_type 1 Branch True seq_branch_adr 0727 0x0727 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 21 TR02:01 typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 1c DEC_A val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 0724 0724 seq_b_timing 1 Latch Condition; Flow C cc=True 0x738 seq_br_type 5 Call True seq_branch_adr 0738 0x0738 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 0725 0725 seq_br_type 7 Unconditional Call; Flow C 0x72f seq_branch_adr 072f 0x072f seq_en_micro 0 0726 0726 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x734 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0734 0x0734 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0727 0727 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0728 0728 seq_b_timing 1 Latch Condition; Flow C cc=True 0x738 seq_br_type 5 Call True seq_branch_adr 0738 0x0738 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU 0729 0729 seq_br_type 7 Unconditional Call; Flow C 0x72f seq_branch_adr 072f 0x072f seq_en_micro 0 072a 072a fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x734 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0734 0x0734 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 072b ; -------------------------------------------------------------------------------------- 072b ; Comes from: 072b ; 0698 C False from color 0x0698 072b ; -------------------------------------------------------------------------------------- 072b 072b fiu_mem_start 2 start-rd; Flow C 0x33c4 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_random 14 clear cpu running ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 33c4 0x33c4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 072c 072c seq_b_timing 1 Latch Condition; Flow C cc=True 0x738 seq_br_type 5 Call True seq_branch_adr 0738 0x0738 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 072d 072d fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x734 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0734 0x0734 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 072e 072e fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x734 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0734 0x0734 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 072f ; -------------------------------------------------------------------------------------- 072f ; Comes from: 072f ; 0725 C from color 0x0000 072f ; 0729 C from color 0x0000 072f ; -------------------------------------------------------------------------------------- 072f 072f fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_offs_lit 19 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 25 TR08:05 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 0730 0730 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0731 0731 fiu_fill_mode_src 0 ; Flow J cc=True 0x733 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0733 0x0733 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 31 VR02:11 val_frame 2 0732 0732 ioc_tvbs 3 fiu+fiu; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 37 TR04:17 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 08 TR04:17 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 37 VR04:17 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 08 VR04:17 val_c_mux_sel 2 ALU val_frame 4 0733 0733 ioc_tvbs 3 fiu+fiu; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 38 TR04:18 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 07 TR04:18 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 38 VR04:18 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 07 VR04:18 val_c_mux_sel 2 ALU val_frame 4 0734 0734 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=True 0x736 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0736 0x0736 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_b_adr 23 VR02:03 val_frame 2 0735 0735 seq_b_timing 0 Early Condition; Flow J cc=True 0x736 ; Flow J cc=#0x0 0x0 seq_br_type b Case False seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0736 0736 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 0737 0737 seq_br_type 3 Unconditional Branch; Flow J 0x734 seq_branch_adr 0734 0x0734 seq_en_micro 0 0738 ; -------------------------------------------------------------------------------------- 0738 ; Comes from: 0738 ; 0724 C True from color 0x0000 0738 ; 0728 C True from color 0x0000 0738 ; 072c C True from color 0x0000 0738 ; -------------------------------------------------------------------------------------- 0738 0738 seq_br_type 7 Unconditional Call; Flow C 0x33ec seq_branch_adr 33ec 0x33ec seq_en_micro 0 seq_random 02 ? 0739 0739 seq_br_type a Unconditional Return; Flow R seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 073a 073a fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 28 VR06:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 073b 073b fiu_mem_start 3 start-wr; Flow J 0x74f seq_br_type 3 Unconditional Branch seq_branch_adr 074f 0x074f seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 28 VR08:08 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 8 073c 073c fiu_mem_start 5 start_rd_if_true; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR09:14 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 073d 073d ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 073e 073e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x749 seq_br_type 1 Branch True seq_branch_adr 0749 0x0749 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_frame 2 073f 073f seq_br_type 1 Branch True; Flow J cc=True 0x742 seq_branch_adr 0742 0x0742 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_alu_func 5 DEC_A_MINUS_B val_b_adr 26 VR05:06 val_frame 5 0740 0740 seq_b_timing 0 Early Condition; Flow J cc=True 0x749 seq_br_type 1 Branch True seq_branch_adr 0749 0x0749 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 0741 0741 fiu_mem_start 2 start-rd; Flow J 0x744 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0744 0x0744 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 6 A_MINUS_B val_b_adr 23 VR05:03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0742 0742 seq_b_timing 0 Early Condition; Flow J cc=False 0x749 seq_br_type 0 Branch False seq_branch_adr 0749 0x0749 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 0743 0743 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1 A_PLUS_B val_b_adr 23 VR05:03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0744 0744 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 2 0745 0745 fiu_load_var 1 hold_var; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0746 0746 ioc_load_wdr 0 ; Flow J 0x747 ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 075d 0x075d seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 0747 0747 seq_br_type 0 Branch False; Flow J cc=False 0x20d seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0748 0748 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x756 seq_br_type 8 Return True seq_branch_adr 0756 0x0756 seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0749 0749 seq_b_timing 1 Latch Condition; Flow C cc=False 0x756 seq_br_type 4 Call False seq_branch_adr 0756 0x0756 seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 074a 074a seq_br_type 2 Push (branch address); Flow J 0x74b seq_branch_adr 074d 0x074d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 13 LOOP_REG val_alu_func 0 PASS_A 074b 074b fiu_load_tar 1 hold_tar; Flow J cc=True 0x33c0 fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_random a clear slice event seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 33c0 0x33c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_b_adr 32 TR07:12 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 074c 074c ioc_random c enable slice timer; Flow J 0x72e seq_br_type 3 Unconditional Branch seq_branch_adr 072e 0x072e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR02:00 typ_frame 2 074d 074d ioc_adrbs 3 seq ; Flow C 0x6c0 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 06c0 0x06c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 074e 074e seq_br_type 7 Unconditional Call; Flow C 0x722 seq_branch_adr 0722 0x0722 seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 074f 074f ioc_load_wdr 0 ; Flow J 0x750 ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 074a 0x074a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_b_adr 0f GP0f 0750 0750 seq_br_type 4 Call False; Flow C cc=False 0x20d seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1e A_AND_B typ_b_adr 04 GP04 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 10 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0751 0751 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x731 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0731 0x0731 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A 0752 0752 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x731 seq_br_type 0 Branch False seq_branch_adr 0731 0x0731 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 34 TR08:14 typ_frame 8 0753 0753 fiu_len_fill_lit 50 zero-fill 0x10 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP 0754 0754 fiu_mem_start 2 start-rd; Flow C 0x332f ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332f 0x332f seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0755 0755 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x731 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0731 0x0731 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 0756 ; -------------------------------------------------------------------------------------- 0756 ; Comes from: 0756 ; 0749 C False from color 0x0000 0756 ; -------------------------------------------------------------------------------------- 0756 0756 seq_br_type 7 Unconditional Call; Flow C 0x33af seq_branch_adr 33af 0x33af seq_en_micro 0 0757 0757 fiu_mem_start 2 start-rd; Flow C 0x7b4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 07b4 0x07b4 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 0758 0758 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0759 0759 ioc_tvbs 2 fiu+val; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 075a 0x075a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 075a 075a seq_en_micro 0 seq_random 06 Pop_stack+? 075b 075b fiu_load_tar 1 hold_tar; Flow J 0x75c fiu_tivi_src 8 type_var seq_br_type 2 Push (branch address) seq_branch_adr 0717 0x0717 seq_en_micro 0 typ_b_adr 32 TR07:12 typ_frame 7 075c 075c ioc_adrbs 3 seq ; Flow J 0x33c0 ioc_random a clear slice event seq_br_type 3 Unconditional Branch seq_branch_adr 33c0 0x33c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 075d 075d fiu_load_tar 1 hold_tar; Flow C 0x33c0 fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_random a clear slice event seq_br_type 7 Unconditional Call seq_branch_adr 33c0 0x33c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_b_adr 32 TR07:12 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL 075e 075e ioc_adrbs 3 seq ; Flow C 0x6c0 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 06c0 0x06c0 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 075f 075f seq_br_type 3 Unconditional Branch; Flow J 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0760 0760 seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0761 0761 seq_br_type 2 Push (branch address); Flow J 0x762 seq_branch_adr 074d 0x074d seq_en_micro 0 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0762 0762 seq_br_type 3 Unconditional Branch; Flow J 0x74b seq_branch_adr 074b 0x074b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 13 LOOP_REG val_alu_func 0 PASS_A 0763 0763 fiu_load_tar 1 hold_tar; Flow C 0x3681 fiu_tivi_src 8 type_var seq_br_type 7 Unconditional Call seq_branch_adr 3681 0x3681 seq_en_micro 0 typ_b_adr 3b TR12:1b typ_frame 12 0764 0764 seq_br_type 3 Unconditional Branch; Flow J 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 0765 0765 ioc_random c enable slice timer seq_en_micro 0 val_a_adr 36 VR13:16 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 13 0766 0766 seq_br_type 3 Unconditional Branch; Flow J 0x32d1 seq_branch_adr 32d1 0x32d1 seq_en_micro 0 val_a_adr 21 VR02:01 val_alu_func 19 X_XOR_B val_b_adr 0f GP0f val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0767 0767 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 02 ? typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 19 VR04:06 val_c_source 0 FIU_BUS val_frame 4 0768 0768 fiu_tivi_src c mar_0xc; Flow J cc=False 0x783 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0783 0x0783 seq_en_micro 0 typ_c_adr 1d TR04:02 typ_c_mux_sel 0 ALU typ_frame 4 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR04:05 val_c_mux_sel 2 ALU val_frame 4 0769 0769 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 02 ? typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 076a 076a fiu_tivi_src c mar_0xc; Flow J cc=False 0x783 ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0783 0x0783 seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR04:02 val_c_mux_sel 2 ALU val_frame 4 076b 076b seq_en_micro 0 val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 4 076c 076c ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 2e TR0d:0e typ_frame d val_c_adr 3c GP03 val_c_source 0 FIU_BUS 076d 076d seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 076e 076e seq_br_type 7 Unconditional Call; Flow C 0x1f1e seq_branch_adr 1f1e 0x1f1e seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 076f 076f seq_b_timing 0 Early Condition; Flow J cc=False 0x76d seq_br_type 0 Branch False seq_branch_adr 076d 0x076d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 0770 0770 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 11 TR0d:0e typ_c_source 0 FIU_BUS typ_frame d val_a_adr 22 VR04:02 val_frame 4 0771 0771 seq_en_micro 0 typ_a_adr 26 TR0d:06 typ_alu_func 0 PASS_A typ_c_adr 17 TR0d:08 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 27 VR0d:07 val_alu_func 0 PASS_A val_c_adr 17 VR0d:08 val_c_mux_sel 2 ALU val_frame d 0772 0772 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 2b TR0d:0b typ_alu_func 0 PASS_A typ_c_adr 10 TR0d:0f typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2b VR0d:0b val_alu_func 0 PASS_A val_c_adr 10 VR0d:0f val_c_mux_sel 2 ALU val_frame d 0773 0773 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0774 0774 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 3b TR02:1b typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 27 VR04:07 val_alu_func 0 PASS_A val_c_adr 18 VR04:07 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0775 0775 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 3b TR02:1b typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 28 VR04:08 val_alu_func 0 PASS_A val_c_adr 17 VR04:08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0776 0776 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0777 0777 fiu_tivi_src c mar_0xc; Flow J cc=False 0x783 ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0783 0x0783 seq_random 02 ? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 25 VR04:05 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR04:05 val_c_mux_sel 2 ALU val_frame 4 0778 0778 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 26 VR04:06 val_c_adr 19 VR04:06 val_c_mux_sel 2 ALU val_frame 4 0779 0779 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x77c seq_br_type 1 Branch True seq_branch_adr 077c 0x077c seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3b TR05:1b typ_frame 5 077a 077a fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA 077b 077b ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 077c 077c fiu_len_fill_lit 75 zero-fill 0x35; Flow C cc=False 0x211 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 1d TR04:02 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 10 TOP val_alu_func 0 PASS_A 077d 077d fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3e VR03:1e val_frame 3 077e 077e fiu_fill_mode_src 0 ; Flow J 0x77f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 0782 0x0782 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 077f 077f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x791 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0791 0x0791 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0780 0780 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_random 06 Pop_stack+? typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0781 0781 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 0782 0782 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0783 0783 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 0784 0784 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP 0785 0785 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0786 0786 <default> 0787 0787 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x78b fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 078b 0x078b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 02 ? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0788 0788 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 0789 0789 <default> 078a 078a ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 078b 078b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x78e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 078e 0x078e typ_a_adr 01 GP01 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 078c 078c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x78e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 078e 0x078e typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1a PASS_B 078d 078d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 078e 078e fiu_fill_mode_src 0 ; Flow J cc=False 0x791 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0791 0x0791 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 078f 078f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0790 0790 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0791 0791 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0792 0792 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0793 0793 fiu_load_var 1 hold_var; Flow J 0x790 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0790 0x0790 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0794 0794 typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_a_adr 2b VR04:0b val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 4 0795 0795 seq_random 02 ? typ_b_adr 1f TOP - 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 14 VR04:0b val_c_mux_sel 2 ALU val_frame 4 0796 0796 ioc_fiubs 2 typ typ_a_adr 2b TR04:0b typ_c_adr 14 TR04:0b typ_c_mux_sel 0 ALU typ_frame 4 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 0797 0797 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0798 0x0798 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 0798 0798 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0799 0799 seq_br_type 3 Unconditional Branch; Flow J 0x79b seq_branch_adr 079b 0x079b seq_en_micro 0 typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 3d VR02:1d val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 079a 079a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x7a2 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 07a2 0x07a2 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 14 ZEROS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_rand 2 DEC_LOOP_COUNTER 079b 079b seq_br_type 1 Branch True; Flow J cc=True 0x79a seq_branch_adr 079a 0x079a seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 13 LOOP_REG typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 26 VR06:06 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 079c 079c fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x79a fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 19 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 079a 0x079a seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 079d 079d fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x79e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 079c 0x079c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 25 TR08:05 typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 079e 079e fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 31 VR02:11 val_frame 2 079f 079f ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x7a1 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 07a1 0x07a1 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT 07a0 07a0 ioc_tvbs 3 fiu+fiu; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 37 TR04:17 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 08 TR04:17 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 37 VR04:17 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 08 VR04:17 val_c_mux_sel 2 ALU val_frame 4 07a1 07a1 ioc_tvbs 3 fiu+fiu; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 38 TR04:18 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 07 TR04:18 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 38 VR04:18 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 07 VR04:18 val_c_mux_sel 2 ALU val_frame 4 07a2 07a2 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 07a3 07a3 fiu_load_var 1 hold_var; Flow C 0x7ab fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 07ab 0x07ab seq_en_micro 0 typ_a_adr 37 TR04:17 typ_frame 4 val_a_adr 24 VR05:04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 07a4 07a4 fiu_load_var 1 hold_var; Flow C cc=True 0x7ab fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 07ab 0x07ab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2d TR05:0d typ_frame 5 val_alu_func 1a PASS_B val_b_adr 37 VR04:17 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 07a5 07a5 fiu_load_var 1 hold_var; Flow C cc=True 0x7ab fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 07ab 0x07ab seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 38 TR04:18 typ_alu_func 0 PASS_A typ_frame 4 val_alu_func 1a PASS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 07a6 07a6 fiu_load_var 1 hold_var; Flow C cc=True 0x7ab fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 07ab 0x07ab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_frame 6 val_alu_func 1a PASS_B val_b_adr 38 VR04:18 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 07a7 07a7 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 08 TR04:17 typ_c_source 0 FIU_BUS typ_frame 4 val_a_adr 14 ZEROS val_c_adr 08 VR04:17 val_c_source 0 FIU_BUS val_frame 4 07a8 07a8 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3e VR05:1e val_frame 5 07a9 07a9 fiu_fill_mode_src 0 ; Flow C 0x7b1 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_br_type 7 Unconditional Call seq_branch_adr 07b1 0x07b1 seq_en_micro 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 07aa 07aa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 07 TR04:18 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_c_adr 07 VR04:18 val_c_source 0 FIU_BUS val_frame 4 07ab ; -------------------------------------------------------------------------------------- 07ab ; Comes from: 07ab ; 07a3 C from color 0x07a3 07ab ; 07a4 C True from color 0x07a3 07ab ; 07a5 C True from color 0x07a3 07ab ; 07a6 C True from color 0x07a3 07ab ; -------------------------------------------------------------------------------------- 07ab 07ab fiu_len_fill_lit 4f zero-fill 0xf; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 07ac 0x07ac seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 07ac 07ac seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR11:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 07ad 07ad fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 01 GP01 07ae 07ae fiu_fill_mode_src 0 ; Flow C cc=True 0x7b1 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 07b1 0x07b1 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 val_rand 2 DEC_LOOP_COUNTER 07af 07af fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 07b0 07b0 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x7ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 07ab 0x07ab seq_en_micro 0 val_a_adr 03 GP03 val_b_adr 39 VR02:19 val_frame 2 07b1 ; -------------------------------------------------------------------------------------- 07b1 ; Comes from: 07b1 ; 07a9 C from color 0x07a3 07b1 ; 07ae C True from color 0x07ab 07b1 ; -------------------------------------------------------------------------------------- 07b1 07b1 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 07b2 07b2 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 07b3 07b3 seq_br_type 8 Return True; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 24 VR05:04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 07b4 ; -------------------------------------------------------------------------------------- 07b4 ; Comes from: 07b4 ; 0693 C from color 0x0693 07b4 ; 06b4 C from color 0x0000 07b4 ; 06bd C from color 0x062d 07b4 ; 06e9 C from color 0x06d2 07b4 ; 0757 C from color 0x0203 07b4 ; -------------------------------------------------------------------------------------- 07b4 07b4 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 07b5 07b5 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 07b6 ; -------------------------------------------------------------------------------------- 07b6 ; Comes from: 07b6 ; 05ad C from color 0x05a7 07b6 ; 06d5 C from color 0x06d2 07b6 ; 364e C from color 0x364d 07b6 ; 3b9d C from color 0x0bab 07b6 ; -------------------------------------------------------------------------------------- 07b6 07b6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x7b5 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_random d disable slice timer ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 07b5 0x07b5 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 3f TR02:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 07b7 07b7 seq_en_micro 0 seq_random 06 Pop_stack+? typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS 07b8 07b8 fiu_load_var 1 hold_var; Flow C 0x210 fiu_mem_start 2 start-rd fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_random 15 ? typ_a_adr 20 TR02:00 typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 16 CSA/VAL_BUS 07b9 07b9 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 65 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 21 TR02:01 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 33 GP0c val_c_source 0 FIU_BUS 07ba 07ba fiu_load_mdr 1 hold_mdr; Flow J cc=False 0x7dd fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 07dd 0x07dd seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 21 VR02:01 val_c_adr 34 GP0b val_frame 2 07bb 07bb seq_en_micro 0 typ_c_adr 32 GP0d val_c_adr 32 GP0d 07bc 07bc fiu_len_fill_lit 6f zero-fill 0x2f; Flow J cc=False 0x7bf fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 07bf 0x07bf seq_cond_sel 53 SEQ.E_MACRO_EVENT~5 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0c GP0c 07bd 07bd fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x3681 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3681 0x3681 seq_en_micro 0 val_a_adr 0c GP0c val_b_adr 3c VR12:1c val_frame 12 07be 07be fiu_mem_start 3 start-wr seq_en_micro 0 07bf 07bf fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_source 0 FIU_BUS 07c0 07c0 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 0e GP0e val_b_adr 0e GP0e 07c1 07c1 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 4 SAVE OFFSET seq_random 06 Pop_stack+? typ_a_adr 2b TR06:0b typ_alu_func 0 PASS_A typ_b_adr 0f GP0f typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 07c2 07c2 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 0e GP0e typ_b_adr 0d GP0d typ_c_adr 33 GP0c typ_c_lit 2 typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0d GP0d 07c3 07c3 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 0e GP0e typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 22 VR02:02 val_frame 2 07c4 07c4 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_mar_cntl 6 INCREMENT_MAR 07c5 07c5 fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 07c6 07c6 fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 07c7 07c7 fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 07c8 07c8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 04 GP04 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 07c9 07c9 fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 05 GP05 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 05 GP05 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 07ca 07ca fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 06 GP06 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 06 GP06 07cb 07cb fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 07 GP07 07cc 07cc fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 08 GP08 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 08 GP08 07cd 07cd fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 09 GP09 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 09 GP09 07ce 07ce fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x7d0 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 07d0 0x07d0 seq_cond_sel 43 SEQ.loop_counter_zero seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 1 seq_random 5b ? typ_a_adr 0c GP0c typ_mar_cntl 6 INCREMENT_MAR 07cf 07cf fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3b fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 07d0 07d0 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=False 0x7d2 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 07d2 0x07d2 seq_cond_sel 43 SEQ.loop_counter_zero seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_b_adr 21 VR0d:01 val_frame d 07d1 07d1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 07d2 07d2 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 0a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 17 LOOP_COUNTER val_b_adr 20 VR0d:00 val_frame d 07d3 07d3 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0b GP0b val_b_adr 22 VR0d:02 val_frame d 07d4 07d4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_random 06 Pop_stack+? typ_mar_cntl 6 INCREMENT_MAR val_b_adr 23 VR0d:03 val_frame d 07d5 07d5 fiu_len_fill_lit 2f sign-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 23 TR02:03 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 23 VR02:03 val_frame 2 07d6 07d6 fiu_len_fill_lit 2f sign-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 24 TR02:04 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 24 VR02:04 val_frame 2 07d7 07d7 fiu_len_fill_lit 2f sign-fill 0x2f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0d GP0d typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0d GP0d 07d8 07d8 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 0b GP0b 07d9 07d9 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_mem_start 3 start-wr fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 34 TR12:14 typ_alu_func 0 PASS_A typ_b_adr 0f GP0f typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 07da 07da fiu_mem_start a start_continue_if_false; Flow J cc=True 0x7dc ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 07dc 0x07dc seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 14 BOT - 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 07db 07db fiu_mem_start a start_continue_if_false; Flow J cc=False 0x7db ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 07db 0x07db seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 15 BOT typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR val_b_adr 15 BOT val_rand 2 DEC_LOOP_COUNTER 07dc 07dc seq_br_type a Unconditional Return; Flow R seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 07dd 07dd seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? val_b_adr 39 VR02:19 val_frame 2 07de 07de fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07df 07df fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e0 07e0 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e1 07e1 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e2 07e2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 07e3 07e3 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e4 07e4 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e5 07e5 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? 07e6 07e6 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION 07e7 07e7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x7bc fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 07bc 0x07bc seq_en_micro 0 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 07e8 07e8 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 07e9 07e9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x7e8 fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 07e8 0x07e8 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_a_adr 3a TR12:1a typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 31 GP0e val_c_source 0 FIU_BUS 07ea 07ea fiu_mem_start a start_continue_if_false; Flow J cc=False 0x7ed seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 07ed 0x07ed seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 30 TR03:10 typ_frame 3 typ_mar_cntl 6 INCREMENT_MAR 07eb 07eb ioc_adrbs 2 typ ; Flow C 0x3ba5 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3ba5 0x3ba5 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 07ec 07ec fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x80f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 080f 0x080f seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3a TR12:1a typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 31 GP0e val_c_source 0 FIU_BUS 07ed 07ed fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 07ee 07ee fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 2b TR06:0b typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_c_adr 30 GP0f typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 07ef 07ef fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 25 TR02:05 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_b_adr 38 VR02:18 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 07f0 07f0 fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_mar_cntl 6 INCREMENT_MAR 07f1 07f1 fiu_len_fill_lit 5a zero-fill 0x1a fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 3f Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 07f2 07f2 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 07f3 07f3 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 07f4 07f4 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 07f5 07f5 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 07f6 07f6 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 07f7 07f7 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 07f8 07f8 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 07f9 07f9 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 07fa 07fa fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 07fb 07fb fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 55 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 07fc 07fc fiu_len_fill_lit 4a zero-fill 0xa fiu_mem_start 4 continue fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 46 ? typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 32 GP0d val_c_source 0 FIU_BUS 07fd 07fd fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR0d:01 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR0d:01 val_c_mux_sel 2 ALU val_frame d 07fe 07fe fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 07ff 07ff fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 4 continue fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR0d:02 val_c_mux_sel 2 ALU val_frame d 0800 0800 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 31 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0d:03 val_c_mux_sel 2 ALU val_frame d 0801 0801 ioc_adrbs 1 val ; Flow J cc=True 0x802 ; Flow J cc=#0x0 0x802 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0802 0x0802 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_lex_adr 2 seq_random 14 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0802 0802 fiu_mem_start 2 start-rd; Flow J 0x806 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0806 0x0806 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 1c VR02:03 val_frame 2 0803 0803 fiu_mem_start 2 start-rd; Flow J 0x806 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0806 0x0806 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 0b ? typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 1c VR02:03 val_frame 2 0804 0804 fiu_mem_start 2 start-rd; Flow J 0x806 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0806 0x0806 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 0b ? typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 1c VR02:03 val_frame 2 0805 0805 seq_br_type 3 Unconditional Branch; Flow J 0x804 seq_branch_adr 0804 0x0804 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 0b ? 0806 0806 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 seq_random 07 Push_stack+? typ_a_adr 22 TR02:02 typ_b_adr 21 TR02:01 typ_c_adr 1b TR02:04 typ_frame 2 val_b_adr 25 VR02:05 val_c_adr 1b VR02:04 val_frame 2 0807 0807 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 2 seq_random 53 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2a VR11:0a val_alu_func 0 PASS_A val_b_adr 0e GP0e val_frame 11 val_rand a PASS_B_HIGH 0808 0808 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x80c ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 080c 0x080c seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 0f Load_control_top+? typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 0e GP0e 0809 0809 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x80b ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 080b 0x080b seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2b BOT - 1 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2b BOT - 1 val_c_mux_sel 2 ALU 080a 080a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x80a ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 080a 0x080a seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 080b 080b fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x80d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 080d 0x080d seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 080c 080c fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x80d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 080d 0x080d seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 07 Push_stack+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2b BOT - 1 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2b BOT - 1 val_c_mux_sel 2 ALU 080d 080d fiu_len_fill_lit 59 zero-fill 0x19 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 0a fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 10 Load_break_mask+? typ_a_adr 0d GP0d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0e GP0e val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 080e 080e fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x2ab4 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 1 ALU >> 16 080f ; -------------------------------------------------------------------------------------- 080f ; Comes from: 080f ; 07ec C from color 0x07e8 080f ; -------------------------------------------------------------------------------------- 080f 080f fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0810 0810 seq_en_micro 0 0811 0811 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x816 seq_br_type 1 Branch True seq_branch_adr 0816 0x0816 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0812 0812 fiu_mem_start 3 start-wr; Flow C 0x3683 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3683 0x3683 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 0813 0813 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl b LOAD_MAR_DATA 0814 0814 fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0815 0815 fiu_tivi_src 4 fiu_var; Flow R cc=True ; Flow J cc=False 0x211 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 8 Return True seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 01 GP01 val_b_adr 39 VR03:19 val_frame 3 0816 0816 fiu_mem_start 5 start_rd_if_true; Flow R cc=False ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 0817 0x0817 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 0f GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_frame 3 0817 0817 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0818 0x0818 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0818 0818 fiu_tivi_src 2 tar_fiu; Flow J 0x812 ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0812 0x0812 seq_en_micro 0 typ_a_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_frame 3 0819 0819 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_c_adr 34 GP0b val_c_source 0 FIU_BUS 081a 081a fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 16 stage data register ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_a_adr 0b GP0b val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 081b 081b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x20b fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 020b 0x020b seq_cond_sel 7d IOC.IOC_XFER.PERR~ seq_en_micro 0 typ_b_adr 0b GP0b typ_c_adr 34 GP0b val_b_adr 0b GP0b 081c 081c fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 34 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 081d 081d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x81e ; Flow J cc=#0x0 0x81f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 081f 0x081f seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 25 TR00:05 val_a_adr 0b GP0b 081e 081e seq_br_type 7 Unconditional Call; Flow C 0x20c seq_branch_adr 020c 0x020c seq_en_micro 0 081f 081f seq_br_type 3 Unconditional Branch; Flow J 0x825 seq_branch_adr 0825 0x0825 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 19 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 19 0820 0820 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x846 fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0846 0x0846 seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0821 0821 fiu_len_fill_lit 57 zero-fill 0x17; Flow J 0x871 fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 0871 0x0871 seq_en_micro 0 0822 0822 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0x85d fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 085d 0x085d seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0823 0823 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x865 fiu_load_mdr 1 hold_mdr fiu_mem_start f start_physical_tag_rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0865 0x0865 seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0824 0824 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x86c fiu_load_mdr 1 hold_mdr fiu_mem_start d start_physical_rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 086c 0x086c seq_en_micro 0 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0825 0825 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x211 fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_c_adr 1e TR19:01 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_frame 3 0826 0826 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 3c TR03:1c typ_alu_func 7 INC_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 0 NO_OP val_c_adr 1e VR19:01 val_c_source 0 FIU_BUS val_frame 19 0827 0827 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x20c fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 4 Call False seq_branch_adr 020c 0x020c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 3f TR06:1f typ_alu_func 18 NOT_A_AND_B typ_b_adr 0b GP0b typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 20 VR02:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3d VR02:1d val_frame 2 0828 0828 fiu_len_fill_lit 7c zero-fill 0x3c fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 1c TR19:03 typ_c_mux_sel 0 ALU typ_frame 19 val_c_adr 1c VR19:03 val_c_source 0 FIU_BUS val_frame 19 0829 0829 fiu_len_fill_lit 42 zero-fill 0x2 fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 03 TR03:1c typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 34 GP0b val_c_source 0 FIU_BUS 082a 082a fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 72 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 1d TR19:02 typ_c_mux_sel 0 ALU typ_frame 19 val_a_adr 23 VR19:03 val_alu_func 6 A_MINUS_B val_b_adr 0b GP0b val_c_adr 1c VR19:03 val_c_mux_sel 2 ALU val_frame 19 082b 082b fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 2c TR08:0c typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 3 082c 082c seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR08:0b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_c_adr 1d VR19:02 val_c_mux_sel 2 ALU val_frame 19 082d 082d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x211 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 0a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 082e 082e fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x211 fiu_mem_start 4 continue fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 val_c_adr 3f GP00 082f 082f ioc_load_wdr 0 ; Flow J cc=True 0x830 ; Flow J cc=#0x0 0x830 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0830 0x0830 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0830 0830 fiu_vmux_sel 1 fill value; Flow J 0x834 ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0834 0x0834 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 23 VR19:03 val_c_adr 1d VR19:02 val_c_source 0 FIU_BUS val_frame 19 val_rand 3 CONDITION_TO_FIU 0831 0831 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 0832 0832 fiu_mem_start 11 start_tag_query; Flow J 0x836 ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0836 0x0836 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 23 VR19:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame 19 0833 0833 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 0834 0834 seq_en_micro 0 val_c_adr 1c VR19:03 val_c_mux_sel 2 ALU val_frame 19 0835 0835 ioc_fiubs 2 typ ; Flow J 0x83e seq_br_type 3 Unconditional Branch seq_branch_adr 083e 0x083e seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0836 0836 fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=True 0x834 fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0834 0x0834 seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 0837 0837 seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0838 0838 fiu_tivi_src 3 tar_frame; Flow C cc=False 0x211 ioc_adrbs 1 val ioc_random 1c read ioc memory and increment address ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 0839 0839 ioc_adrbs 1 val ; Flow C 0x2ab4 ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 03 GP03 val_alu_func 0 PASS_A 083a 083a fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 083b 083b fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 32 TR11:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 083c 083c fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x20b fiu_mem_start e start_physical_wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_br_type 4 Call False seq_branch_adr 020b 0x020b seq_cond_sel 7d IOC.IOC_XFER.PERR~ seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 083d 083d ioc_fiubs 2 typ ; Flow J cc=True 0x839 ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0839 0x0839 seq_en_micro 0 typ_a_adr 21 TR05:01 typ_b_adr 05 GP05 typ_frame 5 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 083e 083e seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 083f 083f fiu_mem_start 2 start-rd; Flow C 0x810 fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0810 0x0810 seq_en_micro 0 typ_a_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_frame 3 0840 0840 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 23 TR06:03 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0841 0841 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3743 seq_br_type 1 Branch True seq_branch_adr 3743 0x3743 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 3c VR02:1c val_alu_func 19 X_XOR_B val_b_adr 09 GP09 val_frame 2 0842 0842 seq_br_type 4 Call False; Flow C cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0843 0843 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3743 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3743 0x3743 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0844 0844 seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 3e VR04:1e val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0845 0845 fiu_mem_start 2 start-rd; Flow J 0x3743 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3743 0x3743 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0846 0846 fiu_load_oreg 1 hold_oreg fiu_mem_start 11 start_tag_query fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 04 GP04 typ_c_adr 3f GP00 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_frame 12 0847 0847 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x20c fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020c 0x020c seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_frame 3 0848 0848 fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x20c fiu_mem_start 13 start_available_query fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020c 0x020c seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 0849 0849 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x20c fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020c 0x020c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR10:01 typ_frame 10 084a 084a seq_br_type 7 Unconditional Call; Flow C 0x3525 seq_branch_adr 3525 0x3525 seq_en_micro 0 084b 084b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x211 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 084c 084c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 34 fiu_op_sel 3 insert seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 31 TR02:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 084d 084d fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 3a fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 04 GP04 typ_frame 6 084e 084e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 31 VR02:11 val_frame 2 084f 084f fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_random 1c read ioc memory and increment address ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 0850 0850 fiu_tivi_src 2 tar_fiu; Flow C 0x8a5 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 08a5 0x08a5 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 0851 0851 ioc_adrbs 1 val ; Flow C 0x2ab4 ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 03 GP03 val_alu_func 0 PASS_A 0852 0852 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 0853 0853 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0854 0854 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x20b fiu_mem_start e start_physical_wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_br_type 4 Call False seq_branch_adr 020b 0x020b seq_cond_sel 7d IOC.IOC_XFER.PERR~ seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0855 0855 ioc_load_wdr 0 ; Flow J cc=False 0x851 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0851 0x0851 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 0856 0856 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 0b GP0b val_a_adr 34 VR03:14 val_b_adr 16 CSA/VAL_BUS val_frame 3 val_rand c START_MULTIPLY 0857 0857 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 35 VR03:15 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 3 0858 0858 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_en_micro 0 val_a_adr 0b GP0b 0859 0859 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 32 VR02:12 val_frame 2 085a 085a fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_random 14 clear cpu running seq_en_micro 0 val_a_adr 14 ZEROS 085b 085b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 085c 085c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_random 4 write request fifo ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 085d 085d fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_rand e CHECK_CLASS_SYSTEM_B 085e 085e ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1e A_AND_B typ_b_adr 3a TR02:1a typ_frame 2 085f 085f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2ab4 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 13 LOOP_REG val_rand 1 INC_LOOP_COUNTER 0860 0860 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x85d fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 085d 0x085d seq_en_micro 0 typ_a_adr 0b GP0b 0861 0861 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert seq_en_micro 0 typ_c_adr 34 GP0b 0862 0862 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 34 VR03:14 val_b_adr 16 CSA/VAL_BUS val_frame 3 val_rand c START_MULTIPLY 0863 0863 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 21 TR10:01 typ_b_adr 0b GP0b typ_frame 10 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 35 VR03:15 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 3 0864 0864 fiu_tivi_src 4 fiu_var; Flow J 0x859 ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0859 0x0859 seq_en_micro 0 val_a_adr 0b GP0b val_c_adr 34 GP0b 0865 0865 fiu_mem_start 15 setup_tag_read fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0866 0866 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x868 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 8 typ+mem seq_br_type 3 Unconditional Branch seq_branch_adr 0868 0x0868 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 6 0867 0867 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x861 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs a fiu+mem seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0861 0x0861 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 6 0868 0868 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x867 fiu_load_tar 1 hold_tar fiu_mem_start 15 setup_tag_read fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0867 0x0867 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_rand d SET_PASS_PRIVACY_BIT 0869 0869 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 086a 086a fiu_mem_start f start_physical_tag_rd seq_en_micro 0 086b 086b fiu_mem_start 15 setup_tag_read; Flow J 0x867 seq_br_type 3 Unconditional Branch seq_branch_adr 0867 0x0867 seq_en_micro 0 086c 086c seq_br_type 3 Unconditional Branch; Flow J 0x86f seq_branch_adr 086f 0x086f seq_en_micro 0 086d 086d fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 7 INC_A typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 0 NO_OP val_a_adr 0b GP0b 086e 086e ioc_random 1e write ioc memory and increment address; Flow J cc=True 0x861 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0861 0x0861 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 086f 086f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ab4 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1e write ioc memory and increment address ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0870 0870 fiu_tivi_src c mar_0xc; Flow J 0x86d ioc_fiubs 0 fiu ioc_random 1e write ioc memory and increment address seq_br_type 3 Unconditional Branch seq_branch_adr 086d 0x086d seq_en_micro 0 typ_b_adr 0b GP0b typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_rand d SET_PASS_PRIVACY_BIT 0871 0871 fiu_len_fill_lit 57 zero-fill 0x17 fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_b_adr 32 TR02:12 typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_c_adr 0d VR03:12 val_c_mux_sel 2 ALU val_frame 3 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0872 0872 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20c seq_br_type 5 Call True seq_branch_adr 020c 0x020c seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_frame 3 0873 0873 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 0874 0874 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3e VR03:1e val_frame 3 0875 0875 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0876 0876 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0877 0877 fiu_mem_start 2 start-rd; Flow C 0x33c4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 33c4 0x33c4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 0878 0878 seq_b_timing 1 Latch Condition; Flow C cc=True 0x211 seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_en_micro 0 val_a_adr 3e VR03:1e val_alu_func 0 PASS_A val_c_adr 05 VR03:1a val_c_mux_sel 2 ALU val_frame 3 0879 0879 ioc_fiubs 1 val ; Flow C 0xb92 seq_br_type 7 Unconditional Call seq_branch_adr 0b92 0x0b92 seq_en_micro 0 typ_c_adr 1b TR1b:04 typ_c_mux_sel 0 ALU typ_frame 1b typ_rand c WRITE_OUTER_FRAME val_c_adr 1b VR1b:04 val_c_mux_sel 2 ALU val_frame 1b val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 087a 087a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 087b 087b fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP 087c 087c ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 087d 087d typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 19 087e 087e typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1e VR19:01 val_c_mux_sel 2 ALU val_frame 19 087f 087f typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR19:02 val_c_mux_sel 2 ALU val_frame 19 0880 0880 typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1c VR19:03 val_c_mux_sel 2 ALU val_frame 19 0881 0881 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0882 0882 fiu_mem_start 2 start-rd; Flow J 0x3743 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3743 0x3743 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 23 TR06:03 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 0883 0883 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x211 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 14 ZEROS typ_b_adr 1e TOP - 2 typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 20 VR06:00 val_frame 6 0884 0884 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x888 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0888 0x0888 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1d TOP - 3 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0885 0885 fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 0886 0886 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x88c fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 088c 0x088c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 val_alu_func 1 A_PLUS_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0887 0887 fiu_fill_mode_src 0 ; Flow J 0x88e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 088e 0x088e val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0888 0888 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ val_a_adr 1d TOP - 3 val_alu_func 1 A_PLUS_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0889 0889 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 088a 088a fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 088b 088b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x88e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 088e 0x088e val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 088c 088c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 088d 088d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x88e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 088e 0x088e val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 24 VR05:04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 088e 088e fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x211 fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 33 VR03:13 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 3 088f 088f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x211 seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR05:01 val_frame 5 0890 0890 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 34 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 3e TR03:1e typ_alu_func 7 INC_A typ_c_adr 01 TR03:1e typ_c_mux_sel 0 ALU typ_frame 3 0891 0891 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_b_adr 1e TOP - 2 typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 03 GP03 0892 0892 fiu_len_fill_lit 4a zero-fill 0xa; Flow C cc=True 0x211 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand 1 INC_LOOP_COUNTER val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3b VR05:1b val_frame 5 0893 0893 ioc_load_wdr 0 ; Flow J cc=True 0x89c ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 089c 0x089c typ_a_adr 3c TR03:1c typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 0 NO_OP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0894 0894 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0895 0895 fiu_len_fill_lit 4c zero-fill 0xc; Flow C cc=False 0x211 fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_en_micro 0 val_a_adr 04 GP04 val_b_adr 34 VR03:14 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 3 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 0896 0896 fiu_mem_start d start_physical_rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 36 VR03:16 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 3 0897 0897 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_en_micro 0 val_a_adr 05 GP05 0898 0898 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ab4 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1e write ioc memory and increment address ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 0899 0899 ioc_random 1e write ioc memory and increment address seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_b_adr 06 GP06 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 3d VR02:1d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 089a 089a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 0 NO_OP val_a_adr 06 GP06 089b 089b ioc_random 1e write ioc memory and increment address; Flow J cc=True 0x898 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0898 0x0898 seq_en_micro 0 089c 089c fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 3f TR06:1f typ_alu_func 18 NOT_A_AND_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_b_adr 34 VR03:14 val_c_adr 3f GP00 val_frame 3 val_rand c START_MULTIPLY 089d 089d seq_en_micro 0 typ_c_adr 3f GP00 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 35 VR03:15 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 3 089e 089e fiu_mem_start 2 start-rd; Flow C 0x810 fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0810 0x0810 seq_en_micro 0 typ_a_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR03:11 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_frame 3 089f 089f fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_random 1 load transfer address ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 03 TR03:1c typ_c_mux_sel 0 ALU typ_frame 3 val_a_adr 05 GP05 08a0 08a0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_random 1e write ioc memory and increment address seq_en_micro 0 08a1 08a1 ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 08a2 08a2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 08a3 08a3 ioc_random 1e write ioc memory and increment address ioc_tvbs 2 fiu+val seq_en_micro 0 08a4 08a4 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_random 4 write request fifo ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 08a5 ; -------------------------------------------------------------------------------------- 08a5 ; Comes from: 08a5 ; 0850 C from color 0x0820 08a5 ; -------------------------------------------------------------------------------------- 08a5 08a5 fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_vmux_sel 1 fill value ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 08a6 08a6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 08a7 08a7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x34fd fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_br_type 7 Unconditional Call seq_branch_adr 34fd 0x34fd seq_en_micro 0 08a8 08a8 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 08 GP08 val_b_adr 08 GP08 08a9 08a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 09 GP09 08aa 08aa fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 20 TR08:00 typ_frame 8 typ_mar_cntl 5 RESTORE_MAR_REFRESH val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_b_adr 30 VR02:10 val_frame 2 08ab 08ab fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc seq_en_micro 0 val_a_adr 3a VR08:1a val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 08ac 08ac seq_en_micro 0 val_alu_func 6 A_MINUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 08ad 08ad fiu_len_fill_lit 6f zero-fill 0x2f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3f VR02:1f val_frame 2 08ae 08ae fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 33 TR09:13 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 9 typ_rand c WRITE_OUTER_FRAME 08af 08af fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl 5 RESTORE_MAR_REFRESH val_c_adr 13 VR0d:0c val_c_mux_sel 2 ALU val_frame d 08b0 08b0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 12 VR0d:0d val_c_source 0 FIU_BUS val_frame d 08b1 08b1 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 2d VR0d:0d val_alu_func 7 INC_A val_c_adr 12 VR0d:0d val_c_mux_sel 2 ALU val_frame d 08b2 08b2 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3e GP01 val_c_mux_sel 2 ALU 08b3 08b3 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_mux_sel 2 ALU 08b4 08b4 seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 08b5 08b5 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 3 LEFT_I_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 08b6 08b6 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 04 GP04 08b7 08b7 seq_br_type 0 Branch False; Flow J cc=False 0x8c4 seq_branch_adr 08c4 0x08c4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 08b8 08b8 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR09:1d val_frame 9 08b9 08b9 fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3e TR12:1e typ_frame 12 08ba 08ba fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR11:1d val_frame 11 08bb 08bb fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3a TR05:1a typ_frame 5 08bc 08bc fiu_mem_start f start_physical_tag_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR09:1d val_frame 9 08bd 08bd fiu_mem_start 15 setup_tag_read ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 04 GP04 08be 08be fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x20d fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val ioc_tvbs a fiu+mem seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 2c VR0d:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 08bf 08bf fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 20 TR08:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_c_adr 13 VR0d:0c val_c_source 0 FIU_BUS val_frame d 08c0 08c0 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 08c1 08c1 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x8c0 fiu_tivi_src c mar_0xc seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 08c0 0x08c0 seq_en_micro 0 08c2 08c2 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 08c3 08c3 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 08c4 08c4 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x8b5 fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 08b5 0x08b5 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 29 VR08:09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 08c5 08c5 seq_br_type 7 Unconditional Call; Flow C 0x8e6 seq_branch_adr 08e6 0x08e6 seq_en_micro 0 08c6 08c6 fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 24 TR08:04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_b_adr 2c VR0d:0c val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame d 08c7 08c7 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 0c fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 08c8 08c8 seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 08c9 08c9 fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 3 LEFT_I_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 08ca 08ca fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 12 TR0d:0d typ_c_source 0 FIU_BUS typ_frame d 08cb 08cb seq_br_type 0 Branch False; Flow J cc=False 0x8d9 seq_branch_adr 08d9 0x08d9 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 08cc 08cc fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR09:1d val_frame 9 08cd 08cd fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3e TR12:1e typ_frame 12 08ce 08ce fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR11:1d val_frame 11 08cf 08cf fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3a TR05:1a typ_frame 5 08d0 08d0 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR09:1d val_frame 9 08d1 08d1 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 08d2 08d2 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x20d seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2c VR0d:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 08d3 08d3 fiu_mem_start e start_physical_wr fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 20 TR08:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 2c VR0d:0c val_alu_func 1a PASS_B val_b_adr 02 GP02 val_frame d 08d4 08d4 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 08d5 08d5 fiu_mem_start e start_physical_wr; Flow J cc=True 0x8d4 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 08d4 0x08d4 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 08d6 08d6 fiu_mem_start 18 acknowledge_refresh; Flow J cc=False 0x8d3 fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 08d3 0x08d3 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 39 VR08:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 08d7 08d7 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 08d8 08d8 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 08d9 08d9 fiu_mem_start 18 acknowledge_refresh; Flow J cc=True 0x8c9 fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 08c9 0x08c9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 29 VR08:09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 08da 08da seq_br_type 7 Unconditional Call; Flow C 0x8e6 seq_branch_adr 08e6 0x08e6 seq_en_micro 0 08db 08db fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 2c VR0d:0c val_frame d 08dc 08dc fiu_len_fill_lit 7d zero-fill 0x3d fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 11 VR0d:0e val_c_source 0 FIU_BUS val_frame d 08dd 08dd seq_en_micro 0 val_a_adr 23 VR08:03 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 8 08de 08de fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_frame d val_a_adr 33 VR05:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 08df 08df fiu_mem_start 13 start_available_query ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 08e0 08e0 seq_en_micro 0 08e1 08e1 fiu_mem_start f start_physical_tag_rd; Flow C 0x352c fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 352c 0x352c seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 08e2 08e2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_en_micro 0 08e3 08e3 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 74 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 04 GP04 08e4 08e4 ioc_load_wdr 0 ; Flow J cc=False 0x8df ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 08df 0x08df seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 08e5 08e5 seq_br_type 3 Unconditional Branch; Flow J 0x8f6 seq_branch_adr 08f6 0x08f6 seq_en_micro 0 08e6 ; -------------------------------------------------------------------------------------- 08e6 ; Comes from: 08e6 ; 08c5 C from color 0x0127 08e6 ; 08da C from color 0x0127 08e6 ; -------------------------------------------------------------------------------------- 08e6 08e6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 08e7 08e7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 08e8 08e8 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 08e9 08e9 fiu_len_fill_lit 43 zero-fill 0x3 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 08ea 08ea seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8ec seq_br_type 1 Branch True seq_branch_adr 08ec 0x08ec seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 08eb 08eb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 08ec 08ec fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 04 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 08ed 08ed seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8ef seq_br_type 1 Branch True seq_branch_adr 08ef 0x08ef seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 08ee 08ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 08ef 08ef fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 08f0 08f0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8f2 seq_br_type 1 Branch True seq_branch_adr 08f2 0x08f2 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 08f1 08f1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 08f2 08f2 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 08f3 08f3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x8f5 seq_br_type 1 Branch True seq_branch_adr 08f5 0x08f5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 08f4 08f4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 08f5 08f5 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 08f6 08f6 fiu_mem_start 18 acknowledge_refresh; Flow C 0x367b fiu_tivi_src c mar_0xc ioc_random 1 load transfer address seq_br_type 7 Unconditional Call seq_branch_adr 367b 0x367b seq_en_micro 0 seq_random 0a ? typ_b_adr 33 TR02:13 typ_frame 2 08f7 08f7 ioc_random 1c read ioc memory and increment address seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? val_b_adr 30 VR02:10 val_frame 2 08f8 08f8 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 08f9 08f9 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 seq_random 55 ? typ_c_adr 0c TR03:13 typ_c_source 0 FIU_BUS typ_frame 3 val_c_adr 0c VR03:13 val_c_source 0 FIU_BUS val_frame 3 08fa 08fa fiu_mem_start 13 start_available_query ioc_adrbs 2 typ ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR05:00 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 38 VR05:18 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 08fb 08fb seq_en_micro 0 08fc 08fc fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3a VR11:1a val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 11 08fd 08fd fiu_mem_start 17 scavenger_write; Flow J cc=False 0x8fc fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 08fc 0x08fc seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_b_adr 22 VR07:02 val_frame 7 val_rand 2 DEC_LOOP_COUNTER 08fe 08fe fiu_mem_start f start_physical_tag_rd; Flow J cc=False 0x8fb ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 08fb 0x08fb seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 38 VR05:18 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 08ff 08ff fiu_tivi_src 8 type_var; Flow C 0x2ab4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 typ_b_adr 33 TR09:13 typ_frame 9 typ_mar_cntl 4 RESTORE_MAR 0900 0900 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_c_adr 0b VR03:14 val_c_source 0 FIU_BUS val_frame 3 0901 0901 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_en_micro 0 val_c_adr 0a VR03:15 val_c_source 0 FIU_BUS val_frame 3 0902 0902 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_random 1c read ioc memory and increment address ioc_tvbs 4 ioc+ioc seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 09 VR03:16 val_c_source 0 FIU_BUS val_frame 3 0903 0903 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0xb53 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0b53 0x0b53 typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 0904 0904 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0905 0905 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_b_adr 1f TOP - 1 0906 0906 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 0 fiu typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0907 0907 ioc_fiubs 1 val ; Flow C cc=False 0x32dc ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 2f VR12:0f val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 12 0908 0908 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 0909 0909 ioc_fiubs 0 fiu typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 090a 090a fiu_mem_start 2 start-rd; Flow C 0x329e ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 090b 090b typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 090c 090c fiu_mem_start 8 start_wr_if_false; Flow C 0x32d7 ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame f typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 090d 090d seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 090e 090e fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x90b ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 090b 0x090b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 090f 090f fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 03 GP03 val_rand a PASS_B_HIGH 0910 0910 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_random 0f Load_control_top+? typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_csa_cntl 1 START_POP_DOWN typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0911 0911 fiu_mem_start 3 start-wr; Flow C 0x332e ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl a LOAD_MAR_IMPORT typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 04 GP04 0912 0912 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0913 0913 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0914 0914 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0915 0915 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x916 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 32de 0x32de typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_c_adr 37 GP08 val_c_mux_sel 2 ALU 0916 0916 fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=False ; Flow J cc=True 0x3971 fiu_offs_lit 45 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 3971 0x3971 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 0917 0917 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0918 0918 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0919 0919 ioc_adrbs 1 val ; Flow C 0x34cd seq_br_type 7 Unconditional Call seq_branch_adr 34cd 0x34cd typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 091a 091a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x91e fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 091e 0x091e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 20 TR08:00 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 091b 091b <default> 091c 091c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 091d 091d ioc_load_wdr 0 ; Flow J 0x94d ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 094d 0x094d 091e 091e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 091f 091f <halt> ; Flow R 0920 ; -------------------------------------------------------------------------------------- 0920 ; 0x020d Execute Module,Elaborate 0920 ; -------------------------------------------------------------------------------------- 0920 MACRO_Execute_Module,Elaborate: 0920 0920 dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0920 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0921 0921 fiu_mem_start 4 continue; Flow C cc=True 0x32db ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR 0922 0922 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0923 0923 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32db fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0924 0924 fiu_mem_start 3 start-wr; Flow C cc=True 0x32db ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0925 0925 ioc_load_wdr 0 seq_random 02 ? typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 0926 0926 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0927 0927 <halt> ; Flow R 0928 ; -------------------------------------------------------------------------------------- 0928 ; 0x0206 Execute Module,Check_Elaborated 0928 ; -------------------------------------------------------------------------------------- 0928 MACRO_Execute_Module,Check_Elaborated: 0928 0928 dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0928 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1d typ_mar_cntl d LOAD_MAR_TYPE 0929 0929 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 092a 0x092a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 092a 092a fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32a9 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 092b 092b fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 092c 092c fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 092d 092d ioc_load_wdr 0 ; Flow J 0x926 seq_br_type 3 Unconditional Branch seq_branch_adr 0926 0x0926 typ_b_adr 01 GP01 val_b_adr 01 GP01 092e ; -------------------------------------------------------------------------------------- 092e ; 0x020f Execute Module,Activate 092e ; -------------------------------------------------------------------------------------- 092e MACRO_Execute_Module,Activate: 092e 092e dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 092e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 092f 092f fiu_tivi_src c mar_0xc; Flow C cc=False 0x32a9 ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 0930 0930 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 0931 0931 seq_br_type 7 Unconditional Call; Flow C 0x3971 seq_branch_adr 3971 0x3971 seq_random 02 ? typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA 0932 ; -------------------------------------------------------------------------------------- 0932 ; 0x020e Execute Module,Augment_Imports 0932 ; -------------------------------------------------------------------------------------- 0932 MACRO_Execute_Module,Augment_Imports: 0932 0932 dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0932 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0933 0933 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32db fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0934 0934 fiu_mem_start 4 continue ioc_fiubs 0 fiu typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 0935 0935 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x936 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 093a 0x093a typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0936 0936 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=False 0x943 fiu_load_tar 1 hold_tar fiu_offs_lit 2c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0943 0x0943 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0937 0937 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32db fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 16 CSA/VAL_BUS typ_frame 2 0938 0938 fiu_mem_start 6 start_rd_if_false; Flow C cc=False 0x948 ioc_adrbs 3 seq seq_br_type 4 Call False seq_branch_adr 0948 0x0948 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 0939 0939 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32db fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 093a 093a ioc_fiubs 1 val ; Flow C cc=True 0x32dc seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dc 0x32dc seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 1f TOP - 1 val_alu_func 1d A_AND_NOT_B val_b_adr 3a VR05:1a val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 093b 093b fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x940 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0940 0x0940 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 093c 093c typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 093d 093d fiu_mem_start 3 start-wr; Flow J cc=True 0x949 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0949 0x0949 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame f typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 093e 093e seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 093f 093f fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x93c ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 093c 0x093c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 0940 0940 ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_csa_cntl 1 START_POP_DOWN val_alu_func 1 A_PLUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0941 0941 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl d LOAD_MAR_TYPE 0942 0942 ioc_load_wdr 0 ; Flow J 0x926 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0926 0x0926 val_b_adr 01 GP01 0943 0943 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32db fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 16 CSA/VAL_BUS typ_frame 2 0944 0944 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32db fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0945 0945 fiu_mem_start 6 start_rd_if_false; Flow C cc=False 0x948 ioc_adrbs 3 seq seq_br_type 4 Call False seq_branch_adr 0948 0x0948 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 0946 0946 fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0xb53 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0b53 0x0b53 typ_a_adr 10 TOP 0947 0947 fiu_tivi_src c mar_0xc; Flow J 0x3339 ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3339 0x3339 typ_a_adr 21 TR10:01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 10 typ_rand c WRITE_OUTER_FRAME val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0948 ; -------------------------------------------------------------------------------------- 0948 ; Comes from: 0948 ; 0938 C False from color 0x0921 0948 ; 0945 C False from color 0x0921 0948 ; -------------------------------------------------------------------------------------- 0948 0948 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 0949 0949 fiu_mem_start 3 start-wr; Flow C 0x332e ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 094a 094a seq_br_type 3 Unconditional Branch; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 094b 094b <halt> ; Flow R 094c ; -------------------------------------------------------------------------------------- 094c ; 0x0209 Execute Task,Abort 094c ; -------------------------------------------------------------------------------------- 094c MACRO_Execute_Task,Abort: 094c 094c dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 094c typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 36 GP09 val_c_mux_sel 2 ALU 094d 094d seq_br_type 7 Unconditional Call; Flow C 0x3a6e seq_branch_adr 3a6e 0x3a6e val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 094e ; -------------------------------------------------------------------------------------- 094e ; 0x0208 Execute Task,Abort_Multiple 094e ; -------------------------------------------------------------------------------------- 094e MACRO_Execute_Task,Abort_Multiple: 094e 094e dispatch_brk_class 8 ; Flow J 0x329c dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 094e seq_br_type 3 Unconditional Branch seq_branch_adr 329c 0x329c typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 094f 094f <halt> ; Flow R 0950 ; -------------------------------------------------------------------------------------- 0950 ; 0x020c Execute Module,Is_Callable 0950 ; -------------------------------------------------------------------------------------- 0950 MACRO_Execute_Module,Is_Callable: 0950 0950 dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0950 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 0951 0951 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x958 seq_br_type 1 Branch True seq_branch_adr 0958 0x0958 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 3c VR02:1c val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_frame 2 0952 0952 fiu_load_tar 1 hold_tar; Flow J cc=False 0x959 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0959 0x0959 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 0953 0953 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x957 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0957 0x0957 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_rand 2 DEC_LOOP_COUNTER 0954 0954 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x956 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0956 0x0956 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 23 VR05:03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0955 0955 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x957 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type d Dispatch False seq_branch_adr 0957 0x0957 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 04 Load_save_offset+? typ_a_adr 20 TR05:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0956 0956 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0957 0x0957 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 20 TR05:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0957 0957 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0958 0958 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0959 0959 seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 095a 095a fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x957 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0957 0x0957 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 095b 095b fiu_load_tar 1 hold_tar; Flow J 0x953 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0953 0x0953 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 095c 095c fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x957 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0957 0x0957 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 095d 095d ioc_tvbs 1 typ+fiu; Flow J 0x950 seq_br_type 3 Unconditional Branch seq_branch_adr 0950 MACRO_Execute_Module,Is_Callable typ_a_adr 24 TR00:04 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 095e ; -------------------------------------------------------------------------------------- 095e ; 0x020b Execute Module,Is_Terminated 095e ; -------------------------------------------------------------------------------------- 095e MACRO_Execute_Module,Is_Terminated: 095e 095e dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 095e fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 095f 095f fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x963 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0963 0x0963 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0960 0960 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0961 0x0961 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0961 0961 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR07:0d val_alu_func 0 PASS_A val_frame 7 val_rand a PASS_B_HIGH 0962 0962 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x958 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0958 0x0958 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 0963 0963 seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0964 0964 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x958 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0958 0x0958 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_frame 4 val_rand a PASS_B_HIGH 0965 0965 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x960 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0960 0x0960 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0966 ; -------------------------------------------------------------------------------------- 0966 ; 0x0205 QQUnknown InMicrocode 0966 ; -------------------------------------------------------------------------------------- 0966 MACRO_0966_QQUnknown_InMicrocode: 0966 0966 dispatch_brk_class 0 ; Flow J cc=False 0x96b dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0966 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 096b 0x096b seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 10 TOP typ_frame 1c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0967 0967 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x969 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0969 0x0969 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0968 0968 fiu_fill_mode_src 0 ; Flow J 0x96f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 096f 0x096f val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0969 0969 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 096a 096a fiu_fill_mode_src 0 ; Flow J 0x96f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 096f 0x096f val_c_adr 3f GP00 val_c_source 0 FIU_BUS 096b 096b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x96f seq_br_type 0 Branch False seq_branch_adr 096f 0x096f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 5 val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU 096c 096c seq_br_type 1 Branch True; Flow J cc=True 0x96e seq_branch_adr 096e 0x096e seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 10 TOP typ_frame a 096d 096d seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 096e 096e fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 096f 096f fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 0970 ; -------------------------------------------------------------------------------------- 0970 ; 0x020a Execute Module,Get_Name 0970 ; -------------------------------------------------------------------------------------- 0970 MACRO_Execute_Module,Get_Name: 0970 0970 dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0970 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0971 0x0971 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL 0971 0971 typ_c_adr 2f TOP 0972 0972 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32d7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_frame 1c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0973 0973 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x975 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0975 0x0975 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0974 0974 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0975 0975 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0976 0976 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0977 0977 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_c_lit 1 typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 0978 0978 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x97a fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 097a 0x097a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0979 0979 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 097a 097a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 097b 097b seq_br_type 1 Branch True; Flow J cc=True 0x97d seq_branch_adr 097d 0x097d seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 29 VR0c:09 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_frame c 097c 097c seq_br_type 7 Unconditional Call; Flow C 0x32f5 seq_branch_adr 32f5 0x32f5 seq_en_micro 0 097d 097d seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_en_micro 0 097e 097e fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x957 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 0957 0x0957 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 097f 097f seq_br_type 3 Unconditional Branch; Flow J 0x978 seq_branch_adr 0978 0x0978 0980 ; -------------------------------------------------------------------------------------- 0980 ; 0x02c7 Declare_Variable Any 0980 ; -------------------------------------------------------------------------------------- 0980 MACRO_Declare_Variable_Any: 0980 0980 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0980 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0981 0981 fiu_fill_mode_src 0 ; Flow J cc=True 0x3194 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3194 MACRO_Declare_Variable_Discrete seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0982 0982 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x983 ; Flow J cc=#0x0 0x983 seq_br_type b Case False seq_branch_adr 0983 0x0983 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0983 0983 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0984 0984 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0985 0985 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0986 0986 seq_br_type 3 Unconditional Branch; Flow J 0xaee seq_branch_adr 0aee MACRO_Declare_Variable_Package 0987 0987 seq_br_type 3 Unconditional Branch; Flow J 0xaf2 seq_branch_adr 0af2 MACRO_Declare_Variable_Task 0988 0988 seq_br_type 3 Unconditional Branch; Flow J 0x135a seq_branch_adr 135a MACRO_Declare_Variable_Array 0989 0989 seq_br_type 3 Unconditional Branch; Flow J 0x135a seq_branch_adr 135a MACRO_Declare_Variable_Array 098a 098a seq_br_type 3 Unconditional Branch; Flow J 0x135a seq_branch_adr 135a MACRO_Declare_Variable_Array 098b 098b seq_br_type 3 Unconditional Branch; Flow J 0x1f14 seq_branch_adr 1f14 MACRO_Declare_Variable_Record 098c 098c seq_br_type 3 Unconditional Branch; Flow J 0x1304 seq_branch_adr 1304 MACRO_Declare_Variable_Variant_Record 098d 098d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 098e 098e seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 098f 098f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0990 ; -------------------------------------------------------------------------------------- 0990 ; 0x02c6 Declare_Variable Any,Visible 0990 ; -------------------------------------------------------------------------------------- 0990 MACRO_Declare_Variable_Any,Visible: 0990 0990 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0990 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0991 0991 fiu_fill_mode_src 0 ; Flow J cc=True 0x3192 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3192 MACRO_Declare_Variable_Discrete,Visible seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0992 0992 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x993 ; Flow J cc=#0x0 0x993 seq_br_type b Case False seq_branch_adr 0993 0x0993 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0993 0993 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0994 0994 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0995 0995 seq_br_type 3 Unconditional Branch; Flow J 0x30fc seq_branch_adr 30fc MACRO_Declare_Variable_Float,Visible 0996 0996 seq_br_type 3 Unconditional Branch; Flow J 0xaf8 seq_branch_adr 0af8 MACRO_Declare_Variable_Package,Visible 0997 0997 seq_br_type 3 Unconditional Branch; Flow J 0xafe seq_branch_adr 0afe MACRO_Declare_Variable_Task,Visible 0998 0998 seq_br_type 3 Unconditional Branch; Flow J 0x136c seq_branch_adr 136c MACRO_Declare_Variable_Array,Visible 0999 0999 seq_br_type 3 Unconditional Branch; Flow J 0x136c seq_branch_adr 136c MACRO_Declare_Variable_Array,Visible 099a 099a seq_br_type 3 Unconditional Branch; Flow J 0x136c seq_branch_adr 136c MACRO_Declare_Variable_Array,Visible 099b 099b seq_br_type 3 Unconditional Branch; Flow J 0x1f06 seq_branch_adr 1f06 MACRO_Declare_Variable_Record,Visible 099c 099c seq_br_type 3 Unconditional Branch; Flow J 0x12f8 seq_branch_adr 12f8 MACRO_Declare_Variable_Variant_Record,Visible 099d 099d seq_br_type 4 Call False; Flow C cc=False 0x32da seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 099e 099e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 099f 099f seq_br_type 4 Call False; Flow C cc=False 0x32da seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 09a0 09a0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 09a1 09a1 <halt> ; Flow R 09a2 ; -------------------------------------------------------------------------------------- 09a2 ; 0x012f Execute Any,Equal 09a2 ; -------------------------------------------------------------------------------------- 09a2 MACRO_Execute_Any,Equal: 09a2 09a2 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 09a2 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 09a3 09a3 fiu_fill_mode_src 0 ; Flow J cc=True 0x2fcc fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2fcc MACRO_Execute_Discrete,Equal seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 09a4 09a4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x9a5 ; Flow J cc=#0x0 0x9a5 seq_br_type b Case False seq_branch_adr 09a5 0x09a5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 09a5 09a5 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 09a6 09a6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 09a7 09a7 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09a8 09a8 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 09a9 09a9 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 09aa 09aa seq_br_type 3 Unconditional Branch; Flow J 0x1b74 seq_branch_adr 1b74 MACRO_Execute_Array,Equal 09ab 09ab seq_br_type 3 Unconditional Branch; Flow J 0x184a seq_branch_adr 184a MACRO_Execute_Vector,Equal 09ac 09ac seq_br_type 3 Unconditional Branch; Flow J 0x1468 seq_branch_adr 1468 MACRO_Execute_Matrix,Equal 09ad 09ad seq_br_type 3 Unconditional Branch; Flow J 0x1820 seq_branch_adr 1820 MACRO_Execute_Record,Equal 09ae 09ae seq_br_type 3 Unconditional Branch; Flow J 0x1774 seq_branch_adr 1774 MACRO_Execute_Variant_Record,Equal 09af 09af fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09b0 09b0 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 09b1 09b1 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09b2 ; -------------------------------------------------------------------------------------- 09b2 ; 0x012e Execute Any,Not_Equal 09b2 ; -------------------------------------------------------------------------------------- 09b2 MACRO_Execute_Any,Not_Equal: 09b2 09b2 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 09b2 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 09b3 09b3 fiu_fill_mode_src 0 ; Flow J cc=True 0x2fd0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2fd0 MACRO_Execute_Discrete,Not_Equal seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 09b4 09b4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x9b5 ; Flow J cc=#0x0 0x9b5 seq_br_type b Case False seq_branch_adr 09b5 0x09b5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 09b5 09b5 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 09b6 09b6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 09b7 09b7 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09b8 09b8 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 09b9 09b9 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 09ba 09ba seq_br_type 3 Unconditional Branch; Flow J 0x1b74 seq_branch_adr 1b74 MACRO_Execute_Array,Equal 09bb 09bb seq_br_type 3 Unconditional Branch; Flow J 0x184a seq_branch_adr 184a MACRO_Execute_Vector,Equal 09bc 09bc seq_br_type 3 Unconditional Branch; Flow J 0x1468 seq_branch_adr 1468 MACRO_Execute_Matrix,Equal 09bd 09bd seq_br_type 3 Unconditional Branch; Flow J 0x1820 seq_branch_adr 1820 MACRO_Execute_Record,Equal 09be 09be seq_br_type 3 Unconditional Branch; Flow J 0x1774 seq_branch_adr 1774 MACRO_Execute_Variant_Record,Equal 09bf 09bf fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09c0 09c0 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 09c1 09c1 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 09c2 ; -------------------------------------------------------------------------------------- 09c2 ; 0x012d Execute Any,Address 09c2 ; -------------------------------------------------------------------------------------- 09c2 MACRO_Execute_Any,Address: 09c2 09c2 dispatch_brk_class 8 ; Flow J cc=False 0x9c6 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 09c2 seq_br_type 0 Branch False seq_branch_adr 09c6 0x09c6 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 5 09c3 09c3 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x9c7 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 09c7 0x09c7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_frame 1d typ_mar_cntl d LOAD_MAR_TYPE 09c4 09c4 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x9c8 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 09c8 0x09c8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 10 TOP typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 09c5 09c5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 3f VR1e:1f val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 1e 09c6 09c6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 09c7 09c7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 23 VR11:03 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 11 09c8 09c8 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 23 VR11:03 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 11 09c9 09c9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 09ca ; -------------------------------------------------------------------------------------- 09ca ; 0x0116 Execute Any,Address_Of_Type 09ca ; -------------------------------------------------------------------------------------- 09ca MACRO_Execute_Any,Address_Of_Type: 09ca 09ca dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 09ca ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_b_adr 10 TOP typ_frame 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 09cb 09cb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1e A_AND_B val_b_adr 3f VR1e:1f val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 1e 09cc ; -------------------------------------------------------------------------------------- 09cc ; 0x012c Execute Any,Size 09cc ; -------------------------------------------------------------------------------------- 09cc MACRO_Execute_Any,Size: 09cc 09cc dispatch_brk_class 8 ; Flow J cc=False 0x9d1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 09cc fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 09d1 0x09d1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 09cd 09cd seq_b_timing 3 Late Condition, Hint False; Flow C 0x32d7 seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 09ce 09ce fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 09cf 0x09cf seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 09cf 09cf fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 09d0 0x09d0 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL 09d0 09d0 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_en_micro 0 seq_random 02 ? 09d1 09d1 ioc_fiubs 0 fiu ; Flow J cc=True 0x9f4 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 09f4 0x09f4 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 09d2 09d2 fiu_load_tar 1 hold_tar; Flow J cc=False 0x9d5 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 09d5 0x09d5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 09d3 09d3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 09d4 0x09d4 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 09d4 09d4 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_en_micro 0 seq_random 02 ? 09d5 09d5 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 09d6 09d6 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=False 0x9e5 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 48 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 09e5 0x09e5 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 09d7 09d7 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x9da ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 09da 0x09da seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 09d8 09d8 fiu_fill_mode_src 0 ; Flow C cc=False 0x9e1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 09e1 0x09e1 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 09d9 09d9 seq_br_type 3 Unconditional Branch; Flow J 0x9dd seq_branch_adr 09dd 0x09dd seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_rand c START_MULTIPLY 09da 09da fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 09db 09db fiu_fill_mode_src 0 ; Flow C cc=False 0x9e1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 09e1 0x09e1 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 09dc 09dc seq_br_type 3 Unconditional Branch; Flow J 0x9dd seq_branch_adr 09dd 0x09dd seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_rand c START_MULTIPLY 09dd 09dd seq_b_timing 1 Latch Condition; Flow J cc=True 0x9e0 seq_br_type 1 Branch True seq_branch_adr 09e0 0x09e0 seq_en_micro 0 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 09de 09de seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 09df 09df seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 09e0 09e0 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x9ec ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 09ec 0x09ec seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 19 X_XOR_B 09e1 ; -------------------------------------------------------------------------------------- 09e1 ; Comes from: 09e1 ; 09d8 C False from color MACRO_Execute_Any,Size 09e1 ; 09db C False from color MACRO_Execute_Any,Size 09e1 ; -------------------------------------------------------------------------------------- 09e1 09e1 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x9e3 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 09e3 0x09e3 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 09e2 09e2 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3b GP04 val_c_source 0 FIU_BUS 09e3 09e3 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 09e4 09e4 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3b GP04 val_c_source 0 FIU_BUS 09e5 09e5 fiu_len_fill_lit 7a zero-fill 0x3a; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 02 GP02 typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 09e6 09e6 fiu_len_fill_lit 7d zero-fill 0x3d fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 09e7 09e7 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x9ea seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 09ea 0x09ea seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 09e8 09e8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 09e9 09e9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 09ea 09ea fiu_mem_start 2 start-rd; Flow R cc=False fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 09eb 0x09eb seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 09eb 09eb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 38 VR13:18 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 13 09ec 09ec fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 val_a_adr 03 GP03 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 09ed 09ed fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x9f2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 09f2 0x09f2 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 09ee 09ee fiu_mem_start a start_continue_if_false; Flow J cc=False 0x9f0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 09f0 0x09f0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 09ef 09ef fiu_fill_mode_src 0 ; Flow J 0x9ec fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 09ec 0x09ec typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 09f0 09f0 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 09f1 09f1 fiu_fill_mode_src 0 ; Flow J 0x9ec fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 09ec 0x09ec typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 09f2 09f2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 09f3 09f3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 09f4 09f4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x9ce seq_br_type 1 Branch True seq_branch_adr 09ce 0x09ce seq_cond_sel 00 VAL.ALU_ZERO(late) val_b_adr 10 TOP val_rand a PASS_B_HIGH 09f5 09f5 fiu_mem_start 2 start-rd; Flow C 0x2484 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2484 0x2484 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 09f6 09f6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 09f7 09f7 <halt> ; Flow R 09f8 ; -------------------------------------------------------------------------------------- 09f8 ; 0x012a Execute Any,Change_Utility 09f8 ; -------------------------------------------------------------------------------------- 09f8 MACRO_Execute_Any,Change_Utility: 09f8 09f8 dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 09f8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 10 TOP typ_frame 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 09f9 09f9 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=False 0x32d9 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 09fa 09fa fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 10 TOP typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 09fb 09fb ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32d9 seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 09fc 09fc fiu_mem_start 8 start_wr_if_false; Flow C 0x32d7 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 09fd 09fd ioc_load_wdr 0 seq_random 02 ? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_b_adr 1f TOP - 1 09fe 09fe fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 09ff 09ff <halt> ; Flow R 0a00 ; -------------------------------------------------------------------------------------- 0a00 ; 0x0129 Execute Any,Make_Visible 0a00 ; -------------------------------------------------------------------------------------- 0a00 MACRO_Execute_Any,Make_Visible: 0a00 0a00 dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a00 seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 0a01 0a01 fiu_load_tar 1 hold_tar; Flow R cc=False fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a02 0x0a02 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0a02 0a02 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a03 0x0a03 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x09) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0a03 0a03 ioc_tvbs 2 fiu+val; Flow C 0x32d7 seq_br_type 7 Unconditional Call seq_branch_adr 32d7 0x32d7 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU 0a04 ; -------------------------------------------------------------------------------------- 0a04 ; 0x0128 QQUnknown InMicrocode 0a04 ; -------------------------------------------------------------------------------------- 0a04 MACRO_0a04_QQUnknown_InMicrocode: 0a04 0a04 dispatch_brk_class 0 ; Flow R cc=False dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a04 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a05 0x0a05 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0a05 0a05 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0a06 ; -------------------------------------------------------------------------------------- 0a06 ; 0x0124 Execute Any,Is_Constrained 0a06 ; -------------------------------------------------------------------------------------- 0a06 MACRO_Execute_Any,Is_Constrained: 0a06 0a06 dispatch_brk_class 8 ; Flow J cc=True 0xa09 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a06 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 0a09 0x0a09 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_b_adr 10 TOP typ_c_lit 2 typ_frame b 0a07 0a07 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 0a08 0x0a08 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0a08 0a08 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0a09 0a09 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a0a 0x0a0a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0a0a 0a0a seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 0a0b 0a0b <halt> ; Flow R 0a0c ; -------------------------------------------------------------------------------------- 0a0c ; 0x0112 Execute Any,Make_Constrained 0a0c ; -------------------------------------------------------------------------------------- 0a0c MACRO_Execute_Any,Make_Constrained: 0a0c 0a0c dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a0c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0a0d 0x0a0d seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 21 TR0c:01 typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL 0a0d 0a0d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32d7 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 0a0e ; -------------------------------------------------------------------------------------- 0a0e ; 0x0123 Execute Any,Make_Aligned 0a0e ; -------------------------------------------------------------------------------------- 0a0e MACRO_Execute_Any,Make_Aligned: 0a0e 0a0e dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a0e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_frame 2 0a0f 0a0f ioc_tvbs 5 seq+seq; Flow C cc=True 0x32db seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS 0a10 0a10 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x32d7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 23 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a11 0a11 ioc_load_wdr 0 ; Flow J cc=False 0x9c9 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 09c9 0x09c9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 0a12 0a12 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a13 0a13 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu 0a14 0a14 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 0a15 0a15 <halt> ; Flow R 0a16 ; -------------------------------------------------------------------------------------- 0a16 ; 0x0122 Execute Any,Make_Root_Type 0a16 ; -------------------------------------------------------------------------------------- 0a16 MACRO_Execute_Any,Make_Root_Type: 0a16 0a16 dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a16 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR09:00 val_frame 9 0a17 0a17 seq_br_type 4 Call False; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 val_b_adr 39 VR02:19 val_frame 2 0a18 0a18 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32a9 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0a19 0a19 fiu_len_fill_lit 44 zero-fill 0x4; Flow R cc=True fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 0a1a 0x0a1a seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS 0a1a 0a1a fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0xa1c ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0a1c 0x0a1c seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 0a1b 0a1b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0a1c 0a1c <default> 0a1d 0a1d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 0a1e 0a1e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 0 PASS_A val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 0a1f 0a1f seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 0a20 ; -------------------------------------------------------------------------------------- 0a20 ; 0x0121 Execute Any,Is_Default 0a20 ; -------------------------------------------------------------------------------------- 0a20 MACRO_Execute_Any,Is_Default: 0a20 0a20 dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a20 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a21 0x0a21 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0a21 0a21 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xa1f ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 0a1f 0x0a1f seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a22 ; -------------------------------------------------------------------------------------- 0a22 ; 0x0120 Execute Any,Is_Value 0a22 ; -------------------------------------------------------------------------------------- 0a22 MACRO_Execute_Any,Is_Value: 0a22 0a22 dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a22 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 1 0a23 0a23 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0a24 ; -------------------------------------------------------------------------------------- 0a24 ; 0x011f Execute Any,Is_Scalar 0a24 ; -------------------------------------------------------------------------------------- 0a24 MACRO_Execute_Any,Is_Scalar: 0a24 0a24 dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0a24 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 1 0a25 0a25 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 34 VR05:14 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0a26 ; -------------------------------------------------------------------------------------- 0a26 ; 0x011e Execute Any,Convert 0a26 ; -------------------------------------------------------------------------------------- 0a26 MACRO_Execute_Any,Convert: 0a26 0a26 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a26 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a27 0a27 fiu_fill_mode_src 0 ; Flow J cc=True 0x301e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 301e MACRO_Execute_Discrete,Convert seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a28 0a28 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa29 ; Flow J cc=#0x0 0xa29 seq_br_type b Case False seq_branch_adr 0a29 0x0a29 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a29 0a29 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0a2a 0a2a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a2b 0a2b seq_br_type 3 Unconditional Branch; Flow J 0x2900 seq_branch_adr 2900 MACRO_Execute_Float,Convert 0a2c 0a2c seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0a2d 0a2d seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0a2e 0a2e seq_br_type 3 Unconditional Branch; Flow J 0x1c06 seq_branch_adr 1c06 MACRO_Execute_Array,Convert 0a2f 0a2f seq_br_type 3 Unconditional Branch; Flow J 0x1a88 seq_branch_adr 1a88 MACRO_Execute_Vector,Convert 0a30 0a30 seq_br_type 3 Unconditional Branch; Flow J 0x1582 seq_branch_adr 1582 MACRO_Execute_Matrix,Convert 0a31 0a31 seq_br_type 3 Unconditional Branch; Flow J 0x1834 seq_branch_adr 1834 MACRO_Execute_Record,Convert 0a32 0a32 seq_br_type 3 Unconditional Branch; Flow J 0x17ce seq_branch_adr 17ce MACRO_Execute_Variant_Record,Convert 0a33 0a33 seq_br_type 0 Branch False; Flow J cc=False 0x1b23 seq_branch_adr 1b23 0x1b23 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand 8 SPARE_0x08 0a34 0a34 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1b3b ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1b3b 0x1b3b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0a35 0a35 seq_br_type 0 Branch False; Flow J cc=False 0xc33 seq_branch_adr 0c33 0x0c33 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 8 SPARE_0x08 0a36 0a36 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xc4b ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0c4b 0x0c4b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0a37 0a37 <halt> ; Flow R 0a38 ; -------------------------------------------------------------------------------------- 0a38 ; 0x011d Execute Any,Convert_To_Formal 0a38 ; -------------------------------------------------------------------------------------- 0a38 MACRO_Execute_Any,Convert_To_Formal: 0a38 0a38 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a38 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a39 0a39 fiu_fill_mode_src 0 ; Flow J cc=True 0x301e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 301e MACRO_Execute_Discrete,Convert seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a3a 0a3a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa3b ; Flow J cc=#0x0 0xa3b seq_br_type b Case False seq_branch_adr 0a3b 0x0a3b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a3b 0a3b seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0a3c 0a3c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a3d 0a3d seq_br_type 3 Unconditional Branch; Flow J 0x2900 seq_branch_adr 2900 MACRO_Execute_Float,Convert 0a3e 0a3e seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0a3f 0a3f seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0a40 0a40 seq_br_type 3 Unconditional Branch; Flow J 0x1c6c seq_branch_adr 1c6c MACRO_Execute_Array,Convert_To_Formal 0a41 0a41 seq_br_type 3 Unconditional Branch; Flow J 0x1ac8 seq_branch_adr 1ac8 MACRO_Execute_Vector,Convert_To_Formal 0a42 0a42 seq_br_type 3 Unconditional Branch; Flow J 0x15f8 seq_branch_adr 15f8 MACRO_Execute_Matrix,Convert_To_Formal 0a43 0a43 seq_br_type 3 Unconditional Branch; Flow J 0x1834 seq_branch_adr 1834 MACRO_Execute_Record,Convert 0a44 0a44 seq_br_type 3 Unconditional Branch; Flow J 0x17ce seq_branch_adr 17ce MACRO_Execute_Variant_Record,Convert 0a45 0a45 seq_br_type 0 Branch False; Flow J cc=False 0x1b23 seq_branch_adr 1b23 0x1b23 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand 8 SPARE_0x08 0a46 0a46 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1b3b ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1b3b 0x1b3b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0a47 0a47 seq_br_type 0 Branch False; Flow J cc=False 0xc33 seq_branch_adr 0c33 0x0c33 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 8 SPARE_0x08 0a48 0a48 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xc4b ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0c4b 0x0c4b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0a49 0a49 <halt> ; Flow R 0a4a ; -------------------------------------------------------------------------------------- 0a4a ; 0x011c Execute Any,Convert_Unchecked 0a4a ; -------------------------------------------------------------------------------------- 0a4a MACRO_Execute_Any,Convert_Unchecked: 0a4a 0a4a dispatch_brk_class 4 ; Flow C cc=False 0xa4f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0a4a fiu_len_fill_lit 42 zero-fill 0x2 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0a4f 0x0a4f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a4b 0a4b fiu_load_tar 1 hold_tar; Flow J cc=True 0xa4d fiu_tivi_src 8 type_var seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0a4d 0x0a4d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 3 0a4c 0a4c fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0a4d 0x0a4d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 11 TOP + 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL 0a4d 0a4d ioc_tvbs 2 fiu+val; Flow C 0x32d7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 7 0a4e 0a4e seq_br_type 7 Unconditional Call; Flow C 0x32db seq_branch_adr 32db 0x32db 0a4f ; -------------------------------------------------------------------------------------- 0a4f ; Comes from: 0a4f ; 0a4a C False from color MACRO_Execute_Any,Convert_Unchecked 0a4f ; -------------------------------------------------------------------------------------- 0a4f 0a4f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=#0x0 0xa52 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0a52 0x0a52 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0a50 0a50 fiu_tivi_src 4 fiu_var; Flow J cc=True 0xa51 ; Flow J cc=#0x0 0xa63 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 0a63 0x0a63 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_frame 7 val_b_adr 1f TOP - 1 val_c_adr 3f GP00 0a51 0a51 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0a52 ; -------------------------------------------------------------------------------------- 0a52 ; Comes from: 0a52 ; 0a4f C #0x0 from color 0x0a4e 0a52 ; -------------------------------------------------------------------------------------- 0a52 0a52 fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a53 0a53 fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False ; Flow J cc=True 0xa5a fiu_mem_start 6 start_rd_if_false fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0a5a 0x0a5a typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a54 0a54 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a55 0a55 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a56 0a56 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a57 0a57 fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False ; Flow J cc=True 0xa5c fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0a5c 0x0a5c typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a58 0a58 fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False ; Flow J cc=True 0xa5d fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0a5d 0x0a5d typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a59 0a59 fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False ; Flow J cc=True 0xa5e fiu_mem_start 6 start_rd_if_false fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0a5e 0x0a5e typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a5a 0a5a fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 0a5b 0a5b fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=True ; Flow J cc=False 0xa6f fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 0a6f 0x0a6f seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a5c 0a5c fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type a Unconditional Return val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0a5d 0a5d fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type a Unconditional Return val_a_adr 34 VR07:14 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 0a5e 0a5e fiu_mem_start 2 start-rd; Flow C 0x32d7 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a5f 0a5f fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 val_b_adr 1f TOP - 1 val_c_adr 3f GP00 0a60 0a60 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0a61 0a61 fiu_len_fill_lit 42 zero-fill 0x2 fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_random 06 Pop_stack+? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 01 GP01 val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 0a62 0a62 seq_b_timing 0 Early Condition; Flow J cc=True 0xa63 ; Flow J cc=#0x0 0xa63 seq_br_type b Case False seq_branch_adr 0a63 0x0a63 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0a63 0a63 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0xa6d seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0a6d 0x0a6d seq_cond_sel 07 VAL.ALU_32_CO(late) typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0a64 0a64 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0xa6b seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0a6b 0x0a6b seq_cond_sel 07 VAL.ALU_32_CO(late) typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0a65 0a65 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a66 0a66 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a67 0a67 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a68 0a68 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0xa63 seq_br_type 8 Return True seq_branch_adr 0a63 0x0a63 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP 0a69 0a69 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0xa63 seq_br_type 8 Return True seq_branch_adr 0a63 0x0a63 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP 0a6a 0a6a seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0xa63 seq_br_type 8 Return True seq_branch_adr 0a63 0x0a63 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP 0a6b 0a6b fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0xa6d ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0a6d 0x0a6d seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE 0a6c 0a6c ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32db seq_br_type 4 Call False seq_branch_adr 32db 0x32db seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0a6d 0a6d fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_br_type c Dispatch True seq_branch_adr 0a6e 0x0a6e seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 28 TR09:08 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0a6e 0a6e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 01 GP01 typ_c_adr 2f TOP typ_csa_cntl 2 PUSH_CSA val_c_adr 2f TOP 0a6f 0a6f seq_br_type 7 Unconditional Call; Flow C 0x32db seq_branch_adr 32db 0x32db 0a70 ; -------------------------------------------------------------------------------------- 0a70 ; 0x011b Execute Any,In_Type 0a70 ; -------------------------------------------------------------------------------------- 0a70 MACRO_Execute_Any,In_Type: 0a70 0a70 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a70 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a71 0a71 fiu_fill_mode_src 0 ; Flow J cc=True 0x301a fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 301a MACRO_Execute_Discrete,In_Type seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a72 0a72 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa73 ; Flow J cc=#0x0 0xa73 seq_br_type b Case False seq_branch_adr 0a73 0x0a73 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a73 0a73 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0a74 0a74 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a75 0a75 seq_br_type 3 Unconditional Branch; Flow J 0x2924 seq_branch_adr 2924 MACRO_Execute_Float,In_Type 0a76 0a76 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa80 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a80 0x0a80 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a77 0a77 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa80 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a80 0x0a80 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a78 0a78 seq_br_type 3 Unconditional Branch; Flow J 0x1bd6 seq_branch_adr 1bd6 MACRO_Execute_Array,In_Type 0a79 0a79 seq_br_type 3 Unconditional Branch; Flow J 0x1ad0 seq_branch_adr 1ad0 MACRO_Execute_Vector,In_Type 0a7a 0a7a seq_br_type 3 Unconditional Branch; Flow J 0x14e0 seq_branch_adr 14e0 MACRO_Execute_Matrix,In_Type 0a7b 0a7b fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa80 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a80 0x0a80 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a7c 0a7c seq_br_type 3 Unconditional Branch; Flow J 0x17e0 seq_branch_adr 17e0 MACRO_Execute_Variant_Record,In_Type 0a7d 0a7d fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x1b2d fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b2d 0x1b2d seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a7e 0a7e seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 0a7f 0a7f fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xc3d fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c3d 0x0c3d seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a80 0a80 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0a81 0a81 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a82 0a82 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0a83 0a83 <halt> ; Flow R 0a84 ; -------------------------------------------------------------------------------------- 0a84 ; 0x011a Execute Any,Not_In_Type 0a84 ; -------------------------------------------------------------------------------------- 0a84 MACRO_Execute_Any,Not_In_Type: 0a84 0a84 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a84 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a85 0a85 fiu_fill_mode_src 0 ; Flow J cc=True 0x301c fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 301c MACRO_Execute_Discrete,Not_In_Type seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a86 0a86 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa87 ; Flow J cc=#0x0 0xa87 seq_br_type b Case False seq_branch_adr 0a87 0x0a87 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a87 0a87 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0a88 0a88 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a89 0a89 seq_br_type 3 Unconditional Branch; Flow J 0x2926 seq_branch_adr 2926 MACRO_Execute_Float,Not_In_Type 0a8a 0a8a fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa94 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a94 0x0a94 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a8b 0a8b fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa94 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a94 0x0a94 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a8c 0a8c seq_br_type 3 Unconditional Branch; Flow J 0x1be4 seq_branch_adr 1be4 MACRO_Execute_Array,Not_In_Type 0a8d 0a8d seq_br_type 3 Unconditional Branch; Flow J 0x1ade seq_branch_adr 1ade MACRO_Execute_Vector,Not_In_Type 0a8e 0a8e seq_br_type 3 Unconditional Branch; Flow J 0x14e4 seq_branch_adr 14e4 MACRO_Execute_Matrix,Not_In_Type 0a8f 0a8f fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xa94 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0a94 0x0a94 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a90 0a90 seq_br_type 3 Unconditional Branch; Flow J 0x17e4 seq_branch_adr 17e4 MACRO_Execute_Variant_Record,Not_In_Type 0a91 0a91 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x1b33 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b33 0x1b33 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a92 0a92 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 0a93 0a93 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0xc43 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c43 0x0c43 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a94 0a94 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0a95 0a95 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0a96 0a96 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0a97 0a97 <halt> ; Flow R 0a98 ; -------------------------------------------------------------------------------------- 0a98 ; 0x0119 Execute Any,Check_In_Formal_Type 0a98 ; -------------------------------------------------------------------------------------- 0a98 MACRO_Execute_Any,Check_In_Formal_Type: 0a98 0a98 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0a98 dispatch_uses_tos 1 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 0a99 0a99 fiu_fill_mode_src 0 ; Flow J cc=True 0x302a fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 302a MACRO_Execute_Discrete,Check_In_Type seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 33 TR08:13 typ_frame 8 val_b_adr 27 VR09:07 val_frame 9 0a9a 0a9a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xa9b ; Flow J cc=#0x0 0xa9b seq_br_type b Case False seq_branch_adr 0a9b 0x0a9b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1 0a9b 0a9b seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0a9c 0a9c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0a9d 0a9d seq_br_type 3 Unconditional Branch; Flow J 0x292a seq_branch_adr 292a MACRO_Execute_Float,Check_In_Type 0a9e 0a9e fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xaa8 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0aa8 0x0aa8 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0a9f 0a9f fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xaa8 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0aa8 0x0aa8 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0aa0 0aa0 seq_br_type 3 Unconditional Branch; Flow J 0x1bf2 seq_branch_adr 1bf2 MACRO_Execute_Array,Check_In_Type 0aa1 0aa1 seq_br_type 3 Unconditional Branch; Flow J 0x1ae6 seq_branch_adr 1ae6 MACRO_Execute_Vector,Check_In_Type 0aa2 0aa2 seq_br_type 3 Unconditional Branch; Flow J 0x14e8 seq_branch_adr 14e8 MACRO_Execute_Matrix,Check_In_Type 0aa3 0aa3 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xaa8 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0aa8 0x0aa8 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0aa4 0aa4 seq_br_type 3 Unconditional Branch; Flow J 0x17ee seq_branch_adr 17ee MACRO_Execute_Variant_Record,Check_In_Formal_Type 0aa5 0aa5 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1b39 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b39 0x1b39 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0aa6 0aa6 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 0aa7 0aa7 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xc49 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c49 0x0c49 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0aa8 0aa8 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 11 TOP + 1 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0aa9 0aa9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0aaa ; -------------------------------------------------------------------------------------- 0aaa ; 0x0118 Execute Any,Write_Unchecked 0aaa ; -------------------------------------------------------------------------------------- 0aaa MACRO_Execute_Any,Write_Unchecked: 0aaa 0aaa dispatch_brk_class 2 ; Flow C 0x1d78 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0aaa fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d78 0x1d78 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0aab 0aab fiu_mem_start 6 start_rd_if_false; Flow C 0x32d7 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0aac 0aac seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xaaf seq_br_type 0 Branch False seq_branch_adr 0aaf 0x0aaf seq_cond_sel 28 TYP.OF_KIND_MATCH(0x04) Discrete_Var Float_Var typ_b_adr 1f TOP - 1 typ_frame 4 0aad 0aad fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d78 0x1d78 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE 0aae 0aae seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 0aaf 0aaf fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR05:01 typ_alu_func 19 X_XOR_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0ab0 0ab0 fiu_fill_mode_src 0 ; Flow J cc=False 0xab2 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0ab2 0x0ab2 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 0ab1 0ab1 fiu_fill_mode_src 0 ; Flow J 0xab5 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0ab5 0x0ab5 typ_a_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 0ab2 0ab2 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0ab3 0ab3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0ab4 0ab4 fiu_load_var 1 hold_var; Flow J 0xab5 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0ab5 0x0ab5 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0ab5 0ab5 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA 0ab6 0ab6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0ab7 0ab7 <halt> ; Flow R 0ab8 ; -------------------------------------------------------------------------------------- 0ab8 ; 0x0117 Execute Any,Structure_Query 0ab8 ; -------------------------------------------------------------------------------------- 0ab8 MACRO_Execute_Any,Structure_Query: 0ab8 0ab8 dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_free 3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ab8 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0ab9 0ab9 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=#0x0 0xabb fiu_load_var 1 hold_var fiu_mem_start a start_continue_if_false fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 0abb 0x0abb seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 2 typ_frame b typ_mar_cntl 6 INCREMENT_MAR 0aba 0aba seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 0abb ; -------------------------------------------------------------------------------------- 0abb ; Comes from: 0abb ; 0ab9 C #0x0 from color 0x0ab9 0abb ; -------------------------------------------------------------------------------------- 0abb 0abb fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32a9 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0abc 0abc fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32a9 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0abd 0abd fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32a9 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0abe 0abe fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32a9 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 22 VR05:02 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0abf 0abf seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 typ_a_adr 10 TOP typ_c_lit 2 typ_rand b CARRY IN = Q BIT FROM VAL 0ac0 0ac0 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 typ_a_adr 10 TOP typ_c_lit 2 typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL 0ac1 0ac1 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0ac2 0ac2 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32a9 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0ac3 0ac3 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True ; Flow J cc=False 0xacd fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0acd 0x0acd seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ac4 0ac4 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0xace seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0ace 0x0ace seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 0ac5 0ac5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0ac6 0ac6 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32a9 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR03:1e val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 3 0ac7 0ac7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 0ac8 0ac8 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0xacb ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0acb 0x0acb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ac9 0ac9 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0xacb ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0acb 0x0acb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR val_c_adr 2f TOP val_c_source 0 FIU_BUS 0aca 0aca fiu_mem_start 4 continue; Flow R cc=True ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0acb 0x0acb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR val_c_adr 2f TOP val_c_source 0 FIU_BUS 0acb 0acb typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 24 VR05:04 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 5 0acc 0acc fiu_len_fill_lit 45 zero-fill 0x5; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 0acd 0acd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 29 VR05:09 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 5 0ace 0ace fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0acf 0acf fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ad0 0ad0 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0xadf fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0adf 0x0adf seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 24 TR05:04 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0ad1 0ad1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 0ad2 0ad2 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0xad7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ad7 0x0ad7 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0ad3 0ad3 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0ad4 0ad4 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0ad5 0ad5 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0ad6 0ad6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2a VR05:0a val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 5 0ad7 0ad7 fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=True 0xad3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ad3 0x0ad3 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0ad8 0ad8 ioc_tvbs 1 typ+fiu val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0ad9 0ad9 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0xad3 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0ad3 0x0ad3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0ada 0ada typ_rand e CHECK_CLASS_SYSTEM_B val_rand 2 DEC_LOOP_COUNTER 0adb 0adb fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x2ab4 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 0adc 0adc seq_br_type 1 Branch True; Flow J cc=True 0xad9 seq_branch_adr 0ad9 0x0ad9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 0add 0add fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 17 LOOP_COUNTER val_alu_func 7 INC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0ade 0ade ioc_tvbs 1 typ+fiu; Flow J 0xad5 seq_br_type 3 Unconditional Branch seq_branch_adr 0ad5 0x0ad5 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 0adf ; -------------------------------------------------------------------------------------- 0adf ; Comes from: 0adf ; 0ad0 C True from color 0x0ac4 0adf ; -------------------------------------------------------------------------------------- 0adf 0adf ioc_tvbs 3 fiu+fiu; Flow C 0x33af seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0ae0 0ae0 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return typ_b_adr 04 GP04 val_b_adr 04 GP04 0ae1 0ae1 <halt> ; Flow R 0ae2 ; -------------------------------------------------------------------------------------- 0ae2 ; 0x0126 Execute Any,Has_Default_Initialization 0ae2 ; -------------------------------------------------------------------------------------- 0ae2 MACRO_Execute_Any,Has_Default_Initialization: 0ae2 0ae2 dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ae2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_frame 2 0ae3 0ae3 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 3d 0ae4 0ae4 fiu_fill_mode_src 0 ; Flow C 0x32d7 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 10 TOP typ_frame 8 0ae5 0ae5 ioc_load_wdr 0 ; Flow J 0x9c9 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 09c9 0x09c9 seq_random 02 ? typ_csa_cntl 3 POP_CSA 0ae6 ; -------------------------------------------------------------------------------------- 0ae6 ; 0x0111 Execute Any,Has_Repeated_Initialization 0ae6 ; -------------------------------------------------------------------------------------- 0ae6 MACRO_Execute_Any,Has_Repeated_Initialization: 0ae6 0ae6 dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ae6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_frame 2 0ae7 0ae7 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0xae4 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 3d seq_br_type 3 Unconditional Branch seq_branch_adr 0ae4 0x0ae4 0ae8 ; -------------------------------------------------------------------------------------- 0ae8 ; 0x0110 Execute Any,Is_Initialization_Repeated 0ae8 ; -------------------------------------------------------------------------------------- 0ae8 MACRO_Execute_Any,Is_Initialization_Repeated: 0ae8 0ae8 dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0ae8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0ae9 0ae9 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x32d7 fiu_mem_start 2 start-rd fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0aea ; -------------------------------------------------------------------------------------- 0aea ; 0x012b Execute Any,Spare14 0aea ; -------------------------------------------------------------------------------------- 0aea MACRO_Execute_Any,Spare14: 0aea 0aea dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0aea fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0aeb 0aeb fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x32d7 fiu_offs_lit 3b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0aec 0aec fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0aed 0aed <halt> ; Flow R 0aee ; -------------------------------------------------------------------------------------- 0aee ; 0x0387 Declare_Variable Package 0aee ; -------------------------------------------------------------------------------------- 0aee MACRO_Declare_Variable_Package: 0aee 0aee dispatch_brk_class 4 ; Flow J 0xaef dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0aee fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b4b 0x0b4b seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0aef 0aef fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_b_adr 10 TOP typ_c_lit 1 typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0af0 0af0 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0af1 0af1 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0xb5f fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 0b5f 0x0b5f typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 0af2 ; -------------------------------------------------------------------------------------- 0af2 ; 0x036f Declare_Variable Task 0af2 ; -------------------------------------------------------------------------------------- 0af2 MACRO_Declare_Variable_Task: 0af2 0af2 dispatch_brk_class 4 ; Flow J 0xaf3 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0af2 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0af3 0af3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_b_adr 10 TOP typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0af4 0af4 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2e VR02:0e val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0af5 0af5 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0af6 0af6 seq_br_type 3 Unconditional Branch; Flow J 0xb5f seq_branch_adr 0b5f 0x0b5f typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0af7 0af7 <halt> ; Flow R 0af8 ; -------------------------------------------------------------------------------------- 0af8 ; 0x0386 Declare_Variable Package,Visible 0af8 ; -------------------------------------------------------------------------------------- 0af8 MACRO_Declare_Variable_Package,Visible: 0af8 0af8 dispatch_brk_class 4 ; Flow J 0xaf9 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0af8 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b4b 0x0b4b seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0af9 0af9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 20 TR18:00 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0afa 0afa ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0afb 0afb fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xb5f fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 0b5f 0x0b5f seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 0afc 0afc seq_br_type 7 Unconditional Call; Flow C 0x32da seq_branch_adr 32da 0x32da 0afd 0afd <halt> ; Flow R 0afe ; -------------------------------------------------------------------------------------- 0afe ; 0x036e Declare_Variable Task,Visible 0afe ; -------------------------------------------------------------------------------------- 0afe MACRO_Declare_Variable_Task,Visible: 0afe 0afe dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0afe fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0aff 0aff fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb00 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e typ_b_adr 10 TOP typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b00 0b00 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x32da fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 2e VR02:0e val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0b01 0b01 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value 0b02 0b02 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0b03 0b03 seq_br_type 3 Unconditional Branch; Flow J 0xb5f seq_branch_adr 0b5f 0x0b5f typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b04 ; -------------------------------------------------------------------------------------- 0b04 ; 0x036d Declare_Variable Task,On_Processor 0b04 ; -------------------------------------------------------------------------------------- 0b04 MACRO_Declare_Variable_Task,On_Processor: 0b04 0b04 dispatch_brk_class 4 ; Flow C 0x329e dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b04 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 0b05 0b05 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0b06 0b06 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b07 0b07 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb08 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b08 0b08 fiu_load_var 1 hold_var; Flow J 0xb5f fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0b5f 0x0b5f typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b09 0b09 <halt> ; Flow R 0b0a ; -------------------------------------------------------------------------------------- 0b0a ; 0x036c Declare_Variable Task,Visible,On_Processor 0b0a ; -------------------------------------------------------------------------------------- 0b0a MACRO_Declare_Variable_Task,Visible,On_Processor: 0b0a 0b0a dispatch_brk_class 4 ; Flow C 0x329e dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b0a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 0b0b 0b0b fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0b0c 0b0c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b0d 0b0d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb0e fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b0e 0b0e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xb5f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0b5f 0x0b5f seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b0f 0b0f seq_br_type 7 Unconditional Call; Flow C 0x32da seq_branch_adr 32da 0x32da typ_csa_cntl 3 POP_CSA 0b10 ; -------------------------------------------------------------------------------------- 0b10 ; 0x036b Declare_Variable Task,As_Component 0b10 ; -------------------------------------------------------------------------------------- 0b10 MACRO_Declare_Variable_Task,As_Component: 0b10 0b10 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b10 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_frame 2 0b11 0b11 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb12 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0b12 0b12 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b13 0b13 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x32db fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 29 VR0c:09 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame c 0b14 0b14 fiu_load_var 1 hold_var; Flow C 0xb1f fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0b1f 0x0b1f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b15 0b15 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xb5f fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 0b5f 0x0b5f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 08 GP08 val_alu_func 1a PASS_B 0b16 0b16 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 0b17 0b17 <halt> ; Flow R 0b18 ; -------------------------------------------------------------------------------------- 0b18 ; 0x036a Declare_Variable Task,On_Processor,As_Component 0b18 ; -------------------------------------------------------------------------------------- 0b18 MACRO_Declare_Variable_Task,On_Processor,As_Component: 0b18 0b18 dispatch_brk_class 4 ; Flow C 0x329e dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b18 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 0b19 0b19 ioc_fiubs 1 val ; Flow J cc=True 0x32db ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 29 VR0c:09 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame c 0b1a 0b1a fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b1b 0b1b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xb1c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0b1c 0b1c fiu_load_var 1 hold_var; Flow C 0xb1f fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 0b1f 0x0b1f typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b1d 0b1d fiu_load_var 1 hold_var; Flow J cc=True 0xb5f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 0b5f 0x0b5f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 1a PASS_B 0b1e 0b1e seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 0b1f 0b1f fiu_mem_start a start_continue_if_false; Flow J cc=False 0xb21 ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0b21 0x0b21 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b20 0b20 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0b21 0b21 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0b22 0b22 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0b23 0b23 <halt> ; Flow R 0b24 ; -------------------------------------------------------------------------------------- 0b24 ; 0x0385 Declare_Variable Package,On_Processor 0b24 ; -------------------------------------------------------------------------------------- 0b24 MACRO_Declare_Variable_Package,On_Processor: 0b24 0b24 dispatch_brk_class 4 ; Flow C 0x329e dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b24 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 0b25 0b25 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0b26 0b26 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0xb27 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b4b 0x0b4b seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b27 0b27 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b28 0b28 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xb5f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0b5f 0x0b5f seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b29 0b29 seq_br_type 3 Unconditional Branch; Flow J 0x32a9 seq_branch_adr 32a9 0x32a9 0b2a ; -------------------------------------------------------------------------------------- 0b2a ; 0x0384 Declare_Variable Package,Visible,On_Processor 0b2a ; -------------------------------------------------------------------------------------- 0b2a MACRO_Declare_Variable_Package,Visible,On_Processor: 0b2a 0b2a dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 0b2a seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 0b2b 0b2b fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x329e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 0b2c 0b2c ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0b2d 0b2d fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0xb2e fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 0b4b 0x0b4b seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR02:00 val_c_adr 3b GP04 val_frame 2 0b2e 0b2e fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b2f 0b2f fiu_load_var 1 hold_var; Flow J cc=True 0xb5f fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0b5f 0x0b5f seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b30 0b30 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 0b31 0b31 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 10 TOP 0b32 0b32 ioc_adrbs 1 val ; Flow C 0xb6b ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b6b 0x0b6b typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b33 0b33 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 20 VR02:00 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0b34 0b34 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 02 GP02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b35 0b35 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 18 0b36 0b36 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0xb37 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 0b4e 0x0b4e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 0b37 0b37 ioc_adrbs 1 val ; Flow R cc=False ; Flow J cc=True 0xb4b ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0b4b 0x0b4b typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0b38 0b38 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR02:00 val_frame 2 0b39 0b39 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_c_adr 37 GP08 val_c_source 0 FIU_BUS 0b3a 0b3a fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b3b 0b3b fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 70 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 6 0b3c 0b3c fiu_mem_start 4 continue; Flow C 0x329e ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 36 VR05:16 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0b3d 0b3d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 23 VR11:03 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 0b3e 0b3e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 25 VR11:05 val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_frame 11 0b3f 0b3f ioc_load_wdr 0 ; Flow C 0x32d7 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1d val_b_adr 16 CSA/VAL_BUS 0b40 0b40 ioc_fiubs 0 fiu ; Flow C cc=True 0xb4a seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0b4a 0x0b4a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 01 GP01 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_frame 10 val_alu_func 1b A_OR_B val_b_adr 31 VR02:11 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 0b41 0b41 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_csa_cntl 1 START_POP_DOWN val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 0b42 0b42 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 27 TR02:07 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0b43 0b43 fiu_load_var 1 hold_var; Flow C 0xb5f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0b5f 0x0b5f typ_c_adr 2e TOP + 1 typ_csa_cntl 2 PUSH_CSA val_a_adr 02 GP02 val_c_adr 2e TOP + 1 0b44 0b44 fiu_tivi_src c mar_0xc; Flow J cc=True 0xb48 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0b48 0x0b48 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 39 GP06 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 16 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b45 0b45 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 0b46 0b46 fiu_len_fill_lit 46 zero-fill 0x6; Flow C 0x32d7 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 16 CSA/VAL_BUS typ_frame 1b val_a_adr 24 VR11:04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 11 0b47 0b47 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 0b48 0b48 seq_br_type 1 Branch True; Flow J cc=True 0x3916 seq_branch_adr 3916 0x3916 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 31 VR02:11 val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_frame 2 0b49 0b49 seq_br_type 3 Unconditional Branch; Flow J 0x3916 seq_branch_adr 3916 0x3916 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1 0b4a ; -------------------------------------------------------------------------------------- 0b4a ; Comes from: 0b4a ; 0b40 C True from color 0x0b32 0b4a ; -------------------------------------------------------------------------------------- 0b4a 0b4a seq_br_type 8 Return True; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 01 GP01 typ_c_lit 0 typ_frame 16 0b4b 0b4b fiu_tivi_src c mar_0xc; Flow C 0x3331 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3331 0x3331 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b4c 0b4c seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x3916 seq_br_type 0 Branch False seq_branch_adr 3916 0x3916 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0b4d 0b4d fiu_mem_start 2 start-rd; Flow J 0xb51 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0b51 0x0b51 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0b4e 0b4e fiu_tivi_src c mar_0xc; Flow C 0x3330 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3330 0x3330 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b4f 0b4f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x3916 seq_br_type 0 Branch False seq_branch_adr 3916 0x3916 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 0b50 0b50 fiu_mem_start 2 start-rd; Flow J 0xb51 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0b51 0x0b51 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0b51 0b51 seq_br_type 2 Push (branch address); Flow J 0xb52 seq_branch_adr 0b49 0x0b49 0b52 0b52 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x3916 seq_br_type 9 Return False seq_branch_adr 3916 0x3916 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 22 VR08:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 8 0b53 ; -------------------------------------------------------------------------------------- 0b53 ; Comes from: 0b53 ; 0903 C from color 0x0903 0b53 ; 0946 C from color 0x0921 0b53 ; -------------------------------------------------------------------------------------- 0b53 0b53 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0xb74 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0b74 0x0b74 seq_en_micro 0 typ_b_adr 3d TR11:1d typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 11 val_a_adr 2e VR0d:0e val_frame d 0b54 0b54 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xb5b fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0b5b 0x0b5b seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 23 TR0d:03 typ_frame d typ_mar_cntl a LOAD_MAR_IMPORT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0b55 0b55 ioc_fiubs 1 val ; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_a_adr 21 VR04:01 val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 4 0b56 0b56 fiu_tivi_src c mar_0xc; Flow C cc=True 0x211 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 3c VR04:1c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b57 0b57 fiu_tivi_src c mar_0xc; Flow C 0xb7d ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b7d 0x0b7d seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0b58 0b58 fiu_load_var 1 hold_var; Flow J cc=True 0xb56 fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 0b56 0x0b56 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1c DEC_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU 0b59 0b59 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xb5c fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0b5c 0x0b5c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl a LOAD_MAR_IMPORT 0b5a 0b5a seq_br_type 3 Unconditional Branch; Flow J 0xb53 seq_branch_adr 0b53 0x0b53 seq_en_micro 0 val_a_adr 21 VR04:01 val_alu_func 7 INC_A val_c_adr 1e VR04:01 val_c_mux_sel 2 ALU val_frame 4 0b5b 0b5b fiu_len_fill_lit 49 zero-fill 0x9; Flow C cc=True 0x32d3 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d3 0x32d3 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 3c VR04:1c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b5c 0b5c fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 3d TR11:1d typ_frame 11 0b5d 0b5d fiu_load_var 1 hold_var; Flow C 0xb78 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0b78 0x0b78 seq_en_micro 0 0b5e 0b5e ioc_adrbs 1 val ; Flow J 0x3449 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3449 0x3449 seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0b5f ; -------------------------------------------------------------------------------------- 0b5f ; Comes from: 0b5f ; 0b43 C from color 0x0b32 0b5f ; -------------------------------------------------------------------------------------- 0b5f 0b5f fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0xb74 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0b74 0x0b74 seq_en_micro 0 typ_b_adr 3d TR11:1d typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 11 val_a_adr 2e VR0d:0e val_frame d 0b60 0b60 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xb67 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0b67 0x0b67 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 23 TR0d:03 typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0b61 0b61 ioc_fiubs 1 val ; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_a_adr 21 VR04:01 val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 4 0b62 0b62 fiu_tivi_src c mar_0xc; Flow C cc=True 0x211 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR04:1c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b63 0b63 fiu_tivi_src c mar_0xc; Flow C 0xb7d ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b7d 0x0b7d seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0b64 0b64 fiu_load_var 1 hold_var; Flow J cc=True 0xb62 fiu_tivi_src c mar_0xc seq_br_type 1 Branch True seq_branch_adr 0b62 0x0b62 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1c DEC_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU 0b65 0b65 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xb68 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0b68 0x0b68 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 0b66 0b66 seq_br_type 3 Unconditional Branch; Flow J 0xb5f seq_branch_adr 0b5f 0x0b5f seq_en_micro 0 val_a_adr 21 VR04:01 val_alu_func 7 INC_A val_c_adr 1e VR04:01 val_c_mux_sel 2 ALU val_frame 4 0b67 0b67 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0x32d3 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32d3 0x32d3 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR04:1c val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b68 0b68 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 3d TR11:1d typ_frame 11 0b69 0b69 fiu_load_var 1 hold_var; Flow C 0xb78 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 0b78 0x0b78 seq_en_micro 0 0b6a 0b6a ioc_adrbs 1 val ; Flow R ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0b6b ; -------------------------------------------------------------------------------------- 0b6b ; Comes from: 0b6b ; 0b32 C from color 0x0b32 0b6b ; -------------------------------------------------------------------------------------- 0b6b 0b6b fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0b6c 0b6c fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0xb74 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 7 Unconditional Call seq_branch_adr 0b74 0x0b74 seq_en_micro 0 typ_b_adr 3d TR11:1d typ_frame 11 0b6d 0b6d ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32d3 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d3 0x32d3 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0b6e 0b6e ioc_adrbs 1 val ; Flow C 0x34cd seq_br_type 7 Unconditional Call seq_branch_adr 34cd 0x34cd seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0e GP0e val_alu_func 0 PASS_A 0b6f 0b6f seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32d3 seq_br_type 9 Return False seq_branch_adr 32d3 0x32d3 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0b70 0b70 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 3d TR11:1d typ_frame 11 val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 36 VR05:16 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0b71 0b71 fiu_len_fill_lit 55 zero-fill 0x15; Flow C 0x32f5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32f5 0x32f5 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 8 LOAD_MAR_SYSTEM typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 19 X_XOR_B val_b_adr 10 TOP 0b72 0b72 fiu_fill_mode_src 0 ; Flow C cc=False 0x211 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0b73 0b73 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR08:01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 8 0b74 ; -------------------------------------------------------------------------------------- 0b74 ; Comes from: 0b74 ; 0b53 C from color 0x0b53 0b74 ; 0b5f C from color 0x0000 0b74 ; 0b6c C from color 0x0000 0b74 ; -------------------------------------------------------------------------------------- 0b74 0b74 fiu_len_fill_lit 55 zero-fill 0x15 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 8 LOAD_MAR_SYSTEM 0b75 0b75 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0b76 0b76 fiu_fill_mode_src 0 ; Flow C cc=False 0x211 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 35 VR09:15 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 9 0b77 0b77 fiu_len_fill_lit 55 zero-fill 0x15; Flow R fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type a Unconditional Return seq_en_micro 0 val_a_adr 0f GP0f 0b78 ; -------------------------------------------------------------------------------------- 0b78 ; Comes from: 0b78 ; 0b5d C from color 0x0b53 0b78 ; 0b69 C from color 0x0000 0b78 ; -------------------------------------------------------------------------------------- 0b78 0b78 fiu_len_fill_lit 55 zero-fill 0x15 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 8 LOAD_MAR_SYSTEM val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0b79 0b79 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0e GP0e 0b7a 0b7a fiu_fill_mode_src 0 ; Flow C cc=False 0x211 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0b7b 0b7b ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0b7c 0b7c fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type a Unconditional Return seq_en_micro 0 val_a_adr 0e GP0e 0b7d ; -------------------------------------------------------------------------------------- 0b7d ; Comes from: 0b7d ; 0b57 C from color 0x0b53 0b7d ; 0b63 C from color 0x0000 0b7d ; -------------------------------------------------------------------------------------- 0b7d 0b7d seq_br_type 7 Unconditional Call; Flow C 0xb85 seq_branch_adr 0b85 0x0b85 seq_en_micro 0 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0b7e 0b7e fiu_tivi_src c mar_0xc; Flow J cc=True 0xb82 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0b82 0x0b82 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 5 0b7f 0b7f fiu_tivi_src c mar_0xc; Flow C 0xb85 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b85 0x0b85 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0b80 0b80 fiu_tivi_src c mar_0xc; Flow C 0xb85 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b85 0x0b85 seq_en_micro 0 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0b81 0b81 fiu_tivi_src c mar_0xc; Flow C 0xb85 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0b85 0x0b85 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 0b82 0b82 seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 0b83 0x0b83 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 19 X_XOR_B typ_b_adr 0c GP0c val_a_adr 0b GP0b val_alu_func 19 X_XOR_B val_b_adr 0c GP0c 0b83 0b83 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0b84 0x0b84 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 6 A_MINUS_B typ_b_adr 0c GP0c val_a_adr 0c GP0c val_alu_func 5 DEC_A_MINUS_B val_b_adr 0b GP0b 0b84 0b84 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0b85 ; -------------------------------------------------------------------------------------- 0b85 ; Comes from: 0b85 ; 0b7d C from color 0x0b7d 0b85 ; 0b7f C from color 0x0b7d 0b85 ; 0b80 C from color 0x0b7d 0b85 ; 0b81 C from color 0x0b7d 0b85 ; -------------------------------------------------------------------------------------- 0b85 0b85 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 0b86 0b86 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 12 start_lru_query fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0b87 0b87 seq_b_timing 0 Early Condition; Flow J cc=True 0xb8b seq_br_type 1 Branch True seq_branch_adr 0b8b 0x0b8b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0b88 0b88 fiu_mem_start f start_physical_tag_rd; Flow C 0x352c fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 352c 0x352c seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b89 0b89 fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 12 start_lru_query fiu_offs_lit 7a fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 val_rand 2 DEC_LOOP_COUNTER 0b8a 0b8a seq_b_timing 0 Early Condition; Flow J cc=False 0xb88 seq_br_type 0 Branch False seq_branch_adr 0b88 0x0b88 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func c PASS_A_ELSE_INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0b8b 0b8b fiu_mem_start f start_physical_tag_rd; Flow C 0x352c fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 352c 0x352c seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0b8c 0b8c fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 7a fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0b8d 0b8d fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 2e TR0c:0e typ_frame c typ_mar_cntl 4 RESTORE_MAR val_a_adr 2e VR0c:0e val_alu_func 0 PASS_A val_frame c 0b8e 0b8e seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func c PASS_A_ELSE_INC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0b8f 0b8f seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0c GP0c 0b90 0b90 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 0f GP0f typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 0f GP0f val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0b91 0b91 <halt> ; Flow R 0b92 ; -------------------------------------------------------------------------------------- 0b92 ; Comes from: 0b92 ; 0879 C from color 0x0821 0b92 ; -------------------------------------------------------------------------------------- 0b92 0b92 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 2d TR1d:0d typ_frame 1d val_c_adr 04 VR0d:1b val_c_source 0 FIU_BUS val_frame d 0b93 0b93 fiu_tivi_src c mar_0xc ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 09 TR0d:16 typ_c_mux_sel 0 ALU typ_frame d 0b94 0b94 fiu_tivi_src 4 fiu_var; Flow R ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 34 TR0d:14 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0b TR0d:14 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 34 VR02:14 val_frame 2 0b95 0b95 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xba4 seq_br_type 1 Branch True seq_branch_adr 0ba4 0x0ba4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 0b96 0b96 ioc_fiubs 1 val ; Flow C 0x2ab4 seq_br_type 7 Unconditional Call seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 3b VR0d:1b val_frame d 0b97 0b97 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 39 TR0d:19 typ_alu_func 0 PASS_A typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0b98 0b98 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 26 TR05:06 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR02:11 val_frame 2 0b99 0b99 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0b TR0d:14 typ_c_mux_sel 0 ALU typ_frame d typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0b9a 0b9a fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 39 TR0d:19 typ_alu_func 0 PASS_A typ_c_adr 02 TR0d:1d typ_c_source 0 FIU_BUS typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0b9b 0b9b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 0a TR0d:15 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 01 GP01 val_b_adr 01 GP01 0b9c 0b9c fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=False 0xba3 fiu_offs_lit 36 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0ba3 0x0ba3 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0b TR0d:14 typ_c_mux_sel 0 ALU typ_frame d val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0b9d 0b9d fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 12 TR1d:0d typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_frame 5 0b9e 0b9e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3a VR08:1a val_frame 8 0b9f 0b9f fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 36 TR0d:16 typ_frame d 0ba0 0ba0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_frame 2 0ba1 0ba1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 0a VR0d:15 val_c_source 0 FIU_BUS val_frame d 0ba2 0ba2 fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_en_micro 0 typ_mar_cntl 5 RESTORE_MAR_REFRESH val_a_adr 35 VR0d:15 val_alu_func 1c DEC_A val_c_adr 0a VR0d:15 val_c_mux_sel 2 ALU val_frame d 0ba3 0ba3 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0xbaa seq_br_type 8 Return True seq_branch_adr 0baa 0x0baa seq_en_micro 0 val_a_adr 35 VR0d:15 val_alu_func 0 PASS_A val_c_adr 0b VR0d:14 val_c_mux_sel 2 ALU val_frame d 0ba4 0ba4 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 12 TR1d:0d typ_c_source 0 FIU_BUS typ_frame 1d val_a_adr 3b VR0d:1b val_frame d 0ba5 0ba5 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 34 TR0d:14 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0b TR0d:14 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 3e VR05:1e val_frame 5 0ba6 0ba6 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 39 TR0d:19 typ_alu_func 0 PASS_A typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0ba7 0ba7 fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 35 TR0d:15 typ_b_adr 34 TR0d:14 typ_frame d typ_mar_cntl 6 INCREMENT_MAR 0ba8 0ba8 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 3d TR0d:1d typ_frame d val_b_adr 39 VR02:19 val_frame 2 0ba9 0ba9 fiu_tivi_src 8 type_var; Flow C 0x2ab4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 typ_b_adr 36 TR0d:16 typ_frame d typ_mar_cntl 5 RESTORE_MAR_REFRESH 0baa 0baa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0bab ; -------------------------------------------------------------------------------------- 0bab ; Comes from: 0bab ; 013a C from color ME_REFRESH 0bab ; 364d C True from color 0x364d 0bab ; -------------------------------------------------------------------------------------- 0bab 0bab fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xbad fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0bad 0x0bad seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 14 ZEROS typ_c_adr 0d TR0d:12 typ_frame d val_a_adr 24 VR09:04 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 9 0bac 0bac fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 30 TR12:10 typ_frame 12 0bad 0bad fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 38 TR0d:18 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0bae 0bae fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=True 0xbaf ; Flow J cc=#0x0 0xbb2 fiu_load_var 1 hold_var fiu_offs_lit 4b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 0bb2 0x0bb2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 34 TR0d:14 typ_c_adr 0f TR0d:10 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 0f GP0f val_alu_func 0 PASS_A val_c_adr 0f VR0d:10 val_c_mux_sel 2 ALU val_frame d 0baf 0baf ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 35 TR0d:15 typ_alu_func 7 INC_A typ_b_adr 0f GP0f typ_c_adr 0a TR0d:15 typ_c_mux_sel 0 ALU typ_frame d val_b_adr 0f GP0f val_c_adr 0d VR0d:12 val_frame d 0bb0 0bb0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xbb6 seq_br_type 0 Branch False seq_branch_adr 0bb6 0x0bb6 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_frame d 0bb1 0bb1 fiu_len_fill_lit 4a zero-fill 0xa; Flow J 0xbd4 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0bd4 0x0bd4 seq_en_micro 0 typ_c_adr 04 TR0d:1b typ_c_source 0 FIU_BUS typ_frame d 0bb2 0bb2 fiu_mem_start 3 start-wr; Flow J 0xbaf ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0baf 0x0baf seq_en_micro 0 typ_a_adr 2f TR08:0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bb3 0bb3 fiu_mem_start 3 start-wr; Flow J 0xbaf ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0baf 0x0baf seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bb4 0bb4 fiu_mem_start 3 start-wr; Flow J 0xbaf ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0baf 0x0baf seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 0bb5 0bb5 fiu_mem_start 3 start-wr; Flow J 0xbaf ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0baf 0x0baf seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0bb6 0bb6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xbd2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0bd2 0x0bd2 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 36 VR0d:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0bb7 0bb7 fiu_tivi_src 1 tar_val; Flow J cc=False 0xbbe ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0bbe 0x0bbe seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0bb8 0bb8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bb9 0bb9 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0xbd2 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0bd2 0x0bd2 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 33 TR0d:13 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bba 0bba fiu_len_fill_lit 7a zero-fill 0x3a; Flow J cc=True 0xbc5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 0bc5 0x0bc5 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 37 TR0d:17 typ_alu_func 1e A_AND_B typ_b_adr 0f GP0f typ_frame d 0bbb 0bbb fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xbbf fiu_mem_start 3 start-wr fiu_offs_lit 40 seq_br_type 1 Branch True seq_branch_adr 0bbf 0x0bbf seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 33 TR0d:13 typ_alu_func 1c DEC_A typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 33 VR0d:13 val_alu_func 7 INC_A val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bbc 0bbc fiu_mem_start 8 start_wr_if_false; Flow J 0xbbd fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0bbd 0x0bbd seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 14 ZEROS typ_alu_func 7 INC_A typ_b_adr 34 TR0d:14 typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame d typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR0d:13 val_alu_func 1c DEC_A val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bbd 0bbd ioc_load_wdr 0 ; Flow J 0xbd2 seq_br_type 3 Unconditional Branch seq_branch_adr 0bd2 0x0bd2 seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bbe 0bbe fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bbf 0bbf fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0xbd2 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 1 Branch True seq_branch_adr 0bd2 0x0bd2 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 33 VR0d:13 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame d 0bc0 0bc0 fiu_len_fill_lit 7a zero-fill 0x3a; Flow J cc=True 0xbc5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 0bc5 0x0bc5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 37 VR0d:17 val_alu_func 1e A_AND_B val_b_adr 0f GP0f val_frame d 0bc1 0bc1 fiu_mem_start 3 start-wr; Flow J cc=True 0xbc3 ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0bc3 0x0bc3 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 33 VR0d:13 val_alu_func 1c DEC_A val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bc2 0bc2 fiu_mem_start 8 start_wr_if_false; Flow J 0xbbd fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0bbd 0x0bbd seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_b_adr 34 TR0d:14 typ_frame d val_a_adr 14 ZEROS val_alu_func 7 INC_A val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame d val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0bc3 0bc3 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bc4 0bc4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xbb7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0bb7 0x0bb7 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 36 VR0d:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0bc5 0bc5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xbd2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0bd2 0x0bd2 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR0d:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame d 0bc6 0bc6 fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 14 ZEROS 0bc7 0bc7 fiu_fill_mode_src 0 ; Flow C cc=False 0x20a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0bc8 0bc8 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0bc9 0bc9 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 5 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0bca 0bca fiu_len_fill_lit 53 zero-fill 0x13 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0bcb 0bcb fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 0bcc 0bcc seq_b_timing 0 Early Condition; Flow J cc=True 0xbcd ; Flow J cc=#0x0 0xbcd seq_br_type b Case False seq_branch_adr 0bcd 0x0bcd seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0bcd 0bcd fiu_mem_start 3 start-wr; Flow J 0xbd1 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bd1 0x0bd1 seq_en_micro 0 typ_a_adr 2f TR08:0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bce 0bce fiu_mem_start 3 start-wr; Flow J 0xbd1 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bd1 0x0bd1 seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0bcf 0bcf fiu_mem_start 3 start-wr; Flow J 0xbd1 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bd1 0x0bd1 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 0bd0 0bd0 fiu_mem_start 3 start-wr; Flow J 0xbd1 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0bd1 0x0bd1 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0bd1 0bd1 ioc_load_wdr 0 ; Flow J 0xbd2 seq_br_type 3 Unconditional Branch seq_branch_adr 0bd2 0x0bd2 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 0bd2 0bd2 ioc_load_wdr 0 ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0bd3 0x0bd3 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 30 TR0d:10 typ_alu_func 0 PASS_A typ_b_adr 32 TR0d:12 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d val_a_adr 30 VR0d:10 val_alu_func 0 PASS_A val_b_adr 32 VR0d:12 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame d 0bd3 0bd3 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 0bd4 0bd4 fiu_tivi_src 1 tar_val; Flow C 0xbea ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 0bea 0x0bea seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0bd5 0bd5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR02:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0bd6 0bd6 seq_en_micro 0 0bd7 0bd7 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xbe7 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0be7 0x0be7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 0bd8 0bd8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xbdf fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0bdf 0x0bdf seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 03 VR0d:1c val_c_source 0 FIU_BUS val_frame d 0bd9 0bd9 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0xc04 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0c04 0x0c04 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3d VR0d:1d val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame d 0bda 0bda seq_en_micro 0 0bdb 0bdb fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0xbe7 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0be7 0x0be7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0bdc 0bdc fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 03 VR0d:1c val_c_mux_sel 2 ALU val_frame d 0bdd 0bdd fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=False 0xbe7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0be7 0x0be7 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0bde 0bde fiu_mem_start 2 start-rd; Flow J cc=False 0xbe7 ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 0 Branch False seq_branch_adr 0be7 0x0be7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR0d:1c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0bdf 0bdf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xbe7 seq_br_type 1 Branch True seq_branch_adr 0be7 0x0be7 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3b TR0d:1b typ_alu_func 1c DEC_A typ_c_adr 04 TR0d:1b typ_c_mux_sel 0 ALU typ_frame d 0be0 0be0 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0xbe7 seq_br_type 0 Branch False seq_branch_adr 0be7 0x0be7 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0be1 0be1 fiu_tivi_src c mar_0xc; Flow C 0xbea ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0bea 0x0bea seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 02 VR0d:1d val_c_mux_sel 2 ALU val_frame d 0be2 0be2 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3a VR0d:1a val_alu_func 1 A_PLUS_B val_b_adr 3d VR0d:1d val_frame d 0be3 0be3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xbe7 seq_br_type 1 Branch True seq_branch_adr 0be7 0x0be7 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 3d VR0d:1d val_alu_func 6 A_MINUS_B val_b_adr 3a VR0d:1a val_c_adr 02 VR0d:1d val_c_mux_sel 2 ALU val_frame d 0be4 0be4 seq_br_type 0 Branch False; Flow J cc=False 0xbe7 seq_branch_adr 0be7 0x0be7 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0be5 0be5 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0xbd9 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0bd9 0x0bd9 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 22 TR01:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 39 VR0d:19 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d 0be6 0be6 fiu_mem_start 2 start-rd; Flow J cc=True 0xbdf ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 1 Branch True seq_branch_adr 0bdf 0x0bdf seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR0d:1c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0be7 0be7 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0be8 0be8 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 0be9 0be9 seq_br_type 3 Unconditional Branch; Flow J 0xc04 seq_branch_adr 0c04 0x0c04 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_a_adr 3d TR0d:1d typ_alu_func 7 INC_A typ_c_adr 02 TR0d:1d typ_c_mux_sel 0 ALU typ_frame d 0bea 0bea fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_var 1 hold_var fiu_offs_lit 4b fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 0beb 0beb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xbee fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0bee 0x0bee seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 37 TR0d:17 typ_alu_func 1e A_AND_B typ_b_adr 0f GP0f typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 36 VR0d:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0bec 0bec fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 14 ZEROS typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bed 0bed ioc_load_wdr 0 ; Flow J 0xc04 seq_br_type 3 Unconditional Branch seq_branch_adr 0c04 0x0c04 seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bee 0bee seq_b_timing 0 Early Condition; Flow J cc=False 0xbf3 seq_br_type 0 Branch False seq_branch_adr 0bf3 0x0bf3 seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 0bef 0bef fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 0bf0 0x0bf0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bf0 0bf0 fiu_mem_start 3 start-wr ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bf1 0bf1 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xc03 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0c03 0x0c03 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 33 TR0d:13 typ_c_adr 01 TR0d:1e typ_c_mux_sel 0 ALU typ_frame d val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0bf2 0bf2 fiu_len_fill_lit 7a zero-fill 0x3a; Flow R cc=False ; Flow J cc=True 0xbf7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 9 Return False seq_branch_adr 0bf7 0x0bf7 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 37 TR0d:17 typ_alu_func 1e A_AND_B typ_b_adr 3e TR0d:1e typ_frame d 0bf3 0bf3 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 0bf4 0x0bf4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0c TR0d:13 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0c VR0d:13 val_c_mux_sel 2 ALU val_frame d 0bf4 0bf4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 33 TR0d:13 typ_frame d val_b_adr 33 VR0d:13 val_frame d 0bf5 0bf5 ioc_tvbs 2 fiu+val; Flow J cc=True 0xc03 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0c03 0x0c03 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 33 VR0d:13 val_c_adr 01 VR0d:1e val_c_mux_sel 2 ALU val_frame d 0bf6 0bf6 fiu_len_fill_lit 7a zero-fill 0x3a; Flow R cc=False fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 9 Return False seq_branch_adr 0bf7 0x0bf7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 37 VR0d:17 val_alu_func 1e A_AND_B val_b_adr 3e VR0d:1e val_frame d 0bf7 0bf7 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR0d:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame d 0bf8 0bf8 fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_b_adr 0f GP0f 0bf9 0bf9 fiu_fill_mode_src 0 ; Flow C cc=False 0x20a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0bfa 0bfa fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0bfb 0bfb fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 5 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0bfc 0bfc fiu_len_fill_lit 53 zero-fill 0x13 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0bfd 0bfd fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 0bfe 0bfe seq_b_timing 0 Early Condition; Flow J cc=True 0xbff ; Flow J cc=#0x0 0xbff seq_br_type b Case False seq_branch_adr 0bff 0x0bff seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0bff 0bff fiu_mem_start 3 start-wr; Flow J 0xc03 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c03 0x0c03 seq_en_micro 0 typ_a_adr 2f TR08:0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0c00 0c00 fiu_mem_start 3 start-wr; Flow J 0xc03 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c03 0x0c03 seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0c01 0c01 fiu_mem_start 3 start-wr; Flow J 0xc03 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c03 0x0c03 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 0c02 0c02 fiu_mem_start 3 start-wr; Flow J 0xc03 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c03 0x0c03 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0c03 0c03 ioc_load_wdr 0 ; Flow J 0xc04 seq_br_type 3 Unconditional Branch seq_branch_adr 0c04 0x0c04 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 0f GP0f val_b_adr 0f GP0f 0c04 0c04 ioc_load_wdr 0 ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0c05 0x0c05 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 30 TR0d:10 typ_alu_func 0 PASS_A typ_b_adr 32 TR0d:12 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d val_a_adr 30 VR0d:10 val_alu_func 0 PASS_A val_b_adr 32 VR0d:12 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame d 0c05 0c05 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 0c06 ; -------------------------------------------------------------------------------------- 0c06 ; 0x021f Execute Heap_Access,Equal 0c06 ; -------------------------------------------------------------------------------------- 0c06 MACRO_Execute_Heap_Access,Equal: 0c06 0c06 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c06 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0c07 0c07 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0c08 ; -------------------------------------------------------------------------------------- 0c08 ; 0x021e Execute Heap_Access,Maximum 0c08 ; -------------------------------------------------------------------------------------- 0c08 MACRO_Execute_Heap_Access,Maximum: 0c08 0c08 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c08 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0c09 0c09 <halt> ; Flow R 0c0a ; -------------------------------------------------------------------------------------- 0c0a ; 0x021d Execute Heap_Access,Is_Null 0c0a ; -------------------------------------------------------------------------------------- 0c0a MACRO_Execute_Heap_Access,Is_Null: 0c0a 0c0a dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c0a fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 0c0b 0c0b <halt> ; Flow R 0c0c ; -------------------------------------------------------------------------------------- 0c0c ; 0x021c Execute Heap_Access,Not_Null 0c0c ; -------------------------------------------------------------------------------------- 0c0c MACRO_Execute_Heap_Access,Not_Null: 0c0c 0c0c dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c0c fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 0c0d 0c0d <halt> ; Flow R 0c0e ; -------------------------------------------------------------------------------------- 0c0e ; 0x021b Execute Heap_Access,Set_Null 0c0e ; -------------------------------------------------------------------------------------- 0c0e MACRO_Execute_Heap_Access,Set_Null: 0c0e 0c0e dispatch_brk_class 8 ; Flow J cc=True 0xc12 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c0e fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0c12 0x0c12 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_lit 2 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0c0f 0c0f fiu_mem_start 5 start_rd_if_true; Flow C 0x32d7 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 0c10 0c10 fiu_load_tar 1 hold_tar; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 0c11 0c11 ioc_load_wdr 0 ; Flow J 0xc07 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0c07 0x0c07 val_b_adr 39 VR02:19 val_frame 2 0c12 0c12 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x32a9 fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 10 TOP 0c13 0c13 fiu_load_mdr 1 hold_mdr; Flow J cc=False 0xc15 fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c15 0x0c15 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 39 VR02:19 val_frame 2 0c14 0c14 fiu_fill_mode_src 0 ; Flow J 0xc18 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c18 0x0c18 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0c15 0c15 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c16 0c16 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0c17 0c17 fiu_load_var 1 hold_var; Flow J 0xc18 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c18 0x0c18 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0c18 0c18 ioc_load_wdr 0 ; Flow J 0xc07 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c07 0x0c07 0c19 0c19 <halt> ; Flow R 0c1a ; -------------------------------------------------------------------------------------- 0c1a ; 0x021a Execute Heap_Access,Element_Type 0c1a ; -------------------------------------------------------------------------------------- 0c1a MACRO_Execute_Heap_Access,Element_Type: 0c1a 0c1a dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0c1a dispatch_uses_tos 1 typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL 0c1b 0c1b fiu_load_tar 1 hold_tar; Flow J cc=False 0xc1e fiu_mem_start 5 start_rd_if_true fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0c1e 0x0c1e seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE 0c1c 0c1c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 0c1d 0c1d fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator 0c1e 0c1e fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 0c1f 0x0c1f seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c1f 0c1f seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_en_micro 0 seq_random 02 ? 0c20 ; -------------------------------------------------------------------------------------- 0c20 ; 0x0219 Execute Heap_Access,All_Read 0c20 ; -------------------------------------------------------------------------------------- 0c20 MACRO_Execute_Heap_Access,All_Read: 0c20 0c20 dispatch_brk_class 8 ; Flow C cc=True 0x32a1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0c20 dispatch_uses_tos 1 ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a1 0x32a1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 20 VR07:00 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 7 0c21 0c21 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xc27 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0c27 0x0c27 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0c22 0c22 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0c23 0c23 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xc25 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c25 0x0c25 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 0c24 0c24 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0xc28 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0c28 0x0c28 seq_random 04 Load_save_offset+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c25 0c25 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c26 0c26 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0xc28 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0c28 0x0c28 seq_random 04 Load_save_offset+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c27 0c27 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c28 0c28 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0c29 0x0c29 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0c29 0c29 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c2a ; -------------------------------------------------------------------------------------- 0c2a ; 0x0218 Execute Heap_Access,All_Write 0c2a ; -------------------------------------------------------------------------------------- 0c2a MACRO_Execute_Heap_Access,All_Write: 0c2a 0c2a dispatch_brk_class 2 ; Flow C cc=True 0x32a1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0c2a dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a1 0x32a1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0c2b 0c2b fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d78 0x1d78 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0c2c 0c2c fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0c2d 0c2d fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 0c2e 0c2e fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d78 0x1d78 0c2f 0c2f <halt> ; Flow R 0c30 ; -------------------------------------------------------------------------------------- 0c30 ; 0x0217 Execute Heap_Access,All_Reference 0c30 ; -------------------------------------------------------------------------------------- 0c30 MACRO_Execute_Heap_Access,All_Reference: 0c30 0c30 dispatch_brk_class 8 ; Flow C cc=True 0x32a1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 0c30 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a1 0x32a1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0c31 0c31 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 0c32 ; -------------------------------------------------------------------------------------- 0c32 ; 0x0216 Execute Heap_Access,Convert 0c32 ; -------------------------------------------------------------------------------------- 0c32 MACRO_Execute_Heap_Access,Convert: 0c32 0c32 dispatch_brk_class 4 ; Flow J cc=True 0xc34 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c32 seq_br_type 1 Branch True seq_branch_adr 0c34 0x0c34 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand 8 SPARE_0x08 0c33 0c33 seq_br_type 7 Unconditional Call; Flow C 0x24c4 seq_branch_adr 24c4 0x24c4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0c34 0c34 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xc4b ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0c4b 0x0c4b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0c35 0c35 <halt> ; Flow R 0c36 ; -------------------------------------------------------------------------------------- 0c36 ; 0x0211 Execute Heap_Access,Convert_Reference 0c36 ; -------------------------------------------------------------------------------------- 0c36 MACRO_Execute_Heap_Access,Convert_Reference: 0c36 0c36 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c36 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0c37 0c37 typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1b A_OR_B val_b_adr 3e VR03:1e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 3 0c38 0c38 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 0c39 0c39 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL 0c3a 0c3a fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 0c3b 0x0c3b seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c3b 0c3b seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 typ_csa_cntl 3 POP_CSA 0c3c ; -------------------------------------------------------------------------------------- 0c3c ; 0x0215 Execute Heap_Access,In_Type 0c3c ; -------------------------------------------------------------------------------------- 0c3c MACRO_Execute_Heap_Access,In_Type: 0c3c 0c3c dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c3c fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c3d 0x0c3d seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0c3d 0c3d ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c3e 0c3e typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0c3f 0c3f seq_br_type 7 Unconditional Call; Flow C 0x24c4 seq_branch_adr 24c4 0x24c4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0c40 0c40 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0c41 0c41 <halt> ; Flow R 0c42 ; -------------------------------------------------------------------------------------- 0c42 ; 0x0214 Execute Heap_Access,Not_In_Type 0c42 ; -------------------------------------------------------------------------------------- 0c42 MACRO_Execute_Heap_Access,Not_In_Type: 0c42 0c42 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c42 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c43 0x0c43 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0c43 0c43 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c44 0c44 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 0c45 0c45 seq_br_type 7 Unconditional Call; Flow C 0x24c4 seq_branch_adr 24c4 0x24c4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0c46 0c46 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0c47 0c47 <halt> ; Flow R 0c48 ; -------------------------------------------------------------------------------------- 0c48 ; 0x0213 Execute Heap_Access,Check_In_Type 0c48 ; -------------------------------------------------------------------------------------- 0c48 MACRO_Execute_Heap_Access,Check_In_Type: 0c48 0c48 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c48 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0c49 0x0c49 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 0c49 0c49 seq_br_type 7 Unconditional Call; Flow C 0x24c4 seq_branch_adr 24c4 0x24c4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0c4a 0c4a fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 0c4b 0x0c4b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 0c4b 0c4b fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 11 TOP + 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 0c4c 0c4c <default> 0c4d 0c4d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a4 0x32a4 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c 0c4e 0c4e seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 0c4f 0c4f <halt> ; Flow R 0c50 ; -------------------------------------------------------------------------------------- 0c50 ; 0x0212 Execute Heap_Access,Address 0c50 ; -------------------------------------------------------------------------------------- 0c50 MACRO_Execute_Heap_Access,Address: 0c50 0c50 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c50 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL 0c51 0c51 <halt> ; Flow R 0c52 ; -------------------------------------------------------------------------------------- 0c52 ; 0x0210 Execute Heap_Access,Get_Segment 0c52 ; -------------------------------------------------------------------------------------- 0c52 MACRO_Execute_Heap_Access,Get_Segment: 0c52 0c52 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c52 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0c53 0c53 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 30 TR0b:10 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c54 ; -------------------------------------------------------------------------------------- 0c54 ; 0x0144 Execute Heap_Access,Get_Name 0c54 ; -------------------------------------------------------------------------------------- 0c54 MACRO_Execute_Heap_Access,Get_Name: 0c54 0c54 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c54 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 0c55 0c55 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c56 ; -------------------------------------------------------------------------------------- 0c56 ; 0x0148 Execute Heap_Access,Get_Offset 0c56 ; -------------------------------------------------------------------------------------- 0c56 MACRO_Execute_Heap_Access,Get_Offset: 0c56 0c56 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c56 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0c57 0c57 <halt> ; Flow R 0c58 ; -------------------------------------------------------------------------------------- 0c58 ; 0x0147 Execute Heap_Access,Construct_Segment 0c58 ; -------------------------------------------------------------------------------------- 0c58 MACRO_Execute_Heap_Access,Construct_Segment: 0c58 0c58 dispatch_brk_class 8 ; Flow C cc=True 0x32e1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c58 fiu_len_fill_lit 55 zero-fill 0x15 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32e1 0x32e1 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 21 VR08:01 val_frame 8 0c59 0c59 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32e1 fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32e1 0x32e1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 0c5a 0c5a fiu_len_fill_lit 49 zero-fill 0x9; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 56 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 30 TR0b:10 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0c5b 0c5b <halt> ; Flow R 0c5c ; -------------------------------------------------------------------------------------- 0c5c ; 0x0146 Execute Heap_Access,Hash 0c5c ; -------------------------------------------------------------------------------------- 0c5c MACRO_Execute_Heap_Access,Hash: 0c5c 0c5c dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c5c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0c5d 0c5d ioc_tvbs 1 typ+fiu typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c5e 0c5e fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 0c5f 0x0c5f seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 30 TR06:10 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR06:16 val_frame 6 0c5f 0c5f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c60 ; -------------------------------------------------------------------------------------- 0c60 ; 0x0070-0x0074 QQUnknown InMicrocode 0c60 ; 0x0145 Execute Heap_Access,Diana_Tree_Kind 0c60 ; -------------------------------------------------------------------------------------- 0c60 MACRO_0c60_QQUnknown_InMicrocode: 0c60 MACRO_Execute_Heap_Access,Diana_Tree_Kind: 0c60 0c60 dispatch_brk_class 8 ; Flow J cc=True 0xc65 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c60 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0c65 0x0c65 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 26 VR05:06 val_frame 5 0c61 0c61 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xc63 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c63 0x0c63 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR 0c62 0c62 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c63 0c63 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c64 0c64 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c65 0c65 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0c66 0c66 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x32d9 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c67 ; -------------------------------------------------------------------------------------- 0c67 ; Comes from: 0c67 ; 0c72 C from color MACRO_Execute_Discrete,Diana_Map_Kind_To_Vci 0c67 ; 0c76 C from color MACRO_Execute_Discrete,Diana_Arity_For_Kind 0c67 ; 0c78 C from color MACRO_Execute_Discrete,Diana_Spare0 0c67 ; 0c7a C from color MACRO_Execute_Discrete,Diana_Spare2 0c67 ; 0c7c C from color 0x0000 0c67 ; 0c97 C from color 0x0000 0c67 ; -------------------------------------------------------------------------------------- 0c67 0c67 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x329e fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 329e 0x329e seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2b TR09:0b typ_frame 9 val_a_adr 05 GP05 0c68 0c68 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0xc69 ; Flow J cc=#0x0 0xc69 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0c69 0x0c69 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2d TR06:0d typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 35 VR06:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 0c69 0c69 fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6a 0c6a fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6b 0c6b fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6c 0c6c fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6d 0c6d fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6e 0c6e fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c6f 0c6f fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c70 0c70 fiu_len_fill_lit 4f zero-fill 0xf; Flow R fiu_load_var 1 hold_var fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return typ_a_adr 33 TR0b:13 typ_alu_func 0 PASS_A typ_b_adr 13 LOOP_REG typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame b val_b_adr 13 LOOP_REG 0c71 0c71 <halt> ; Flow R 0c72 ; -------------------------------------------------------------------------------------- 0c72 ; 0x008f Execute Discrete,Diana_Map_Kind_To_Vci 0c72 ; -------------------------------------------------------------------------------------- 0c72 MACRO_Execute_Discrete,Diana_Map_Kind_To_Vci: 0c72 0c72 dispatch_brk_class 8 ; Flow C 0xc67 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c72 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c67 0x0c67 typ_a_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c73 0c73 fiu_len_fill_lit 46 zero-fill 0x6; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 74 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 0c74 0x0c74 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR12:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0c74 0c74 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR05:16 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0c75 0c75 <halt> ; Flow R 0c76 ; -------------------------------------------------------------------------------------- 0c76 ; 0x008e Execute Discrete,Diana_Arity_For_Kind 0c76 ; -------------------------------------------------------------------------------------- 0c76 MACRO_Execute_Discrete,Diana_Arity_For_Kind: 0c76 0c76 dispatch_brk_class 8 ; Flow C 0xc67 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c76 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c67 0x0c67 typ_a_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c77 0c77 fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c78 ; -------------------------------------------------------------------------------------- 0c78 ; 0x008a Execute Discrete,Diana_Spare0 0c78 ; -------------------------------------------------------------------------------------- 0c78 MACRO_Execute_Discrete,Diana_Spare0: 0c78 0c78 dispatch_brk_class 8 ; Flow C 0xc67 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c78 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c67 0x0c67 typ_a_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c79 0c79 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c7a ; -------------------------------------------------------------------------------------- 0c7a ; 0x0087 Execute Discrete,Diana_Spare2 0c7a ; -------------------------------------------------------------------------------------- 0c7a MACRO_Execute_Discrete,Diana_Spare2: 0c7a 0c7a dispatch_brk_class 8 ; Flow C 0xc67 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0c7a fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c67 0x0c67 typ_a_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c7b 0c7b fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0c7c ; -------------------------------------------------------------------------------------- 0c7c ; 0x008d Execute Heap_Access,Diana_Allocate_Tree_Node 0c7c ; -------------------------------------------------------------------------------------- 0c7c MACRO_Execute_Heap_Access,Diana_Allocate_Tree_Node: 0c7c 0c7c dispatch_brk_class 8 ; Flow C 0xc67 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c7c fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0c67 0x0c67 typ_a_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c7d 0c7d ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 3e VR12:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 12 0c7e 0c7e fiu_tivi_src c mar_0xc; Flow J 0xc7f ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 0c87 0x0c87 typ_a_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 0c7f 0c7f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xc84 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0c84 0x0c84 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR12:1e typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 0c80 0c80 seq_b_timing 1 Latch Condition; Flow J cc=True 0xc83 seq_br_type 1 Branch True seq_branch_adr 0c83 0x0c83 seq_random 05 ? typ_a_adr 20 TR13:00 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 0c81 0c81 fiu_mem_start 2 start-rd; Flow J cc=True 0x35c6 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 35c6 0x35c6 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 3f VR09:1f val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 9 0c82 0c82 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 2c TR0b:0c typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0c83 0c83 fiu_mem_start 2 start-rd; Flow J 0x35c6 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 35c6 0x35c6 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 33 VR05:13 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 5 0c84 0c84 fiu_len_fill_lit 4e zero-fill 0xe fiu_offs_lit 74 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 0c85 0c85 fiu_fill_mode_src 0 ; Flow J cc=False 0x35c6 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 0c86 0c86 seq_br_type 7 Unconditional Call; Flow C 0x35c6 seq_branch_adr 35c6 0x35c6 val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 28 VR13:08 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 13 0c87 0c87 seq_br_type 7 Unconditional Call; Flow C 0x2a5e seq_branch_adr 2a5e 0x2a5e typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 3f TR12:1f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0c88 0c88 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 val_b_adr 10 TOP 0c89 0c89 fiu_len_fill_lit 50 zero-fill 0x10; Flow J cc=True 0xc8b fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0c8b 0x0c8b typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0c8a 0c8a fiu_len_fill_lit 50 zero-fill 0x10 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 0c8b 0c8b fiu_fill_mode_src 0 ; Flow J cc=False 0xc8f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c8f 0x0c8f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0c8c 0c8c fiu_fill_mode_src 0 ; Flow J 0xc8d fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c8d 0x0c8d typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0c8d 0c8d ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 2c TR0b:0c typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0c8e 0c8e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 0c8f 0c8f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 0c90 0c90 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0c91 0c91 fiu_load_var 1 hold_var; Flow J 0xc8d fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c8d 0x0c8d seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0c92 ; -------------------------------------------------------------------------------------- 0c92 ; 0x008c Execute Heap_Access,Diana_Put_Node_On_Seq_Type 0c92 ; -------------------------------------------------------------------------------------- 0c92 MACRO_Execute_Heap_Access,Diana_Put_Node_On_Seq_Type: 0c92 0c92 dispatch_brk_class 8 ; Flow J cc=True 0x32a1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0c92 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a1 0x32a1 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 26 VR05:06 val_frame 5 0c93 0c93 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xc95 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c95 0x0c95 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 29 VR13:09 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 13 0c94 0c94 fiu_fill_mode_src 0 ; Flow J 0xc97 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c97 0x0c97 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0c95 0c95 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c96 0c96 fiu_fill_mode_src 0 ; Flow J 0xc97 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c97 0x0c97 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 0c97 0c97 fiu_len_fill_lit 7c zero-fill 0x3c; Flow C 0xc67 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 0c67 0x0c67 val_a_adr 04 GP04 val_alu_func 1e A_AND_B val_b_adr 24 VR05:04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 0c98 0c98 ioc_fiubs 2 typ ; Flow J cc=True 0xca0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ca0 0x0ca0 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 25 TR13:05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 12 0c99 0c99 fiu_len_fill_lit 5a zero-fill 0x1a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0c9a 0c9a fiu_fill_mode_src 0 ; Flow J cc=False 0xc9d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0c9d 0x0c9d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 0c9b 0c9b fiu_fill_mode_src 0 ; Flow J 0xc9c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0c9c 0x0c9c typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0c9c 0c9c ioc_load_wdr 0 ; Flow J 0xc8e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c8e 0x0c8e typ_a_adr 2e TR0b:0e typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame b val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0c9d 0c9d fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0c9e 0c9e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0c9f 0c9f fiu_load_var 1 hold_var; Flow J 0xc9c fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c9c 0x0c9c seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0ca0 0ca0 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 0ca1 0ca1 fiu_len_fill_lit 59 zero-fill 0x19 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0ca2 0ca2 fiu_fill_mode_src 0 ; Flow J cc=False 0xca6 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0ca6 0x0ca6 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP 0ca3 0ca3 fiu_fill_mode_src 0 ; Flow J 0xca4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0ca4 0x0ca4 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0ca4 0ca4 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 2a VR13:0a val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 13 0ca5 0ca5 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0xc9a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0c9a 0x0c9a typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0ca6 0ca6 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0ca7 0ca7 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0ca8 0ca8 fiu_load_var 1 hold_var; Flow J 0xca4 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0ca4 0x0ca4 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0ca9 0ca9 <halt> ; Flow R 0caa ; -------------------------------------------------------------------------------------- 0caa ; 0x008b Execute Heap_Access,Diana_Seq_Type_Get_Head 0caa ; -------------------------------------------------------------------------------------- 0caa MACRO_Execute_Heap_Access,Diana_Seq_Type_Get_Head: 0caa 0caa dispatch_brk_class 8 ; Flow J cc=True 0xcb3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0caa fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cb3 0x0cb3 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 0cab 0cab val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 28 VR13:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0cac 0cac fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 2c TR0b:0c typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame b val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0cad 0cad fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src 1 tar_val ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 0cae 0x0cae seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_source 0 FIU_BUS 0cae 0cae fiu_len_fill_lit 59 zero-fill 0x19 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0caf 0caf fiu_mem_start a start_continue_if_false; Flow J cc=False 0xcb1 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0cb1 0x0cb1 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0cb0 0cb0 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cb1 0cb1 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0cb2 0cb2 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cb3 0cb3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 2c TR0b:0c typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0cb4 ; -------------------------------------------------------------------------------------- 0cb4 ; 0x0089 Execute Discrete,Diana_Spare1 0cb4 ; -------------------------------------------------------------------------------------- 0cb4 MACRO_Execute_Discrete,Diana_Spare1: 0cb4 0cb4 dispatch_brk_class 8 ; Flow J cc=True 0xcb9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0cb4 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 1e fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cb9 0x0cb9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 29 VR13:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 0cb5 0cb5 fiu_len_fill_lit 7a zero-fill 0x3a; Flow J cc=True 0xcb8 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cb8 0x0cb8 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 1e A_AND_B typ_b_adr 27 TR13:07 typ_frame 13 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 22 VR09:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 9 val_rand 9 PASS_A_HIGH 0cb6 0cb6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_b_adr 38 TR11:18 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0cb7 0cb7 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 2c TR0b:0c typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cb8 0cb8 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32de ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32de 0x32de seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 2c TR0b:0c typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0cb9 0cb9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 2c TR0b:0c typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0cba ; -------------------------------------------------------------------------------------- 0cba ; 0x0088 Execute Heap_Access,Diana_Spare2 0cba ; -------------------------------------------------------------------------------------- 0cba MACRO_Execute_Heap_Access,Diana_Spare2: 0cba 0cba dispatch_brk_class 8 ; Flow J cc=True 0xcd3 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 0cba fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cd3 0x0cd3 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 0cbb 0cbb fiu_mem_start 2 start-rd; Flow J cc=True 0xcd4 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cd4 0x0cd4 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 38 TR05:18 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0cbc 0cbc typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0cbd 0cbd fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1e TOP - 2 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 29 VR13:09 val_alu_func 1e A_AND_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0cbe 0cbe fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xcc2 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0cc2 0x0cc2 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0cbf 0cbf fiu_load_tar 1 hold_tar; Flow C 0x2ab4 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 1e TOP - 2 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 29 VR13:09 val_alu_func 1e A_AND_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0cc0 0cc0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0cc1 0cc1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcc7 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cc7 0x0cc7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 0cc2 0cc2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcc7 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cc7 0x0cc7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 0cc3 0cc3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcc7 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cc7 0x0cc7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 0cc4 0cc4 ioc_load_wdr 0 ; Flow J cc=True 0xcc7 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cc7 0x0cc7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_rand 1 INC_LOOP_COUNTER 0cc5 0cc5 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0xcd5 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0cd5 0x0cd5 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 0cc6 0cc6 seq_br_type 3 Unconditional Branch; Flow J 0xcbf seq_branch_adr 0cbf 0x0cbf 0cc7 0cc7 ioc_fiubs 1 val ioc_load_wdr 0 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_b_adr 32 TR02:12 typ_c_adr 3e GP01 typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 val_rand 2 DEC_LOOP_COUNTER 0cc8 0cc8 fiu_len_fill_lit 65 zero-fill 0x25; Flow J cc=True 0xcca fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0cca 0x0cca seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1e A_AND_B val_b_adr 21 VR05:01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0cc9 0cc9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0cca 0cca ioc_fiubs 1 val ; Flow J cc=True 0xccc seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ccc 0x0ccc typ_c_adr 20 TOP - 0x1 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0ccb 0ccb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0ccc 0ccc fiu_mem_start 2 start-rd; Flow J cc=True 0xccd ; Flow J cc=#0x0 0xccd ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0ccd 0x0ccd seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0ccd 0ccd fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xcd1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd1 0x0cd1 0cce 0cce fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xcd1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd1 0x0cd1 0ccf 0ccf fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xcd1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd1 0x0cd1 0cd0 0cd0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xcd1 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd1 0x0cd1 0cd1 0cd1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 0cd2 0cd2 ioc_load_wdr 0 ; Flow J 0xc8e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0c8e 0x0c8e 0cd3 0cd3 fiu_load_var 1 hold_var; Flow J 0xcd6 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd6 0x0cd6 typ_a_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 29 VR13:09 val_alu_func 1e A_AND_B val_b_adr 1f TOP - 1 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 13 val_rand 9 PASS_A_HIGH 0cd4 0cd4 fiu_load_var 1 hold_var; Flow J 0xcd6 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0cd6 0x0cd6 typ_a_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 31 VR02:11 val_alu_func 1c DEC_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 2 0cd5 0cd5 fiu_load_var 1 hold_var; Flow J 0xcd6 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 0cd6 0x0cd6 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 2 0cd6 0cd6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0cd7 0cd7 <halt> ; Flow R 0cd8 ; -------------------------------------------------------------------------------------- 0cd8 ; 0x0142 Execute Heap_Access,Diana_Find_Permanent_Attribute 0cd8 ; -------------------------------------------------------------------------------------- 0cd8 MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute: 0cd8 0cd8 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0cd8 fiu_len_fill_lit 65 zero-fill 0x25 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 0cd9 0cd9 fiu_len_fill_lit 59 zero-fill 0x19; Flow J cc=True 0xce8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ce8 0x0ce8 typ_a_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2b VR13:0b val_frame 13 val_rand 9 PASS_A_HIGH 0cda 0cda fiu_mem_start a start_continue_if_false; Flow J cc=False 0xcdc ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0cdc 0x0cdc seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0cdb 0cdb fiu_fill_mode_src 0 ; Flow J 0xcde fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0cde 0x0cde typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 10 NOT_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0cdc 0cdc fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0cdd 0cdd fiu_fill_mode_src 0 ; Flow J 0xcde fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0cde 0x0cde typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 10 NOT_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0cde 0cde ioc_fiubs 2 typ ; Flow J cc=True 0xce6 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ce6 0x0ce6 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 0cdf 0cdf fiu_len_fill_lit 65 zero-fill 0x25; Flow J cc=True 0xce9 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ce9 0x0ce9 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR06:17 typ_frame 6 typ_mar_cntl b LOAD_MAR_DATA 0ce0 0ce0 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xce3 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0ce3 0x0ce3 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 0ce1 0ce1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0ce2 0ce2 seq_br_type 3 Unconditional Branch; Flow J 0xcde seq_branch_adr 0cde 0x0cde typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 26 TR13:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 2c VR13:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0ce3 0ce3 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0ce4 0ce4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0ce5 0ce5 seq_br_type 3 Unconditional Branch; Flow J 0xcde seq_branch_adr 0cde 0x0cde typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 26 TR13:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 2c VR13:0c val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 13 0ce6 0ce6 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type d Dispatch False seq_branch_adr 0ce7 0x0ce7 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 32 TR0b:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0ce7 0ce7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 32 TR0b:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0ce8 0ce8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 32 TR0b:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0ce9 0ce9 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B 0cea 0cea seq_br_type 1 Branch True; Flow J cc=True 0xcdf seq_branch_adr 0cdf 0x0cdf seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 29 TR06:09 typ_frame 6 0ceb 0ceb seq_br_type 7 Unconditional Call; Flow C 0x32f5 seq_branch_adr 32f5 0x32f5 0cec ; -------------------------------------------------------------------------------------- 0cec ; 0x0143 Execute Heap_Access,Adaptive_Balanced_Tree_Lookup 0cec ; -------------------------------------------------------------------------------------- 0cec MACRO_Execute_Heap_Access,Adaptive_Balanced_Tree_Lookup: 0cec 0cec dispatch_brk_class 8 ; Flow C 0x332e dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 0cec fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0ced 0ced fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 0cee 0cee fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 0cef 0cef fiu_mem_start 4 continue; Flow J 0xcf0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 0d03 0x0d03 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 0cf0 0cf0 fiu_mem_start 4 continue; Flow J cc=True 0xd02 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d02 0x0d02 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 0cf1 0cf1 fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0cf2 0cf2 fiu_load_tar 1 hold_tar; Flow C cc=True 0x32d9 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_frame 5 0cf3 0cf3 ioc_tvbs 2 fiu+val typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0cf4 0cf4 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0xcf6 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0cf6 0x0cf6 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0cf5 0cf5 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xd02 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d02 0x0d02 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 35 TR07:15 typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0cf6 0cf6 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd00 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d00 0x0d00 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0cf7 0cf7 fiu_fill_mode_src 0 ; Flow R cc=True fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0cf8 0x0cf8 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 0cf8 0cf8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xcfc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0cfc 0x0cfc seq_cond_sel 64 OFFSET_REGISTER_???? typ_mar_cntl 6 INCREMENT_MAR 0cf9 0cf9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xcf5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0cf5 0x0cf5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cfa 0cfa fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcf5 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 0cf5 0x0cf5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cfb 0cfb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 0cfc 0cfc fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0cfd 0cfd fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xcf5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0cf5 0x0cf5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cfe 0cfe fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xcf5 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 0cf5 0x0cf5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0cff 0cff fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d00 0d00 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d01 0d01 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0xcf8 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0cf8 0x0cf8 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 0d02 0d02 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d03 0d03 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B 0d04 0d04 seq_br_type 2 Push (branch address); Flow J 0xd05 seq_branch_adr 0d03 0x0d03 0d05 0d05 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0xcf8 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 0cf8 0x0cf8 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 24 TR05:04 typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 0d06 0d06 seq_br_type 7 Unconditional Call; Flow C 0x32f5 seq_branch_adr 32f5 0x32f5 0d07 0d07 <halt> ; Flow R 0d08 ; -------------------------------------------------------------------------------------- 0d08 ; 0x01be Execute Vector,Hash 0d08 ; -------------------------------------------------------------------------------------- 0d08 MACRO_Execute_Vector,Hash: 0d08 0d08 dispatch_brk_class 8 ; Flow J cc=False 0xd0e dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 0d08 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 0d0e 0x0d0e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 0d09 0d09 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd0b seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d0b 0x0d0b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 0d0a 0d0a fiu_fill_mode_src 0 ; Flow J 0xd0d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d0d 0x0d0d 0d0b 0d0b fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d0c 0d0c fiu_fill_mode_src 0 ; Flow J 0xd0d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d0d 0x0d0d 0d0d 0d0d fiu_len_fill_lit 7c zero-fill 0x3c; Flow J 0xd10 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d10 0x0d10 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0d0e 0d0e fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 0d0f 0d0f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xd10 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d10 0x0d10 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0d10 0d10 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0xd21 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d21 0x0d21 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 0d11 0d11 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 0d12 0d12 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd1d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d1d 0x0d1d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 0d13 0d13 fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0d14 0d14 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd1f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d1f 0x0d1f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 3f VR05:1f val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0d15 0d15 fiu_fill_mode_src 0 ; Flow J 0xd16 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d16 0x0d16 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0d16 0d16 val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3f VR05:1f val_c_adr 3d GP02 val_c_mux_sel 0 ALU << 1 val_frame 5 0d17 0d17 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d18 0d18 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d19 0d19 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 14 ZEROS val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0d1a 0d1a fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type c Dispatch True seq_branch_adr 0d1b 0x0d1b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR06:16 val_frame 6 0d1b 0d1b fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0d1c 0x0d1c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR01:01 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR02:10 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 0d1c 0d1c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 7 INC_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0d1d 0d1d fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d1e 0d1e fiu_fill_mode_src 0 ; Flow J 0xd14 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d14 0x0d14 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0d1f 0d1f fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d20 0d20 fiu_fill_mode_src 0 ; Flow J 0xd16 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d16 0x0d16 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0d21 0d21 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 20 TR08:00 typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA 0d22 0d22 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd26 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d26 0x0d26 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 0d23 0d23 fiu_fill_mode_src 0 ; Flow J 0xd24 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d24 0x0d24 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0d24 0d24 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3f VR05:1f val_c_adr 3d GP02 val_c_mux_sel 0 ALU << 1 val_frame 5 0d25 0d25 ioc_tvbs 1 typ+fiu; Flow J 0xd17 seq_br_type 3 Unconditional Branch seq_branch_adr 0d17 0x0d17 val_a_adr 3f VR05:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0d26 0d26 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d27 0d27 fiu_fill_mode_src 0 ; Flow J 0xd24 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d24 0x0d24 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0d28 ; -------------------------------------------------------------------------------------- 0d28 ; 0x0075 QQUnknown InMicrocode 0d28 ; -------------------------------------------------------------------------------------- 0d28 MACRO_0d28_QQUnknown_InMicrocode: 0d28 0d28 dispatch_brk_class 0 ; Flow J cc=True 0x32a1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 0d28 ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a1 0x32a1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 22 VR11:02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 11 0d29 0d29 ioc_fiubs 1 val ; Flow J cc=True 0x32a1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a1 0x32a1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 1e TOP - 2 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 22 VR11:02 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 11 0d2a 0d2a fiu_mem_start 2 start-rd; Flow J cc=False 0x32dc ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 32dc 0x32dc seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 35 VR13:15 val_frame 13 0d2b 0d2b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x32dc seq_br_type 1 Branch True seq_branch_adr 32dc 0x32dc seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 35 VR09:15 val_frame 9 0d2c 0d2c fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x32db fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 0d2d 0d2d seq_b_timing 3 Late Condition, Hint False; Flow C 0x329e seq_br_type 1 Branch True seq_branch_adr 329e 0x329e seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A 0d2e 0d2e fiu_vmux_sel 1 fill value; Flow J cc=False 0x32d2 ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 32d2 0x32d2 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0d2f 0d2f ioc_tvbs 5 seq+seq; Flow C cc=False 0xd38 seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0d38 0x0d38 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_b_adr 16 CSA/VAL_BUS 0d30 0d30 fiu_mem_start 2 start-rd; Flow J cc=False 0x32cc ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0d31 0d31 fiu_vmux_sel 1 fill value; Flow J cc=False 0x32d2 ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 32d2 0x32d2 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0d32 0d32 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0d33 0d33 ioc_tvbs 5 seq+seq; Flow C cc=False 0xd38 seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0d38 0x0d38 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 04 GP04 typ_b_adr 16 CSA/VAL_BUS 0d34 0d34 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x32cc seq_br_type 0 Branch False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0d35 0d35 ioc_fiubs 1 val typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0d36 0d36 ioc_fiubs 1 val ; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 0d37 0d37 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0d38 ; -------------------------------------------------------------------------------------- 0d38 ; Comes from: 0d38 ; 0d2f C False from color 0x0000 0d38 ; 0d33 C False from color 0x0000 0d38 ; -------------------------------------------------------------------------------------- 0d38 0d38 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return val_b_adr 21 VR02:01 val_frame 2 0d39 0d39 <halt> ; Flow R 0d3a ; -------------------------------------------------------------------------------------- 0d3a ; 0x0076 QQUnknown InMicrocode 0d3a ; -------------------------------------------------------------------------------------- 0d3a MACRO_0d3a_QQUnknown_InMicrocode: 0d3a 0d3a dispatch_brk_class 0 ; Flow J cc=True 0x32a1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 0d3a ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a1 0x32a1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 22 VR11:02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 11 0d3b 0d3b ioc_fiubs 1 val ; Flow J cc=True 0x32a1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32a1 0x32a1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 1e TOP - 2 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 22 VR11:02 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 11 0d3c 0d3c fiu_mem_start 2 start-rd; Flow J cc=False 0x32dc ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 32dc 0x32dc seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 35 VR13:15 val_frame 13 0d3d 0d3d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x32dc seq_br_type 1 Branch True seq_branch_adr 32dc 0x32dc seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 35 VR09:15 val_frame 9 0d3e 0d3e fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x32db fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 0d3f 0d3f seq_b_timing 3 Late Condition, Hint False; Flow C 0x329e seq_br_type 1 Branch True seq_branch_adr 329e 0x329e seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A 0d40 0d40 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xd52 seq_br_type 1 Branch True seq_branch_adr 0d52 0x0d52 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A 0d41 0d41 seq_b_timing 3 Late Condition, Hint False; Flow C 0x329e seq_br_type 1 Branch True seq_branch_adr 329e 0x329e seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 0d42 0d42 fiu_vmux_sel 1 fill value; Flow J cc=False 0x32d2 ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 32d2 0x32d2 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0d43 0d43 ioc_tvbs 5 seq+seq; Flow C cc=False 0xd56 seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0d56 0x0d56 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_b_adr 16 CSA/VAL_BUS 0d44 0d44 fiu_mem_start 2 start-rd; Flow J cc=False 0x32ac ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 32ac 0x32ac seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0d45 0d45 fiu_vmux_sel 1 fill value; Flow J cc=False 0x32d2 ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 32d2 0x32d2 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0d46 0d46 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0d47 0d47 ioc_tvbs 5 seq+seq; Flow C cc=False 0xd55 seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0d55 0x0d55 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 04 GP04 typ_b_adr 16 CSA/VAL_BUS 0d48 0d48 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x32cc seq_br_type 0 Branch False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0d49 0d49 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 0d4a 0d4a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 1e TOP - 2 0d4b 0d4b ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0d4c 0d4c fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val typ_b_adr 3a TR11:1a typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0d4d 0d4d fiu_fill_mode_src 0 ; Flow J cc=False 0xd4f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d4f 0x0d4f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 0d4e 0d4e fiu_fill_mode_src 0 ; Flow J 0xd52 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d52 0x0d52 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 0d4f 0d4f fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d50 0d50 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0d51 0d51 fiu_load_var 1 hold_var; Flow J 0xd52 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d52 0x0d52 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0d52 0d52 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA 0d53 0d53 typ_csa_cntl 3 POP_CSA 0d54 0d54 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0d55 ; -------------------------------------------------------------------------------------- 0d55 ; Comes from: 0d55 ; 0d47 C False from color 0x0000 0d55 ; -------------------------------------------------------------------------------------- 0d55 0d55 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_br_type a Unconditional Return val_b_adr 21 VR02:01 val_frame 2 0d56 ; -------------------------------------------------------------------------------------- 0d56 ; Comes from: 0d56 ; 0d43 C False from color 0x0000 0d56 ; -------------------------------------------------------------------------------------- 0d56 0d56 fiu_len_fill_lit 5a zero-fill 0x1a; Flow R fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type a Unconditional Return seq_int_reads 6 CONTROL TOP 0d57 0d57 ioc_load_wdr 0 ; Flow J 0xe4f seq_br_type 3 Unconditional Branch seq_branch_adr 0e4f 0x0e4f seq_en_micro 0 0d58 0d58 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0d59 ; -------------------------------------------------------------------------------------- 0d59 ; Comes from: 0d59 ; 0d5f C from color 0x0000 0d59 ; 0dae C from color 0x0000 0d59 ; 0db5 C from color 0x0000 0d59 ; 0e0d C from color 0x0000 0d59 ; 0e13 C from color 0x0000 0d59 ; 0e19 C from color 0x0e17 0d59 ; 0e7f C from color 0x0e7b 0d59 ; 0e99 C from color 0x0e8e 0d59 ; 0eb1 C from color 0x0eb0 0d59 ; 0eb4 C from color 0x0eb3 0d59 ; 0ed0 C from color 0x0000 0d59 ; 0eee C from color 0x0000 0d59 ; 0f0d C from color 0x0000 0d59 ; -------------------------------------------------------------------------------------- 0d59 0d59 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 0d5a ; -------------------------------------------------------------------------------------- 0d5a ; Comes from: 0d5a ; 0767 C from color 0x0767 0d5a ; 0769 C from color 0x0767 0d5a ; 0776 C from color 0x0767 0d5a ; 0d6b C from color 0x0d6b 0d5a ; 0d7f C from color 0x0d7f 0d5a ; 0d95 C from color 0x0d65 0d5a ; 0d97 C from color 0x0d65 0d5a ; 0dd0 C from color 0x0dd0 0d5a ; 0dd5 C from color 0x0dd0 0d5a ; 0de4 C from color 0x0de2 0d5a ; 0de6 C from color 0x0de2 0d5a ; 0deb C from color 0x0de2 0d5a ; 0e09 C from color 0x0e09 0d5a ; 0e17 C from color 0x0e17 0d5a ; 0e29 C from color 0x0e29 0d5a ; 0e50 C from color 0x0e50 0d5a ; 0e53 C from color 0x0e53 0d5a ; 0e68 C from color 0x0e68 0d5a ; 0e6e C from color 0x0e6e 0d5a ; 0e7b C from color 0x0e7b 0d5a ; 0e84 C from color 0x0e84 0d5a ; 0e85 C from color 0x0e84 0d5a ; 0e88 C from color 0x0e88 0d5a ; 0ea1 C from color 0x0ea1 0d5a ; 0ea9 C from color 0x0ea9 0d5a ; 0eb0 C from color 0x0eb0 0d5a ; 0eb3 C from color 0x0eb3 0d5a ; 0ecc C from color 0x0ecc 0d5a ; 3ba1 C from color 0x0bab 0d5a ; 3ba9 C from color 0x3ba9 0d5a ; -------------------------------------------------------------------------------------- 0d5a 0d5a fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd5c seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d5c 0x0d5c seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0d5b 0d5b fiu_fill_mode_src 0 ; Flow J 0xd5e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d5e 0x0d5e typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 0d5c 0d5c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d5d 0d5d fiu_fill_mode_src 0 ; Flow J 0xd5e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d5e 0x0d5e typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 0d5e 0d5e fiu_len_fill_lit 75 zero-fill 0x35; Flow J 0xd5f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d5f 0x0d5f seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 0d5f 0d5f fiu_load_oreg 1 hold_oreg; Flow C 0xd59 fiu_mem_start 11 start_tag_query fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d59 0x0d59 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_frame 2 0d60 0d60 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xd63 fiu_load_tar 1 hold_tar fiu_mem_start f start_physical_tag_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d63 0x0d63 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_latch 1 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0d61 0d61 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 0d62 0d62 fiu_mem_start 15 setup_tag_read; Flow R ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_frame 2 0d63 0d63 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 0d64 0d64 fiu_mem_start 15 setup_tag_read; Flow R cc=True ; Flow J cc=False 0xe4f ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 0e4f 0x0e4f seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_frame 2 0d65 0d65 fiu_mem_start a start_continue_if_false; Flow J cc=False 0xd67 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d67 0x0d67 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0d66 0d66 fiu_fill_mode_src 0 ; Flow J 0xd6a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0d6a 0x0d6a typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 0d67 0d67 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 0d68 0d68 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0d69 0d69 fiu_load_var 1 hold_var; Flow J 0xd6a fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d6a 0x0d6a seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 0d6a 0d6a ioc_load_wdr 0 ; Flow J 0xda4 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0da4 0x0da4 0d6b 0d6b fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0d6c 0d6c fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x32d7 fiu_load_tar 1 hold_tar fiu_offs_lit 3a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 2c TYP.CLASS_A_B_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 val_a_adr 3e VR09:1e val_b_adr 1f TOP - 1 val_frame 9 0d6d 0d6d ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0d6e 0d6e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xd58 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 34 GP0b val_c_source 0 FIU_BUS 0d6f 0d6f seq_br_type 7 Unconditional Call; Flow C 0x33f9 seq_branch_adr 33f9 0x33f9 seq_en_micro 0 0d70 0d70 seq_b_timing 1 Latch Condition; Flow J cc=False 0xd72 seq_br_type 0 Branch False seq_branch_adr 0d72 0x0d72 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 0d71 0d71 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d72 0d72 fiu_mem_start 11 start_tag_query seq_en_micro 0 typ_a_adr 2f TR11:0f typ_alu_func 1e A_AND_B typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 0d73 0d73 seq_b_timing 0 Early Condition; Flow J cc=True 0xd78 seq_br_type 1 Branch True seq_branch_adr 0d78 0x0d78 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 30 VR05:10 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 0d74 0d74 seq_br_type 7 Unconditional Call; Flow C 0x3525 seq_branch_adr 3525 0x3525 seq_en_micro 0 0d75 0d75 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 36 VR12:16 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0d76 0d76 fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0d77 0d77 ioc_load_wdr 0 seq_en_micro 0 0d78 0d78 fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start e start_physical_wr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0d79 0d79 fiu_mem_start 4 continue; Flow J cc=False 0xd79 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d79 0x0d79 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 39 VR02:19 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 0d7a 0d7a seq_en_micro 0 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d7b 0d7b fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0d7c 0d7c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_en_micro 0 0d7d 0d7d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0d7e 0d7e ioc_load_wdr 0 ; Flow J 0xd58 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d58 0x0d58 seq_en_micro 0 0d7f 0d7f fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0d80 0d80 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32d7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 2c TYP.CLASS_A_B_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_a_adr 2c VR12:0c val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 12 0d81 0d81 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xd84 fiu_load_tar 1 hold_tar fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d84 0x0d84 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_b_adr 10 TOP 0d82 0d82 seq_br_type 7 Unconditional Call; Flow C 0x33f9 seq_branch_adr 33f9 0x33f9 seq_en_micro 0 val_a_adr 3e VR09:1e val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 9 0d83 0d83 seq_b_timing 1 Latch Condition; Flow J cc=True 0xd58 seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d84 0d84 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3523 fiu_load_mdr 1 hold_mdr fiu_mem_start 11 start_tag_query fiu_rdata_src 0 rotator seq_br_type 7 Unconditional Call seq_branch_adr 3523 0x3523 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0d85 0d85 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x20d fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 20 VR12:00 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0d86 0d86 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0xd87 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0d57 0x0d57 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 33 TR07:13 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR12:08 val_frame 12 0d87 0d87 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0xd58 fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0d58 0x0d58 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 32 TR11:12 typ_frame 11 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 12 0d88 0d88 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0xe31 fiu_load_tar 1 hold_tar fiu_mem_start 10 start_physical_tag_wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 0e31 0x0e31 seq_en_micro 0 typ_a_adr 2f TR11:0f typ_frame 11 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 4 0d89 0d89 ioc_load_wdr 0 seq_en_micro 0 0d8a 0d8a fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 0d8b 0d8b fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0d8c 0d8c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 02 GP02 0d8d 0d8d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0d8e 0d8e ioc_load_wdr 0 ; Flow J 0xe4f ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e4f 0x0e4f seq_en_micro 0 0d8f 0d8f fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0d90 0d90 fiu_load_var 1 hold_var; Flow J cc=True 0xd93 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d93 0x0d93 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 32 TR02:12 typ_frame 2 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0d91 0d91 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd92 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 0e4f 0x0e4f seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0d92 0d92 ioc_load_wdr 0 ; Flow J 0x350a seq_br_type 3 Unconditional Branch seq_branch_adr 350a 0x350a seq_en_micro 0 0d93 0d93 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xd91 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d91 0x0d91 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0d94 0d94 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd57 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d57 0x0d57 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0d95 0d95 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0d96 0d96 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0d97 0d97 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3d VR02:1d val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 0d98 0d98 fiu_mem_start 2 start-rd; Flow J 0xd9a fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d9a 0x0d9a seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0d99 0d99 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 0 PASS_A 0d9a 0d9a fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 0d9b 0d9b fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl 6 INCREMENT_MAR 0d9c 0d9c fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0d9d 0d9d ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0d9e 0d9e ioc_tvbs c mem+mem+csa+dummy; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0d9f 0d9f fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 0 PASS_A 0da0 0da0 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0da1 0da1 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 0da2 0da2 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 0da3 0da3 ioc_load_wdr 0 ; Flow J cc=False 0xd99 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d99 0x0d99 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 04 GP04 val_b_adr 04 GP04 0da4 0da4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0da5 0da5 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0da6 0da6 fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xdac ioc_tvbs 8 typ+mem seq_br_type 1 Branch True seq_branch_adr 0dac 0x0dac seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0da7 0da7 fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xdac ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0dac 0x0dac seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0da8 0da8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xdaa fiu_load_mdr 1 hold_mdr fiu_mem_start 15 setup_tag_read fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 8 typ+mem seq_br_type 1 Branch True seq_branch_adr 0daa 0x0daa seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_b_adr 2d TR05:0d typ_frame 5 val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0da9 0da9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 15 setup_tag_read fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 21 TR10:01 typ_frame 10 0daa 0daa fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 15 setup_tag_read fiu_offs_lit 38 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0dab 0dab fiu_len_fill_lit 4c zero-fill 0xc; Flow J 0xdad fiu_mem_start 15 setup_tag_read fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0dad 0x0dad seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 3d VR02:1d val_alu_func 18 NOT_A_AND_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0dac 0dac fiu_len_fill_lit 4c zero-fill 0xc fiu_mem_start 15 setup_tag_read fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 3d VR02:1d val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 0dad 0dad fiu_len_fill_lit 4f zero-fill 0xf fiu_mem_start 15 setup_tag_read fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 0dae 0dae fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0xd59 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d59 0x0d59 seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0daf 0daf fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 39 GP06 val_c_source 0 FIU_BUS 0db0 0db0 ioc_fiubs 1 val typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP 0db1 0db1 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0db2 0db2 fiu_len_fill_lit 4c zero-fill 0xc fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 25 VR05:05 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 5 0db3 0db3 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_frame 2 0db4 0db4 seq_br_type 7 Unconditional Call; Flow C 0x33f9 seq_branch_adr 33f9 0x33f9 seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 18 NOT_A_AND_B val_b_adr 25 VR05:05 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 0db5 0db5 fiu_mem_start 11 start_tag_query; Flow C 0xd59 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d59 0x0d59 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR 0db6 0db6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xdce fiu_load_tar 1 hold_tar fiu_mem_start 11 start_tag_query fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 0dce 0x0dce seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0db7 0db7 ioc_tvbs 2 fiu+val; Flow J cc=True 0xd58 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0db8 0db8 seq_br_type 7 Unconditional Call; Flow C 0x3525 seq_branch_adr 3525 0x3525 seq_en_micro 0 0db9 0db9 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0dba 0dba fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0dbb 0dbb ioc_load_wdr 0 seq_en_micro 0 val_b_adr 01 GP01 0dbc 0dbc fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 0dbd 0dbd fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0dbe 0dbe fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 06 GP06 0dbf 0dbf fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0dc0 0dc0 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0dc1 0dc1 fiu_mem_start d start_physical_rd; Flow C 0xdc4 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0dc4 0x0dc4 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 0dc2 0dc2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0dc3 0dc3 fiu_mem_start d start_physical_rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 0dc4 ; -------------------------------------------------------------------------------------- 0dc4 ; Comes from: 0dc4 ; 0dc1 C from color 0x0000 0dc4 ; 0ddd C from color 0x0dd0 0dc4 ; 0df1 C from color 0x0de2 0dc4 ; -------------------------------------------------------------------------------------- 0dc4 0dc4 fiu_mem_start 4 continue seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 0dc5 0dc5 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0dc6 0dc6 fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0dc7 0dc7 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0dc8 0dc8 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0dc9 0dc9 fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 02 GP02 val_alu_func 0 PASS_A 0dca 0dca fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 0dcb 0dcb fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 0dcc 0dcc fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 0dcd 0dcd ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0xdc3 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 0dc3 0x0dc3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 05 GP05 val_b_adr 05 GP05 0dce 0dce seq_b_timing 1 Latch Condition; Flow C cc=False 0x34c5 seq_br_type 4 Call False seq_branch_adr 34c5 0x34c5 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 0dcf 0dcf fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0dd0 0dd0 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0dd1 0dd1 fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0xdd9 fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0dd9 0x0dd9 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 val_rand 1 INC_LOOP_COUNTER 0dd2 0dd2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xdd9 seq_br_type 1 Branch True seq_branch_adr 0dd9 0x0dd9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 2c VR12:0c val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_frame 12 val_rand 1 INC_LOOP_COUNTER 0dd3 0dd3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xdd9 seq_br_type 1 Branch True seq_branch_adr 0dd9 0x0dd9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 01 GP01 val_frame 5 val_rand 1 INC_LOOP_COUNTER 0dd4 0dd4 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 0dd5 0dd5 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0dd6 0dd6 fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0xdda fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0dda 0x0dda seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 val_rand 1 INC_LOOP_COUNTER 0dd7 0dd7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xdd9 seq_br_type 1 Branch True seq_branch_adr 0dd9 0x0dd9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_frame 12 0dd8 0dd8 seq_br_type 1 Branch True; Flow J cc=True 0xde0 seq_branch_adr 0de0 0x0de0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 01 GP01 val_frame 5 val_rand 1 INC_LOOP_COUNTER 0dd9 0dd9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0dda 0dda seq_br_type 7 Unconditional Call; Flow C 0x33f9 seq_branch_adr 33f9 0x33f9 seq_en_micro 0 val_a_adr 22 VR13:02 val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 13 0ddb 0ddb fiu_load_var 1 hold_var; Flow J cc=True 0xdd9 fiu_tivi_src 3 tar_frame seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0dd9 0x0dd9 seq_en_micro 0 val_a_adr 23 VR05:03 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 0ddc 0ddc ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 val_a_adr 3d VR02:1d val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 0ddd 0ddd fiu_mem_start d start_physical_rd; Flow C 0xdc4 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 0dc4 0x0dc4 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0dde 0dde fiu_mem_start 11 start_tag_query; Flow C 0x34c5 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 34c5 0x34c5 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_mar_cntl 6 INCREMENT_MAR 0ddf 0ddf fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 0de0 0de0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0de1 0de1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xddc fiu_load_var 1 hold_var fiu_mem_start 10 start_physical_tag_wr fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0ddc 0x0ddc seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 22 VR13:02 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 0de2 0de2 seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_en_micro 0 0de3 0de3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xdf2 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_br_type 0 Branch False seq_branch_adr 0df2 0x0df2 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 0de4 0de4 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0de5 0de5 seq_b_timing 1 Latch Condition; Flow J cc=False 0xde2 seq_br_type 0 Branch False seq_branch_adr 0de2 0x0de2 typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame 4 typ_rand 1 INC_LOOP_COUNTER 0de6 0de6 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0de7 0de7 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0xded fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ded 0x0ded seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 36 VR12:16 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0de8 0de8 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 val_a_adr 3e VR09:1e val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 9 0de9 0de9 seq_br_type 7 Unconditional Call; Flow C 0x33f9 seq_branch_adr 33f9 0x33f9 seq_en_micro 0 0dea 0dea seq_b_timing 1 Latch Condition; Flow J cc=True 0xde4 seq_br_type 1 Branch True seq_branch_adr 0de4 0x0de4 seq_en_micro 0 0deb 0deb fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0dec 0dec fiu_len_fill_lit 41 zero-fill 0x1; Flow C 0x210 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_en_micro 0 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 36 VR12:16 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0ded 0ded seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0xdf0 seq_br_type 5 Call True seq_branch_adr 0df0 0x0df0 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 0dee 0dee fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 0def 0def ioc_load_wdr 0 ; Flow J 0xdf1 seq_br_type 3 Unconditional Branch seq_branch_adr 0df1 0x0df1 seq_en_micro 0 val_b_adr 01 GP01 0df0 ; -------------------------------------------------------------------------------------- 0df0 ; Comes from: 0df0 ; 0ded C True from color 0x0de2 0df0 ; -------------------------------------------------------------------------------------- 0df0 0df0 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 2f TR11:0f typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 0df1 0df1 fiu_mem_start d start_physical_rd; Flow C 0xdc4 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0dc4 0x0dc4 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 0df2 0df2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 17 LOOP_COUNTER typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 0df3 0df3 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0df4 0df4 fiu_tivi_src 3 tar_frame; Flow J cc=False 0xdfa ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0dfa 0x0dfa seq_en_micro 0 typ_a_adr 2d TR0d:0d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 0df5 0df5 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0df6 0df6 fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 01 GP01 val_alu_func 0 PASS_A 0df7 0df7 fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xd58 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_en_micro 0 typ_a_adr 2d TR0d:0d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame d 0df8 0df8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32f5 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f5 0x32f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0df9 0df9 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0xd57 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 73 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d57 0x0d57 seq_en_micro 0 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0dfa 0dfa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0dfb 0dfb fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0dfc 0dfc fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0xd58 fiu_load_mdr 1 hold_mdr fiu_mem_start 15 setup_tag_read fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2f TR11:0f typ_frame 11 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0dfd 0dfd fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 7a fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 12 0dfe 0dfe fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=False 0xd57 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0d57 0x0d57 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 14 ZEROS val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 0dff 0dff fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xe4f fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e4f 0x0e4f seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_frame 2 0e00 0e00 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0xe01 ; Flow J cc=#0x0 0xe01 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0e01 0x0e01 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0e01 0e01 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xe03 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e03 0x0e03 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR04:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 0e02 0e02 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xe03 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e03 0x0e03 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR02:12 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0e03 0e03 ioc_load_wdr 0 ; Flow C 0x3509 seq_br_type 7 Unconditional Call seq_branch_adr 3509 0x3509 seq_en_micro 0 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0e04 0e04 fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x34fe fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 34fe 0x34fe seq_en_micro 0 0e05 0e05 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x211 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0211 0x0211 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 0e06 0e06 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e07 0e07 fiu_load_var 1 hold_var; Flow J cc=True 0xe4f fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e4f 0x0e4f seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0e08 0e08 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd57 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d57 0x0d57 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR05:0d val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0e09 0e09 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e0a 0e0a fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0e0b 0e0b fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e0c 0e0c fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0e0d 0e0d fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0xd59 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d59 0x0d59 seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 30 VR02:10 val_frame 2 0e0e 0e0e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0e0f 0e0f fiu_fill_mode_src 0 ; Flow J cc=True 0xe4f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e4f 0x0e4f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0e10 0e10 ioc_load_wdr 0 ; Flow J 0xe4f ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e4f 0x0e4f seq_en_micro 0 0e11 0e11 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e12 0e12 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0e13 0e13 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0xd59 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d59 0x0d59 seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR02:19 val_frame 2 0e14 0e14 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0e15 0e15 fiu_fill_mode_src 0 ; Flow J cc=True 0xe4f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e4f 0x0e4f seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0e16 0e16 ioc_load_wdr 0 ; Flow J 0xe4f ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e4f 0x0e4f seq_en_micro 0 0e17 0e17 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e18 0e18 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0e19 0e19 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0xd59 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 0d59 0x0d59 seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0e1a 0e1a fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e1b 0e1b fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e1c 0e1c fiu_mem_start 10 start_physical_tag_wr; Flow C cc=False 0x211 ioc_adrbs 2 typ ioc_tvbs a fiu+mem seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e1d 0e1d ioc_load_wdr 0 ; Flow J 0xd58 seq_br_type 3 Unconditional Branch seq_branch_adr 0d58 0x0d58 seq_en_micro 0 0e1e 0e1e fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR05:02 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0e1f 0e1f fiu_load_var 1 hold_var; Flow J cc=True 0xd58 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2e TR11:0e typ_frame 11 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0e20 0e20 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xe23 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e23 0x0e23 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 33 VR13:13 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 0e21 0e21 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR13:00 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 0e22 0e22 ioc_fiubs 2 typ ; Flow J 0xd58 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 0d58 0x0d58 seq_en_micro 0 typ_a_adr 32 TR02:12 typ_frame 2 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e23 0e23 ioc_fiubs 2 typ ; Flow J cc=True 0xd58 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 21 TR05:01 typ_frame 5 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 0e24 0e24 ioc_fiubs 2 typ ; Flow J cc=True 0xd58 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0e25 0e25 ioc_fiubs 2 typ ; Flow J 0xd58 seq_br_type 3 Unconditional Branch seq_branch_adr 0d58 0x0d58 seq_en_micro 0 typ_a_adr 2f TR11:0f typ_frame 11 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e26 0e26 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e27 0e27 fiu_mem_start 10 start_physical_tag_wr; Flow C cc=False 0x211 ioc_adrbs 2 typ ioc_tvbs a fiu+mem seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR12:0d val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e28 0e28 ioc_load_wdr 0 ; Flow J 0xd58 seq_br_type 3 Unconditional Branch seq_branch_adr 0d58 0x0d58 seq_en_micro 0 0e29 0e29 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e2a 0e2a fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0e2b 0e2b fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e2c 0e2c fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0e2d 0e2d fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xe4f ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e4f 0x0e4f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0e2e 0e2e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 20 VR12:00 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 12 0e2f 0e2f fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0xe30 fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 0d57 0x0d57 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 33 TR07:13 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 28 VR12:08 val_frame 12 0e30 0e30 fiu_mem_start 10 start_physical_tag_wr; Flow R cc=False ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 0e31 0x0e31 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2c VR12:0c val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e31 0e31 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0e32 0e32 fiu_mem_start 11 start_tag_query; Flow C 0x3523 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3523 0x3523 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_rand 9 PASS_A_HIGH 0e33 0e33 ioc_tvbs 8 typ+mem; Flow J cc=True 0xe3f seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e3f 0x0e3f seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0e34 0e34 fiu_mem_start d start_physical_rd; Flow J cc=False 0xe3f fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0e3f 0x0e3f seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0e35 0e35 fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0e36 0e36 fiu_len_fill_lit 07 sign-fill 0x7; Flow C 0x210 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0e37 0e37 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xe3a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e3a 0x0e3a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 01 GP01 val_alu_func 10 NOT_A 0e38 0e38 fiu_fill_mode_src 0 ; Flow J cc=False 0xe3f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0e3f 0x0e3f seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 26 VR0d:06 val_frame d 0e39 0e39 fiu_fill_mode_src 0 ; Flow J cc=True 0xe3a ; Flow J cc=#0x0 0xe3b fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0e3b 0x0e3b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_b_adr 28 TR0d:08 typ_frame d val_b_adr 28 VR0d:08 val_frame d 0e3a 0e3a fiu_fill_mode_src 0 ; Flow J cc=False 0xe3f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0e3f 0x0e3f seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_b_adr 2f TR0d:0f typ_frame d val_b_adr 2f VR0d:0f val_frame d 0e3b 0e3b seq_b_timing 0 Early Condition; Flow J cc=True 0xe3c ; Flow J cc=#0x0 0xe3d seq_br_type b Case False seq_branch_adr 0e3d 0x0e3d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0e3c 0e3c seq_br_type 3 Unconditional Branch; Flow J 0xe3f seq_branch_adr 0e3f 0x0e3f seq_en_micro 0 0e3d 0e3d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0e3e 0e3e ioc_fiubs 1 val ; Flow C 0x36c1 seq_br_type 7 Unconditional Call seq_branch_adr 36c1 0x36c1 seq_en_micro 0 val_a_adr 23 VR04:03 val_alu_func 1a PASS_B val_c_adr 1c VR04:03 val_c_mux_sel 2 ALU val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0e3f 0e3f fiu_load_var 1 hold_var; Flow C 0x352c fiu_mem_start f start_physical_tag_rd fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 352c 0x352c seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 0e40 0e40 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_en_micro 0 0e41 0e41 fiu_len_fill_lit 43 zero-fill 0x3; Flow R fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 74 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_en_micro 0 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0e42 0e42 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e43 0e43 fiu_load_var 1 hold_var; Flow J cc=True 0xe4f fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e4f 0x0e4f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0e44 0e44 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xe4f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e4f 0x0e4f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 20 TR08:00 typ_frame 8 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 0e45 0e45 fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e46 0e46 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=True 0xe47 ; Flow J cc=#0x0 0xe47 fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0e47 0x0e47 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 0e47 0e47 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0xe49 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0e49 0x0e49 seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1b A_OR_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 0e48 0e48 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0xe49 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0e49 0x0e49 seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR02:12 val_alu_func 1b A_OR_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0e49 0e49 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 33 TR12:13 typ_alu_func 18 NOT_A_AND_B typ_c_adr 3e GP01 typ_frame 12 0e4a 0e4a fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_mem_start f start_physical_tag_rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 0e4b 0e4b fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 15 setup_tag_read fiu_offs_lit 7b fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0e4c 0e4c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 01 GP01 val_alu_func a PASS_A_ELSE_PASS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0e4d 0e4d fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x350a fiu_load_var 1 hold_var fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 74 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 350a 0x350a seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1e A_AND_B val_frame 12 0e4e 0e4e ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 0e4f 0e4f fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x211 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0211 0x0211 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 0e50 0e50 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e51 0e51 fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0e52 0e52 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0e53 0e53 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e54 0e54 fiu_mem_start 15 setup_tag_read; Flow C 0xe56 seq_br_type 7 Unconditional Call seq_branch_adr 0e56 0x0e56 seq_en_micro 0 0e55 0e55 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0e56 ; -------------------------------------------------------------------------------------- 0e56 ; Comes from: 0e56 ; 0e54 C from color 0x0e53 0e56 ; 0e5a C from color 0x0000 0e56 ; -------------------------------------------------------------------------------------- 0e56 0e56 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xe58 fiu_mem_start 15 setup_tag_read fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e58 0x0e58 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0e57 0e57 fiu_len_fill_lit 40 zero-fill 0x0; Flow R cc=True fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_br_type 8 Return True seq_branch_adr 0e58 0x0e58 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e58 0e58 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 val_a_adr 14 ZEROS val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e59 0e59 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e5a 0e5a fiu_mem_start 15 setup_tag_read; Flow C 0xe56 seq_br_type 7 Unconditional Call seq_branch_adr 0e56 0x0e56 seq_en_micro 0 0e5b 0e5b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xd58 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_frame 2 0e5c 0e5c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 73 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED 0e5d 0e5d ioc_load_wdr 0 ; Flow J 0xd58 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0d58 0x0d58 seq_en_micro 0 0e5e 0e5e fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e5f 0e5f fiu_load_var 1 hold_var; Flow J cc=True 0xe4f fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e4f 0x0e4f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0e60 0e60 ioc_fiubs 0 fiu ; Flow J cc=True 0xe62 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e62 0x0e62 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 12 0e61 0e61 seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e62 0e62 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd57 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0d57 0x0d57 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 25 VR05:05 val_alu_func 1b A_OR_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0e63 0e63 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3a VR02:1a val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0e64 0e64 fiu_load_var 1 hold_var; Flow J cc=True 0xe4f fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e4f 0x0e4f seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0e65 0e65 ioc_fiubs 0 fiu ; Flow J cc=True 0xe67 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e67 0x0e67 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 12 0e66 0e66 seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0e67 0e67 fiu_mem_start 10 start_physical_tag_wr; Flow J 0xd57 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0d57 0x0d57 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 25 VR05:05 val_alu_func 18 NOT_A_AND_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 0e68 0e68 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e69 0e69 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 val_rand 3 CONDITION_TO_FIU 0e6a 0e6a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32f5 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f5 0x32f5 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 3e VR03:1e val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 3 0e6b 0e6b fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0e6c 0x0e6c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 0e6c 0e6c fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 0e6d 0x0e6d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL 0e6d 0e6d seq_br_type 3 Unconditional Branch; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 0e6e 0e6e fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e6f 0e6f fiu_mem_start 2 start-rd; Flow C 0x32f5 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type c Dispatch True seq_branch_adr 32f5 0x32f5 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 0e70 0e70 fiu_len_fill_lit 4b zero-fill 0xb fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 0e71 0e71 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 10 TOP 0e72 0e72 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x329e fiu_load_mdr 1 hold_mdr fiu_offs_lit 24 fiu_rdata_src 0 rotator seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_alu_func 6 A_MINUS_B val_b_adr 2c VR0d:0c val_frame d 0e73 0e73 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 72 fiu_op_sel 3 insert seq_en_micro 0 val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 21 VR06:01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 0e74 0e74 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x329e fiu_load_mdr 1 hold_mdr fiu_offs_lit 27 fiu_rdata_src 0 rotator seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_alu_func 6 A_MINUS_B val_b_adr 2d VR0d:0d val_frame d 0e75 0e75 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 70 fiu_op_sel 3 insert seq_en_micro 0 0e76 0e76 fiu_mem_start f start_physical_tag_rd; Flow C 0x32d7 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0e77 0e77 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0x32d7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 15 setup_tag_read fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP typ_c_lit 1 typ_frame 4 val_a_adr 10 TOP val_alu_func 0 PASS_A 0e78 0e78 fiu_len_fill_lit 75 zero-fill 0x35 fiu_load_mdr 1 hold_mdr fiu_mem_start 15 setup_tag_read fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 2c VR12:0c val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 12 val_rand 3 CONDITION_TO_FIU 0e79 0e79 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_en_micro 0 0e7a 0e7a fiu_fill_mode_src 0 ; Flow J 0xd65 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0d65 0x0d65 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0e7b 0e7b fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0e7c 0e7c fiu_mem_start 12 start_lru_query fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0e7d 0e7d seq_br_type 3 Unconditional Branch; Flow J 0xe7f seq_branch_adr 0e7f 0x0e7f seq_en_micro 0 0e7e 0e7e fiu_tivi_src 8 type_var; Flow C 0x1001 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1001 0x1001 seq_en_micro 0 typ_mar_cntl 4 RESTORE_MAR val_alu_func 0 PASS_A 0e7f 0e7f fiu_mem_start 13 start_available_query; Flow C 0xd59 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d59 0x0d59 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl 4 RESTORE_MAR val_alu_func 0 PASS_A 0e80 0e80 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0xe7e ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0e7e 0x0e7e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0e81 0e81 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR0d:0d val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame d 0e82 0e82 seq_en_micro 0 val_a_adr 2c VR0d:0c val_b_adr 2d VR0d:0d val_frame d val_rand c START_MULTIPLY 0e83 0e83 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 0e84 0e84 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 10 TOP 0e85 0e85 fiu_load_oreg 1 hold_oreg; Flow C 0xd5a fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_source 0 FIU_BUS 0e86 0e86 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 7 fiu_frame ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 2d TR0d:0d typ_frame d val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0e87 0e87 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 0e88 0e88 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 22 TR08:02 typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP 0e89 0e89 fiu_len_fill_lit 4b zero-fill 0xb; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src b type_frame fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0e8a 0e8a ioc_fiubs 1 val ; Flow C 0x329e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_b_adr 1f TOP - 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3a VR02:1a val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 0e8b 0e8b ioc_adrbs 1 val ioc_fiubs 1 val typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP val_rand a PASS_B_HIGH 0e8c 0e8c seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0xe8e seq_br_type f Unconditional Case Call seq_branch_adr 0e8e 0x0e8e seq_en_micro 0 typ_csa_cntl 3 POP_CSA 0e8d 0e8d seq_br_type 3 Unconditional Branch; Flow J 0xd58 seq_branch_adr 0d58 0x0d58 seq_en_micro 0 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0e8e ; -------------------------------------------------------------------------------------- 0e8e ; Comes from: 0e8e ; 0e8c C #0x0 from color 0x0e8b 0e8e ; -------------------------------------------------------------------------------------- 0e8e 0e8e fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0xe91 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 79 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e91 0x0e91 seq_en_micro 0 typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0e8f 0e8f seq_br_type a Unconditional Return; Flow R seq_en_micro 0 0e90 0e90 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0xe94 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e94 0x0e94 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 0e91 0e91 seq_en_micro 0 0e92 0e92 fiu_fill_mode_src 0 ; Flow J cc=False 0xe9e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0e9e 0x0e9e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 0e93 0e93 fiu_load_oreg 1 hold_oreg; Flow J 0x3456 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3456 0x3456 seq_en_micro 0 val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 0e94 0e94 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 32 VR07:12 val_frame 7 0e95 0e95 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0xe98 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 0e98 0x0e98 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0e96 0e96 ioc_tvbs 1 typ+fiu; Flow J cc=False 0xe9e seq_br_type 0 Branch False seq_branch_adr 0e9e 0x0e9e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 2e VR04:0e val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0e97 0e97 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0xe91 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e91 0x0e91 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0e98 0e98 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xe9d seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0e9d 0x0e9d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 2b VR05:0b val_frame 5 0e99 0e99 fiu_mem_start 2 start-rd; Flow C 0xd59 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d59 0x0d59 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR02:1e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 2 val_rand a PASS_B_HIGH 0e9a 0e9a fiu_len_fill_lit 44 zero-fill 0x4 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 0e9b 0e9b fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 02 GP02 typ_frame d 0e9c 0e9c ioc_load_wdr 0 ; Flow J 0xe9d ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0e9d 0x0e9d seq_en_micro 0 0e9d 0e9d fiu_mem_start 2 start-rd; Flow J 0x348b ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 348b 0x348b seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 5 val_rand a PASS_B_HIGH 0e9e 0e9e fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0x32d7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A 0e9f 0e9f fiu_len_fill_lit 7c zero-fill 0x3c; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 val_alu_func 1a PASS_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 0ea0 0ea0 fiu_fill_mode_src 0 ; Flow J 0xd65 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0d65 0x0d65 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 0ea1 0ea1 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0ea2 0ea2 fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs a fiu+mem seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 0ea3 0ea3 ioc_load_wdr 0 ; Flow C 0x32f5 seq_br_type 4 Call False seq_branch_adr 32f5 0x32f5 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 2e VR12:0e val_alu_func 1d A_AND_NOT_B val_frame 12 0ea4 0ea4 fiu_mem_start d start_physical_rd; Flow C 0x32f5 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f5 0x32f5 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 33 TR12:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1e A_AND_B val_b_adr 2c VR11:0c val_frame 11 0ea5 0ea5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xea7 seq_br_type 1 Branch True seq_branch_adr 0ea7 0x0ea7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_frame 5 0ea6 0ea6 fiu_mem_start d start_physical_rd; Flow C 0x32f5 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32f5 0x32f5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_frame 1 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3b VR05:1b val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0ea7 0ea7 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start e start_physical_wr fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0ea8 0ea8 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J 0xd58 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 0d58 0x0d58 seq_en_micro 0 typ_b_adr 01 GP01 val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ea9 0ea9 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 0eaa 0eaa fiu_len_fill_lit 41 zero-fill 0x1 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs a fiu+mem seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0eab 0eab ioc_fiubs 1 val ; Flow C 0x32f5 seq_br_type 4 Call False seq_branch_adr 32f5 0x32f5 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 11 val_alu_func 1e A_AND_B val_b_adr 3d VR02:1d val_frame 2 0eac 0eac fiu_mem_start d start_physical_rd; Flow C 0x32f5 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f5 0x32f5 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1e A_AND_B typ_b_adr 33 TR12:13 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 2c VR11:0c val_alu_func 1e A_AND_B val_frame 11 0ead 0ead seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xeaf seq_br_type 1 Branch True seq_branch_adr 0eaf 0x0eaf seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_frame 5 0eae 0eae fiu_mem_start d start_physical_rd; Flow C 0x32f5 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32f5 0x32f5 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_frame 1 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 3b VR05:1b val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0eaf 0eaf fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0eb0 0eb0 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0eb1 0eb1 fiu_mem_start 2 start-rd; Flow C 0xd59 seq_br_type 7 Unconditional Call seq_branch_adr 0d59 0x0d59 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 0eb2 0eb2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0eb3 0eb3 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0eb4 0eb4 fiu_mem_start 3 start-wr; Flow C 0xd59 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 0d59 0x0d59 seq_en_micro 0 seq_random 02 ? typ_b_adr 32 TR02:12 typ_csa_cntl 3 POP_CSA typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 0eb5 0eb5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0eb6 0eb6 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 0eb7 0eb7 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 0eb8 0eb8 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 3d VR02:1d val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 0eb9 0eb9 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 0eba 0eba fiu_mem_start 4 continue seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 0ebb 0ebb fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 0ebc 0ebc fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 0ebd 0ebd ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0ebe 0ebe ioc_tvbs c mem+mem+csa+dummy; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 0ebf 0ebf fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 01 GP01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ec0 0ec0 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR05:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 0ec1 0ec1 fiu_mem_start 4 continue; Flow J cc=True 0xd58 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0ec2 0ec2 fiu_mem_start 4 continue; Flow J cc=True 0xd58 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0ec3 0ec3 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xd58 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0ec4 0ec4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xd58 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0ec5 0ec5 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0xeba ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0eba 0x0eba seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 0 PASS_A 0ec6 0ec6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0ec7 0ec7 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0ec8 0ec8 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0xd58 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0d58 0x0d58 seq_en_micro 0 val_a_adr 2d VR0d:0d val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame d 0ec9 0ec9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 17 LOOP_COUNTER val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 0eca 0eca fiu_mem_start 12 start_lru_query; Flow J cc=True 0xec9 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ec9 0x0ec9 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0ecb 0ecb seq_br_type 3 Unconditional Branch; Flow J 0xd58 seq_branch_adr 0d58 0x0d58 seq_en_micro 0 0ecc 0ecc fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 0ecd 0ecd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 0ece 0ece seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xd58 seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0ecf 0ecf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xd58 seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 29 TR04:09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_frame 4 0ed0 0ed0 fiu_mem_start 2 start-rd; Flow C 0xd59 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d59 0x0d59 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 0 PASS_A val_frame 4 0ed1 0ed1 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 0ed2 0ed2 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=True 0xef1 fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0ef1 0x0ef1 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_alu_func 1a PASS_B typ_mar_cntl f LOAD_MAR_RESERVED 0ed3 0ed3 fiu_mem_start 15 setup_tag_read; Flow J cc=True 0xef5 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ef5 0x0ef5 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 0ed4 0ed4 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=False 0xef3 fiu_load_var 1 hold_var fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_br_type 0 Branch False seq_branch_adr 0ef3 0x0ef3 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR06:1f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 25 VR06:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 0ed5 0ed5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xed2 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0ed2 0x0ed2 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 31 TR11:11 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 1e A_AND_B val_b_adr 2c VR12:0c val_c_adr 3f GP00 val_frame 12 0ed6 0ed6 fiu_tivi_src 4 fiu_var; Flow J cc=False 0xed2 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 0ed2 0x0ed2 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_alu_func 18 NOT_A_AND_B val_b_adr 2c VR12:0c val_frame 12 0ed7 0ed7 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=True 0xee4 fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0ee4 0x0ee4 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 0ed8 0ed8 fiu_tivi_src 4 fiu_var; Flow J cc=False 0xee4 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0ee4 0x0ee4 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_alu_func 1e A_AND_B val_b_adr 30 VR11:10 val_frame 11 0ed9 0ed9 fiu_mem_start 11 start_tag_query; Flow C 0x3523 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3523 0x3523 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_rand 9 PASS_A_HIGH 0eda 0eda ioc_tvbs 8 typ+mem; Flow J cc=True 0xee4 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ee4 0x0ee4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0edb 0edb fiu_mem_start d start_physical_rd; Flow J cc=False 0xee3 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0ee3 0x0ee3 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 0edc 0edc fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 0edd 0edd fiu_len_fill_lit 07 sign-fill 0x7; Flow C 0x210 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_frame 1 0ede 0ede ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 0edf 0edf fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0xee4 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 0ee4 0x0ee4 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_alu_func 15 NOT_B typ_b_adr 05 GP05 0ee0 0ee0 fiu_fill_mode_src 0 ; Flow J cc=True 0xed2 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ed2 0x0ed2 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 26 VR0d:06 val_frame d 0ee1 0ee1 seq_b_timing 0 Early Condition; Flow J cc=True 0xee2 ; Flow J cc=#0x0 0xee2 seq_br_type b Case False seq_branch_adr 0ee2 0x0ee2 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0ee2 0ee2 seq_br_type 3 Unconditional Branch; Flow J 0xed2 seq_branch_adr 0ed2 0x0ed2 seq_en_micro 0 0ee3 0ee3 seq_en_micro 0 0ee4 0ee4 fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 2 typ seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR06:1f typ_frame 6 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1b A_OR_B val_b_adr 3f VR08:1f val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 0ee5 0ee5 ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 33 TR12:13 typ_alu_func 18 NOT_A_AND_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 01 GP01 0ee6 0ee6 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0ee7 0ee7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 14 ZEROS 0ee8 0ee8 fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 0ee9 0ee9 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR0d:0e typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 02 GP02 val_frame 2 0eea 0eea seq_b_timing 1 Latch Condition; Flow J cc=True 0xed2 seq_br_type 1 Branch True seq_branch_adr 0ed2 0x0ed2 seq_en_micro 0 0eeb 0eeb fiu_len_fill_lit 4f zero-fill 0xf fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 0eec 0eec fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 33 TR06:13 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 2 0eed 0eed seq_br_type 1 Branch True; Flow J cc=True 0xed2 seq_branch_adr 0ed2 0x0ed2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 val_c_adr 3c GP03 0eee 0eee fiu_mem_start 3 start-wr; Flow C 0xd59 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 0d59 0x0d59 seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 03 GP03 0eef 0eef fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_frame d typ_mar_cntl b LOAD_MAR_DATA 0ef0 0ef0 ioc_load_wdr 0 ; Flow J 0xed2 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0ed2 0x0ed2 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 26 TR07:06 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 0ef1 0ef1 ioc_load_wdr 0 seq_en_micro 0 typ_alu_func 0 PASS_A typ_b_adr 04 GP04 typ_c_adr 16 TR04:09 typ_c_mux_sel 0 ALU typ_frame 4 val_b_adr 04 GP04 0ef2 0ef2 fiu_mem_start 3 start-wr; Flow J cc=True 0xd58 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0d58 0x0d58 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2e TR0d:0e typ_alu_func 0 PASS_A typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2c VR0d:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 0ef3 0ef3 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR07:07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 7 0ef4 0ef4 seq_br_type 3 Unconditional Branch; Flow J 0xed2 seq_branch_adr 0ed2 0x0ed2 seq_en_micro 0 typ_alu_func 1e A_AND_B typ_b_adr 31 TR05:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 0ef5 0ef5 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 0ef6 0ef6 seq_br_type 3 Unconditional Branch; Flow J 0xed2 seq_branch_adr 0ed2 0x0ed2 seq_en_micro 0 0ef7 0ef7 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0ef8 0ef8 fiu_tivi_src c mar_0xc; Flow C cc=True 0x211 ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_c_adr 0e VR03:11 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 3 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0ef9 0ef9 fiu_mem_start 3 start-wr; Flow C cc=False 0x211 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_en_micro 0 typ_a_adr 37 TR08:17 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_a_adr 31 VR03:11 val_alu_func 0 PASS_A val_frame 3 0efa 0efa fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 39 VR02:19 val_frame 2 0efb 0efb seq_br_type 3 Unconditional Branch; Flow J 0xd58 seq_branch_adr 0d58 0x0d58 seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 03 TR03:1c typ_c_mux_sel 0 ALU typ_frame 3 0efc 0efc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR03:10 val_alu_func 6 A_MINUS_B val_b_adr 3e VR03:1e val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 3 0efd 0efd seq_br_type 0 Branch False; Flow J cc=False 0x211 seq_branch_adr 0211 0x0211 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP 0efe 0efe seq_br_type 7 Unconditional Call; Flow C 0x213 seq_branch_adr 0213 0x0213 seq_en_micro 0 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 08 VR03:17 val_c_mux_sel 2 ALU val_frame 3 0eff 0eff seq_br_type 7 Unconditional Call; Flow C 0x212 seq_branch_adr 0212 0x0212 seq_en_micro 0 0f00 0f00 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x211 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 0d TR03:12 typ_c_mux_sel 0 ALU typ_frame 3 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_c_adr 0d VR03:12 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 3 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0f01 0f01 fiu_mem_start 2 start-rd; Flow C 0x332f ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332f 0x332f seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 2a VR0c:0a val_frame c 0f02 0f02 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 25 TR0c:05 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 3d VR07:1d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0f03 0f03 ioc_load_wdr 0 ; Flow C cc=False 0x211 seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP 0f04 0f04 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x20d ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 0f05 0f05 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 3b TR02:1b typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 24 VR04:04 val_alu_func 0 PASS_A val_c_adr 1b VR04:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0f06 0f06 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x211 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 3b TR02:1b typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR04:1e val_alu_func 0 PASS_A val_c_adr 01 VR04:1e val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0f07 0f07 fiu_mem_start 11 start_tag_query; Flow C 0x3523 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3523 0x3523 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0f08 0f08 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_mem_start 2 start-rd fiu_offs_lit 7a fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 0f09 0f09 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_frame 3 0f0a 0f0a fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x329e fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 2e VR12:0e val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 12 0f0b 0f0b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 24 VR1b:04 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 1b 0f0c 0f0c fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 02 ? typ_b_adr 10 TOP typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 0f0d 0f0d fiu_mem_start 2 start-rd; Flow C 0xd59 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d59 0x0d59 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 38 VR06:18 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 6 0f0e 0f0e fiu_mem_start 3 start-wr seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 34 VR11:14 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 0f0f 0f0f fiu_mem_start 4 continue ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_b_adr 2a TR1d:0a typ_frame 1d typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1c DEC_A val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 0f10 0f10 fiu_mem_start 4 continue; Flow J cc=False 0xf10 ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0f10 0x0f10 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_b_adr 13 LOOP_REG typ_mar_cntl 6 INCREMENT_MAR typ_rand e CHECK_CLASS_SYSTEM_B val_alu_func 1c DEC_A val_b_adr 13 LOOP_REG val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 1 INC_LOOP_COUNTER 0f11 0f11 ioc_load_wdr 0 ; Flow J 0xd58 seq_br_type 3 Unconditional Branch seq_branch_adr 0d58 0x0d58 typ_b_adr 13 LOOP_REG val_b_adr 13 LOOP_REG 0f12 0f12 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 36 VR04:16 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 4 0f13 0f13 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 36 TR04:16 typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0f14 0f14 ioc_fiubs 1 val ; Flow C 0x329e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 3a VR05:1a val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 0f15 0f15 seq_en_micro 0 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 13 LOOP_REG val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 0f16 0f16 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 13 LOOP_REG typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 0f17 0f17 seq_br_type 7 Unconditional Call; Flow C 0x3683 seq_branch_adr 3683 0x3683 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 34 VR04:14 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 4 0f18 0f18 typ_a_adr 1e TOP - 2 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR03:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 3 0f19 0f19 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2c VR06:0c val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 6 0f1a 0f1a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 32 TR02:12 typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 0b VR04:14 val_c_mux_sel 2 ALU val_frame 4 0f1b 0f1b fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 0b VR04:14 val_c_mux_sel 2 ALU val_frame 4 0f1c 0f1c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 00 TR04:1f typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 00 VR04:1f val_c_source 0 FIU_BUS val_frame 4 0f1d 0f1d seq_br_type 3 Unconditional Branch; Flow J 0x329c seq_branch_adr 329c 0x329c 0f1e 0f1e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ab4 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 2a TR12:0a typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl 4 RESTORE_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0d:03 val_c_source 0 FIU_BUS val_frame d 0f1f 0f1f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xf24 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f24 0x0f24 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 0f20 0f20 fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x20d fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame d typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 0f21 0f21 seq_br_type 7 Unconditional Call; Flow C 0x3525 seq_branch_adr 3525 0x3525 seq_en_micro 0 0f22 0f22 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0xf23 ; Flow J cc=#0x0 0xf40 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0f40 0x0f40 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0f23 0f23 fiu_len_fill_lit 4d zero-fill 0xd; Flow J cc=True 0xf24 ; Flow J cc=#0x0 0xf26 fiu_load_var 1 hold_var fiu_offs_lit 72 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0f26 0x0f26 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 0f24 0f24 seq_b_timing 0 Early Condition; Flow C cc=True 0x20d seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 0f25 0f25 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de seq_en_micro 0 0f26 0f26 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 0f27 0f27 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 0f28 0f28 fiu_load_var 1 hold_var; Flow J 0xf39 fiu_tivi_src b type_frame ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0f39 0x0f39 seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 0f29 0f29 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xf91 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f91 0x0f91 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 27 VR12:07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0f2a 0f2a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xf2b fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_br_type 2 Push (branch address) seq_branch_adr 0ffa 0x0ffa seq_en_micro 0 val_c_adr 30 GP0f 0f2b ; -------------------------------------------------------------------------------------- 0f2b ; Comes from: 0f2b ; 34d5 C from color 0x34cd 0f2b ; -------------------------------------------------------------------------------------- 0f2b 0f2b fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0xf37 fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f37 0x0f37 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 0f GP0f val_frame 2 0f2c 0f2c fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xf2d ; Flow J cc=#0x0 0xf2d fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0f2d 0x0f2d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 3d VR02:1d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0f2d 0f2d fiu_len_fill_lit 52 zero-fill 0x12; Flow J 0xf2f fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0f2f 0x0f2f seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0f2e 0f2e fiu_len_fill_lit 52 zero-fill 0x12; Flow J 0xf2f fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0f2f 0x0f2f seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 0f2f 0f2f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ab4 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1d A_AND_NOT_B typ_b_adr 33 TR12:13 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3e VR03:1e val_b_adr 0f GP0f val_frame 3 0f30 0f30 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0xf32 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0f32 0x0f32 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 21 VR11:01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 11 0f31 0f31 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_en_micro 0 val_b_adr 2f VR02:0f val_frame 2 0f32 0f32 fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 0f33 0f33 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR0d:0e typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0f34 0f34 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 0f35 0x0f35 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 0f35 0f35 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 33 TR06:13 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 6 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 0f36 0f36 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0x34fe fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 34fe 0x34fe seq_en_micro 0 typ_a_adr 2a TR04:0a typ_alu_func 1c DEC_A typ_b_adr 0d GP0d typ_c_adr 15 TR04:0a typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 0f GP0f val_b_adr 0d GP0d 0f37 0f37 fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0f38 0f38 fiu_mem_start 3 start-wr; Flow J 0x3b8d ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b8d 0x3b8d seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 0f39 0f39 fiu_load_tar 1 hold_tar; Flow C cc=False 0x20d fiu_mem_start 11 start_tag_query fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 62 FIU.WRITE_LAST seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 0f3a 0f3a ioc_tvbs 2 fiu+val; Flow C cc=True 0x32f2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f2 0x32f2 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_c_adr 30 GP0f 0f3b 0f3b seq_br_type 0 Branch False; Flow J cc=False 0x32f2 seq_branch_adr 32f2 0x32f2 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 0f3c 0f3c fiu_mem_start f start_physical_tag_rd; Flow C 0x352c fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 352c 0x352c seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0f3d 0f3d ioc_tvbs 8 typ+mem; Flow C cc=True 0x32f2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32f2 0x32f2 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0f3e 0f3e fiu_mem_start 10 start_physical_tag_wr; Flow J 0xf3f ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 0ffa 0x0ffa seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0f3f 0f3f ioc_load_wdr 0 ; Flow J 0x350a seq_br_type 3 Unconditional Branch seq_branch_adr 350a 0x350a seq_en_micro 0 val_b_adr 0f GP0f 0f40 0f40 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0f41 0f41 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf48 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f48 0x0f48 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f42 0f42 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf5b fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f5b 0x0f5b seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f43 0f43 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf64 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f64 0x0f64 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f44 0f44 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf6e fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f6e 0x0f6e seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f45 0f45 fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf86 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f86 0x0f86 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR0c:03 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0f46 0f46 fiu_len_fill_lit 4d zero-fill 0xd; Flow J 0xf8e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 72 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 0f8e 0x0f8e seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_frame d 0f47 0f47 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0f48 0f48 fiu_load_var 1 hold_var; Flow C cc=False 0xf93 fiu_mem_start 6 start_rd_if_false fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0f93 0x0f93 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0c:03 val_c_mux_sel 2 ALU val_frame c 0f49 0f49 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 33 TR02:13 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 0f4a 0f4a fiu_len_fill_lit 00 sign-fill 0x0; Flow J cc=False 0xf54 fiu_load_var 1 hold_var fiu_offs_lit 28 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0f54 0x0f54 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 20 TR0d:00 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame d val_a_adr 30 VR05:10 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 0f4b 0f4b ioc_fiubs 0 fiu ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 0f4c 0f4c fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame d 0f4d 0f4d fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0xf52 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f52 0x0f52 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f4e 0f4e fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0xfd1 fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fd1 0x0fd1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f4f 0f4f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xfd1 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fd1 0x0fd1 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 2b TR12:0b typ_alu_func 1d A_AND_NOT_B typ_b_adr 0e GP0e typ_frame 12 val_a_adr 31 VR04:11 val_alu_func 1e A_AND_B val_b_adr 0e GP0e val_frame 4 0f50 0f50 fiu_mem_start 11 start_tag_query; Flow J cc=False 0xfab fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0fab 0x0fab seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS 0f51 0f51 seq_br_type 3 Unconditional Branch; Flow J 0xfd1 seq_branch_adr 0fd1 0x0fd1 seq_en_micro 0 0f52 0f52 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32ac fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ac 0x32ac seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 0b GP0b val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 29 VR12:09 val_frame 12 0f53 0f53 fiu_mem_start 11 start_tag_query; Flow J 0xfab ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fab 0x0fab seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_c_adr 34 GP0b 0f54 0f54 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xfd1 seq_br_type 1 Branch True seq_branch_adr 0fd1 0x0fd1 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2b TR12:0b typ_alu_func 1e A_AND_B typ_b_adr 0e GP0e typ_frame 12 0f55 0f55 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0xfde fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0fde 0x0fde seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame d 0f56 0f56 ioc_tvbs 3 fiu+fiu; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 0f57 0f57 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0xf52 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f52 0x0f52 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0d GP0d 0f58 0f58 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 30 VR05:10 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 5 0f59 0f59 fiu_mem_start 11 start_tag_query; Flow J cc=False 0xfab seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0fab 0x0fab seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0d GP0d 0f5a 0f5a seq_br_type 3 Unconditional Branch; Flow J 0xfcd seq_branch_adr 0fcd 0x0fcd seq_en_micro 0 0f5b 0f5b fiu_load_var 1 hold_var; Flow C cc=False 0xf9c fiu_mem_start 6 start_rd_if_false fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0f9c 0x0f9c seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0c:03 val_c_mux_sel 2 ALU val_frame c 0f5c 0f5c fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 32 TR12:12 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 0f5d 0f5d ioc_tvbs 1 typ+fiu; Flow J cc=False 0xfd1 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0fd1 0x0fd1 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1c DEC_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 0 NO_OP val_a_adr 30 VR05:10 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 0f5e 0f5e seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 2c TR12:0c typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 0f5f 0f5f fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0f60 0f60 fiu_len_fill_lit 14 sign-fill 0x14; Flow J cc=False 0xf62 fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f62 0x0f62 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_adr 34 GP0b val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f61 0f61 seq_br_type 3 Unconditional Branch; Flow J 0xfcd seq_branch_adr 0fcd 0x0fcd seq_en_micro 0 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 0f62 0f62 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32cb fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32cb 0x32cb seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 2f VR12:0f val_frame 12 0f63 0f63 fiu_mem_start 11 start_tag_query; Flow J 0xfab ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fab 0x0fab seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU 0f64 0f64 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c 0f65 0f65 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 33 TR02:13 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_frame d 0f66 0f66 fiu_mem_start 4 continue ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 7 INC_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_a_adr 30 VR05:10 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 0f67 0f67 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0xfde seq_br_type 0 Branch False seq_branch_adr 0fde 0x0fde seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2d TR12:0d typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 16 CSA/VAL_BUS 0f68 0f68 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0f69 0f69 fiu_tivi_src 2 tar_fiu; Flow C 0x210 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR01:02 typ_frame 1 val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0f6a 0f6a ioc_tvbs 1 typ+fiu; Flow J cc=True 0xfd1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fd1 0x0fd1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 34 GP0b val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f6b 0f6b ioc_fiubs 0 fiu ; Flow C cc=True 0x32ce seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32ce 0x32ce seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 2f VR12:0f val_frame 12 0f6c 0f6c fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A val_a_adr 0b GP0b val_b_adr 0f GP0f 0f6d 0f6d fiu_mem_start 11 start_tag_query; Flow J 0xfab ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0fab 0x0fab seq_en_micro 0 val_c_adr 34 GP0b val_c_source 0 FIU_BUS 0f6e 0f6e fiu_load_var 1 hold_var; Flow C cc=False 0xf9c fiu_mem_start 6 start_rd_if_false fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0f9c 0x0f9c seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0c:03 val_c_mux_sel 2 ALU val_frame c 0f6f 0f6f fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 32 TR12:12 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 0f70 0f70 ioc_tvbs 1 typ+fiu; Flow J cc=False 0xf77 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 0f77 0x0f77 seq_en_micro 0 val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 0f71 0f71 fiu_vmux_sel 1 fill value; Flow C 0x210 ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 21 VR02:01 val_alu_func 1c DEC_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0f72 0f72 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f val_b_adr 16 CSA/VAL_BUS 0f73 0f73 fiu_mem_start 11 start_tag_query; Flow J cc=False 0xf75 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0f75 0x0f75 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 34 GP0b val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b 0f74 0f74 seq_br_type 3 Unconditional Branch; Flow J 0xfcd seq_branch_adr 0fcd 0x0fcd seq_en_micro 0 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 0f75 0f75 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32cc seq_br_type 5 Call True seq_branch_adr 32cc 0x32cc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 0f76 0f76 fiu_mem_start 11 start_tag_query; Flow J 0xfab seq_br_type 3 Unconditional Branch seq_branch_adr 0fab 0x0fab seq_en_micro 0 val_a_adr 0b GP0b val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 0f77 0f77 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xf72 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 0f72 0x0f72 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0f78 0f78 ioc_tvbs 1 typ+fiu; Flow J cc=False 0xfde seq_br_type 0 Branch False seq_branch_adr 0fde 0x0fde seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 2e VR04:0e val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0f79 0f79 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xfe4 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fe4 0x0fe4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3a VR05:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 0f7a 0f7a fiu_mem_start 2 start-rd; Flow C 0x1000 fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 1000 0x1000 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 21 TR05:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_frame d val_rand 9 PASS_A_HIGH 0f7b 0f7b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_en_micro 0 0f7c 0f7c fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0xfde fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0fde 0x0fde seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 0f7d 0f7d fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 33 GP0c val_c_source 0 FIU_BUS 0f7e 0f7e fiu_len_fill_lit 00 sign-fill 0x0; Flow C 0x1000 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 1000 0x1000 seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0c GP0c 0f7f 0f7f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR0d:00 val_c_adr 33 GP0c val_c_source 0 FIU_BUS val_frame d val_rand 9 PASS_A_HIGH 0f80 0f80 seq_en_micro 0 val_a_adr 3f VR06:1f val_alu_func 1e A_AND_B val_b_adr 0c GP0c val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 6 0f81 0f81 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 typ_b_adr 0b GP0b val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 0f82 0f82 ioc_load_wdr 0 ; Flow J cc=True 0xfcd ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0fcd 0x0fcd seq_en_micro 0 typ_b_adr 0c GP0c typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 38 VR02:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 0f83 0f83 seq_en_micro 0 typ_c_adr 33 GP0c val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_b_adr 33 VR02:13 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 0f84 0f84 fiu_mem_start 11 start_tag_query; Flow J cc=True 0xfab seq_br_type 1 Branch True seq_branch_adr 0fab 0x0fab seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e 0f85 0f85 seq_br_type 7 Unconditional Call; Flow C 0x32e6 seq_branch_adr 32e6 0x32e6 seq_en_micro 0 0f86 0f86 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c 0f87 0f87 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 20 VR0d:00 val_frame d val_rand a PASS_B_HIGH 0f88 0f88 ioc_fiubs 0 fiu ; Flow J cc=True 0xfd2 ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 0fd2 0x0fd2 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2b TR12:0b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0f89 0f89 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0xfde fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0fde 0x0fde seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 0f8a 0f8a fiu_tivi_src c mar_0xc; Flow J cc=True 0xf8d ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f8d 0x0f8d seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 25 TR00:05 typ_alu_func 0 PASS_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0f8b 0f8b ioc_tvbs 2 fiu+val; Flow J cc=False 0xfe5 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0fe5 0x0fe5 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 0e GP0e val_alu_func 1e A_AND_B val_b_adr 32 VR06:12 val_frame 6 0f8c 0f8c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0f8d 0f8d fiu_mem_start 11 start_tag_query; Flow J 0xfab ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 0fab 0x0fab seq_en_micro 0 typ_a_adr 3f TR06:1f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 6 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 0f8e 0f8e ioc_tvbs 3 fiu+fiu; Flow J cc=False 0xfe5 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0fe5 0x0fe5 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 2b TR12:0b typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 val_a_adr 27 VR12:07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0f8f 0f8f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0xf91 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0f91 0x0f91 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 val_a_adr 3e VR09:1e val_frame 9 0f90 0f90 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xfe5 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0fe5 0x0fe5 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame d 0f91 0f91 fiu_mem_start 2 start-rd; Flow C 0x1000 seq_br_type 7 Unconditional Call seq_branch_adr 1000 0x1000 seq_en_micro 0 0f92 0f92 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 0f93 ; -------------------------------------------------------------------------------------- 0f93 ; Comes from: 0f93 ; 0f48 C False from color 0x0f29 0f93 ; -------------------------------------------------------------------------------------- 0f93 0f93 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xf9d fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 0f9d 0x0f9d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_a_adr 2b VR0c:0b val_alu_func 6 A_MINUS_B val_b_adr 23 VR0c:03 val_frame c 0f94 0f94 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 23 TR0c:03 typ_frame c 0f95 0f95 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0f96 0f96 fiu_mem_start 2 start-rd ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR0c:03 val_c_mux_sel 2 ALU val_frame c 0f97 0f97 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xf95 seq_br_type 1 Branch True seq_branch_adr 0f95 0x0f95 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_a_adr 2b VR0c:0b val_alu_func 6 A_MINUS_B val_b_adr 23 VR0c:03 val_frame c 0f98 0f98 fiu_len_fill_lit 57 zero-fill 0x17; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0c:05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame c val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 0f99 0f99 ioc_fiubs 2 typ ; Flow C cc=True 0x32d1 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d1 0x32d1 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d val_a_adr 25 VR0c:05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0c:05 val_c_source 0 FIU_BUS val_frame c 0f9a 0f9a seq_en_micro 0 val_a_adr 25 VR0c:05 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 1a VR0c:05 val_c_mux_sel 2 ALU val_frame c 0f9b 0f9b ioc_tvbs 1 typ+fiu; Flow R cc=False ; Flow J cc=True 0x32d1 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32d1 0x32d1 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 25 VR0c:05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame c 0f9c ; -------------------------------------------------------------------------------------- 0f9c ; Comes from: 0f9c ; 0f5b C False from color 0x0f29 0f9c ; 0f6e C False from color 0x0f29 0f9c ; -------------------------------------------------------------------------------------- 0f9c 0f9c fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xf94 fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f94 0x0f94 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_a_adr 2b VR0c:0b val_alu_func 6 A_MINUS_B val_b_adr 23 VR0c:03 val_frame c 0f9d 0f9d fiu_len_fill_lit 57 zero-fill 0x17; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0c:05 val_c_mux_sel 2 ALU val_frame c val_rand 9 PASS_A_HIGH 0f9e 0f9e ioc_fiubs 0 fiu ; Flow J cc=True 0xfa0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fa0 0x0fa0 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_c_adr 1b TR0c:04 typ_c_source 0 FIU_BUS typ_frame c val_a_adr 25 VR0c:05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame c 0f9f 0f9f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0xf94 seq_br_type 0 Branch False seq_branch_adr 0f94 0x0f94 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 6 A_MINUS_B typ_b_adr 24 TR0c:04 typ_frame c 0fa0 0fa0 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0xf94 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f94 0x0f94 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2e TR13:0e typ_alu_func 1e A_AND_B typ_b_adr 0b GP0b typ_c_adr 32 GP0d typ_frame 13 val_a_adr 20 VR0d:00 val_frame d 0fa1 0fa1 ioc_fiubs 0 fiu ; Flow J cc=True 0xfa9 seq_br_type 1 Branch True seq_branch_adr 0fa9 0x0fa9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1e A_AND_B typ_b_adr 26 TR0c:06 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame c 0fa2 0fa2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xf94 seq_br_type 1 Branch True seq_branch_adr 0f94 0x0f94 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 19 X_XOR_B typ_b_adr 0c GP0c val_c_adr 1a VR0c:05 val_frame c 0fa3 0fa3 fiu_load_var 1 hold_var; Flow J cc=True 0xf94 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f94 0x0f94 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_a_adr 20 TR02:00 typ_b_adr 20 TR02:00 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame 2 0fa4 0fa4 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xf94 seq_br_type 1 Branch True seq_branch_adr 0f94 0x0f94 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 1e A_AND_B typ_b_adr 0b GP0b typ_frame 2 val_a_adr 2d VR0c:0d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame c 0fa5 0fa5 fiu_mem_start 3 start-wr seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1b A_OR_B typ_b_adr 26 TR0c:06 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame c 0fa6 0fa6 ioc_fiubs 2 typ ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 2d TR13:0d typ_b_adr 0d GP0d typ_frame 13 val_b_adr 25 VR0c:05 val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame c 0fa7 0fa7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3681 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_random d disable slice timer seq_br_type 7 Unconditional Call seq_branch_adr 3681 0x3681 seq_en_micro 0 typ_a_adr 3c TR12:1c typ_frame 12 val_a_adr 21 VR02:01 val_alu_func 1b A_OR_B val_b_adr 0b GP0b val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 0fa8 0fa8 ioc_random c enable slice timer; Flow J 0xf94 seq_br_type 3 Unconditional Branch seq_branch_adr 0f94 0x0f94 seq_en_micro 0 0fa9 0fa9 fiu_mem_start 3 start-wr seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 6 A_MINUS_B typ_b_adr 30 TR07:10 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 1a VR0c:05 val_frame c 0faa 0faa ioc_load_wdr 0 ; Flow J 0xf94 seq_br_type 3 Unconditional Branch seq_branch_adr 0f94 0x0f94 seq_en_micro 0 typ_b_adr 0d GP0d val_b_adr 25 VR0c:05 val_frame c 0fab 0fab fiu_len_fill_lit 4c zero-fill 0xc; Flow C 0x3524 fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 7 Unconditional Call seq_branch_adr 3524 0x3524 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_b_adr 20 TR0d:00 typ_frame d val_b_adr 20 VR0d:00 val_frame d 0fac 0fac ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 0c GP0c val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0fad 0fad fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_mem_start 13 start_available_query fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 20 TR0d:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_b_adr 0f GP0f val_frame d 0fae 0fae fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=False 0x32f2 fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32f2 0x32f2 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A val_a_adr 25 VR05:05 val_alu_func 1d A_AND_NOT_B val_b_adr 0f GP0f val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 5 0faf 0faf seq_br_type 7 Unconditional Call; Flow C 0x3525 seq_branch_adr 3525 0x3525 seq_en_micro 0 0fb0 0fb0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xfc8 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0fc8 0x0fc8 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 30 VR12:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 0fb1 0fb1 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 0fb2 0fb2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert seq_en_micro 0 0fb3 0fb3 fiu_len_fill_lit 00 sign-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 72 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 0d GP0d typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_c_adr 33 GP0c val_c_source 0 FIU_BUS 0fb4 0fb4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU val_a_adr 0c GP0c 0fb5 0fb5 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 0fb6 0fb6 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 0fb7 0fb7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start f start_physical_tag_rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 0e GP0e typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0c GP0c val_alu_func 1e A_AND_B val_b_adr 21 VR05:01 val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 5 0fb8 0fb8 fiu_mem_start 15 setup_tag_read; Flow C 0x210 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame d val_a_adr 0c GP0c 0fb9 0fb9 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 30 VR12:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 0fba 0fba fiu_mem_start 10 start_physical_tag_wr ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_b_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU 0fbb 0fbb fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x34fd fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 34fd 0x34fd seq_en_micro 0 val_b_adr 0e GP0e 0fbc 0fbc fiu_load_var 1 hold_var; Flow J cc=True 0xfc3 fiu_tivi_src c mar_0xc seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0fc3 0x0fc3 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 0fbd 0fbd seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation seq_en_micro 0 seq_latch 1 typ_b_adr 0f GP0f typ_c_lit 2 typ_frame 1e 0fbe 0fbe fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 0c GP0c typ_mar_cntl 6 INCREMENT_MAR 0fbf 0fbf fiu_load_tar 1 hold_tar; Flow C 0x1000 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1000 0x1000 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_b_adr 0b GP0b val_b_adr 0b GP0b 0fc0 0fc0 fiu_mem_start e start_physical_wr; Flow J cc=False 0xfc5 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0fc5 0x0fc5 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 3d TR08:1d typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 0fc1 0fc1 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 0fc2 0fc2 fiu_mem_start e start_physical_wr; Flow J 0xfc5 seq_br_type 3 Unconditional Branch seq_branch_adr 0fc5 0x0fc5 seq_en_micro 0 0fc3 0fc3 fiu_load_tar 1 hold_tar; Flow J cc=True 0xffa fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 1 Branch True seq_branch_adr 0ffa 0x0ffa seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_b_adr 0f GP0f typ_c_lit 2 typ_frame 1e val_b_adr 0e GP0e 0fc4 0fc4 fiu_mem_start e start_physical_wr; Flow J cc=True 0xfc1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fc1 0x0fc1 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 3d TR08:1d typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 0fc5 0fc5 fiu_mem_start 4 continue; Flow J cc=False 0xfc5 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0fc5 0x0fc5 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 39 VR02:19 val_frame 2 0fc6 0fc6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xffa fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ffa 0x0ffa seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 0fc7 0fc7 fiu_mem_start e start_physical_wr; Flow J 0xfc5 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0fc5 0x0fc5 seq_en_micro 0 typ_a_adr 3d TR08:1d typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0fc8 0fc8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 1a TR0d:05 typ_c_mux_sel 0 ALU typ_frame d val_c_adr 1a VR0d:05 val_c_source 0 FIU_BUS val_frame d 0fc9 0fc9 seq_br_type 7 Unconditional Call; Flow C 0x1001 seq_branch_adr 1001 0x1001 seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 0b GP0b val_alu_func 0 PASS_A val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 0fca 0fca fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xffa fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 0ffa 0x0ffa seq_en_micro 0 typ_a_adr 24 TR0d:04 typ_alu_func 0 PASS_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame d val_a_adr 25 VR0d:05 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame d 0fcb 0fcb fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0xffa fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 0 Branch False seq_branch_adr 0ffa 0x0ffa seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 25 TR0d:05 typ_alu_func 0 PASS_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame d val_a_adr 24 VR0d:04 val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame d 0fcc 0fcc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xfae fiu_mem_start 13 start_available_query fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0fae 0x0fae seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0fcd 0fcd fiu_mem_start f start_physical_tag_rd; Flow C 0x352c fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 352c 0x352c seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 0fce 0fce ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 0c GP0c val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 0fcf 0fcf fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 0f GP0f 0fd0 0fd0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0xfd2 fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0fd2 0x0fd2 seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 0fd1 0fd1 fiu_mem_start 2 start-rd; Flow J 0xfd2 fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 0fd2 0x0fd2 seq_en_micro 0 typ_a_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR0d:00 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 0fd2 0fd2 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x32de ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 35 TR07:15 typ_alu_func 14 A_NOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 20 VR0d:00 val_frame d val_rand 9 PASS_A_HIGH 0fd3 0fd3 seq_br_type 0 Branch False; Flow J cc=False 0xfe5 seq_branch_adr 0fe5 0x0fe5 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0fd4 0fd4 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x3525 seq_br_type 7 Unconditional Call seq_branch_adr 3525 0x3525 seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 0fd5 0fd5 ioc_load_wdr 0 ; Flow J cc=True 0xf2a ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0f2a 0x0f2a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0fd6 0fd6 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0xfe5 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fe5 0x0fe5 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 0fd7 0fd7 seq_br_type 3 Unconditional Branch; Flow J 0xfd8 seq_branch_adr 0fd8 0x0fd8 seq_en_micro 0 0fd8 0fd8 fiu_len_fill_lit 4c zero-fill 0xc; Flow C cc=False 0x32e6 fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32e6 0x32e6 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 20 TR0d:00 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS typ_frame d typ_mar_cntl 4 RESTORE_MAR typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_b_adr 20 VR0d:00 val_frame d 0fd9 0fd9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xfdc fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0fdc 0x0fdc seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d 0fda 0fda fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0xfae fiu_mem_start 13 start_available_query fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 0fae 0x0fae seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 0fdb 0fdb seq_br_type 3 Unconditional Branch; Flow J 0xffa seq_branch_adr 0ffa 0x0ffa seq_en_micro 0 0fdc 0fdc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0xffa seq_br_type 1 Branch True seq_branch_adr 0ffa 0x0ffa seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_latch 1 typ_a_adr 3c TR07:1c typ_alu_func 0 PASS_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 33 VR02:13 val_alu_func 0 PASS_A val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 2 0fdd 0fdd seq_br_type 7 Unconditional Call; Flow C 0x32e6 seq_branch_adr 32e6 0x32e6 seq_en_micro 0 0fde 0fde fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 11 start_tag_query fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 20 TR0d:00 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame d typ_rand c WRITE_OUTER_FRAME 0fdf 0fdf fiu_tivi_src 4 fiu_var; Flow C cc=True 0x32de ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 35 TR07:15 typ_alu_func 14 A_NOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 20 VR0d:00 val_frame d val_rand 9 PASS_A_HIGH 0fe0 0fe0 seq_br_type 7 Unconditional Call; Flow C 0x3525 seq_branch_adr 3525 0x3525 seq_en_micro 0 0fe1 0fe1 fiu_load_var 1 hold_var; Flow J cc=False 0xfe6 fiu_tivi_src 1 tar_val ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 0fe6 0x0fe6 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 0fe2 0fe2 ioc_load_wdr 0 ; Flow J cc=True 0xf2a ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 0f2a 0x0f2a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 0fe3 0fe3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0fe4 0fe4 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x32de ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 35 TR07:15 typ_alu_func 14 A_NOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 20 VR0d:00 val_frame d val_rand 9 PASS_A_HIGH 0fe5 0fe5 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 0fe6 0fe6 seq_br_type 7 Unconditional Call; Flow C 0xfe9 seq_branch_adr 0fe9 0x0fe9 seq_en_micro 0 0fe7 0fe7 seq_b_timing 1 Latch Condition; Flow J cc=False 0xffa seq_br_type 0 Branch False seq_branch_adr 0ffa 0x0ffa seq_en_micro 0 0fe8 0fe8 seq_br_type 3 Unconditional Branch; Flow J 0xfd8 seq_branch_adr 0fd8 0x0fd8 seq_en_micro 0 0fe9 ; -------------------------------------------------------------------------------------- 0fe9 ; Comes from: 0fe9 ; 0fe6 C from color 0x0f29 0fe9 ; 34d9 C False from color 0x34cd 0fe9 ; -------------------------------------------------------------------------------------- 0fe9 0fe9 fiu_tivi_src c mar_0xc; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_en_micro 0 typ_a_adr 23 TR05:03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 0fea 0fea seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 0feb 0x0feb seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 0feb 0feb seq_br_type 7 Unconditional Call; Flow C 0x3654 seq_branch_adr 3654 0x3654 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 0fec 0fec fiu_mem_start 2 start-rd; Flow C 0x1000 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 1000 0x1000 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR09:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0fed 0fed ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 0fee 0fee fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 0fef 0fef fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0xff2 fiu_load_var 1 hold_var fiu_offs_lit 7b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ff2 0x0ff2 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 0c GP0c val_frame 5 0ff0 0ff0 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 39 VR12:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 0ff1 0ff1 ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0b GP0b val_b_adr 0b GP0b 0ff2 0ff2 ioc_tvbs 1 typ+fiu; Flow J cc=True 0xff3 ; Flow J cc=#0x0 0xff4 seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 0ff4 0x0ff4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 3e VR03:1e val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 3 0ff3 0ff3 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 0ff4 0ff4 seq_br_type a Unconditional Return; Flow R seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 0ff5 0ff5 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 0ff6 0ff6 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 0ff7 0ff7 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 0ff8 0ff8 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x365c fiu_load_var 1 hold_var fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 365c 0x365c seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_mar_cntl 1 RESTORE_RDR val_b_adr 0c GP0c 0ff9 0ff9 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 0ffa 0ffa fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0xff9 fiu_len_fill_reg_ctl 2 fiu_load_oreg 1 hold_oreg fiu_offs_lit 27 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0ff9 0x0ff9 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 0ffb 0ffb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0xffc ; Flow J cc=#0x0 0xffc fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start b start_last_cmd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 0ffc 0x0ffc seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d val_b_adr 23 VR0d:03 val_frame d 0ffc 0ffc fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d val_a_adr 22 VR0d:02 val_b_adr 21 VR0d:01 val_frame d 0ffd 0ffd seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 0ffe 0ffe fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 22 VR0d:02 val_b_adr 21 VR0d:01 val_frame d 0fff 0fff fiu_load_var 1 hold_var; Flow R fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 22 VR0d:02 val_b_adr 21 VR0d:01 val_frame d 1000 ; -------------------------------------------------------------------------------------- 1000 ; Comes from: 1000 ; 0f7a C from color 0x0f29 1000 ; 0f7e C from color 0x0f29 1000 ; 0f91 C from color 0x0f29 1000 ; 0fbf C from color 0x0f29 1000 ; 0fec C from color 0x0fea 1000 ; -------------------------------------------------------------------------------------- 1000 1000 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 1001 ; -------------------------------------------------------------------------------------- 1001 ; Comes from: 1001 ; 0e7e C from color 0x0e7b 1001 ; 0fc9 C from color 0x0f29 1001 ; 3409 C from color 0x0f36 1001 ; 366f C from color 0x1004 1001 ; 3674 C from color 0x3667 1001 ; -------------------------------------------------------------------------------------- 1001 1001 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 3 val_rand a PASS_B_HIGH 1002 1002 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 1003 1003 fiu_vmux_sel 1 fill value; Flow C 0x2ab4 ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1004 1004 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 12 start_lru_query fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1005 1005 fiu_fill_mode_src 0 ; Flow J cc=False 0x100c fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 100c 0x100c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR05:01 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 3f VR08:1f val_frame 8 1006 1006 fiu_mem_start f start_physical_tag_rd fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 1007 1007 fiu_mem_start 15 setup_tag_read seq_en_micro 0 1008 1008 fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 1009 1009 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x1010 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1010 0x1010 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR05:01 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 5 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 25 VR06:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 100a 100a seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 100b 100b fiu_mem_start 12 start_lru_query; Flow J 0x1005 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1005 0x1005 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 100c 100c fiu_mem_start f start_physical_tag_rd; Flow J cc=True 0x1007 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1007 0x1007 seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 100d 100d fiu_mem_start 15 setup_tag_read seq_en_micro 0 100e 100e fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 100f 100f fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x100a fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 100a 0x100a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_a_adr 25 VR06:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 1010 1010 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1012 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 1012 0x1012 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_frame 2 1011 1011 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1013 seq_br_type 1 Branch True seq_branch_adr 1013 0x1013 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 3f VR08:1f val_frame 8 1012 1012 fiu_fill_mode_src 0 ; Flow J 0x1013 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 3 Unconditional Branch seq_branch_adr 1013 0x1013 seq_en_micro 0 typ_rand e CHECK_CLASS_SYSTEM_B 1013 1013 fiu_len_fill_lit 52 zero-fill 0x12 fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 4 1014 1014 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame d val_alu_func 13 ONES val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 1015 1015 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 typ_alu_func 13 ONES typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 0d GP0d val_alu_func 1a PASS_B val_b_adr 2d VR12:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 1016 1016 fiu_mem_start f start_physical_tag_rd; Flow J 0x1017 ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1017 0x1017 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 06 TR03:19 typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl f LOAD_MAR_RESERVED 1017 1017 fiu_len_fill_lit 7b zero-fill 0x3b; Flow J cc=True 0x1071 fiu_load_var 1 hold_var fiu_mem_start 15 setup_tag_read fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1071 0x1071 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_latch 1 typ_b_adr 0d GP0d typ_mar_cntl 1 RESTORE_RDR typ_rand d SET_PASS_PRIVACY_BIT 1018 1018 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x101d fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs a fiu+mem seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 101d 0x101d seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_mar_cntl 3 SPARE_0x03 val_a_adr 3c VR02:1c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 1019 1019 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x101a ; Flow J cc=#0x0 0x1032 fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 1032 0x1032 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_c_adr 32 GP0d 101a 101a seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 101b 101b fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x1019 fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1019 0x1019 seq_en_micro 0 val_b_adr 0d GP0d 101c 101c fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=False 0x1019 fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs a fiu+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1019 0x1019 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 3c VR02:1c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 101d 101d fiu_mem_start f start_physical_tag_rd; Flow J cc=True 0x1023 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1023 0x1023 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 2d VR12:0d val_frame 12 101e 101e fiu_mem_start 15 setup_tag_read ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0c GP0c val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 101f 101f fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 1020 1020 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_c_adr 28 LOOP_COUNTER typ_frame 11 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 2 1021 1021 seq_br_type 7 Unconditional Call; Flow C 0x350a seq_branch_adr 350a 0x350a seq_en_micro 0 1022 1022 fiu_len_fill_reg_ctl 2 ; Flow R fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 1023 1023 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1025 seq_br_type 1 Branch True seq_branch_adr 1025 0x1025 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_b_adr 0c GP0c val_rand a PASS_B_HIGH 1024 1024 fiu_len_fill_reg_ctl 2 ; Flow R cc=False ; Flow J cc=True 0x107d fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 107d 0x107d seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_mar_cntl 4 RESTORE_MAR val_a_adr 0c GP0c val_alu_func 1a PASS_B val_b_adr 0b GP0b val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1025 1025 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 12 start_lru_query fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1026 1026 seq_b_timing 0 Early Condition; Flow J cc=True 0x102d seq_br_type 1 Branch True seq_branch_adr 102d 0x102d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_rand 2 DEC_LOOP_COUNTER 1027 1027 fiu_mem_start f start_physical_tag_rd; Flow C 0x352c fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 352c 0x352c seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 1028 1028 fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 1029 1029 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ab4 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 2b VR12:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 102a 102a fiu_mem_start 12 start_lru_query; Flow J cc=False 0x1026 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1026 0x1026 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 val_a_adr 0d GP0d val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_frame 2 102b 102b seq_b_timing 0 Early Condition; Flow J cc=True 0x1031 seq_br_type 1 Branch True seq_branch_adr 1031 0x1031 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_rand 2 DEC_LOOP_COUNTER 102c 102c fiu_mem_start 12 start_lru_query; Flow J 0x102b seq_br_type 3 Unconditional Branch seq_branch_adr 102b 0x102b seq_en_micro 0 102d 102d fiu_mem_start f start_physical_tag_rd; Flow C 0x352c fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 352c 0x352c seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 102e 102e fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 102f 102f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 val_a_adr 2b VR12:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 1030 1030 fiu_tivi_src 4 fiu_var; Flow J cc=False 0x1024 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 1024 0x1024 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 val_a_adr 0d GP0d val_alu_func 19 X_XOR_B val_b_adr 32 VR02:12 val_frame 2 1031 1031 fiu_mem_start f start_physical_tag_rd; Flow J 0x101e ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 101e 0x101e seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED 1032 1032 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 1033 1033 fiu_tivi_src 4 fiu_var; Flow J 0x103a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 103a 0x103a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 2b TR06:0b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 0d GP0d val_alu_func 18 NOT_A_AND_B val_b_adr 30 VR11:10 val_frame 11 1034 1034 fiu_mem_start 11 start_tag_query; Flow J 0x1061 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1061 0x1061 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0d GP0d val_rand 9 PASS_A_HIGH 1035 1035 fiu_mem_start f start_physical_tag_rd; Flow J 0x1017 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1017 0x1017 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_mar_cntl f LOAD_MAR_RESERVED 1036 1036 fiu_mem_start 11 start_tag_query; Flow J 0x1069 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1069 0x1069 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0d GP0d val_rand 9 PASS_A_HIGH 1037 1037 fiu_mem_start f start_physical_tag_rd; Flow J 0x1017 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1017 0x1017 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_mar_cntl f LOAD_MAR_RESERVED 1038 1038 fiu_mem_start f start_physical_tag_rd; Flow J 0x1017 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1017 0x1017 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_mar_cntl f LOAD_MAR_RESERVED 1039 1039 fiu_mem_start f start_physical_tag_rd; Flow J 0x1017 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1017 0x1017 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED 103a 103a fiu_mem_start 11 start_tag_query; Flow C 0x3523 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3523 0x3523 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0d GP0d val_rand 9 PASS_A_HIGH 103b 103b fiu_tivi_src 3 tar_frame; Flow J cc=False 0x1035 ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1035 0x1035 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 8 103c 103c ioc_adrbs 2 typ ; Flow J cc=True 0x1035 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1035 0x1035 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_frame 12 103d 103d fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1044 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1044 0x1044 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 3b TR02:1b typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 0d GP0d 103e 103e fiu_mem_start d start_physical_rd; Flow J cc=False 0x1042 ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1042 0x1042 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 103f 103f fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 1040 1040 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x1035 seq_br_type 0 Branch False seq_branch_adr 1035 0x1035 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 1041 1041 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1035 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1035 0x1035 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 1042 1042 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1035 seq_br_type 0 Branch False seq_branch_adr 1035 0x1035 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 32 GP0d 1043 1043 fiu_mem_start f start_physical_tag_rd; Flow J 0x101e ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 101e 0x101e seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1044 1044 seq_br_type 1 Branch True; Flow J cc=True 0x1046 seq_branch_adr 1046 0x1046 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1e A_AND_B typ_b_adr 0d GP0d typ_frame 6 val_a_adr 0d GP0d val_alu_func 1e A_AND_B val_b_adr 3c VR06:1c val_frame 6 1045 1045 seq_br_type 3 Unconditional Branch; Flow J 0x1043 seq_branch_adr 1043 0x1043 seq_en_micro 0 typ_c_adr 32 GP0d 1046 1046 fiu_mem_start d start_physical_rd; Flow J cc=True 0x1058 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1058 0x1058 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1e A_AND_B typ_b_adr 0d GP0d typ_frame 6 1047 1047 fiu_mem_start 9 start_continue_if_true; Flow J cc=False 0x1056 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1056 0x1056 seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 1048 1048 fiu_len_fill_lit 07 sign-fill 0x7; Flow C 0x210 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 1 1049 1049 fiu_mem_start 11 start_tag_query ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0d GP0d val_alu_func 13 ONES val_rand 9 PASS_A_HIGH 104a 104a fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x1054 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1054 0x1054 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 15 NOT_B typ_b_adr 0d GP0d 104b 104b fiu_fill_mode_src 0 ; Flow J cc=False 0x104e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 104e 0x104e seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 26 VR0d:06 val_frame d 104c 104c fiu_fill_mode_src 0 ; Flow J cc=True 0x104d ; Flow J cc=#0x0 0x104d fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 104d 0x104d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_b_adr 28 TR0d:08 typ_c_adr 32 GP0d typ_frame d val_b_adr 28 VR0d:08 val_c_adr 32 GP0d val_frame d 104d 104d seq_b_timing 0 Early Condition; Flow J cc=True 0x104e ; Flow J cc=#0x0 0x1056 seq_br_type b Case False seq_branch_adr 1056 0x1056 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1b A_OR_B typ_b_adr 2b TR08:0b typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 0d GP0d val_alu_func 1b A_OR_B val_b_adr 2d VR12:0d val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 104e 104e fiu_tivi_src c mar_0xc; Flow C 0x3526 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3526 0x3526 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 104f 104f fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x1035 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1035 0x1035 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 1050 1050 seq_br_type 0 Branch False; Flow J cc=False 0x1035 seq_branch_adr 1035 0x1035 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 2 1051 1051 fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 1052 1052 ioc_load_wdr 0 ; Flow C 0x350a seq_br_type 7 Unconditional Call seq_branch_adr 350a 0x350a seq_en_micro 0 typ_c_adr 32 GP0d val_b_adr 0d GP0d val_c_adr 32 GP0d 1053 1053 ioc_load_wdr 0 ; Flow J 0x1035 seq_br_type 3 Unconditional Branch seq_branch_adr 1035 0x1035 seq_en_micro 0 typ_b_adr 0d GP0d val_b_adr 0d GP0d 1054 1054 fiu_fill_mode_src 0 ; Flow J cc=False 0x1035 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1035 0x1035 seq_en_micro 0 typ_b_adr 2f TR0d:0f typ_c_adr 32 GP0d typ_frame d val_b_adr 2f VR0d:0f val_c_adr 32 GP0d val_frame d 1055 1055 seq_b_timing 0 Early Condition; Flow J cc=True 0x1056 ; Flow J cc=#0x0 0x1056 seq_br_type b Case False seq_branch_adr 1056 0x1056 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1b A_OR_B typ_b_adr 2b TR08:0b typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 0d GP0d val_alu_func 1b A_OR_B val_b_adr 2d VR12:0d val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 1056 1056 fiu_mem_start f start_physical_tag_rd; Flow J 0x1017 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1017 0x1017 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED 1057 1057 ioc_load_wdr 0 ; Flow J 0x1035 seq_br_type 3 Unconditional Branch seq_branch_adr 1035 0x1035 seq_en_micro 0 typ_b_adr 0d GP0d val_b_adr 0d GP0d 1058 1058 fiu_mem_start d start_physical_rd seq_en_micro 0 1059 1059 fiu_mem_start 9 start_continue_if_true; Flow J cc=False 0x1056 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1056 0x1056 seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 105a 105a fiu_len_fill_lit 07 sign-fill 0x7 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 105b 105b fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_alu_func 10 NOT_A typ_b_adr 16 CSA/VAL_BUS 105c 105c fiu_fill_mode_src 0 ; Flow J cc=True 0x1054 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1054 0x1054 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_alu_func 10 NOT_A typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 26 VR0d:06 val_frame d 105d 105d fiu_fill_mode_src 0 ; Flow J cc=True 0x105e ; Flow J cc=#0x0 0x105f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 105f 0x105f seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 typ_b_adr 28 TR0d:08 typ_c_adr 32 GP0d typ_frame d val_b_adr 28 VR0d:08 val_c_adr 32 GP0d val_frame d 105e 105e fiu_mem_start f start_physical_tag_rd; Flow J 0x101e ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 101e 0x101e seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 105f 105f seq_b_timing 0 Early Condition; Flow J cc=True 0x1060 ; Flow J cc=#0x0 0x1056 seq_br_type b Case False seq_branch_adr 1056 0x1056 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1b A_OR_B typ_b_adr 2b TR08:0b typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 0d GP0d val_alu_func 1b A_OR_B val_b_adr 2d VR12:0d val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 1060 1060 fiu_mem_start f start_physical_tag_rd; Flow J 0x101e ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 101e 0x101e seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1061 1061 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1035 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1035 0x1035 seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 0d GP0d 1062 1062 seq_br_type 7 Unconditional Call; Flow C 0x3525 seq_branch_adr 3525 0x3525 seq_en_micro 0 1063 1063 fiu_tivi_src 3 tar_frame; Flow J cc=False 0x1035 ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1035 0x1035 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 8 1064 1064 fiu_mem_start d start_physical_rd ioc_adrbs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_frame 12 1065 1065 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1035 seq_br_type 1 Branch True seq_branch_adr 1035 0x1035 seq_en_micro 0 1066 1066 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 2a TR09:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 9 1067 1067 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1035 seq_br_type 0 Branch False seq_branch_adr 1035 0x1035 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 32 GP0d 1068 1068 fiu_mem_start f start_physical_tag_rd; Flow J 0x101e ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 101e 0x101e seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1069 1069 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1035 seq_br_type 1 Branch True seq_branch_adr 1035 0x1035 seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1e A_AND_B val_b_adr 2c VR11:0c val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 11 106a 106a seq_br_type 7 Unconditional Call; Flow C 0x3525 seq_branch_adr 3525 0x3525 seq_en_micro 0 106b 106b fiu_tivi_src 3 tar_frame; Flow J cc=False 0x1035 ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1035 0x1035 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 3f VR08:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 8 106c 106c fiu_mem_start d start_physical_rd ioc_adrbs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 3f TR02:1f typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 2c VR12:0c val_frame 12 106d 106d seq_b_timing 1 Latch Condition; Flow J cc=True 0x1035 seq_br_type 1 Branch True seq_branch_adr 1035 0x1035 seq_en_micro 0 106e 106e ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 106f 106f seq_br_type 1 Branch True; Flow J cc=True 0x1035 seq_branch_adr 1035 0x1035 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 32 GP0d val_a_adr 0e GP0e val_alu_func 5 DEC_A_MINUS_B val_b_adr 0d GP0d 1070 1070 fiu_mem_start f start_physical_tag_rd; Flow J 0x101e ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 101e 0x101e seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1071 1071 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED 1072 1072 fiu_len_fill_lit 46 zero-fill 0x6 fiu_mem_start 2 start-rd fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 39 TR03:19 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl b LOAD_MAR_DATA 1073 1073 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x107a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 107a 0x107a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1d A_AND_NOT_B typ_b_adr 33 TR12:13 typ_frame 12 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR04:02 val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 4 1074 1074 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 1075 1075 fiu_mem_start 2 start-rd; Flow C 0x10ab ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 10ab 0x10ab seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_frame 4 1076 1076 fiu_len_fill_lit 4f zero-fill 0xf fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 1077 1077 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 1078 1078 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU 1079 1079 seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU 107a 107a fiu_mem_start f start_physical_tag_rd; Flow J cc=False 0x101c ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 101c 0x101c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 39 VR03:19 val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e val_frame 3 107b 107b fiu_mem_start 15 setup_tag_read seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 0 PASS_A val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 107c 107c fiu_mem_start 15 setup_tag_read; Flow J 0x101c seq_br_type 3 Unconditional Branch seq_branch_adr 101c 0x101c seq_en_micro 0 typ_c_adr 30 GP0f val_c_adr 30 GP0f 107d ; -------------------------------------------------------------------------------------- 107d ; Comes from: 107d ; 340b C True from color 0x0f36 107d ; 342e C from color 0x3411 107d ; -------------------------------------------------------------------------------------- 107d 107d fiu_mem_start f start_physical_tag_rd; Flow C cc=True 0x109e fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 109e 0x109e seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 107e 107e fiu_mem_start 15 setup_tag_read; Flow J 0x107f seq_br_type 2 Push (branch address) seq_branch_adr 1095 0x1095 seq_en_micro 0 107f 107f fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x1083 fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type 3 Unconditional Branch seq_branch_adr 1083 0x1083 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1080 1080 fiu_mem_start f start_physical_tag_rd; Flow C cc=True 0x109e fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 109e 0x109e seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl f LOAD_MAR_RESERVED 1081 1081 fiu_mem_start 15 setup_tag_read; Flow J 0x1082 seq_br_type 2 Push (branch address) seq_branch_adr 1096 0x1096 seq_en_micro 0 1082 1082 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x1083 fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type 3 Unconditional Branch seq_branch_adr 1083 0x1083 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1083 1083 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1084 ; Flow J cc=#0x0 0x1085 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 1085 0x1085 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 31 TR11:11 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 2c VR12:0c val_frame 12 1084 1084 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 1085 1085 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 1086 1086 fiu_mem_start 11 start_tag_query; Flow J 0x108d ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 108d 0x108d seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 5 val_rand a PASS_B_HIGH 1087 1087 fiu_mem_start 11 start_tag_query; Flow J 0x108d ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 108d 0x108d seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 5 val_rand a PASS_B_HIGH 1088 1088 fiu_mem_start 11 start_tag_query; Flow J 0x108d ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 108d 0x108d seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 5 val_rand a PASS_B_HIGH 1089 1089 fiu_mem_start 11 start_tag_query; Flow J 0x108d ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 108d 0x108d seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_frame 5 val_rand a PASS_B_HIGH 108a 108a fiu_mem_start 11 start_tag_query; Flow J 0x108d ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 108d 0x108d seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS val_rand a PASS_B_HIGH 108b 108b ioc_adrbs 1 val ; Flow J 0x3658 seq_br_type 3 Unconditional Branch seq_branch_adr 3658 0x3658 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 108c 108c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 108d 108d fiu_tivi_src 4 fiu_var; Flow C 0x210 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 2c VR12:0c val_frame 12 108e 108e fiu_tivi_src 3 tar_frame; Flow J cc=False 0x1094 ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 1094 0x1094 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 4 108f 108f fiu_tivi_src c mar_0xc; Flow C 0x3526 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3526 0x3526 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 1090 1090 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 8 typ+mem seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0c GP0c val_alu_func 1 A_PLUS_B val_b_adr 0b GP0b 1091 1091 ioc_tvbs 3 fiu+fiu; Flow J cc=False 0x1094 seq_br_type 0 Branch False seq_branch_adr 1094 0x1094 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 2c VR12:0c val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 12 1092 1092 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1094 seq_br_type 1 Branch True seq_branch_adr 1094 0x1094 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 1093 1093 ioc_adrbs 1 val ; Flow J 0x3659 seq_br_type 3 Unconditional Branch seq_branch_adr 3659 0x3659 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 1094 1094 ioc_adrbs 1 val ; Flow J 0x3658 seq_br_type 3 Unconditional Branch seq_branch_adr 3658 0x3658 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 1095 1095 fiu_mem_start 2 start-rd; Flow J 0x1097 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1097 0x1097 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR09:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 31 VR02:11 val_frame 2 1096 1096 fiu_mem_start 2 start-rd; Flow J 0x1097 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1097 0x1097 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR09:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 39 VR02:19 val_frame 2 1097 1097 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 1098 1098 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 1099 1099 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 109a 109a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x109d seq_br_type 1 Branch True seq_branch_adr 109d 0x109d seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 0b GP0b val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 5 109b 109b fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 39 VR12:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 12 109c 109c ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0c GP0c val_b_adr 0c GP0c 109d 109d fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x365c fiu_load_var 1 hold_var fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 365c 0x365c seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 0d GP0d typ_mar_cntl 1 RESTORE_RDR val_b_adr 0d GP0d 109e ; -------------------------------------------------------------------------------------- 109e ; Comes from: 109e ; 107d C True from color 0x1004 109e ; 1080 C True from color 0x1004 109e ; -------------------------------------------------------------------------------------- 109e 109e fiu_mem_start 15 setup_tag_read; Flow J cc=True 0x10ac seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 10ac 0x10ac seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 10 NOT_A typ_c_adr 34 GP0b val_c_adr 34 GP0b 109f 109f ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 10a0 10a0 ioc_fiubs 1 val ; Flow C 0x36c1 seq_br_type 7 Unconditional Call seq_branch_adr 36c1 0x36c1 seq_en_micro 0 val_a_adr 23 VR04:03 val_c_adr 1c VR04:03 val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 10a1 10a1 seq_br_type 0 Branch False; Flow J cc=False 0x10a3 seq_branch_adr 10a3 0x10a3 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 typ_a_adr 24 TR0d:04 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame d val_a_adr 24 VR0d:04 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame d 10a2 10a2 fiu_mem_start f start_physical_tag_rd; Flow C 0x210 ioc_adrbs 2 typ seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2b TR08:0b typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 2d VR12:0d val_frame 12 10a3 10a3 fiu_mem_start 11 start_tag_query; Flow J cc=True 0x10a7 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 10a7 0x10a7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 2d VR12:0d val_frame 12 10a4 10a4 seq_en_micro 0 typ_a_adr 2b TR08:0b typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 10a5 10a5 fiu_mem_start d start_physical_rd; Flow C 0x210 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 10a6 10a6 fiu_mem_start f start_physical_tag_rd; Flow R cc=True ; Flow J cc=False 0x10a8 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 10a8 0x10a8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED 10a7 10a7 fiu_mem_start f start_physical_tag_rd; Flow C 0x352c ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 352c 0x352c seq_en_micro 0 typ_a_adr 2b TR08:0b typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl f LOAD_MAR_RESERVED 10a8 10a8 fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 10 start_physical_tag_wr fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_en_micro 0 seq_random 06 Pop_stack+? typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 12 10a9 10a9 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 0c GP0c val_frame 2 10aa 10aa seq_br_type 7 Unconditional Call; Flow C 0x350a seq_branch_adr 350a 0x350a seq_en_micro 0 10ab ; -------------------------------------------------------------------------------------- 10ab ; Comes from: 10ab ; 1075 C from color 0x1004 10ab ; -------------------------------------------------------------------------------------- 10ab 10ab seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 10ac 10ac fiu_tivi_src 8 type_var; Flow C 0x2ab4 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_mar_cntl 4 RESTORE_MAR val_alu_func 1a PASS_B val_b_adr 0b GP0b 10ad 10ad fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 12 start_lru_query fiu_offs_lit 5c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 10ae 10ae seq_en_micro 0 10af 10af seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 10b0 10b0 fiu_mem_start f start_physical_tag_rd; Flow C 0x352c fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 352c 0x352c seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 10b1 10b1 fiu_mem_start 15 setup_tag_read fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 0b GP0b typ_mar_cntl 4 RESTORE_MAR val_a_adr 0b GP0b val_alu_func 0 PASS_A 10b2 10b2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x10b6 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 10b6 0x10b6 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 10b3 10b3 fiu_mem_start 12 start_lru_query; Flow J cc=True 0x10af fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 10af 0x10af seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 30 TR11:10 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 0c GP0c val_alu_func 18 NOT_A_AND_B val_b_adr 2c VR12:0c val_frame 12 10b4 10b4 seq_br_type 1 Branch True; Flow J cc=True 0x10af seq_branch_adr 10af 0x10af seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 0 PASS_A 10b5 10b5 ioc_tvbs 2 fiu+val; Flow J 0x10af seq_br_type 3 Unconditional Branch seq_branch_adr 10af 0x10af seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 10b6 10b6 fiu_load_var 1 hold_var; Flow J cc=True 0x10b9 fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 10b9 0x10b9 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 30 TR11:10 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 0c GP0c val_alu_func 18 NOT_A_AND_B val_b_adr 2c VR12:0c val_frame 12 10b7 10b7 seq_br_type 1 Branch True; Flow J cc=True 0x10b9 seq_branch_adr 10b9 0x10b9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 0 PASS_A 10b8 10b8 ioc_tvbs 2 fiu+val; Flow J 0x10b9 seq_br_type 3 Unconditional Branch seq_branch_adr 10b9 0x10b9 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 10b9 10b9 fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x2ab4 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 0f GP0f 10ba 10ba fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=True 0x10bc fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 10bc 0x10bc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 06 Pop_stack+? typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 34 GP0b val_c_source 0 FIU_BUS 10bb 10bb fiu_mem_start 3 start-wr; Flow J 0x3b8d ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b8d 0x3b8d seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 10bc 10bc fiu_mem_start 3 start-wr; Flow C 0x211 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 0211 0x0211 seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 0b GP0b 10bd 10bd <halt> ; Flow R 10be ; -------------------------------------------------------------------------------------- 10be ; 0x03bf Declare_Variable Access 10be ; -------------------------------------------------------------------------------------- 10be MACRO_Declare_Variable_Access: 10be 10be dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 10be fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 20 TR10:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 10bf 10bf <halt> ; Flow R 10c0 ; -------------------------------------------------------------------------------------- 10c0 ; 0x03be Declare_Variable Access,Visible 10c0 ; -------------------------------------------------------------------------------------- 10c0 MACRO_Declare_Variable_Access,Visible: 10c0 10c0 dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 10c0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 10c1 10c1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3e TR07:1e typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 10c2 ; -------------------------------------------------------------------------------------- 10c2 ; 0x03bd Declare_Variable Access,Duplicate 10c2 ; -------------------------------------------------------------------------------------- 10c2 MACRO_Declare_Variable_Access,Duplicate: 10c2 10c2 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 10c2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 10c3 10c3 <halt> ; Flow R 10c4 ; -------------------------------------------------------------------------------------- 10c4 ; 0x039f Declare_Variable Heap_Access 10c4 ; -------------------------------------------------------------------------------------- 10c4 MACRO_Declare_Variable_Heap_Access: 10c4 10c4 dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 10c4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 20 TR18:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 10c5 10c5 <halt> ; Flow R 10c6 ; -------------------------------------------------------------------------------------- 10c6 ; 0x039e Declare_Variable Heap_Access,Visible 10c6 ; -------------------------------------------------------------------------------------- 10c6 MACRO_Declare_Variable_Heap_Access,Visible: 10c6 10c6 dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 10c6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 10c7 10c7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 39 TR11:19 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 10c8 ; -------------------------------------------------------------------------------------- 10c8 ; 0x039d Declare_Variable Heap_Access,Duplicate 10c8 ; -------------------------------------------------------------------------------------- 10c8 MACRO_Declare_Variable_Heap_Access,Duplicate: 10c8 10c8 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 10c8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 10c9 ; -------------------------------------------------------------------------------------- 10c9 ; Comes from: 10c9 ; 10d8 C from color MACRO_Declare_Variable_Access,By_Allocation 10c9 ; 1130 C from color MACRO_Declare_Variable_Access,By_Allocation,With_Value 10c9 ; 1214 C from color MACRO_Declare_Variable_Access,By_Allocation,With_Subtype 10c9 ; 1272 C from color MACRO_Declare_Variable_Access,By_Allocation,With_Constraint 10c9 ; -------------------------------------------------------------------------------------- 10c9 10c9 <default> 10ca 10ca fiu_load_tar 1 hold_tar; Flow J 0x10cd fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 10cd 0x10cd typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 10cb ; -------------------------------------------------------------------------------------- 10cb ; Comes from: 10cb ; 10e0 C from color 0x10da 10cb ; 1138 C from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Value 10cb ; 121c C from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Subtype 10cb ; 127a C from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Constraint 10cb ; -------------------------------------------------------------------------------------- 10cb 10cb fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32da fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 2 10cc 10cc fiu_load_tar 1 hold_tar; Flow J 0x10cd fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 10cd 0x10cd typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 10cd 10cd ioc_tvbs 2 fiu+val; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 01 GP01 10ce 10ce fiu_len_fill_lit 43 zero-fill 0x3; Flow R cc=False fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 10cf 0x10cf seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 10cf 10cf seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 10d0 ; -------------------------------------------------------------------------------------- 10d0 ; Comes from: 10d0 ; 10dc C from color 0x10da 10d0 ; 1134 C from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Value 10d0 ; 1218 C from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Subtype 10d0 ; 1276 C from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Constraint 10d0 ; -------------------------------------------------------------------------------------- 10d0 10d0 <default> 10d1 10d1 fiu_load_tar 1 hold_tar; Flow J 0x10d4 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 10d4 0x10d4 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 10d2 ; -------------------------------------------------------------------------------------- 10d2 ; Comes from: 10d2 ; 10e4 C from color 0x10da 10d2 ; 113c C from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Value 10d2 ; 1220 C from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Subtype 10d2 ; 127e C from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Constraint 10d2 ; -------------------------------------------------------------------------------------- 10d2 10d2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32da fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_frame 2 10d3 10d3 fiu_load_tar 1 hold_tar; Flow J 0x10d4 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 10d4 0x10d4 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 10d4 10d4 ioc_tvbs 2 fiu+val; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL 10d5 10d5 fiu_len_fill_lit 43 zero-fill 0x3; Flow R cc=False fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 10d6 0x10d6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 10d6 10d6 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 10d7 10d7 <halt> ; Flow R 10d8 ; -------------------------------------------------------------------------------------- 10d8 ; 0x03bc Declare_Variable Access,By_Allocation 10d8 ; -------------------------------------------------------------------------------------- 10d8 MACRO_Declare_Variable_Access,By_Allocation: 10d8 10d8 dispatch_brk_class 4 ; Flow C 0x10c9 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 10d8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10c9 0x10c9 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR10:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 10d9 10d9 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x10e8 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10e8 0x10e8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE 10da 10da fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1103 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1103 0x1103 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 10db 10db seq_br_type 7 Unconditional Call; Flow C 0x32dc seq_branch_adr 32dc 0x32dc 10dc ; -------------------------------------------------------------------------------------- 10dc ; 0x039c Declare_Variable Heap_Access,By_Allocation 10dc ; -------------------------------------------------------------------------------------- 10dc MACRO_Declare_Variable_Heap_Access,By_Allocation: 10dc 10dc dispatch_brk_class 4 ; Flow C 0x10d0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 10dc fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10d0 0x10d0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR18:00 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 10dd 10dd fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x10e8 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10e8 0x10e8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE 10de 10de fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1103 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1103 0x1103 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 10df 10df seq_br_type 7 Unconditional Call; Flow C 0x32dc seq_branch_adr 32dc 0x32dc 10e0 ; -------------------------------------------------------------------------------------- 10e0 ; 0x03bb Declare_Variable Access,Visible,By_Allocation 10e0 ; -------------------------------------------------------------------------------------- 10e0 MACRO_Declare_Variable_Access,Visible,By_Allocation: 10e0 10e0 dispatch_brk_class 4 ; Flow C 0x10cb dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 10e0 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10cb 0x10cb typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 10e1 10e1 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x10e8 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10e8 0x10e8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE 10e2 10e2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1103 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1103 0x1103 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 10e3 10e3 seq_br_type 7 Unconditional Call; Flow C 0x32dc seq_branch_adr 32dc 0x32dc 10e4 ; -------------------------------------------------------------------------------------- 10e4 ; 0x039b Declare_Variable Heap_Access,Visible,By_Allocation 10e4 ; -------------------------------------------------------------------------------------- 10e4 MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation: 10e4 10e4 dispatch_brk_class 4 ; Flow C 0x10d2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 10e4 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10d2 0x10d2 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 10e5 10e5 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x10e8 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 10e8 0x10e8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE 10e6 10e6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1103 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1103 0x1103 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 10e7 10e7 seq_br_type 7 Unconditional Call; Flow C 0x32dc seq_branch_adr 32dc 0x32dc 10e8 ; -------------------------------------------------------------------------------------- 10e8 ; Comes from: 10e8 ; 10d9 C #0x0 from color MACRO_Declare_Variable_Access,By_Allocation 10e8 ; -------------------------------------------------------------------------------------- 10e8 10e8 seq_br_type 3 Unconditional Branch; Flow J 0x10f8 seq_branch_adr 10f8 0x10f8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10e9 10e9 seq_br_type 3 Unconditional Branch; Flow J 0x10f8 seq_branch_adr 10f8 0x10f8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10ea 10ea seq_br_type 3 Unconditional Branch; Flow J 0x10f8 seq_branch_adr 10f8 0x10f8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10eb 10eb seq_br_type 3 Unconditional Branch; Flow J 0x10f8 seq_branch_adr 10f8 0x10f8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10ec 10ec seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10ed 10ed seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10ee 10ee seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10ef 10ef seq_br_type 3 Unconditional Branch; Flow J 0x10f8 seq_branch_adr 10f8 0x10f8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10f0 10f0 seq_br_type 3 Unconditional Branch; Flow J 0x10f8 seq_branch_adr 10f8 0x10f8 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10f1 10f1 seq_br_type 3 Unconditional Branch; Flow J 0x10fc seq_branch_adr 10fc 0x10fc val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10f2 10f2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10f3 10f3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10f4 10f4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 10f5 10f5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x10f8 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 10f8 0x10f8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR05:00 typ_b_adr 01 GP01 typ_frame 5 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10f6 10f6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x10f8 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 10f8 0x10f8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 2f TR11:0f typ_b_adr 01 GP01 typ_frame 11 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10f7 10f7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 10f8 0x10f8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 2e TR11:0e typ_b_adr 01 GP01 typ_frame 11 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 10f8 10f8 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 10f9 10f9 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 10fa 0x10fa seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 10fa 10fa seq_br_type 7 Unconditional Call; Flow C 0x2a5e seq_branch_adr 2a5e 0x2a5e typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 10fb 10fb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 10fc 10fc ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32d9 seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 10fd 10fd fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 10fe 10fe seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 10ff 10ff typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 1100 1100 ioc_fiubs 2 typ typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 37 GP08 val_c_source 0 FIU_BUS 1101 1101 seq_br_type 7 Unconditional Call; Flow C 0x29e5 seq_branch_adr 29e5 0x29e5 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1102 1102 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1103 1103 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=#0x0 0x1105 fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 1105 0x1105 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1104 1104 seq_br_type 7 Unconditional Call; Flow C 0x32d2 seq_branch_adr 32d2 0x32d2 1105 ; -------------------------------------------------------------------------------------- 1105 ; Comes from: 1105 ; 1103 C #0x0 from color 0x10da 1105 ; -------------------------------------------------------------------------------------- 1105 1105 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1106 1106 ioc_fiubs 0 fiu ; Flow R cc=False ; Flow J cc=True 0x110d seq_br_type 9 Return False seq_branch_adr 110d 0x110d seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 1107 1107 ioc_fiubs 2 typ ; Flow J 0x1121 seq_br_type 3 Unconditional Branch seq_branch_adr 1121 0x1121 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 27 TR09:07 typ_frame 9 val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 1108 1108 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1109 1109 <default> 110a 110a fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 110b 110b seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 110c 110c seq_br_type 3 Unconditional Branch; Flow J 0x1122 seq_branch_adr 1122 0x1122 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 110d 110d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1112 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1112 0x1112 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 110e 110e fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_mux_sel 2 ALU 110f 110f val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 1110 1110 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1111 1111 seq_br_type 4 Call False; Flow C cc=False 0x32dc seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_frame 6 1112 1112 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1113 1113 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_random 02 ? typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1114 1114 fiu_fill_mode_src 0 ; Flow J cc=False 0x111e fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 111e 0x111e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR 1115 1115 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1116 1116 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 val_a_adr 04 GP04 val_alu_func 0 PASS_A 1117 1117 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 1118 0x1118 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 10 TOP 1118 1118 seq_b_timing 1 Latch Condition; Flow J cc=True 0x111b seq_br_type 1 Branch True seq_branch_adr 111b 0x111b 1119 1119 seq_br_type 7 Unconditional Call; Flow C 0x2a5e seq_branch_adr 2a5e 0x2a5e typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 111a 111a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 111b 111b fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x11bc fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 11bc 0x11bc typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 111c 111c ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 111d 111d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 111e 111e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 111f 111f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1120 1120 fiu_load_var 1 hold_var; Flow J 0x1116 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1116 0x1116 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1121 1121 typ_a_adr 2f TR11:0f typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 1122 1122 ioc_fiubs 0 fiu ; Flow J cc=False 0x1125 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1125 0x1125 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1123 1123 ioc_fiubs 2 typ ; Flow C 0x2286 seq_br_type 7 Unconditional Call seq_branch_adr 2286 0x2286 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1124 1124 ioc_fiubs 2 typ ; Flow C cc=True 0x112e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 112e 0x112e seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 2 1125 1125 seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 1126 0x1126 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1126 1126 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1127 1127 ioc_fiubs 2 typ ; Flow C 0x2258 seq_br_type 7 Unconditional Call seq_branch_adr 2258 0x2258 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1128 1128 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1129 0x1129 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 2f TOP val_c_source 0 FIU_BUS 1129 1129 ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 112a 112a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2278 seq_br_type 5 Call True seq_branch_adr 2278 0x2278 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 04 GP04 112b 112b fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 112c 0x112c seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_mar_cntl e LOAD_MAR_CONTROL 112c 112c seq_br_type 7 Unconditional Call; Flow C 0x2a5e seq_branch_adr 2a5e 0x2a5e typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 112d 112d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 112e ; -------------------------------------------------------------------------------------- 112e ; Comes from: 112e ; 1124 C True from color 0x1107 112e ; -------------------------------------------------------------------------------------- 112e 112e seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 112f 112f seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1130 ; -------------------------------------------------------------------------------------- 1130 ; 0x03b6 Declare_Variable Access,By_Allocation,With_Value 1130 ; -------------------------------------------------------------------------------------- 1130 MACRO_Declare_Variable_Access,By_Allocation,With_Value: 1130 1130 dispatch_brk_class 4 ; Flow C 0x10c9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1130 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10c9 0x10c9 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR10:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1131 1131 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x113f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 113f 0x113f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2c) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1132 1132 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1133 1133 <halt> ; Flow R 1134 ; -------------------------------------------------------------------------------------- 1134 ; 0x0396 Declare_Variable Heap_Access,By_Allocation,With_Value 1134 ; -------------------------------------------------------------------------------------- 1134 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Value: 1134 1134 dispatch_brk_class 4 ; Flow C 0x10d0 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1134 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10d0 0x10d0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR18:00 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1135 1135 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x113f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 113f 0x113f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2c) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1136 1136 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1137 1137 <halt> ; Flow R 1138 ; -------------------------------------------------------------------------------------- 1138 ; 0x03b5 Declare_Variable Access,Visible,By_Allocation,With_Value 1138 ; -------------------------------------------------------------------------------------- 1138 MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Value: 1138 1138 dispatch_brk_class 4 ; Flow C 0x10cb dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1138 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10cb 0x10cb typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 1139 1139 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x113f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 113f 0x113f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2c) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 113a 113a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 113b 113b <halt> ; Flow R 113c ; -------------------------------------------------------------------------------------- 113c ; 0x0395 Declare_Variable Heap_Access,Visible,By_Allocation,With_Value 113c ; -------------------------------------------------------------------------------------- 113c MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Value: 113c 113c dispatch_brk_class 4 ; Flow C 0x10d2 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 113c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10d2 0x10d2 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 113d 113d fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x113f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 113f 0x113f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2c) Variant_Record_Var seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 2 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 113e 113e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 113f ; -------------------------------------------------------------------------------------- 113f ; Comes from: 113f ; 1131 C #0x0 from color MACRO_Declare_Variable_Access,By_Allocation,With_Value 113f ; 1135 C #0x0 from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Value 113f ; 1139 C #0x0 from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Value 113f ; 113d C #0x0 from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Value 113f ; -------------------------------------------------------------------------------------- 113f 113f ioc_fiubs 1 val ; Flow J 0x1153 seq_br_type 3 Unconditional Branch seq_branch_adr 1153 0x1153 typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 1140 1140 ioc_fiubs 1 val ; Flow J 0x1161 seq_br_type 3 Unconditional Branch seq_branch_adr 1161 0x1161 typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 1141 1141 seq_br_type 3 Unconditional Branch; Flow J 0x116f seq_branch_adr 116f 0x116f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1142 1142 seq_br_type 7 Unconditional Call; Flow C 0x32db seq_branch_adr 32db 0x32db 1143 1143 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1144 1144 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1145 1145 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1146 1146 seq_br_type 3 Unconditional Branch; Flow J 0x1179 seq_branch_adr 1179 0x1179 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL 1147 1147 seq_br_type 3 Unconditional Branch; Flow J 0x118a seq_branch_adr 118a 0x118a seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_lit 1 typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL 1148 1148 ioc_fiubs 0 fiu ; Flow J 0x1191 seq_br_type 3 Unconditional Branch seq_branch_adr 1191 0x1191 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 1149 1149 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 114a 114a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 114b 114b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 114c 114c seq_br_type 3 Unconditional Branch; Flow J 0x11a1 seq_branch_adr 11a1 0x11a1 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand a PASS_B_HIGH 114d 114d ioc_fiubs 1 val ; Flow J 0x11e4 seq_br_type 3 Unconditional Branch seq_branch_adr 11e4 0x11e4 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 14 typ_rand a PASS_B_HIGH val_a_adr 35 VR11:15 val_alu_func 1a PASS_B val_b_adr 36 VR11:16 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 11 114e 114e fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 114f 114f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 1c typ_rand a PASS_B_HIGH 1150 1150 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1151 1151 seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1152 1152 seq_br_type 3 Unconditional Branch; Flow J 0x11e4 seq_branch_adr 11e4 0x11e4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 1153 1153 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x115d seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 115d 0x115d seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1154 1154 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1155 1155 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_random 02 ? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 02 GP02 1156 1156 fiu_fill_mode_src 0 ; Flow J cc=False 0x115a fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 115a 0x115a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 1157 1157 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1158 1158 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 1159 1159 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 115a 115a fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_source 0 FIU_BUS 115b 115b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 115c 115c fiu_mem_start 4 continue; Flow J 0x1158 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1158 0x1158 typ_b_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 115d 115d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 115e 115e <default> 115f 115f ioc_tvbs c mem+mem+csa+dummy; Flow C 0x329e seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1160 1160 seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 1161 1161 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 1162 1162 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1166 seq_br_type 1 Branch True seq_branch_adr 1166 0x1166 typ_c_adr 3c GP03 val_c_adr 3c GP03 1163 1163 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1168 seq_br_type 1 Branch True seq_branch_adr 1168 0x1168 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 1164 1164 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1165 1165 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1156 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1156 0x1156 seq_random 02 ? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 02 GP02 1166 1166 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1168 seq_br_type 1 Branch True seq_branch_adr 1168 0x1168 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 03 GP03 1167 1167 seq_br_type 1 Branch True; Flow J cc=True 0x1164 seq_branch_adr 1164 0x1164 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 1168 1168 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1169 1169 seq_b_timing 1 Latch Condition; Flow J cc=True 0x116c seq_br_type 1 Branch True seq_branch_adr 116c 0x116c 116a 116a ioc_tvbs c mem+mem+csa+dummy; Flow C 0x329e seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 116b 116b seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 116c 116c ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a8 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 116d 116d seq_br_type 5 Call True; Flow C 0x329e seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 116e 116e seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 116f 116f seq_b_timing 1 Latch Condition; Flow J cc=True 0x1172 seq_br_type 1 Branch True seq_branch_adr 1172 0x1172 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1170 1170 seq_br_type 7 Unconditional Call; Flow C 0x24ba seq_branch_adr 24ba 0x24ba seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1171 1171 seq_b_timing 1 Latch Condition; Flow J cc=False 0x1174 seq_br_type 0 Branch False seq_branch_adr 1174 0x1174 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1172 1172 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1173 1173 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1156 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1156 0x1156 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 02 GP02 1174 1174 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1175 1175 <default> 1176 1176 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a5 seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c 1177 1177 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32a2 seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame a 1178 1178 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1179 1179 seq_b_timing 1 Latch Condition; Flow J cc=True 0x117c seq_br_type 1 Branch True seq_branch_adr 117c 0x117c typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 117a 117a seq_br_type 7 Unconditional Call; Flow C 0x24c4 seq_branch_adr 24c4 0x24c4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 117b 117b seq_b_timing 1 Latch Condition; Flow J cc=False 0x1174 seq_br_type 0 Branch False seq_branch_adr 1174 0x1174 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 117c 117c fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 117d 117d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_b_adr 02 GP02 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 117e 117e fiu_fill_mode_src 0 ; Flow J cc=False 0x1182 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1182 0x1182 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 06 GP06 117f 117f fiu_fill_mode_src 0 ; Flow C cc=True 0x1186 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1186 0x1186 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1180 1180 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 1181 1181 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1182 1182 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1183 1183 fiu_fill_mode_src 0 ; Flow C cc=True 0x1186 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1186 0x1186 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1184 1184 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR 1185 1185 ioc_load_wdr 0 ; Flow J 0x1181 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1181 0x1181 val_b_adr 04 GP04 1186 ; -------------------------------------------------------------------------------------- 1186 ; Comes from: 1186 ; 117f C True from color 0x113f 1186 ; 1183 C True from color 0x113f 1186 ; -------------------------------------------------------------------------------------- 1186 1186 fiu_tivi_src c mar_0xc; Flow C cc=False 0x32e1 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32e1 0x32e1 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1187 1187 fiu_fill_mode_src 0 ; Flow J cc=False 0x1189 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1189 0x1189 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 1f TOP - 1 1188 1188 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1189 1189 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 118a 118a ioc_fiubs 0 fiu ; Flow C cc=False 0x1190 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1190 0x1190 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 118b 118b fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 118c 118c ioc_fiubs 1 val ; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 2e TR11:0e typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 11 val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 118d 118d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 118e 118e seq_br_type 7 Unconditional Call; Flow C 0x1f1e seq_branch_adr 1f1e 0x1f1e typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 118f 118f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1190 ; -------------------------------------------------------------------------------------- 1190 ; Comes from: 1190 ; 118a C False from color 0x1147 1190 ; -------------------------------------------------------------------------------------- 1190 1190 fiu_mem_start 2 start-rd; Flow J 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1191 1191 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x119a fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 119a 0x119a typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1192 1192 ioc_fiubs 0 fiu ; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1193 1193 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x119b seq_br_type f Unconditional Case Call seq_branch_adr 119b 0x119b seq_en_micro 0 1194 1194 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1195 1195 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 32 TR02:12 typ_alu_func 1 A_PLUS_B typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 1c DEC_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1196 1196 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1197 1197 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 1198 1198 ioc_load_wdr 0 ; Flow C 0x1f1e ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1199 1199 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 119a ; -------------------------------------------------------------------------------------- 119a ; Comes from: 119a ; 1191 C False from color 0x1148 119a ; -------------------------------------------------------------------------------------- 119a 119a fiu_mem_start 2 start-rd; Flow J 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 119b ; -------------------------------------------------------------------------------------- 119b ; Comes from: 119b ; 1193 C #0x0 from color 0x1148 119b ; -------------------------------------------------------------------------------------- 119b 119b seq_br_type 3 Unconditional Branch; Flow J 0x119f seq_branch_adr 119f 0x119f typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 119c 119c fiu_load_oreg 1 hold_oreg; Flow C 0x2515 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2515 0x2515 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 119d 119d seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 119e 0x119e 119e 119e seq_br_type 7 Unconditional Call; Flow C 0x32a4 seq_branch_adr 32a4 0x32a4 119f 119f ioc_fiubs 2 typ ; Flow C 0x2488 seq_br_type 7 Unconditional Call seq_branch_adr 2488 0x2488 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 01 GP01 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 11a0 11a0 seq_br_type a Unconditional Return; Flow R val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 11a1 11a1 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x11e3 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 11e3 0x11e3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 11a2 11a2 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32d9 fiu_mem_start 2 start-rd fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_mux_sel 2 ALU 11a3 11a3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x11ca seq_br_type f Unconditional Case Call seq_branch_adr 11ca 0x11ca seq_en_micro 0 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 11a4 11a4 fiu_load_var 1 hold_var; Flow J cc=True 0x11aa fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 11aa 0x11aa seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 05 GP05 typ_b_adr 01 GP01 val_a_adr 05 GP05 val_alu_func 1c DEC_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU 11a5 11a5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 11a6 11a6 seq_br_type 1 Branch True; Flow J cc=True 0x11c6 seq_branch_adr 11c6 0x11c6 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 11a7 11a7 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 11a8 11a8 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x11c6 seq_br_type 1 Branch True seq_branch_adr 11c6 0x11c6 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 11a9 11a9 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 11aa 11aa fiu_load_var 1 hold_var; Flow J cc=True 0x11ae fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 11ae 0x11ae seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 11ab 11ab ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 11ac 11ac seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e 11ad 11ad seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 11ae 11ae val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 11af 11af fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 11b0 11b0 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 05 GP05 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_frame 6 11b1 11b1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3a GP05 11b2 11b2 fiu_fill_mode_src 0 ; Flow J cc=True 0x11b6 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 11b6 0x11b6 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 11b3 11b3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 11b4 11b4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 11b5 11b5 fiu_load_var 1 hold_var; Flow J 0x11b7 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 11b7 0x11b7 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 11b6 11b6 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 11b7 11b7 ioc_load_wdr 0 ; Flow J cc=True 0x11c1 ioc_tvbs 3 fiu+fiu seq_br_type 1 Branch True seq_branch_adr 11c1 0x11c1 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 11b8 11b8 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x11bc fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 11bc 0x11bc typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 11b9 11b9 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 11ba 11ba seq_br_type 1 Branch True; Flow J cc=True 0x11c3 seq_branch_adr 11c3 0x11c3 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_frame 6 11bb 11bb seq_br_type 7 Unconditional Call; Flow C 0x32dc seq_branch_adr 32dc 0x32dc 11bc ; -------------------------------------------------------------------------------------- 11bc ; Comes from: 11bc ; 111b C from color 0x1106 11bc ; -------------------------------------------------------------------------------------- 11bc 11bc fiu_fill_mode_src 0 ; Flow J cc=True 0x11c0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 11c0 0x11c0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 39 GP06 val_c_source 0 FIU_BUS 11bd 11bd fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 11be 11be fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 30 GP0f typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 11bf 11bf fiu_load_var 1 hold_var; Flow R fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 11c0 11c0 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 11c1 11c1 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 11c2 11c2 ioc_fiubs 1 val ; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 02 GP02 11c3 11c3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 11c4 11c4 ioc_fiubs 1 val ; Flow C 0x22bc seq_br_type 7 Unconditional Call seq_branch_adr 22bc 0x22bc typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 11c5 11c5 seq_b_timing 1 Latch Condition; Flow C cc=False 0x32a2 seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 11c6 11c6 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 11c7 11c7 fiu_load_tar 1 hold_tar; Flow J cc=True 0x11c9 fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 11c9 0x11c9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 11c8 11c8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1f1e fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 11c9 11c9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 11ca ; -------------------------------------------------------------------------------------- 11ca ; Comes from: 11ca ; 11a3 C #0x0 from color 0x114c 11ca ; -------------------------------------------------------------------------------------- 11ca 11ca fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x11cc fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 11cc 0x11cc typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 11cb 11cb fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x11d2 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 11d2 0x11d2 typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 11cc 11cc fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 11cd 11cd fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 11ce 11ce fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 11cf 0x11cf seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_source 0 FIU_BUS 11cf 11cf fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 11d0 11d0 typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 11d1 11d1 ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 11d2 11d2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 11d3 11d3 fiu_fill_mode_src 0 ; Flow C 0x11d8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 11d8 0x11d8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 11d4 11d4 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 0f GP0f val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_rand c START_MULTIPLY 11d5 11d5 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 11d6 0x11d6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 11d6 11d6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 11d7 11d7 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 11d8 ; -------------------------------------------------------------------------------------- 11d8 ; Comes from: 11d8 ; 11d3 C from color 0x11cb 11d8 ; -------------------------------------------------------------------------------------- 11d8 11d8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x11e0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 11e0 0x11e0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 11d9 11d9 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 11da 11da fiu_len_fill_lit 1f sign-fill 0x1f; Flow R cc=True fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 11db 0x11db seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 11db 11db fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 11dc 11dc fiu_mem_start a start_continue_if_false; Flow J cc=False 0x11de seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 11de 0x11de seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 11dd 11dd fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 11de 11de fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 11df 11df fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 11e0 11e0 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 11e1 11e1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 11e2 11e2 fiu_len_fill_lit 1f sign-fill 0x1f; Flow R cc=True ; Flow J cc=False 0x11db fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 11db 0x11db seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 11e3 ; -------------------------------------------------------------------------------------- 11e3 ; Comes from: 11e3 ; 11a1 C False from color 0x114c 11e3 ; 11e4 C False from color 0x114d 11e3 ; -------------------------------------------------------------------------------------- 11e3 11e3 fiu_mem_start 2 start-rd; Flow J 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 11e4 11e4 ioc_fiubs 2 typ ; Flow C cc=False 0x11e3 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 11e3 0x11e3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 11e5 11e5 ioc_fiubs 2 typ ; Flow C cc=True 0x32d9 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 11e6 11e6 seq_b_timing 1 Latch Condition; Flow J cc=True 0x11f7 seq_br_type 1 Branch True seq_branch_adr 11f7 0x11f7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 11e7 11e7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x11c4 seq_br_type 1 Branch True seq_branch_adr 11c4 0x11c4 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 11e8 11e8 seq_br_type 7 Unconditional Call; Flow C 0x22c6 seq_branch_adr 22c6 0x22c6 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 11e9 11e9 seq_b_timing 1 Latch Condition; Flow J cc=True 0x11eb seq_br_type 1 Branch True seq_branch_adr 11eb 0x11eb val_c_adr 3c GP03 val_c_mux_sel 2 ALU 11ea 11ea seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 11eb 11eb ioc_fiubs 2 typ ; Flow C 0x2286 seq_br_type 7 Unconditional Call seq_branch_adr 2286 0x2286 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 11ec 11ec seq_br_type 1 Branch True; Flow J cc=True 0x11c6 seq_branch_adr 11c6 0x11c6 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 11ed 11ed seq_br_type 3 Unconditional Branch; Flow J 0x11c6 seq_branch_adr 11c6 0x11c6 typ_alu_func 13 ONES typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 11ee 11ee ioc_fiubs 1 val ; Flow C 0x229d seq_br_type 7 Unconditional Call seq_branch_adr 229d 0x229d typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 11ef 11ef seq_b_timing 1 Latch Condition; Flow C cc=False 0x32a2 seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 11f0 11f0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1206 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1206 0x1206 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 11f1 11f1 ioc_fiubs 2 typ ; Flow C cc=True 0x1211 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1211 0x1211 typ_a_adr 17 LOOP_COUNTER val_c_adr 30 GP0f val_c_source 0 FIU_BUS 11f2 11f2 seq_br_type 4 Call False; Flow C cc=False 0x32d2 seq_branch_adr 32d2 0x32d2 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 11f3 11f3 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 11f4 11f4 ioc_fiubs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 07 GP07 val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 11f5 11f5 seq_br_type 7 Unconditional Call; Flow C 0x1f1e seq_branch_adr 1f1e 0x1f1e typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 11f6 11f6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 11f7 11f7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x11ee seq_br_type 1 Branch True seq_branch_adr 11ee 0x11ee typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 11f8 11f8 seq_br_type 7 Unconditional Call; Flow C 0x2292 seq_branch_adr 2292 0x2292 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 11f9 11f9 ioc_fiubs 2 typ ; Flow C cc=False 0x32a2 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 11fa 11fa fiu_mem_start 2 start-rd; Flow C cc=True 0x1211 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1211 0x1211 seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 11fb 11fb <default> 11fc 11fc fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 11fd 11fd seq_br_type 4 Call False; Flow C cc=False 0x32d2 seq_branch_adr 32d2 0x32d2 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 11fe 11fe fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 11ff 11ff ioc_fiubs 2 typ ; Flow C 0x2258 seq_br_type 7 Unconditional Call seq_branch_adr 2258 0x2258 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1200 1200 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1203 fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1203 0x1203 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1201 1201 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1f1e fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1202 1202 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1203 1203 ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1204 1204 seq_br_type 7 Unconditional Call; Flow C 0x2278 seq_branch_adr 2278 0x2278 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1205 1205 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1206 ; -------------------------------------------------------------------------------------- 1206 ; Comes from: 1206 ; 11f0 C from color 0x114d 1206 ; -------------------------------------------------------------------------------------- 1206 1206 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x120a seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 120a 0x120a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1207 1207 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 1208 1208 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1209 1209 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x120c fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 120c 0x120c seq_en_micro 0 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 120a 120a fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 120b 120b fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 120c 120c seq_br_type 0 Branch False; Flow J cc=False 0x120e seq_branch_adr 120e 0x120e seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1b A_OR_B val_b_adr 0e GP0e val_rand c START_MULTIPLY 120d 120d seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 120e 120e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 120f 120f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1210 1210 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1211 ; -------------------------------------------------------------------------------------- 1211 ; Comes from: 1211 ; 11f1 C True from color 0x114d 1211 ; 11fa C True from color 0x114d 1211 ; -------------------------------------------------------------------------------------- 1211 1211 seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 1212 1212 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1213 1213 <halt> ; Flow R 1214 ; -------------------------------------------------------------------------------------- 1214 ; 0x03b8 Declare_Variable Access,By_Allocation,With_Subtype 1214 ; -------------------------------------------------------------------------------------- 1214 MACRO_Declare_Variable_Access,By_Allocation,With_Subtype: 1214 1214 dispatch_brk_class 4 ; Flow C 0x10c9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1214 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10c9 0x10c9 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR10:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1215 1215 fiu_mem_start 2 start-rd; Flow C cc=#0x0 0x1223 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 1223 0x1223 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1216 1216 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 1217 1217 <halt> ; Flow R 1218 ; -------------------------------------------------------------------------------------- 1218 ; 0x0398 Declare_Variable Heap_Access,By_Allocation,With_Subtype 1218 ; -------------------------------------------------------------------------------------- 1218 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Subtype: 1218 1218 dispatch_brk_class 4 ; Flow C 0x10d0 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1218 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10d0 0x10d0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR18:00 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1219 1219 fiu_mem_start 2 start-rd; Flow C cc=#0x0 0x1223 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 1223 0x1223 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 121a 121a seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 121b 121b <halt> ; Flow R 121c ; -------------------------------------------------------------------------------------- 121c ; 0x03b7 Declare_Variable Access,Visible,By_Allocation,With_Subtype 121c ; -------------------------------------------------------------------------------------- 121c MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Subtype: 121c 121c dispatch_brk_class 4 ; Flow C 0x10cb dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 121c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10cb 0x10cb typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 121d 121d fiu_mem_start 2 start-rd; Flow C cc=#0x0 0x1223 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 1223 0x1223 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 121e 121e seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 121f 121f <halt> ; Flow R 1220 ; -------------------------------------------------------------------------------------- 1220 ; 0x0397 Declare_Variable Heap_Access,Visible,By_Allocation,With_Subtype 1220 ; -------------------------------------------------------------------------------------- 1220 MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Subtype: 1220 1220 dispatch_brk_class 4 ; Flow C 0x10d2 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1220 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10d2 0x10d2 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 1221 1221 fiu_mem_start 2 start-rd; Flow C cc=#0x0 0x1223 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 1223 0x1223 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1222 1222 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 1223 ; -------------------------------------------------------------------------------------- 1223 ; Comes from: 1223 ; 1215 C #0x0 from color MACRO_Declare_Variable_Access,By_Allocation,With_Subtype 1223 ; 1219 C #0x0 from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Subtype 1223 ; 121d C #0x0 from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Subtype 1223 ; 1221 C #0x0 from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Subtype 1223 ; -------------------------------------------------------------------------------------- 1223 1223 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_random 05 ? 1224 1224 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_random 05 ? 1225 1225 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_random 05 ? 1226 1226 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_random 05 ? 1227 1227 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1228 1228 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1229 1229 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 122a 122a seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_random 05 ? 122b 122b seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_random 05 ? 122c 122c seq_br_type 3 Unconditional Branch; Flow J 0x1237 seq_branch_adr 1237 0x1237 typ_a_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 122d 122d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 122e 122e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 122f 122f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1230 1230 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x123e fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 9 Return False seq_branch_adr 123e 0x123e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_lit 0 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 31 VR02:11 val_frame 2 1231 1231 fiu_load_var 1 hold_var; Flow R cc=False ; Flow J cc=True 0x125c fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 9 Return False seq_branch_adr 125c 0x125c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 14 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 35 VR11:15 val_alu_func 1a PASS_B val_b_adr 36 VR11:16 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 11 1232 1232 fiu_mem_start 9 start_continue_if_true; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 1233 0x1233 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR 1233 1233 typ_b_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand a PASS_B_HIGH 1234 1234 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1235 1235 seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1236 1236 seq_br_type 3 Unconditional Branch; Flow J 0x125c seq_branch_adr 125c 0x125c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 5 1237 1237 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32d9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1238 1238 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 1239 1239 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 123a 123a ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32d9 seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 123b 123b fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 123c 123c fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_source 0 FIU_BUS 123d 123d seq_br_type 3 Unconditional Branch; Flow J 0x10ff seq_branch_adr 10ff 0x10ff seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 123e 123e fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 123f 123f fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1240 1240 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1241 1241 fiu_mem_start 4 continue typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1242 1242 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1243 1243 fiu_load_var 1 hold_var; Flow J cc=True 0x1249 fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1249 0x1249 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1244 1244 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32a2 seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1245 1245 ioc_fiubs 0 fiu ; Flow C cc=False 0x32dc ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_frame 6 1246 1246 seq_br_type 2 Push (branch address); Flow J 0x1247 seq_branch_adr 32cc 0x32cc typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1247 1247 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x124e fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 124e 0x124e seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 06 GP06 val_a_adr 03 GP03 1248 1248 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 1249 1249 fiu_mem_start 2 start-rd; Flow C cc=False 0x32dc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_frame 6 124a 124a seq_br_type 2 Push (branch address); Flow J 0x124b seq_branch_adr 32cc 0x32cc val_c_adr 3b GP04 val_c_mux_sel 2 ALU 124b 124b fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 124c 124c seq_br_type 4 Call False; Flow C cc=False 0x32dc seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_frame 6 124d 124d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x124f fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 124f 0x124f seq_en_micro 0 val_a_adr 03 GP03 124e 124e fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=False ; Flow J cc=True 0x1250 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 9 Return False seq_branch_adr 1250 0x1250 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 124f 124f seq_br_type 3 Unconditional Branch; Flow J 0x1250 seq_branch_adr 1250 0x1250 val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 1250 1250 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x35c6 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 0 PASS_A 1251 1251 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_random 02 ? typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1252 1252 fiu_fill_mode_src 0 ; Flow J cc=False 0x1259 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1259 0x1259 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 1253 1253 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1254 1254 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 val_a_adr 04 GP04 val_alu_func 0 PASS_A 1255 1255 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 1256 0x1256 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 10 TOP 1256 1256 seq_b_timing 1 Latch Condition; Flow J cc=True 0x111b seq_br_type 1 Branch True seq_branch_adr 111b 0x111b 1257 1257 seq_br_type 7 Unconditional Call; Flow C 0x2a5e seq_branch_adr 2a5e 0x2a5e typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1258 1258 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1259 1259 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 125a 125a fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 125b 125b fiu_load_var 1 hold_var; Flow J 0x1254 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1254 0x1254 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 125c 125c fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 125d 125d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 125e 125e ioc_fiubs 0 fiu typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_source 0 FIU_BUS 125f 125f fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1260 1260 seq_br_type 7 Unconditional Call; Flow C 0x2292 seq_branch_adr 2292 0x2292 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1261 1261 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1269 seq_br_type 1 Branch True seq_branch_adr 1269 0x1269 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A val_a_adr 05 GP05 val_alu_func 0 PASS_A 1262 1262 seq_br_type 4 Call False; Flow C cc=False 0x32d2 seq_branch_adr 32d2 0x32d2 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1263 1263 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 1264 1264 seq_random 02 ? val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1265 1265 seq_br_type 7 Unconditional Call; Flow C 0x2258 seq_branch_adr 2258 0x2258 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1266 1266 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1267 0x1267 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 1267 1267 seq_br_type 7 Unconditional Call; Flow C 0x2a5e seq_branch_adr 2a5e 0x2a5e typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1268 1268 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1269 1269 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 126a 126a val_a_adr 04 GP04 val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 126b 126b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 5 126c 126c fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 126d 126d seq_random 02 ? val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 126e 126e seq_br_type 7 Unconditional Call; Flow C 0x2258 seq_branch_adr 2258 0x2258 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 126f 126f seq_br_type 7 Unconditional Call; Flow C 0x2278 seq_branch_adr 2278 0x2278 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1270 1270 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 1271 1271 <halt> ; Flow R 1272 ; -------------------------------------------------------------------------------------- 1272 ; 0x03ba Declare_Variable Access,By_Allocation,With_Constraint 1272 ; -------------------------------------------------------------------------------------- 1272 MACRO_Declare_Variable_Access,By_Allocation,With_Constraint: 1272 1272 dispatch_brk_class 4 ; Flow C 0x10c9 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1272 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10c9 0x10c9 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR10:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1273 1273 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x1281 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 1281 0x1281 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1274 1274 seq_br_type 7 Unconditional Call; Flow C 0x32dc seq_branch_adr 32dc 0x32dc 1275 1275 <halt> ; Flow R 1276 ; -------------------------------------------------------------------------------------- 1276 ; 0x039a Declare_Variable Heap_Access,By_Allocation,With_Constraint 1276 ; -------------------------------------------------------------------------------------- 1276 MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Constraint: 1276 1276 dispatch_brk_class 4 ; Flow C 0x10d0 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1276 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10d0 0x10d0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR18:00 typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1277 1277 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x1281 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 1281 0x1281 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1278 1278 seq_br_type 7 Unconditional Call; Flow C 0x32dc seq_branch_adr 32dc 0x32dc 1279 1279 <halt> ; Flow R 127a ; -------------------------------------------------------------------------------------- 127a ; 0x03b9 Declare_Variable Access,Visible,By_Allocation,With_Constraint 127a ; -------------------------------------------------------------------------------------- 127a MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Constraint: 127a 127a dispatch_brk_class 4 ; Flow C 0x10cb dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 127a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10cb 0x10cb typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 127b 127b fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x1281 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 1281 0x1281 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 127c 127c seq_br_type 7 Unconditional Call; Flow C 0x32dc seq_branch_adr 32dc 0x32dc 127d 127d <halt> ; Flow R 127e ; -------------------------------------------------------------------------------------- 127e ; 0x0399 Declare_Variable Heap_Access,Visible,By_Allocation,With_Constraint 127e ; -------------------------------------------------------------------------------------- 127e MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Constraint: 127e 127e dispatch_brk_class 4 ; Flow C 0x10d2 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 127e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 10d2 0x10d2 typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 31 VR02:11 val_frame 2 127f 127f fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x1281 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 1281 0x1281 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1280 1280 seq_br_type 7 Unconditional Call; Flow C 0x32dc seq_branch_adr 32dc 0x32dc 1281 ; -------------------------------------------------------------------------------------- 1281 ; Comes from: 1281 ; 1273 C #0x0 from color MACRO_Declare_Variable_Access,By_Allocation,With_Constraint 1281 ; 1277 C #0x0 from color MACRO_Declare_Variable_Heap_Access,By_Allocation,With_Constraint 1281 ; 127b C #0x0 from color MACRO_Declare_Variable_Access,Visible,By_Allocation,With_Constraint 1281 ; 127f C #0x0 from color MACRO_Declare_Variable_Heap_Access,Visible,By_Allocation,With_Constraint 1281 ; -------------------------------------------------------------------------------------- 1281 1281 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_random 05 ? 1282 1282 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_random 05 ? 1283 1283 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_random 05 ? 1284 1284 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_random 05 ? 1285 1285 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1286 1286 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1287 1287 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1288 1288 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_random 05 ? 1289 1289 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_random 05 ? 128a 128a seq_br_type 3 Unconditional Branch; Flow J 0x1291 seq_branch_adr 1291 0x1291 128b 128b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 128c 128c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 128d 128d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 128e 128e fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x12ab ioc_fiubs 1 val seq_br_type 9 Return False seq_branch_adr 12ab 0x12ab seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 128f 128f fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x12be ioc_fiubs 1 val seq_br_type 9 Return False seq_branch_adr 12be 0x12be seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 1290 1290 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_random 05 ? 1291 1291 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1292 1292 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 1293 1293 seq_b_timing 0 Early Condition; Flow J cc=True 0x129e seq_br_type 1 Branch True seq_branch_adr 129e 0x129e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1294 1294 ioc_fiubs 1 val ; Flow J 0x1295 ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 1298 0x1298 typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1295 1295 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x24b2 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 24b2 0x24b2 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR05:00 typ_c_adr 37 GP08 typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 1296 1296 seq_br_type 1 Branch True; Flow J cc=True 0x24b2 seq_branch_adr 24b2 0x24b2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 1297 1297 seq_br_type 7 Unconditional Call; Flow C 0x32a4 seq_branch_adr 32a4 0x32a4 1298 1298 ioc_load_wdr 0 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1299 1299 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3d GP02 129a 129a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_random 02 ? typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 129b 129b ioc_tvbs 2 fiu+val; Flow C cc=True 0x2a5e seq_br_type 5 Call True seq_branch_adr 2a5e 0x2a5e seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 129c 129c fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 30 VR02:10 val_b_adr 1f TOP - 1 val_frame 2 129d 129d fiu_len_fill_lit 48 zero-fill 0x8; Flow J 0x12a0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 12a0 0x12a0 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 129e 129e fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 129f 129f fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x12a0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 12a0 0x12a0 seq_random 02 ? typ_alu_func 0 PASS_A typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 30 VR02:10 val_frame 2 12a0 12a0 fiu_fill_mode_src 0 ; Flow J cc=False 0x12a2 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 12a2 0x12a2 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 6 CONTROL TOP typ_c_adr 39 GP06 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3b GP04 val_c_source 0 FIU_BUS 12a1 12a1 fiu_fill_mode_src 0 ; Flow J 0x12a5 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 12a5 0x12a5 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_mar_cntl b LOAD_MAR_DATA 12a2 12a2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 12a3 12a3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 12a4 12a4 fiu_load_var 1 hold_var; Flow J 0x12a5 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 12a5 0x12a5 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 12a5 12a5 ioc_load_wdr 0 ; Flow C 0x1346 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 1346 0x1346 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 06 GP06 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 12a6 12a6 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 12a7 12a7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_random 0f Load_control_top+? typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 12a8 12a8 ioc_tvbs 2 fiu+val; Flow J 0x12a9 seq_br_type 2 Push (branch address) seq_branch_adr 12aa 0x12aa seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN 12a9 12a9 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2a5e ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2a5e 0x2a5e seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 12aa 12aa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 12ab 12ab fiu_load_tar 1 hold_tar; Flow J cc=False 0x12ad fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 12ad 0x12ad seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 12ac 12ac seq_br_type 4 Call False; Flow C cc=False 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 12ad 12ad fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 12ae 12ae ioc_tvbs 1 typ+fiu typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 12af 12af fiu_load_var 1 hold_var; Flow C cc=False 0x12b6 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 12b6 0x12b6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 12b0 12b0 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x12bb seq_br_type 0 Branch False seq_branch_adr 12bb 0x12bb seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 12b1 12b1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 12b2 12b2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x12b9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 12b9 0x12b9 seq_en_micro 0 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 val_m_a_src 2 Bits 32…47 12b3 12b3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 12b4 12b4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 12b5 12b5 seq_br_type 3 Unconditional Branch; Flow J 0x12b9 seq_branch_adr 12b9 0x12b9 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 12b6 ; -------------------------------------------------------------------------------------- 12b6 ; Comes from: 12b6 ; 12af C False from color 0x1106 12b6 ; -------------------------------------------------------------------------------------- 12b6 12b6 ioc_tvbs 1 typ+fiu; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 12b7 0x12b7 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 12b7 12b7 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 12b8 12b8 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x32a2 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32a2 0x32a2 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 12b9 12b9 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 12ba 12ba fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1114 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1114 0x1114 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 12bb 12bb fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 12bc 12bc fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 12bd 12bd seq_br_type 3 Unconditional Branch; Flow J 0x12b9 seq_branch_adr 12b9 0x12b9 typ_csa_cntl 3 POP_CSA val_c_adr 3b GP04 val_c_mux_sel 2 ALU 12be 12be fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 12bf 12bf fiu_mem_start 4 continue typ_a_adr 2f TR09:0f typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 12c0 12c0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x12f5 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 12f5 0x12f5 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 20 TR08:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 12c1 12c1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 12c2 12c2 ioc_tvbs 3 fiu+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 12c3 12c3 ioc_fiubs 2 typ ; Flow C cc=True 0x12f7 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 12f7 0x12f7 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 12c4 12c4 seq_br_type 4 Call False; Flow C cc=False 0x12f7 seq_branch_adr 12f7 0x12f7 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 12c5 12c5 fiu_load_var 1 hold_var; Flow J cc=True 0x12c9 fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 12c9 0x12c9 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 12c6 12c6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 12c7 12c7 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 12c8 12c8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 12c9 12c9 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 12ca 12ca fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 37 TR05:17 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 12cb 12cb fiu_mem_start 4 continue typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR07:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR 12cc 12cc fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 12cd 12cd fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 04 GP04 val_alu_func 1c DEC_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 12ce 12ce ioc_fiubs 2 typ ; Flow C cc=False 0x32dc seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 06 GP06 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 6 12cf 12cf fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_b_adr 03 GP03 12d0 12d0 ioc_tvbs 2 fiu+val; Flow J cc=True 0x12d7 seq_br_type 1 Branch True seq_branch_adr 12d7 0x12d7 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 12d1 12d1 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val 12d2 12d2 fiu_load_var 1 hold_var; Flow C cc=False 0x32dc fiu_tivi_src 2 tar_fiu fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 12d3 12d3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 13 ONES typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_mux_sel 2 ALU 12d4 12d4 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 12d5 12d5 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_frame 6 12d6 12d6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x12df fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 12df 0x12df typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 12d7 12d7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f 12d8 12d8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 12d9 12d9 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 12da 12da fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 12db 12db seq_b_timing 1 Latch Condition; Flow J cc=True 0x12df seq_br_type 1 Branch True seq_branch_adr 12df 0x12df seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 val_m_b_src 2 Bits 32…47 12dc 12dc seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 12dd 12dd seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 12de 12de seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 12df 12df seq_b_timing 0 Early Condition; Flow C cc=False 0x12ef seq_br_type 4 Call False seq_branch_adr 12ef 0x12ef seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 12e0 12e0 fiu_mem_start 2 start-rd; Flow C 0x35c6 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35c6 0x35c6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 12e1 12e1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x12f0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 12f0 0x12f0 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 12e2 12e2 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 12e3 12e3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x12f0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 12f0 0x12f0 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 12e4 12e4 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 04 GP04 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 12e5 12e5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x12f0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 12f0 0x12f0 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 12e6 12e6 ioc_load_wdr 0 ; Flow J cc=True 0x12ea ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 12ea 0x12ea seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 12e7 12e7 ioc_fiubs 2 typ typ_a_adr 07 GP07 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 12e8 12e8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x12f0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 12f0 0x12f0 typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR09:07 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl b LOAD_MAR_DATA 12e9 12e9 ioc_load_wdr 0 ; Flow J 0x12ec ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 12ec 0x12ec 12ea 12ea seq_br_type 1 Branch True; Flow J cc=True 0x12ec seq_branch_adr 12ec 0x12ec seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 12eb 12eb seq_br_type 7 Unconditional Call; Flow C 0x2a5e seq_branch_adr 2a5e 0x2a5e typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR09:07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 34 VR07:14 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 12ec 12ec ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 12ed 12ed seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 12ee 12ee fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 12ef ; -------------------------------------------------------------------------------------- 12ef ; Comes from: 12ef ; 12df C False from color 0x128f 12ef ; -------------------------------------------------------------------------------------- 12ef 12ef seq_br_type a Unconditional Return; Flow R val_a_adr 2c VR08:0c val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 8 12f0 ; -------------------------------------------------------------------------------------- 12f0 ; Comes from: 12f0 ; 12e1 C from color 0x128f 12f0 ; 12e3 C from color 0x128f 12f0 ; 12e5 C from color 0x128f 12f0 ; 12e8 C from color 0x128f 12f0 ; -------------------------------------------------------------------------------------- 12f0 12f0 fiu_fill_mode_src 0 ; Flow J cc=False 0x12f2 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 12f2 0x12f2 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR 12f1 12f1 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 12f2 12f2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 12f3 12f3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 12f4 12f4 fiu_load_var 1 hold_var; Flow R fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 12f5 ; -------------------------------------------------------------------------------------- 12f5 ; Comes from: 12f5 ; 12c0 C False from color 0x128f 12f5 ; -------------------------------------------------------------------------------------- 12f5 12f5 seq_br_type 4 Call False; Flow C cc=False 0x32dc seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 13 ONES typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 12f6 12f6 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 12f7 ; -------------------------------------------------------------------------------------- 12f7 ; Comes from: 12f7 ; 12c3 C True from color 0x128f 12f7 ; 12c4 C False from color 0x128f 12f7 ; -------------------------------------------------------------------------------------- 12f7 12f7 seq_b_timing 0 Early Condition; Flow R cc=False ; Flow J cc=True 0x32a2 seq_br_type 9 Return False seq_branch_adr 32a2 0x32a2 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 12f8 ; -------------------------------------------------------------------------------------- 12f8 ; 0x02fe Declare_Variable Variant_Record,Visible 12f8 ; -------------------------------------------------------------------------------------- 12f8 MACRO_Declare_Variable_Variant_Record,Visible: 12f8 12f8 dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 12f8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 31 VR02:11 val_frame 2 12f9 12f9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32da fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 12fa 12fa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x12fe fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 12fe 0x12fe seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 12fb 12fb seq_br_type 4 Call False; Flow C cc=False 0x32cc seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 12fc 12fc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) val_a_adr 08 GP08 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 12fd 12fd val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 08 GP08 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 12fe 12fe fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 12ff 12ff fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x1302 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 1 Branch True seq_branch_adr 1302 0x1302 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_frame 2 1300 1300 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d2 seq_br_type 5 Call True seq_branch_adr 32d2 0x32d2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 1301 1301 seq_br_type 7 Unconditional Call; Flow C 0x32cc seq_branch_adr 32cc 0x32cc 1302 1302 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x29e5 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 29e5 0x29e5 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1303 1303 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1304 ; -------------------------------------------------------------------------------------- 1304 ; 0x02ff Declare_Variable Variant_Record 1304 ; -------------------------------------------------------------------------------------- 1304 MACRO_Declare_Variable_Variant_Record: 1304 1304 dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1304 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 39 VR02:19 val_frame 2 1305 1305 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x12fa fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 12fa 0x12fa seq_int_reads 6 CONTROL TOP typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1306 ; -------------------------------------------------------------------------------------- 1306 ; 0x02fb Declare_Variable Variant_Record,Visible,With_Constraint 1306 ; -------------------------------------------------------------------------------------- 1306 MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint: 1306 1306 dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1306 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 1307 1307 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32da fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 22 TR02:02 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1308 1308 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x130c fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 130c 0x130c seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 1309 1309 seq_br_type 4 Call False; Flow C cc=False 0x32cc seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 130a 130a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) val_a_adr 04 GP04 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 130b 130b val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 130c 130c fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 130d 130d fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x1310 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1310 0x1310 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 130e 130e fiu_load_var 1 hold_var; Flow J cc=False 0x1315 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 1315 0x1315 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 20 TR08:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_frame 2 130f 130f fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x131a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 131a 0x131a typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 1310 1310 ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a5 seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 1311 1311 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x1313 seq_br_type 1 Branch True seq_branch_adr 1313 0x1313 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1312 1312 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a5 seq_br_type 5 Call True seq_branch_adr 32a5 0x32a5 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 1313 1313 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x24b2 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 24b2 0x24b2 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_b_adr 03 GP03 1314 1314 ioc_tvbs 2 fiu+val; Flow J cc=True 0x1317 seq_br_type 1 Branch True seq_branch_adr 1317 0x1317 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_frame 2 1315 1315 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d2 seq_br_type 5 Call True seq_branch_adr 32d2 0x32d2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 1316 1316 seq_br_type 7 Unconditional Call; Flow C 0x32cc seq_branch_adr 32cc 0x32cc 1317 1317 seq_br_type 5 Call True; Flow C cc=True 0x2a5e seq_branch_adr 2a5e 0x2a5e seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1318 1318 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_b_adr 1f TOP - 1 val_frame 2 1319 1319 fiu_len_fill_lit 48 zero-fill 0x8; Flow J 0x131a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 131a 0x131a typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 131a 131a fiu_fill_mode_src 0 ; Flow J cc=False 0x131c fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 131c 0x131c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 131b 131b fiu_fill_mode_src 0 ; Flow J 0x131f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 131f 0x131f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 131c 131c fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 131d 131d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 131e 131e fiu_load_var 1 hold_var; Flow J 0x131f fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 131f 0x131f seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 131f 131f ioc_load_wdr 0 ; Flow C 0x1346 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 1346 0x1346 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 1320 1320 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1323 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1323 0x1323 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_b_adr 03 GP03 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 03 GP03 1321 1321 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 1322 1322 ioc_tvbs 3 fiu+fiu; Flow C 0x2a5e seq_br_type 7 Unconditional Call seq_branch_adr 2a5e 0x2a5e typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1323 1323 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1328 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1328 0x1328 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_random 02 ? typ_a_adr 21 TR02:01 typ_b_adr 03 GP03 typ_frame 2 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1324 1324 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 1325 1325 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl e LOAD_MAR_CONTROL 1326 1326 ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 1327 1327 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1328 1328 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_b_adr 22 TR02:02 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 21 VR02:01 val_frame 2 1329 1329 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x1331 fiu_load_tar 1 hold_tar fiu_mem_start 9 start_continue_if_true fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1331 0x1331 typ_b_adr 2e TR08:0e typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 22 VR06:02 val_frame 6 132a 132a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 22 TR01:02 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 132b 132b fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 21 fiu_op_sel 3 insert ioc_load_wdr 0 typ_b_adr 07 GP07 val_b_adr 07 GP07 132c 132c ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 132d 132d fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 132e 132e fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_mar_cntl 6 INCREMENT_MAR 132f 132f ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 1330 1330 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1331 1331 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_a_adr 22 TR01:02 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1332 1332 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 1333 1333 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 21 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 1334 1334 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 1335 1335 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 1336 1336 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 22 TR02:02 typ_b_adr 04 GP04 typ_frame 2 val_b_adr 04 GP04 1337 1337 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 23 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 3 seq seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL 1338 1338 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 07 GP07 1339 1339 ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_b_adr 06 GP06 133a 133a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 133b 133b <halt> ; Flow R 133c ; -------------------------------------------------------------------------------------- 133c ; 0x02fc Declare_Variable Variant_Record,With_Constraint 133c ; -------------------------------------------------------------------------------------- 133c MACRO_Declare_Variable_Variant_Record,With_Constraint: 133c 133c dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 133c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 133d 133d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1308 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1308 0x1308 seq_int_reads 6 CONTROL TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 133e ; -------------------------------------------------------------------------------------- 133e ; 0x02fd Declare_Variable Variant_Record,Duplicate 133e ; -------------------------------------------------------------------------------------- 133e MACRO_Declare_Variable_Variant_Record,Duplicate: 133e 133e dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 133e fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 133f 133f fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1340 1340 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1343 fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1343 0x1343 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 1341 1341 seq_br_type 4 Call False; Flow C cc=False 0x32cc seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 02 ? val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1342 1342 ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1343 1343 fiu_mem_start 2 start-rd; Flow C 0x2484 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2484 0x2484 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1344 1344 ioc_fiubs 1 val ; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 5 val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1345 1345 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1346 ; -------------------------------------------------------------------------------------- 1346 ; Comes from: 1346 ; 12a5 C from color 0x0000 1346 ; 131f C from color 0x1307 1346 ; -------------------------------------------------------------------------------------- 1346 1346 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 1347 1347 fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 1348 0x1348 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1348 1348 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_source 0 FIU_BUS 1349 1349 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 134a 134a fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x134d fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 134d 0x134d seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 134b 134b seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 134c 134c fiu_mem_start 2 start-rd seq_en_micro 0 134d 134d typ_c_adr 37 GP08 val_rand 2 DEC_LOOP_COUNTER 134e 134e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 134f 134f ioc_fiubs 0 fiu typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_c_adr 36 GP09 val_c_source 0 FIU_BUS 1350 1350 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a4 0x32a4 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1351 1351 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 08 GP08 1352 1352 fiu_fill_mode_src 0 ; Flow J cc=False 0x1354 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1354 0x1354 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 09 GP09 1353 1353 fiu_fill_mode_src 0 ; Flow J 0x1357 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1357 0x1357 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 1354 1354 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1355 1355 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1356 1356 fiu_load_var 1 hold_var; Flow J 0x1357 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1357 0x1357 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1357 1357 ioc_load_wdr 0 ; Flow J cc=False 0x1349 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1349 0x1349 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 1358 1358 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ab4 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_b_adr 05 GP05 1359 1359 ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 135a ; -------------------------------------------------------------------------------------- 135a ; 0x0337 Declare_Variable Array 135a ; -------------------------------------------------------------------------------------- 135a MACRO_Declare_Variable_Array: 135a 135a dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 135a fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 135b 135b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1368 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1368 0x1368 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR0a:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame a val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 135c 135c ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x135e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 135e 0x135e seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 39 TR06:19 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 135d 135d fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1363 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 1363 0x1363 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 1c ? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 135e 135e ioc_tvbs c mem+mem+csa+dummy; Flow J 0x135f seq_br_type 2 Push (branch address) seq_branch_adr 1362 0x1362 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 135f 135f ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x1369 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1369 0x1369 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS 1360 1360 ioc_fiubs 2 typ ; Flow J cc=False 0x1363 seq_br_type 0 Branch False seq_branch_adr 1363 0x1363 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 02 ? typ_a_adr 03 GP03 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1361 1361 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2a5e ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2a5e 0x2a5e seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP 1362 1362 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1363 1363 ioc_fiubs 2 typ ; Flow J cc=True 0x1365 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1365 0x1365 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 1364 1364 seq_br_type 7 Unconditional Call; Flow C 0x32cc seq_branch_adr 32cc 0x32cc 1365 1365 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 1366 1366 seq_br_type 7 Unconditional Call; Flow C 0x32d2 seq_branch_adr 32d2 0x32d2 1367 1367 fiu_mem_start 2 start-rd; Flow J 0x1363 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1363 0x1363 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1368 1368 ioc_tvbs 2 fiu+val; Flow C 0x32d7 seq_br_type 7 Unconditional Call seq_branch_adr 32d7 0x32d7 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU 1369 ; -------------------------------------------------------------------------------------- 1369 ; Comes from: 1369 ; 135f C True from color 0x0000 1369 ; -------------------------------------------------------------------------------------- 1369 1369 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 136a 136a val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 136b 136b seq_br_type a Unconditional Return; Flow R val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 136c ; -------------------------------------------------------------------------------------- 136c ; 0x0336 Declare_Variable Array,Visible 136c ; -------------------------------------------------------------------------------------- 136c MACRO_Declare_Variable_Array,Visible: 136c 136c dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 136c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 136d 136d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a9 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 136e 136e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x135e fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 135e 0x135e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 39 TR06:19 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 6 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 136f 136f fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1363 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1363 0x1363 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1370 ; -------------------------------------------------------------------------------------- 1370 ; 0x0335 Declare_Variable Array,Duplicate 1370 ; -------------------------------------------------------------------------------------- 1370 MACRO_Declare_Variable_Array,Duplicate: 1370 1370 dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1370 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1371 1371 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1372 1372 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1377 fiu_mem_start 4 continue fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1377 0x1377 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1373 1373 seq_b_timing 1 Latch Condition; Flow C cc=True 0x139e seq_br_type 5 Call True seq_branch_adr 139e 0x139e 1374 1374 ioc_fiubs 2 typ ; Flow J cc=False 0x1363 seq_br_type 0 Branch False seq_branch_adr 1363 0x1363 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 02 ? typ_a_adr 03 GP03 typ_c_adr 39 GP06 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1375 1375 ioc_fiubs 1 val ; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1376 1376 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1377 1377 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x139e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 139e 0x139e typ_c_adr 39 GP06 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1378 1378 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_c_lit 0 typ_frame c val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1379 1379 fiu_len_fill_lit 4b zero-fill 0xb fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 5 137a 137a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x137d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 137d 0x137d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 137b 137b fiu_fill_mode_src 0 ; Flow C cc=False 0x1380 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1380 0x1380 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 137c 137c seq_br_type 3 Unconditional Branch; Flow J 0x1384 seq_branch_adr 1384 0x1384 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 137d 137d fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 137e 137e fiu_fill_mode_src 0 ; Flow C cc=False 0x1380 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1380 0x1380 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 137f 137f seq_br_type 3 Unconditional Branch; Flow J 0x1384 seq_branch_adr 1384 0x1384 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 1380 ; -------------------------------------------------------------------------------------- 1380 ; Comes from: 1380 ; 137b C False from color 0x0000 1380 ; 137e C False from color 0x0000 1380 ; -------------------------------------------------------------------------------------- 1380 1380 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1382 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1382 0x1382 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1381 1381 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1382 1382 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1383 1383 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1384 1384 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=True 0x1388 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1388 0x1388 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1385 1385 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1386 1386 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1387 1387 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1388 1388 ioc_tvbs 1 typ+fiu; Flow J 0x1389 seq_br_type 2 Push (branch address) seq_branch_adr 138d 0x138d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1389 1389 ioc_fiubs 1 val ; Flow J cc=True 0x138b seq_br_type 1 Branch True seq_branch_adr 138b 0x138b seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 138a 138a val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 138b 138b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1390 seq_br_type 1 Branch True seq_branch_adr 1390 0x1390 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 138c 138c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1390 seq_br_type 1 Branch True seq_branch_adr 1390 0x1390 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 138d 138d ioc_fiubs 2 typ ; Flow J cc=False 0x1367 seq_br_type 0 Branch False seq_branch_adr 1367 0x1367 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 02 ? typ_a_adr 03 GP03 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 138e 138e ioc_fiubs 1 val ; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 138f 138f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1390 1390 fiu_len_fill_lit 79 zero-fill 0x39 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1391 1391 ioc_fiubs 0 fiu typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 1392 1392 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1395 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1395 0x1395 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1393 1393 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 1394 1394 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1395 1395 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1399 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1399 0x1399 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 1396 1396 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 1397 1397 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x139b seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 139b 0x139b seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1398 1398 seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x1392 seq_br_type 8 Return True seq_branch_adr 1392 0x1392 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1399 1399 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 139a 139a fiu_fill_mode_src 0 ; Flow J 0x1397 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1397 0x1397 139b 139b fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value val_b_adr 05 GP05 139c 139c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 139d 139d ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 139e ; -------------------------------------------------------------------------------------- 139e ; Comes from: 139e ; 1373 C True from color 0x0000 139e ; 1377 C True from color 0x0000 139e ; -------------------------------------------------------------------------------------- 139e 139e val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 139f 139f val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 13a0 13a0 seq_br_type a Unconditional Return; Flow R val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 13a1 13a1 <halt> ; Flow R 13a2 ; -------------------------------------------------------------------------------------- 13a2 ; 0x0334 Declare_Variable Array,With_Constraint 13a2 ; -------------------------------------------------------------------------------------- 13a2 MACRO_Declare_Variable_Array,With_Constraint: 13a2 13a2 dispatch_brk_class 4 ; Flow J 0x13a3 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 13a2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 3fff 0x3fff seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 21 TR0c:01 typ_c_adr 3c GP03 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13a3 13a3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x13cf fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 13cf 0x13cf seq_int_reads 6 CONTROL TOP typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13a4 13a4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR07:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13a5 13a5 fiu_tivi_src 1 tar_val; Flow J cc=True 0x13c4 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13c4 0x13c4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 6 13a6 13a6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32dc fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 3a GP05 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13a7 13a7 fiu_fill_mode_src 0 ; Flow J cc=True 0x13b2 fiu_length_src 0 length_register fiu_offset_src 0 offset_register ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13b2 0x13b2 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 13a8 13a8 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x13a9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 13aa 0x13aa typ_a_adr 30 TR05:10 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13a9 13a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x13b5 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 13b5 0x13b5 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 13aa 13aa seq_br_type 4 Call False; Flow C cc=False 0x32dc seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 13ab 13ab fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 13ac 13ac fiu_fill_mode_src 0 ; Flow J cc=False 0x13af fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 13af 0x13af seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 13ad 13ad fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 13ae 13ae ioc_load_wdr 0 ; Flow J 0x13c1 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 13c1 0x13c1 13af 13af fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 13b0 13b0 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 2 13b1 13b1 fiu_load_var 1 hold_var; Flow J 0x13ae fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 13ae 0x13ae seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 13b2 13b2 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x13b3 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 13c1 0x13c1 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 13b3 13b3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a2 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 13b4 13b4 fiu_mem_start 2 start-rd; Flow C cc=False 0x32a2 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e 13b5 13b5 fiu_fill_mode_src 0 ; Flow J cc=False 0x13bd fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 13bd 0x13bd seq_en_micro 0 typ_a_adr 07 GP07 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 13b6 13b6 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 13b7 13b7 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 13b8 13b8 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 13b9 0x13b9 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 13b9 13b9 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13ba 13ba seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13bb 13bb seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 13bc 0x13bc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 13bc 13bc seq_br_type 7 Unconditional Call; Flow C 0x32d2 seq_branch_adr 32d2 0x32d2 13bd 13bd fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 13be 13be fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_mar_cntl 6 INCREMENT_MAR 13bf 13bf ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 13c0 13c0 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x13b9 seq_br_type 8 Return True seq_branch_adr 13b9 0x13b9 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 13c1 13c1 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x13cc ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 13cc 0x13cc seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 3 POP_CSA typ_frame 1f val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 13c2 13c2 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 13c3 0x13c3 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13c3 13c3 ioc_fiubs 2 typ ; Flow C 0x32cc seq_br_type 7 Unconditional Call seq_branch_adr 32cc 0x32cc typ_a_adr 03 GP03 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 13c4 13c4 ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 13c5 13c5 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 27 TR02:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 13c6 13c6 ioc_tvbs 2 fiu+val; Flow C cc=True 0x13c9 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 13c9 0x13c9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS 13c7 13c7 seq_b_timing 1 Latch Condition; Flow J cc=False 0x13a6 seq_br_type 0 Branch False seq_branch_adr 13a6 0x13a6 13c8 13c8 ioc_fiubs 1 val ; Flow J 0x13a6 seq_br_type 3 Unconditional Branch seq_branch_adr 13a6 0x13a6 seq_random 07 Push_stack+? val_a_adr 32 VR12:12 val_frame 12 13c9 ; -------------------------------------------------------------------------------------- 13c9 ; Comes from: 13c9 ; 13c6 C True from color MACRO_Declare_Variable_Array,With_Constraint 13c9 ; 13e9 C True from color MACRO_Declare_Variable_Array,With_Constraint 13c9 ; -------------------------------------------------------------------------------------- 13c9 13c9 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 13ca 13ca seq_br_type 4 Call False; Flow C cc=False 0x32cc seq_branch_adr 32cc 0x32cc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 13cb 13cb ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 13cc ; -------------------------------------------------------------------------------------- 13cc ; Comes from: 13cc ; 13c1 C True from color MACRO_Declare_Variable_Array,With_Constraint 13cc ; -------------------------------------------------------------------------------------- 13cc 13cc ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 39 GP06 val_c_mux_sel 2 ALU 13cd 13cd seq_br_type 7 Unconditional Call; Flow C 0x2a5e seq_branch_adr 2a5e 0x2a5e typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 13ce 13ce seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 13cf 13cf fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR07:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13d0 13d0 fiu_mem_start 4 continue; Flow J cc=True 0x13e7 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13e7 0x13e7 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 6 13d1 13d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_c_adr 3a GP05 typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 13d2 13d2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1419 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1419 0x1419 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13d3 13d3 fiu_fill_mode_src 0 ; Flow J cc=True 0x13d7 fiu_length_src 0 length_register fiu_offset_src 0 offset_register ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13d7 0x13d7 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 13d4 13d4 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13d5 13d5 ioc_fiubs 1 val ; Flow C cc=False 0x32dc seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 2b TR08:0b typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 8 typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 13d6 13d6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x13db fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 13db 0x13db typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 13d7 13d7 typ_c_adr 3b GP04 val_c_adr 3b GP04 13d8 13d8 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 13d9 13d9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a2 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 2f TR09:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 13da 13da fiu_mem_start 2 start-rd; Flow C cc=False 0x32a2 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e 13db 13db fiu_fill_mode_src 0 ; Flow J cc=False 0x13e2 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 13e2 0x13e2 typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 13dc 13dc fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 13dd 13dd ioc_load_wdr 0 ; Flow J cc=True 0x13ef ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13ef 0x13ef seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 13de 13de seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13df 13df seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13e0 13e0 seq_br_type 1 Branch True; Flow J cc=True 0x13ef seq_branch_adr 13ef 0x13ef seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 13e1 13e1 seq_br_type 3 Unconditional Branch; Flow J 0x13ef seq_branch_adr 13ef 0x13ef val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 13e2 13e2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 13e3 13e3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR 13e4 13e4 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 13e5 13e5 seq_b_timing 1 Latch Condition; Flow J cc=True 0x13ef seq_br_type 1 Branch True seq_branch_adr 13ef 0x13ef seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 13e6 13e6 seq_br_type 3 Unconditional Branch; Flow J 0x13df seq_branch_adr 13df 0x13df seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 13e7 13e7 ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 13e8 13e8 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 27 TR02:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 13e9 13e9 ioc_tvbs 2 fiu+val; Flow C cc=True 0x13c9 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 13c9 0x13c9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS 13ea 13ea fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x13d1 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 13d1 0x13d1 13eb 13eb fiu_mem_start 2 start-rd; Flow J 0x13d1 ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 13d1 0x13d1 seq_random 07 Push_stack+? val_a_adr 32 VR12:12 val_frame 12 13ec ; -------------------------------------------------------------------------------------- 13ec ; Comes from: 13ec ; 1416 C True from color MACRO_Declare_Variable_Array,With_Constraint 13ec ; -------------------------------------------------------------------------------------- 13ec 13ec ioc_fiubs 1 val ; Flow R cc=False seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 13ed 0x13ed seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 39 GP06 val_c_mux_sel 2 ALU 13ed 13ed seq_br_type 7 Unconditional Call; Flow C 0x2a5e seq_branch_adr 2a5e 0x2a5e typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR09:07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 6 A_MINUS_B val_b_adr 34 VR07:14 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 13ee 13ee seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 13ef 13ef fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 13f0 13f0 fiu_fill_mode_src 0 ; Flow J cc=False 0x13f2 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 13f2 0x13f2 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 13f1 13f1 fiu_fill_mode_src 0 ; Flow J 0x13f5 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 13f5 0x13f5 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 13f2 13f2 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 13f3 13f3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 30 GP0f val_c_source 0 FIU_BUS 13f4 13f4 fiu_load_var 1 hold_var; Flow J 0x13f5 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 13f5 0x13f5 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 13f5 13f5 ioc_load_wdr 0 ; Flow J 0x13f6 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 13f6 0x13f6 13f6 13f6 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1c TOP - 4 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13f7 13f7 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 1c TOP - 4 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 13f8 13f8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32dc fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13f9 13f9 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x13fe fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 13fe 0x13fe seq_cond_sel 65 CROSS_WORD_FIELD~ seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 13fa 13fa fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 13fb 13fb fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value val_b_adr 1d TOP - 3 13fc 13fc ioc_fiubs 0 fiu ; Flow C cc=False 0x32dc seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 1d TOP - 3 val_frame 6 13fd 13fd fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1400 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1400 0x1400 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 13fe 13fe fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a2 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 13ff 13ff fiu_mem_start 2 start-rd; Flow C cc=False 0x32a2 ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e 1400 1400 fiu_fill_mode_src 0 ; Flow J cc=False 0x1407 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1407 0x1407 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1401 1401 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1402 1402 ioc_load_wdr 0 ; Flow J cc=True 0x140d ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 140d 0x140d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_m_a_src 2 Bits 32…47 1403 1403 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1404 1404 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1405 1405 seq_br_type 1 Branch True; Flow J cc=True 0x140d seq_branch_adr 140d 0x140d seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1406 1406 seq_br_type 7 Unconditional Call; Flow C 0x32d2 seq_branch_adr 32d2 0x32d2 1407 1407 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1408 1408 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1409 1409 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 140a 140a ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 140b 140b seq_b_timing 1 Latch Condition; Flow J cc=True 0x140d seq_br_type 1 Branch True seq_branch_adr 140d 0x140d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_m_a_src 2 Bits 32…47 140c 140c seq_br_type 3 Unconditional Branch; Flow J 0x1404 seq_branch_adr 1404 0x1404 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 140d 140d ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 6 140e 140e ioc_fiubs 2 typ ; Flow J cc=True 0x1416 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1416 0x1416 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 0f GP0f typ_csa_cntl 7 FINISH_POP_DOWN 140f 140f fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 1410 1410 fiu_fill_mode_src 0 ; Flow J cc=False 0x1413 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1413 0x1413 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1411 1411 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 1412 1412 ioc_load_wdr 0 ; Flow J 0x1416 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1416 0x1416 1413 1413 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1414 1414 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 7 1415 1415 fiu_load_var 1 hold_var; Flow J 0x1412 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1412 0x1412 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1416 1416 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x13ec ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 13ec 0x13ec seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1417 1417 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 1418 0x1418 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1418 1418 ioc_fiubs 2 typ ; Flow C 0x32cc seq_br_type 7 Unconditional Call seq_branch_adr 32cc 0x32cc typ_a_adr 03 GP03 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 1419 1419 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 141a 141a fiu_len_fill_lit 4d zero-fill 0xd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 141b 141b seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 141c 141c fiu_mem_start 2 start-rd; Flow C cc=False 0x32cc ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 141d 141d ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 141e 141e ioc_tvbs c mem+mem+csa+dummy typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 141f 141f seq_br_type 7 Unconditional Call; Flow C 0x1441 seq_branch_adr 1441 0x1441 typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1420 1420 ioc_fiubs 2 typ ; Flow J cc=True 0x1432 seq_br_type 1 Branch True seq_branch_adr 1432 0x1432 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1e A_AND_B typ_b_adr 37 TR05:17 typ_frame 5 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1421 1421 val_a_adr 17 LOOP_COUNTER val_alu_func 1e A_AND_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 1422 1422 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 1423 1423 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1424 1424 ioc_fiubs 1 val val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1425 1425 seq_br_type 4 Call False; Flow C cc=False 0x32cc seq_branch_adr 32cc 0x32cc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1426 1426 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1429 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1429 0x1429 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 1427 1427 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 1428 1428 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 1429 1429 fiu_mem_start 4 continue typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 142a 142a ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 142b 142b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x142d fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 142d 0x142d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 142c 142c seq_br_type 3 Unconditional Branch; Flow J 0x142e seq_branch_adr 142e 0x142e val_a_adr 22 VR06:02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 142d 142d seq_br_type 4 Call False; Flow C cc=False 0x32dc seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_frame 6 142e 142e fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A 142f 142f fiu_fill_mode_src 0 ; Flow J cc=False 0x1439 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1439 0x1439 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 05 GP05 1430 1430 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A 1431 1431 ioc_load_wdr 0 ; Flow J cc=False 0x1426 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1426 0x1426 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 5 1432 1432 ioc_adrbs 2 typ seq_random 02 ? typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 1433 1433 ioc_fiubs 2 typ seq_en_micro 0 seq_random 0f Load_control_top+? typ_csa_cntl 7 FINISH_POP_DOWN 1434 1434 fiu_tivi_src 4 fiu_var ioc_tvbs 2 fiu+val seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 3 POP_CSA typ_frame 1f 1435 1435 seq_b_timing 1 Latch Condition; Flow C cc=True 0x143c seq_br_type 5 Call True seq_branch_adr 143c 0x143c typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1436 1436 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 1437 0x1437 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1437 1437 ioc_fiubs 2 typ ; Flow C cc=True 0x32d2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d2 0x32d2 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 1438 1438 seq_br_type 7 Unconditional Call; Flow C 0x32cc seq_branch_adr 32cc 0x32cc 1439 1439 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 143a 143a fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 143b 143b fiu_load_var 1 hold_var; Flow J 0x1431 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1431 0x1431 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 143c ; -------------------------------------------------------------------------------------- 143c ; Comes from: 143c ; 1435 C True from color MACRO_Declare_Variable_Array,With_Constraint 143c ; -------------------------------------------------------------------------------------- 143c 143c ioc_fiubs 1 val ; Flow J cc=True 0x143f seq_br_type 1 Branch True seq_branch_adr 143f 0x143f seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B 143d 143d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d2 seq_br_type 5 Call True seq_branch_adr 32d2 0x32d2 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 143e 143e seq_br_type 7 Unconditional Call; Flow C 0x32cc seq_branch_adr 32cc 0x32cc 143f 143f ioc_fiubs 1 val ; Flow C 0x2a5e seq_br_type 7 Unconditional Call seq_branch_adr 2a5e 0x2a5e typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1440 1440 seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1441 ; -------------------------------------------------------------------------------------- 1441 ; Comes from: 1441 ; 141f C from color MACRO_Declare_Variable_Array,With_Constraint 1441 ; -------------------------------------------------------------------------------------- 1441 1441 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 1442 1442 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 1443 1443 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1444 1444 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_a_adr 06 GP06 val_alu_func 1c DEC_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1445 1445 seq_br_type 4 Call False; Flow C cc=False 0x32dc seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_c_adr 3a GP05 val_frame 6 1446 1446 ioc_load_wdr 0 ; Flow J cc=True 0x1457 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1457 0x1457 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 1447 1447 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1448 1448 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x2ab4 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_c_adr 3b GP04 1449 1449 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 144a 144a fiu_fill_mode_src 0 ; Flow J cc=False 0x1458 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1458 0x1458 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 07 GP07 144b 144b fiu_fill_mode_src 0 ; Flow J cc=True 0x145b fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 145b 0x145b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A 144c 144c ioc_load_wdr 0 ; Flow C cc=True 0x32a2 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 144d 144d seq_br_type 0 Branch False; Flow J cc=False 0x1452 seq_branch_adr 1452 0x1452 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 144e 144e fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 144f 144f fiu_fill_mode_src 0 ; Flow J cc=False 0x1463 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1463 0x1463 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1450 1450 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1451 1451 ioc_fiubs 2 typ ; Flow J 0x1441 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1441 0x1441 typ_a_adr 04 GP04 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1452 1452 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1453 1453 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1454 1454 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1455 1455 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x144f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 144f 0x144f seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1456 1456 seq_br_type 3 Unconditional Branch; Flow J 0x144f seq_branch_adr 144f 0x144f val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1457 1457 seq_br_type 3 Unconditional Branch; Flow J 0x1448 seq_branch_adr 1448 0x1448 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 37 TR05:17 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1458 1458 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1459 1459 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 145a 145a fiu_load_var 1 hold_var; Flow J cc=False 0x144c fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 144c 0x144c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 145b 145b ioc_load_wdr 0 ; Flow C cc=True 0x32a2 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 145c 145c seq_br_type 0 Branch False; Flow J cc=False 0x145e seq_branch_adr 145e 0x145e seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 145d 145d seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 145e 145e seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 145f 145f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1460 1460 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1461 1461 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1462 0x1462 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 1462 1462 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1463 1463 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1464 1464 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1465 1465 fiu_load_var 1 hold_var; Flow J 0x1451 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1451 0x1451 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1466 ; -------------------------------------------------------------------------------------- 1466 ; 0x0333 Declare_Variable Array,Visible,With_Constraint 1466 ; -------------------------------------------------------------------------------------- 1466 MACRO_Declare_Variable_Array,Visible,With_Constraint: 1466 1466 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1466 ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 07 Push_stack+? typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR00:02 1467 1467 fiu_mem_start 2 start-rd; Flow J 0x13a3 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 13a3 0x13a3 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1468 ; -------------------------------------------------------------------------------------- 1468 ; 0x01ae Execute Matrix,Not_Equal 1468 ; 0x01af Execute Matrix,Equal 1468 ; -------------------------------------------------------------------------------------- 1468 MACRO_Execute_Matrix,Equal: 1468 MACRO_Execute_Matrix,Not_Equal: 1468 1468 dispatch_brk_class 8 ; Flow J cc=True 0x146a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1468 fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 146a 0x146a seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1469 1469 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 146a 146a fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x147b ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 147b 0x147b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 146b 146b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_a_adr 2f TR08:0f typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 146c 146c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1473 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1473 0x1473 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 146d 146d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 146e 146e fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 146f 146f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1471 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1471 0x1471 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1470 1470 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1477 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1477 0x1477 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 1471 1471 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1472 1472 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1477 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1477 0x1477 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 1473 1473 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x30a7 fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1474 1474 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 5 1475 1475 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 1476 1476 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1477 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1477 0x1477 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 1477 1477 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_rand c START_MULTIPLY 1478 1478 seq_b_timing 1 Latch Condition; Flow J cc=True 0x147e seq_br_type 1 Branch True seq_branch_adr 147e 0x147e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1479 1479 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 147a 147a seq_br_type 3 Unconditional Branch; Flow J 0x147e seq_branch_adr 147e 0x147e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 147b 147b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3a GP05 val_c_source 0 FIU_BUS 147c 147c fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x332e fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 147d 147d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x147e fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 147e 0x147e typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 147e 147e fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x148f ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 148f 0x148f seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 147f 147f fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_a_adr 2f TR08:0f typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1480 1480 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1487 ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1487 0x1487 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 34 VR07:14 val_frame 7 1481 1481 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1482 1482 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 1483 1483 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1485 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1485 0x1485 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1484 1484 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x148b fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 148b 0x148b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1485 1485 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1486 1486 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x148b fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 148b 0x148b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1487 1487 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x30a7 fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1488 1488 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 1489 1489 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_frame 11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 148a 148a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x148b fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 148b 0x148b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 148b 148b seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 148c 148c seq_b_timing 1 Latch Condition; Flow J cc=True 0x1492 seq_br_type 1 Branch True seq_branch_adr 1492 0x1492 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 148d 148d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 148e 148e seq_br_type 3 Unconditional Branch; Flow J 0x1492 seq_branch_adr 1492 0x1492 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 148f 148f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1490 1490 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x332e fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1491 1491 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1492 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1492 0x1492 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1492 1492 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1495 seq_br_type 1 Branch True seq_branch_adr 1495 0x1495 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1493 1493 ioc_fiubs 1 val ; Flow C cc=True 0x272c seq_br_type 5 Call True seq_branch_adr 272c 0x272c seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 1494 1494 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1495 1495 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1494 seq_br_type 0 Branch False seq_branch_adr 1494 0x1494 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A val_a_adr 04 GP04 val_alu_func 0 PASS_A 1496 1496 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1494 seq_br_type 0 Branch False seq_branch_adr 1494 0x1494 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_alu_func 0 PASS_A val_alu_func 0 PASS_A 1497 1497 seq_br_type 3 Unconditional Branch; Flow J 0x1494 seq_branch_adr 1494 0x1494 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1498 ; -------------------------------------------------------------------------------------- 1498 ; 0x01ad Execute Matrix,First 1498 ; -------------------------------------------------------------------------------------- 1498 MACRO_Execute_Matrix,First: 1498 1498 dispatch_brk_class 8 ; Flow J cc=True 0x14a2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1498 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14a2 0x14a2 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1499 1499 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x14a7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14a7 0x14a7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 20 TR14:00 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 149a 149a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x149c seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 149c 0x149c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 149b 149b fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 149c 149c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 149d 149d fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 149e 149e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x14a0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 14a0 0x14a0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 149f 149f fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x32d9 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1c DEC_A val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 14a0 14a0 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 14a1 14a1 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x32d9 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1c DEC_A val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 14a2 14a2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14a4 seq_br_type 1 Branch True seq_branch_adr 14a4 0x14a4 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 14a3 14a3 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x149e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 149e 0x149e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_frame 2 14a4 14a4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE 14a5 14a5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 1c DEC_A 14a6 14a6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14a7 14a7 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE 14a8 14a8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14a9 14a9 <halt> ; Flow R 14aa ; -------------------------------------------------------------------------------------- 14aa ; 0x01ab Execute Matrix,Length 14aa ; -------------------------------------------------------------------------------------- 14aa MACRO_Execute_Matrix,Length: 14aa 14aa dispatch_brk_class 8 ; Flow J cc=True 0x14b1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 14aa seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14b1 0x14b1 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 14ab 14ab seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14b4 seq_br_type 1 Branch True seq_branch_adr 14b4 0x14b4 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 14ac 14ac fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 14ad 14ad fiu_mem_start a start_continue_if_false; Flow J cc=False 0x14af seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 14af 0x14af seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 14ae 14ae fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 14af 14af fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 14b0 14b0 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 14b1 14b1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1c DEC_A 14b2 14b2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14b4 seq_br_type 1 Branch True seq_branch_adr 14b4 0x14b4 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 14b3 14b3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x14ad fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 14ad 0x14ad typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 14b4 14b4 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE 14b5 14b5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 14b6 ; -------------------------------------------------------------------------------------- 14b6 ; Comes from: 14b6 ; 14d2 C from color MACRO_Execute_Matrix,Last 14b6 ; 14d4 C from color MACRO_Execute_Matrix,Bounds 14b6 ; 14d8 C from color MACRO_Execute_Matrix,Reverse_Bounds 14b6 ; -------------------------------------------------------------------------------------- 14b6 14b6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14c7 seq_br_type 1 Branch True seq_branch_adr 14c7 0x14c7 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 14b7 14b7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x14c9 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 14c9 0x14c9 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 14b8 14b8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x14bc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 14bc 0x14bc seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 14b9 14b9 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 5 14ba 14ba fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14bb 14bb ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x14c0 seq_br_type 8 Return True seq_branch_adr 14c0 0x14c0 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 14bc 14bc fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 14bd 14bd fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 5 14be 14be fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14bf 14bf ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 14c0 0x14c0 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 14c0 14c0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14c2 seq_br_type 1 Branch True seq_branch_adr 14c2 0x14c2 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 14c1 14c1 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x14c3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 14c3 0x14c3 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 14c2 14c2 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2c VR12:0c val_frame 12 14c3 ; -------------------------------------------------------------------------------------- 14c3 ; Comes from: 14c3 ; 14fe C from color 0x0aa2 14c3 ; 1503 C from color 0x0aa2 14c3 ; -------------------------------------------------------------------------------------- 14c3 14c3 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x14c5 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 14c5 0x14c5 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 14c4 14c4 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 38 GP07 val_c_source 0 FIU_BUS 14c5 14c5 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 14c6 14c6 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 38 GP07 val_c_source 0 FIU_BUS 14c7 14c7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1c DEC_A 14c8 14c8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x14b8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 14b8 0x14b8 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 14c9 14c9 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE 14ca 14ca ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 14cb 14cb fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x14d0 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 14d0 0x14d0 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14cc 14cc fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 14cd 14cd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14cf seq_br_type 1 Branch True seq_branch_adr 14cf 0x14cf seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 14ce 14ce fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 38 GP07 val_c_source 0 FIU_BUS 14cf 14cf fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 38 GP07 val_c_source 0 FIU_BUS 14d0 14d0 ioc_tvbs 1 typ+fiu; Flow R seq_br_type a Unconditional Return val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 14d1 14d1 <halt> ; Flow R 14d2 ; -------------------------------------------------------------------------------------- 14d2 ; 0x01ac Execute Matrix,Last 14d2 ; -------------------------------------------------------------------------------------- 14d2 MACRO_Execute_Matrix,Last: 14d2 14d2 dispatch_brk_class 8 ; Flow C 0x14b6 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 14d2 seq_br_type 7 Unconditional Call seq_branch_adr 14b6 0x14b6 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 14d3 14d3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14d4 ; -------------------------------------------------------------------------------------- 14d4 ; 0x01aa Execute Matrix,Bounds 14d4 ; -------------------------------------------------------------------------------------- 14d4 MACRO_Execute_Matrix,Bounds: 14d4 14d4 dispatch_brk_class 8 ; Flow C 0x14b6 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 14d4 seq_br_type 7 Unconditional Call seq_branch_adr 14b6 0x14b6 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 14d5 14d5 seq_random 02 ? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14d6 14d6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 14d7 14d7 <halt> ; Flow R 14d8 ; -------------------------------------------------------------------------------------- 14d8 ; 0x01a9 Execute Matrix,Reverse_Bounds 14d8 ; -------------------------------------------------------------------------------------- 14d8 MACRO_Execute_Matrix,Reverse_Bounds: 14d8 14d8 dispatch_brk_class 8 ; Flow C 0x14b6 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 14d8 seq_br_type 7 Unconditional Call seq_branch_adr 14b6 0x14b6 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A 14d9 14d9 seq_random 02 ? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14da 14da fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 14db 14db <halt> ; Flow R 14dc ; -------------------------------------------------------------------------------------- 14dc ; 0x01a8 Execute Matrix,Element_Type 14dc ; -------------------------------------------------------------------------------------- 14dc MACRO_Execute_Matrix,Element_Type: 14dc 14dc dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 14dc fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 14dd 14dd typ_a_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_rand b CARRY IN = Q BIT FROM VAL 14de 14de fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 14df 14df <halt> ; Flow R 14e0 ; -------------------------------------------------------------------------------------- 14e0 ; 0x019d Execute Matrix,In_Type 14e0 ; -------------------------------------------------------------------------------------- 14e0 MACRO_Execute_Matrix,In_Type: 14e0 14e0 dispatch_brk_class 8 ; Flow C cc=False 0x1521 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 14e0 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1521 0x1521 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 14e1 14e1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x14ec fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 14ec 0x14ec seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 14e2 14e2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 14e3 14e3 <halt> ; Flow R 14e4 ; -------------------------------------------------------------------------------------- 14e4 ; 0x019c Execute Matrix,Not_In_Type 14e4 ; -------------------------------------------------------------------------------------- 14e4 MACRO_Execute_Matrix,Not_In_Type: 14e4 14e4 dispatch_brk_class 8 ; Flow C cc=False 0x1521 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 14e4 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1521 0x1521 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 14e5 14e5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x14ec fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 14ec 0x14ec seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 14e6 14e6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 14e7 14e7 <halt> ; Flow R 14e8 ; -------------------------------------------------------------------------------------- 14e8 ; 0x019b Execute Matrix,Check_In_Type 14e8 ; -------------------------------------------------------------------------------------- 14e8 MACRO_Execute_Matrix,Check_In_Type: 14e8 14e8 dispatch_brk_class 8 ; Flow C cc=False 0x1521 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 14e8 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1521 0x1521 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 14e9 14e9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x14ec fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 14ec 0x14ec seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 14ea 14ea fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 14eb 0x14eb seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 31 VR02:11 val_frame 2 14eb 14eb seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 seq_en_micro 0 14ec ; -------------------------------------------------------------------------------------- 14ec ; Comes from: 14ec ; 14e1 C from color 0x0a7a 14ec ; 14e5 C from color 0x0a8e 14ec ; -------------------------------------------------------------------------------------- 14ec 14ec fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1513 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1513 0x1513 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 14 ZEROS val_b_adr 31 VR02:11 val_frame 2 14ed 14ed fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x14fb fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 14fb 0x14fb typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 14ee 14ee <default> 14ef 14ef fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 14f0 14f0 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14fa seq_br_type 1 Branch True seq_branch_adr 14fa 0x14fa seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 39 GP06 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 39 GP06 14f1 14f1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x14f5 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 14f5 0x14f5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 14f2 14f2 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 14f3 14f3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 14f4 14f4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x14fa seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14fa 0x14fa seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 14f5 14f5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14fa seq_br_type 1 Branch True seq_branch_adr 14fa 0x14fa seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 14f6 14f6 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 14f7 0x14f7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 14f7 14f7 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 14f8 14f8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 14f9 14f9 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 14fa 0x14fa seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 14fa 14fa seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 14fb 14fb fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1507 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1507 0x1507 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 14fc 14fc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14fa seq_br_type 1 Branch True seq_branch_adr 14fa 0x14fa seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 39 GP06 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 39 GP06 14fd 14fd seq_br_type 1 Branch True; Flow J cc=True 0x1501 seq_branch_adr 1501 0x1501 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 14fe 14fe fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x14c3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 14c3 0x14c3 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 14ff 14ff fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 07 GP07 1500 1500 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x14fa seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14fa 0x14fa seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 1501 1501 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x14fa seq_br_type 1 Branch True seq_branch_adr 14fa 0x14fa seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1502 1502 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1503 0x1503 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 1503 1503 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x14c3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 14c3 0x14c3 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2c VR12:0c val_frame 12 1504 1504 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 1505 1505 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1506 0x1506 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1506 1506 seq_br_type a Unconditional Return; Flow R val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 1507 ; -------------------------------------------------------------------------------------- 1507 ; Comes from: 1507 ; 14fb C from color 0x0aa2 1507 ; 1518 C from color 0x0aa2 1507 ; -------------------------------------------------------------------------------------- 1507 1507 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x150d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 150d 0x150d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1508 1508 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 1509 1509 fiu_fill_mode_src 0 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_frame 2 150a 150a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1510 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1510 0x1510 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 150b 150b fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 150c 150c fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 150d 150d fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 150e 150e fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 150f 150f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x150a fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 150a 0x150a typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_frame 2 1510 1510 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1511 1511 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 1512 1512 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 1513 1513 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1518 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1518 0x1518 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1514 1514 <default> 1515 1515 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1516 1516 fiu_load_var 1 hold_var; Flow J cc=True 0x14fa fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14fa 0x14fa seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 typ_c_adr 39 GP06 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_c_adr 39 GP06 1517 1517 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x151a seq_br_type 3 Unconditional Branch seq_branch_adr 151a 0x151a typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1518 1518 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1507 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1507 0x1507 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1519 1519 fiu_load_var 1 hold_var; Flow J cc=True 0x14fa fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 14fa 0x14fa seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 typ_c_adr 39 GP06 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_c_adr 39 GP06 151a 151a fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 151b 151b fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 151c 151c seq_br_type 0 Branch False; Flow J cc=False 0x14fa seq_branch_adr 14fa 0x14fa seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 151d 151d fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 151e 151e ioc_tvbs 1 typ+fiu val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 151f 151f seq_br_type 0 Branch False; Flow J cc=False 0x14fa seq_branch_adr 14fa 0x14fa seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1520 1520 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x14fa seq_br_type 9 Return False seq_branch_adr 14fa 0x14fa seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 1521 ; -------------------------------------------------------------------------------------- 1521 ; Comes from: 1521 ; 14e0 C False from color 0x0a7a 1521 ; 14e4 C False from color 0x0a8e 1521 ; 14e8 C False from color 0x0aa2 1521 ; 1582 C False from color 0x0000 1521 ; 15f8 C False from color 0x0000 1521 ; -------------------------------------------------------------------------------------- 1521 1521 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1522 1522 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1523 1523 seq_br_type a Unconditional Return; Flow R 1524 ; -------------------------------------------------------------------------------------- 1524 ; 0x01a4 Execute Matrix,Structure_Write 1524 ; -------------------------------------------------------------------------------------- 1524 MACRO_Execute_Matrix,Structure_Write: 1524 1524 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1524 dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 14 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1525 1525 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e3e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e3e 0x1e3e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1526 ; -------------------------------------------------------------------------------------- 1526 ; 0x01a6 Execute Matrix,Field_Write 1526 ; -------------------------------------------------------------------------------------- 1526 MACRO_Execute_Matrix,Field_Write: 1526 1526 dispatch_brk_class 2 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1526 dispatch_uses_tos 1 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 8 type_var seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 1527 1527 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1535 fiu_mem_start a start_continue_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1535 0x1535 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1528 1528 ioc_fiubs 1 val ; Flow J cc=False 0x152f ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 152f 0x152f seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1529 1529 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 152a 152a fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 152b 152b seq_random 02 ? typ_csa_cntl 3 POP_CSA 152c 152c fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1532 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 152d 152d fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d78 0x1d78 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 152e 152e seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 152f 152f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1530 1530 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1531 1531 seq_br_type 3 Unconditional Branch; Flow J 0x152a seq_branch_adr 152a 0x152a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1532 1532 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1533 1533 seq_en_micro 0 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1534 1534 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d78 0x1d78 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1535 1535 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1561 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1561 0x1561 typ_b_adr 1e TOP - 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1536 1536 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1532 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1532 0x1532 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1537 1537 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d78 0x1d78 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1538 1538 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 1539 1539 <halt> ; Flow R 153a ; -------------------------------------------------------------------------------------- 153a ; 0x01a5 Execute Matrix,Field_Reference 153a ; -------------------------------------------------------------------------------------- 153a MACRO_Execute_Matrix,Field_Reference: 153a 153a dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 153a dispatch_uses_tos 1 fiu_mem_start 4 continue seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 153b 153b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1547 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1547 0x1547 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 153c 153c fiu_mem_start 2 start-rd; Flow J cc=False 0x1541 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1541 0x1541 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 153d 153d fiu_mem_start 4 continue; Flow C cc=False 0x32a2 seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 153e 153e fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 153f 153f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1544 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1544 0x1544 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1540 1540 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x32a2 ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1541 1541 seq_br_type 4 Call False; Flow C cc=False 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1542 1542 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1543 1543 fiu_mem_start 4 continue; Flow J 0x153e seq_br_type 3 Unconditional Branch seq_branch_adr 153e 0x153e seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1544 1544 ioc_tvbs 2 fiu+val; Flow C cc=False 0x32a2 seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1545 1545 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1546 0x1546 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1546 1546 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1547 1547 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1561 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1561 0x1561 typ_a_adr 1e TOP - 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1548 1548 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1544 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1544 0x1544 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1549 1549 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x32a2 ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 04 GP04 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 154a ; -------------------------------------------------------------------------------------- 154a ; 0x01a7 Execute Matrix,Field_Read 154a ; -------------------------------------------------------------------------------------- 154a MACRO_Execute_Matrix,Field_Read: 154a 154a dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 154a dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 154b 154b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x155c fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 155c 0x155c typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 154c 154c fiu_mem_start 2 start-rd; Flow J cc=False 0x1555 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1555 0x1555 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 154d 154d fiu_mem_start 4 continue; Flow C cc=False 0x32a2 seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 154e 154e fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 154f 154f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x155e fiu_load_tar 1 hold_tar fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 155e 0x155e seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1550 1550 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x32a2 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1551 1551 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1553 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1553 0x1553 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 1552 1552 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x1558 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1558 0x1558 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1553 1553 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1554 1554 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x1558 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1558 0x1558 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1555 1555 seq_br_type 4 Call False; Flow C cc=False 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1556 1556 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1557 1557 fiu_mem_start 4 continue; Flow J 0x154e seq_br_type 3 Unconditional Branch seq_branch_adr 154e 0x154e seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1558 1558 seq_br_type 0 Branch False; Flow J cc=False 0x155b seq_branch_adr 155b 0x155b seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 1559 1559 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 155a 0x155a seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 155a 155a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 155b 155b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 155c 155c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1561 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1561 0x1561 typ_a_adr 1e TOP - 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 155d 155d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x1550 fiu_load_tar 1 hold_tar fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1550 0x1550 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 155e 155e ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 155f 155f seq_br_type 2 Push (branch address); Flow J 0x1560 seq_branch_adr 1551 0x1551 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1560 1560 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x32a2 fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 32a2 0x32a2 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1561 ; -------------------------------------------------------------------------------------- 1561 ; Comes from: 1561 ; 1535 C from color MACRO_Execute_Matrix,Field_Write 1561 ; 1547 C from color 0x0000 1561 ; 155c C from color 0x0000 1561 ; -------------------------------------------------------------------------------------- 1561 1561 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1572 ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1572 0x1572 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 1562 1562 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 1563 1563 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1564 1564 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x156d ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 156d 0x156d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR 1565 1565 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1566 1566 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a2 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 1567 1567 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x156f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 156f 0x156f seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 1568 1568 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_b_adr 05 GP05 val_rand c START_MULTIPLY 1569 1569 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 156a 156a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 156b 156b fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 156c 156c fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 21 TR05:01 typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 156d 156d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a2 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 156e 156e fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x1568 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1568 0x1568 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 156f 156f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1570 1570 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1571 1571 fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var seq_br_type a Unconditional Return typ_b_adr 21 TR05:01 typ_frame 5 1572 1572 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1573 1573 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 1574 1574 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x157d fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 157d 0x157d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1575 1575 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 1576 1576 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a2 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 7 1577 1577 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1578 1578 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x157a fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 157a 0x157a seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1579 1579 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1581 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1581 0x1581 seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 157a 157a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 157b 157b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 157c 157c fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1581 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1581 0x1581 seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 157d 157d fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 157e 157e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a2 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 4 157f 157f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x157a fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 157a 0x157a seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1580 1580 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1581 1581 fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_b_adr 21 TR05:01 typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1582 ; -------------------------------------------------------------------------------------- 1582 ; 0x019f Execute Matrix,Convert 1582 ; -------------------------------------------------------------------------------------- 1582 MACRO_Execute_Matrix,Convert: 1582 1582 dispatch_brk_class 4 ; Flow C cc=False 0x1521 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1582 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1521 0x1521 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1583 1583 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1584 1584 seq_b_timing 1 Latch Condition; Flow J cc=True 0x15a9 seq_br_type 1 Branch True seq_branch_adr 15a9 0x15a9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1585 1585 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1594 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1594 0x1594 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1586 1586 ioc_fiubs 1 val typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 1587 1587 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1588 1588 ioc_fiubs 2 typ seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1589 1589 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x158b fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 158b 0x158b typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 158a 158a seq_br_type 1 Branch True; Flow J cc=True 0x158d seq_branch_adr 158d 0x158d seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 158b 158b ioc_fiubs 2 typ ; Flow C cc=False 0x32a2 seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 158c 158c seq_br_type 4 Call False; Flow C cc=False 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 06 GP06 typ_alu_func 0 PASS_A val_a_adr 02 GP02 val_alu_func 0 PASS_A 158d 158d fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 158e 158e fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 158f 158f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1591 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1591 0x1591 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1590 1590 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32cc seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1591 1591 seq_br_type 4 Call False; Flow C cc=False 0x32cc seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 36 GP09 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 1592 1592 ioc_fiubs 1 val ; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP 1593 1593 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 07 GP07 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1594 1594 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1599 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1599 0x1599 typ_a_adr 10 TOP typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1595 1595 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 2 typ seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 4 1596 1596 ioc_fiubs 1 val ; Flow J cc=True 0x158b seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 158b 0x158b typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 1597 1597 seq_br_type 1 Branch True; Flow J cc=True 0x158d seq_branch_adr 158d 0x158d seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 1598 1598 seq_br_type 3 Unconditional Branch; Flow J 0x158b seq_branch_adr 158b 0x158b 1599 ; -------------------------------------------------------------------------------------- 1599 ; Comes from: 1599 ; 1594 C from color 0x0000 1599 ; 15af C from color 0x0000 1599 ; 1605 C from color 0x0000 1599 ; -------------------------------------------------------------------------------------- 1599 1599 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x15a1 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15a1 0x15a1 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 159a 159a fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 5 159b 159b fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 159c 159c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x15a4 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15a4 0x15a4 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 159d 159d fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 2 159e 159e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x15a6 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15a6 0x15a6 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 159f 159f fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 15a0 15a0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 15a1 15a1 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 15a2 15a2 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 5 15a3 15a3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x159c fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 159c 0x159c typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 15a4 15a4 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 15a5 15a5 fiu_fill_mode_src 0 ; Flow J 0x159e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 159e 0x159e val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 2 15a6 15a6 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 15a7 15a7 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 15a8 15a8 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 15a9 15a9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x15af fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15af 0x15af typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 15aa 15aa fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR 15ab 15ab fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 4 continue fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 15ac 15ac fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 38 GP07 val_c_source 0 FIU_BUS 15ad 15ad fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x15b8 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 15b8 0x15b8 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 15ae 15ae seq_br_type 3 Unconditional Branch; Flow J 0x15b1 seq_branch_adr 15b1 0x15b1 15af 15af fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1599 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1599 0x1599 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 15b0 15b0 fiu_load_var 1 hold_var; Flow J cc=True 0x15b8 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 15b8 0x15b8 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 15b1 15b1 fiu_load_var 1 hold_var; Flow J cc=True 0x15b7 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 15b7 0x15b7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 0 PASS_A val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 15b2 15b2 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 04 GP04 val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 15b3 15b3 ioc_tvbs 1 typ+fiu val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 15b4 15b4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 15b5 15b5 fiu_mem_start 2 start-rd; Flow J cc=True 0x15e3 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 15e3 0x15e3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 15b6 15b6 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 15b7 15b7 fiu_mem_start 2 start-rd; Flow J 0x15e3 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 15e3 0x15e3 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 13 ONES val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 15b8 15b8 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 15b9 15b9 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 04 GP04 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 15ba 15ba seq_br_type 4 Call False; Flow C cc=False 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 15bb 15bb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 15bc 15bc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x15b7 seq_br_type 1 Branch True seq_branch_adr 15b7 0x15b7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 06 GP06 15bd 15bd seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 15be 15be fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 06 GP06 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 15bf 15bf ioc_tvbs 1 typ+fiu; Flow J cc=True 0x15ed seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15ed 0x15ed val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 15c0 15c0 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 15c1 15c1 seq_br_type 4 Call False; Flow C cc=False 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_c_adr 36 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 15c2 15c2 ioc_fiubs 1 val ; Flow C cc=True 0x32a9 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 15c3 15c3 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 15c4 15c4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x15c6 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15c6 0x15c6 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 15c5 15c5 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32cc seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 15c6 15c6 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_b_adr 05 GP05 15c7 15c7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32cc fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 15c8 15c8 fiu_fill_mode_src 0 ; Flow J cc=False 0x15d6 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15d6 0x15d6 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 15c9 15c9 fiu_fill_mode_src 0 ; Flow C cc=False 0x32dc fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_frame 6 15ca 15ca ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 15cb 15cb fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 15cc 15cc fiu_fill_mode_src 0 ; Flow J cc=False 0x15d8 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15d8 0x15d8 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 07 GP07 15cd 15cd fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15ce 15ce ioc_load_wdr 0 ; Flow C cc=False 0x32dc ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_frame 6 15cf 15cf fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val typ_b_adr 06 GP06 val_b_adr 06 GP06 15d0 15d0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA 15d1 15d1 fiu_fill_mode_src 0 ; Flow J cc=False 0x15da fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15da 0x15da seq_cond_sel 65 CROSS_WORD_FIELD~ 15d2 15d2 fiu_fill_mode_src 0 ; Flow J cc=False 0x15dc fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15dc 0x15dc seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15d3 15d3 ioc_load_wdr 0 ; Flow C cc=False 0x32cc ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 15d4 15d4 seq_br_type 7 Unconditional Call; Flow C 0x1f1e seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 15d5 15d5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 07 GP07 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 15d6 15d6 fiu_fill_mode_src 0 ; Flow C cc=False 0x32dc fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_frame 6 15d7 15d7 fiu_fill_mode_src 0 ; Flow J 0x15ca fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 15ca 0x15ca typ_mar_cntl 6 INCREMENT_MAR 15d8 15d8 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15d9 15d9 fiu_fill_mode_src 0 ; Flow J 0x15ce fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 15ce 0x15ce typ_mar_cntl 6 INCREMENT_MAR 15da 15da fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15db 15db fiu_fill_mode_src 0 ; Flow J cc=True 0x15d3 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 15d3 0x15d3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR 15dc 15dc ioc_load_wdr 0 ; Flow C cc=False 0x32cc ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2c VR08:0c val_frame 8 15dd 15dd fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val typ_b_adr 03 GP03 val_b_adr 03 GP03 15de 15de fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 15df 15df fiu_fill_mode_src 0 ; Flow J cc=False 0x15e1 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 15e1 0x15e1 seq_cond_sel 65 CROSS_WORD_FIELD~ 15e0 15e0 fiu_fill_mode_src 0 ; Flow J 0x15d3 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 15d3 0x15d3 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15e1 15e1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 15e2 15e2 fiu_fill_mode_src 0 ; Flow J 0x15d3 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 15d3 0x15d3 typ_mar_cntl 6 INCREMENT_MAR 15e3 15e3 seq_b_timing 1 Latch Condition; Flow J cc=True 0x15eb seq_br_type 1 Branch True seq_branch_adr 15eb 0x15eb 15e4 15e4 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 15e5 15e5 typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 5 15e6 15e6 fiu_mem_start 2 start-rd; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 21 VR02:01 val_frame 2 15e7 15e7 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 15e8 15e8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32dc fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 6 15e9 15e9 ioc_fiubs 2 typ ; Flow J 0x15ea seq_br_type 2 Push (branch address) seq_branch_adr 15c4 0x15c4 typ_a_adr 03 GP03 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 15ea 15ea seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32dc seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_frame 6 15eb 15eb fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 15ec 15ec fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x15f3 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 15f3 0x15f3 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 2c VR08:0c val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 15ed 15ed fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 15ee 15ee ioc_fiubs 2 typ ; Flow C cc=False 0x32a2 seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 05 GP05 typ_c_adr 36 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 15ef 15ef seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 15f0 15f0 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x15f3 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15f3 0x15f3 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 val_m_b_src 2 Bits 32…47 15f1 15f1 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 15f2 15f2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 15f3 15f3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x15f5 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 15f5 0x15f5 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 08 Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 15f4 15f4 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32cc seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 15f5 15f5 ioc_fiubs 1 val ; Flow C cc=False 0x32cc seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP 15f6 15f6 ioc_fiubs 1 val ; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 15f7 15f7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 15f8 ; -------------------------------------------------------------------------------------- 15f8 ; 0x019e Execute Matrix,Convert_To_Formal 15f8 ; -------------------------------------------------------------------------------------- 15f8 MACRO_Execute_Matrix,Convert_To_Formal: 15f8 15f8 dispatch_brk_class 4 ; Flow C cc=False 0x1521 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 15f8 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1521 0x1521 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_rand 8 SPARE_0x08 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 15f9 15f9 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 15fa 15fa seq_b_timing 1 Latch Condition; Flow J cc=True 0x15a9 seq_br_type 1 Branch True seq_branch_adr 15a9 0x15a9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 15fb 15fb fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1605 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1605 0x1605 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 15fc 15fc ioc_fiubs 1 val typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 15fd 15fd fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 15fe 15fe seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 15ff 15ff fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1600 1600 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 1601 1601 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1602 1602 fiu_tivi_src 2 tar_fiu; Flow J cc=False 0x158d ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 158d 0x158d seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1603 1603 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 1604 1604 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1612 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1612 0x1612 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1605 1605 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1599 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1599 0x1599 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1606 1606 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 1607 1607 ioc_fiubs 1 val typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 1608 1608 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 1609 1609 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 160a 160a fiu_tivi_src 2 tar_fiu; Flow J cc=False 0x158d ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 158d 0x158d seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 160b 160b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_frame 7 160c 160c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x160f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 160f 0x160f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 160d 160d fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2c VR12:0c val_frame 12 160e 160e fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1612 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1612 0x1612 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_source 0 FIU_BUS 160f 160f fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1610 1610 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2c VR12:0c val_frame 12 1611 1611 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1612 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1612 0x1612 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1612 1612 <default> 1613 1613 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1614 1614 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1615 1615 seq_br_type 3 Unconditional Branch; Flow J 0x158d seq_branch_adr 158d 0x158d 1616 ; -------------------------------------------------------------------------------------- 1616 ; 0x01a3 Execute Matrix,Subarray 1616 ; -------------------------------------------------------------------------------------- 1616 MACRO_Execute_Matrix,Subarray: 1616 1616 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1616 dispatch_uses_tos 1 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP 1617 1617 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32d9 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 14 typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1618 1618 ioc_fiubs 1 val ; Flow J cc=False 0x161c ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 161c 0x161c seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1619 1619 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 161a 161a ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 161b 161b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2d TR08:0d typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 161c 161c seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 161d 161d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 161e 161e seq_br_type 3 Unconditional Branch; Flow J 0x161a seq_branch_adr 161a 0x161a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 161f 161f <halt> ; Flow R 1620 ; -------------------------------------------------------------------------------------- 1620 ; 0x2c00-0x2cff Execute Variant_Record,Field_Read,Fixed,Direct,fieldnum 1620 ; -------------------------------------------------------------------------------------- 1620 MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum: 1620 1620 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1620 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 1621 1621 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1626 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1626 0x1626 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1622 1622 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1624 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1624 0x1624 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1623 1623 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x1628 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1628 0x1628 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3a GP05 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1624 1624 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1625 1625 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x1628 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1628 0x1628 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3a GP05 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1626 1626 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 1627 0x1627 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS 1627 1627 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1628 1628 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1629 0x1629 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 05 GP05 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1629 1629 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 162a ; -------------------------------------------------------------------------------------- 162a ; 0x2e00-0x2eff Execute Variant_Record,Field_Read,Variant,Direct,fieldnum 162a ; -------------------------------------------------------------------------------------- 162a MACRO_Execute_Variant_Record,Field_Read,Variant,Direct,fieldnum: 162a 162a dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 162a dispatch_uses_tos 1 fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 77 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 2e VR04:0e val_frame 4 162b 162b fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1634 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1634 0x1634 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 162c 162c fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame a val_c_adr 3d GP02 val_c_source 0 FIU_BUS 162d 162d fiu_len_fill_lit 48 zero-fill 0x8; Flow J cc=False 0x1637 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1637 0x1637 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 162e 162e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1632 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1632 0x1632 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 162f 162f fiu_fill_mode_src 0 ; Flow R cc=True fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1630 0x1630 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 1630 1630 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 36 VR05:16 val_frame 5 1631 1631 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 1632 1632 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1633 1633 fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x1630 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1630 0x1630 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 1634 1634 fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 4 continue fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame a typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1635 1635 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1636 1636 fiu_len_fill_lit 48 zero-fill 0x8; Flow J cc=True 0x162e fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 162e 0x162e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 1637 1637 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x1640 seq_br_type 0 Branch False seq_branch_adr 1640 0x1640 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_c_lit 2 typ_frame 18 1638 1638 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x163c fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 163c 0x163c seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1639 1639 fiu_fill_mode_src 0 ; Flow J cc=True 0x1630 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1630 0x1630 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 163a 163a fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 163b 0x163b seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 05 GP05 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 163b 163b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 163c 163c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 163d 163d fiu_fill_mode_src 0 ; Flow J cc=True 0x1630 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1630 0x1630 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 163e 163e fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 163f 0x163f seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 05 GP05 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 163f 163f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1640 1640 fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 1641 0x1641 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 1641 1641 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_lit 2 typ_frame a typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1642 1642 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1630 seq_br_type 1 Branch True seq_branch_adr 1630 0x1630 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 1643 1643 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1644 0x1644 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 1644 1644 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x164c fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 164c 0x164c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1645 1645 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS 1646 1646 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1653 fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1653 0x1653 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 7 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1647 1647 ioc_fiubs 1 val ; Flow C 0x1f1e ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 03 GP03 1648 1648 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1649 1649 ioc_tvbs 2 fiu+val; Flow J 0x164a seq_br_type 2 Push (branch address) seq_branch_adr 1648 0x1648 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 164a 164a ioc_fiubs 1 val ; Flow J cc=False 0x1f1e ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1f1e 0x1f1e seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 164b 164b seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 164c 164c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1646 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1646 0x1646 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS 164d 164d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x332e fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3c GP03 val_c_source 0 FIU_BUS 164e 164e fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 164f 164f fiu_len_fill_lit 7d zero-fill 0x3d fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1650 1650 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x1652 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1652 0x1652 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 1651 1651 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1652 1652 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x1647 fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1647 0x1647 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 1653 1653 fiu_tivi_src c mar_0xc; Flow J cc=True 0x1649 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 1649 0x1649 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1654 1654 ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1655 1655 seq_br_type 7 Unconditional Call; Flow C 0x32cc seq_branch_adr 32cc 0x32cc seq_en_micro 0 1656 ; -------------------------------------------------------------------------------------- 1656 ; 0x2800-0x28ff Execute Variant_Record,Field_Write,Fixed,Direct,fieldnum 1656 ; -------------------------------------------------------------------------------------- 1656 MACRO_Execute_Variant_Record,Field_Write,Fixed,Direct,fieldnum: 1656 1656 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1656 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 1657 1657 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d78 0x1d78 seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1658 ; -------------------------------------------------------------------------------------- 1658 ; 0x2900-0x29ff Execute Variant_Record,Field_Write,Fixed,Indirect,fieldnum 1658 ; -------------------------------------------------------------------------------------- 1658 MACRO_Execute_Variant_Record,Field_Write,Fixed,Indirect,fieldnum: 1658 1658 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1658 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 1659 1659 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 165a 165a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x165c seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 165c 0x165c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 165b 165b fiu_fill_mode_src 0 ; Flow J 0x165e fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 165e 0x165e typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 165c 165c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 165d 165d fiu_fill_mode_src 0 ; Flow J 0x165e fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 165e 0x165e typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 165e 165e fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 1d78 0x1d78 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 165f 165f seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de seq_en_micro 0 1660 ; -------------------------------------------------------------------------------------- 1660 ; 0x2a00-0x2aff Execute Variant_Record,Field_Write,Variant,Direct,fieldnum 1660 ; -------------------------------------------------------------------------------------- 1660 MACRO_Execute_Variant_Record,Field_Write,Variant,Direct,fieldnum: 1660 1660 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1660 dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 1661 1661 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 1662 1662 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1667 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1667 0x1667 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3f GP00 1663 1663 fiu_len_fill_lit 47 zero-fill 0x7 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1664 1664 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1d78 0x1d78 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1665 1665 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1666 1666 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 1667 1667 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1668 1668 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x1664 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1664 0x1664 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1669 1669 <halt> ; Flow R 166a ; -------------------------------------------------------------------------------------- 166a ; 0x2b00-0x2bff Execute Variant_Record,Field_Write,Variant,Indirect,fieldnum 166a ; -------------------------------------------------------------------------------------- 166a MACRO_Execute_Variant_Record,Field_Write,Variant,Indirect,fieldnum: 166a 166a dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 166a dispatch_uses_tos 1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 166b 166b fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 166c 166c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x166e ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 166e 0x166e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 166d 166d fiu_fill_mode_src 0 ; Flow J 0x1670 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1670 0x1670 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 166e 166e fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 166f 166f fiu_fill_mode_src 0 ; Flow J 0x1670 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1670 0x1670 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1670 1670 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1673 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1673 0x1673 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1671 1671 fiu_fill_mode_src 0 ; Flow J cc=True 0x1676 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1676 0x1676 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A 1672 1672 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 1673 1673 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1674 1674 fiu_fill_mode_src 0 ; Flow J cc=True 0x1676 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1676 0x1676 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A 1675 1675 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 1676 1676 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1d78 0x1d78 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1677 1677 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 02 ? val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1678 1678 seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 1679 1679 <halt> ; Flow R 167a ; -------------------------------------------------------------------------------------- 167a ; 0x2400-0x24ff Execute Variant_Record,Field_Reference,Fixed,Direct,fieldnum 167a ; -------------------------------------------------------------------------------------- 167a MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum: 167a 167a dispatch_brk_class 8 ; Flow C cc=True 0x32de dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 167a dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 167b 167b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 3c Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 167c ; -------------------------------------------------------------------------------------- 167c ; 0x2500-0x25ff Execute Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 167c ; -------------------------------------------------------------------------------------- 167c MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum: 167c 167c dispatch_brk_class 8 ; Flow C cc=True 0x32de dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 167c dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 167d 167d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 167e 167e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1680 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1680 0x1680 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 167f 167f fiu_fill_mode_src 0 ; Flow J 0x1682 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1682 0x1682 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1680 1680 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1681 1681 fiu_fill_mode_src 0 ; Flow J 0x1682 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1682 0x1682 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1682 1682 fiu_load_var 1 hold_var; Flow C cc=True 0x32de fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 04 GP04 val_b_adr 10 TOP 1683 1683 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1684 0x1684 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1684 1684 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x332e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 seq_random 02 ? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR02:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 1685 1685 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 1686 1686 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x169e ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 169e 0x169e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 1687 1687 <halt> ; Flow R 1688 ; -------------------------------------------------------------------------------------- 1688 ; 0x2600-0x26ff Execute Variant_Record,Field_Reference,Variant,Direct,fieldnum 1688 ; -------------------------------------------------------------------------------------- 1688 MACRO_Execute_Variant_Record,Field_Reference,Variant,Direct,fieldnum: 1688 1688 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1688 dispatch_uses_tos 1 fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_var 1 hold_var fiu_offs_lit 77 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand a PASS_B_HIGH val_b_adr 2e VR04:0e val_frame 4 1689 1689 fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 168a 168a fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x168c fiu_mem_start a start_continue_if_false fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 168c 0x168c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 168b 168b fiu_len_fill_lit 48 zero-fill 0x8; Flow J 0x1640 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1640 0x1640 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 168c 168c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 168d 168d fiu_len_fill_lit 48 zero-fill 0x8; Flow J 0x1640 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1640 0x1640 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 168e ; -------------------------------------------------------------------------------------- 168e ; 0x2700-0x27ff Execute Variant_Record,Field_Reference,Variant,Indirect,fieldnum 168e ; -------------------------------------------------------------------------------------- 168e MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum: 168e 168e dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 168e dispatch_uses_tos 1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_b_adr 2e VR04:0e val_frame 4 168f 168f fiu_load_mdr 1 hold_mdr; Flow C 0x210 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 08 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1690 1690 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x1692 fiu_mem_start a start_continue_if_false fiu_offs_lit 78 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1692 0x1692 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1691 1691 fiu_fill_mode_src 0 ; Flow J 0x1694 fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1694 0x1694 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1692 1692 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1693 1693 fiu_fill_mode_src 0 ; Flow J 0x1694 fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1694 0x1694 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1694 1694 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1697 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1697 0x1697 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1695 1695 fiu_len_fill_lit 48 zero-fill 0x8; Flow J cc=True 0x169a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 169a 0x169a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 1696 1696 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 1697 1697 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1698 1698 fiu_len_fill_lit 48 zero-fill 0x8; Flow J cc=True 0x169a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 169a 0x169a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 1699 1699 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 169a 169a fiu_mem_start 2 start-rd; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 169b 0x169b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 169b 169b fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 169c 169c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x16ad seq_br_type 1 Branch True seq_branch_adr 16ad 0x16ad seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 169d 169d fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 169e 0x169e seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 169e 169e fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 169f 169f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x16a1 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16a1 0x16a1 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 6 CONTROL TOP typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 16a0 16a0 fiu_fill_mode_src 0 ; Flow J 0x16a3 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16a3 0x16a3 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3c GP03 val_c_source 0 FIU_BUS 16a1 16a1 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16a2 16a2 fiu_fill_mode_src 0 ; Flow J 0x16a3 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16a3 0x16a3 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3c GP03 val_c_source 0 FIU_BUS 16a3 16a3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS 16a4 16a4 fiu_load_tar 1 hold_tar; Flow J 0x16a5 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 16ac 0x16ac seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 16a5 16a5 ioc_tvbs 2 fiu+val; Flow J cc=True 0x1f1e seq_br_type 1 Branch True seq_branch_adr 1f1e 0x1f1e seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 16a6 16a6 seq_br_type 1 Branch True; Flow J cc=True 0x16a9 seq_branch_adr 16a9 0x16a9 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 16a7 16a7 ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 16a8 16a8 seq_br_type 7 Unconditional Call; Flow C 0x32cc seq_branch_adr 32cc 0x32cc 16a9 16a9 ioc_tvbs 2 fiu+val; Flow J 0x16aa seq_br_type 2 Push (branch address) seq_branch_adr 16ac 0x16ac seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 16aa 16aa ioc_fiubs 1 val ; Flow J cc=False 0x1f1e ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1f1e 0x1f1e seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 16ab 16ab seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 16ac 16ac fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 16ad 16ad seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 36 VR05:16 val_frame 5 16ae 16ae seq_br_type 7 Unconditional Call; Flow C 0x32a5 seq_branch_adr 32a5 0x32a5 seq_en_micro 0 16af ; -------------------------------------------------------------------------------------- 16af ; Comes from: 16af ; 16b4 C from color MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum 16af ; 16c0 C from color MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum 16af ; 16c6 C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 16af ; -------------------------------------------------------------------------------------- 16af 16af fiu_mem_start 2 start-rd; Flow C cc=True 0x32de ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 16b0 16b0 fiu_len_fill_lit 49 zero-fill 0x9 fiu_load_var 1 hold_var fiu_offs_lit 4f fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 16b1 16b1 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 16b2 0x16b2 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 val_rand 6 IMMEDIATE_OP 16b2 16b2 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 16b3 16b3 <halt> ; Flow R 16b4 ; -------------------------------------------------------------------------------------- 16b4 ; 0x0160 Execute Variant_Record,Field_Read_Dynamic 16b4 ; -------------------------------------------------------------------------------------- 16b4 MACRO_Execute_Variant_Record,Field_Read_Dynamic: 16b4 16b4 dispatch_brk_class 8 ; Flow C 0x16af dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 16b4 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 16af 0x16af typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 22 VR12:02 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 16b5 16b5 seq_b_timing 0 Early Condition; Flow J cc=True 0x16b6 ; Flow J cc=#0x0 0x16b6 seq_br_type b Case False seq_branch_adr 16b6 0x16b6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 16b6 16b6 seq_br_type 3 Unconditional Branch; Flow J 0x1620 seq_branch_adr 1620 MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum 16b7 16b7 seq_br_type 3 Unconditional Branch; Flow J 0x167c seq_branch_adr 167c MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 16b8 16b8 seq_br_type 3 Unconditional Branch; Flow J 0x162a seq_branch_adr 162a MACRO_Execute_Variant_Record,Field_Read,Variant,Direct,fieldnum 16b9 16b9 seq_br_type 3 Unconditional Branch; Flow J 0x168e seq_branch_adr 168e MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum 16ba ; -------------------------------------------------------------------------------------- 16ba ; 0x015f Execute Variant_Record,Field_Write_Dynamic 16ba ; -------------------------------------------------------------------------------------- 16ba MACRO_Execute_Variant_Record,Field_Write_Dynamic: 16ba 16ba dispatch_brk_class 2 ; Flow C 0x16af dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 16ba fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 16af 0x16af typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 21 VR12:01 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 16bb 16bb seq_b_timing 0 Early Condition; Flow J cc=True 0x16bc ; Flow J cc=#0x0 0x16bc seq_br_type b Case False seq_branch_adr 16bc 0x16bc seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 16bc 16bc seq_br_type 3 Unconditional Branch; Flow J 0x1656 seq_branch_adr 1656 MACRO_Execute_Variant_Record,Field_Write,Fixed,Direct,fieldnum 16bd 16bd seq_br_type 3 Unconditional Branch; Flow J 0x1658 seq_branch_adr 1658 MACRO_Execute_Variant_Record,Field_Write,Fixed,Indirect,fieldnum 16be 16be seq_br_type 3 Unconditional Branch; Flow J 0x1660 seq_branch_adr 1660 MACRO_Execute_Variant_Record,Field_Write,Variant,Direct,fieldnum 16bf 16bf seq_br_type 3 Unconditional Branch; Flow J 0x166a seq_branch_adr 166a MACRO_Execute_Variant_Record,Field_Write,Variant,Indirect,fieldnum 16c0 ; -------------------------------------------------------------------------------------- 16c0 ; 0x015e Execute Variant_Record,Field_Reference_Dynamic 16c0 ; -------------------------------------------------------------------------------------- 16c0 MACRO_Execute_Variant_Record,Field_Reference_Dynamic: 16c0 16c0 dispatch_brk_class 8 ; Flow C 0x16af dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 16c0 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 16af 0x16af typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 3c VR05:1c val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 16c1 16c1 seq_b_timing 0 Early Condition; Flow J cc=True 0x16c2 ; Flow J cc=#0x0 0x16c2 seq_br_type b Case False seq_branch_adr 16c2 0x16c2 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 16c2 16c2 seq_br_type 3 Unconditional Branch; Flow J 0x167a seq_branch_adr 167a MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum 16c3 16c3 seq_br_type 3 Unconditional Branch; Flow J 0x167c seq_branch_adr 167c MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 16c4 16c4 seq_br_type 3 Unconditional Branch; Flow J 0x1688 seq_branch_adr 1688 MACRO_Execute_Variant_Record,Field_Reference,Variant,Direct,fieldnum 16c5 16c5 seq_br_type 3 Unconditional Branch; Flow J 0x168e seq_branch_adr 168e MACRO_Execute_Variant_Record,Field_Reference,Variant,Indirect,fieldnum 16c6 ; -------------------------------------------------------------------------------------- 16c6 ; 0x015d Execute Variant_Record,Field_Type_Dynamic 16c6 ; -------------------------------------------------------------------------------------- 16c6 MACRO_Execute_Variant_Record,Field_Type_Dynamic: 16c6 16c6 dispatch_brk_class 8 ; Flow C 0x16af dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 16c6 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 7 Unconditional Call seq_branch_adr 16af 0x16af typ_a_adr 10 TOP typ_b_adr 32 TR02:12 typ_frame 2 typ_rand 9 PASS_A_HIGH val_a_adr 2c VR05:0c val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 16c7 16c7 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32d9 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 16c8 16c8 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 16c9 0x16c9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 16c9 16c9 seq_br_type 7 Unconditional Call; Flow C 0x32e0 seq_branch_adr 32e0 0x32e0 16ca ; -------------------------------------------------------------------------------------- 16ca ; 0x2d00-0x2dff Execute Variant_Record,Field_Append,Fixed,Indirect,fieldnum 16ca ; 0x2f00-0x2fff Execute Variant_Record,Field_Append,Variant,Indirect,fieldnum 16ca ; -------------------------------------------------------------------------------------- 16ca MACRO_Execute_Variant_Record,Field_Append,Fixed,Indirect,fieldnum: 16ca MACRO_Execute_Variant_Record,Field_Append,Variant,Indirect,fieldnum: 16ca 16ca dispatch_brk_class 8 ; Flow C cc=False 0x32db dispatch_csa_valid 3 dispatch_uadr 16ca fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32db 0x32db seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 1e TOP - 2 typ_frame 1f typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS 16cb 16cb fiu_mem_start 2 start-rd; Flow C cc=True 0x32de ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP 16cc 16cc fiu_vmux_sel 1 fill value; Flow C cc=True 0x32e0 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32e0 0x32e0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 02 GP02 typ_b_adr 16 CSA/VAL_BUS val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 16cd 16cd ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x16cf seq_br_type 1 Branch True seq_branch_adr 16cf 0x16cf seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 9 PASS_A_HIGH val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 16ce 16ce fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 16cf 16cf fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x16d4 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 16d4 0x16d4 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 16d0 16d0 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 16d1 16d1 seq_b_timing 0 Early Condition; Flow C cc=True 0x32de seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 16d2 16d2 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x2488 seq_br_type 7 Unconditional Call seq_branch_adr 2488 0x2488 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 16d3 16d3 seq_br_type 3 Unconditional Branch; Flow J 0x16e6 seq_branch_adr 16e6 0x16e6 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 16d4 16d4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x16d6 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 16d6 0x16d6 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 16d5 16d5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal 16d6 16d6 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=False 0x32de fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32de 0x32de seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_c_adr 39 GP06 val_c_source 0 FIU_BUS 16d7 16d7 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 16d8 16d8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x16db seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16db 0x16db seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 16d9 16d9 fiu_fill_mode_src 0 ; Flow J cc=True 0x16de fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16de 0x16de typ_alu_func 1c DEC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 16da 16da fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x16df fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 16df 0x16df typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_c_adr 37 GP08 val_c_source 0 FIU_BUS 16db 16db fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16dc 16dc fiu_fill_mode_src 0 ; Flow J cc=True 0x16de fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16de 0x16de typ_alu_func 1c DEC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 16dd 16dd fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x16df fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 16df 0x16df typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_c_adr 37 GP08 val_c_source 0 FIU_BUS 16de 16de <default> 16df 16df fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 09 GP09 val_alu_func 1b A_OR_B val_b_adr 08 GP08 val_rand c START_MULTIPLY 16e0 16e0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 16e1 16e1 ioc_fiubs 1 val ; Flow J cc=True 0x16e4 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16e4 0x16e4 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 16e2 16e2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 16e3 16e3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 16e4 16e4 seq_br_type 4 Call False; Flow C cc=False 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 05 GP05 16e5 16e5 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x16f8 seq_br_type 5 Call True seq_branch_adr 16f8 0x16f8 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 16e6 16e6 fiu_mem_start 2 start-rd; Flow C cc=True 0x32e0 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32e0 0x32e0 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_source 0 FIU_BUS 16e7 16e7 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 16e8 16e8 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x2488 seq_br_type 7 Unconditional Call seq_branch_adr 2488 0x2488 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 16e9 16e9 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 04 GP04 val_b_adr 03 GP03 16ea 16ea fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 16eb 16eb fiu_fill_mode_src 0 ; Flow J cc=False 0x16f1 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 16f1 0x16f1 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 16ec 16ec fiu_fill_mode_src 0 ; Flow C cc=True 0x32e0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32e0 0x32e0 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 16ed 16ed fiu_fill_mode_src 0 ; Flow C cc=True 0x32e0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32e0 0x32e0 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 16ee 16ee ioc_load_wdr 0 ; Flow J 0x16f6 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 16f6 0x16f6 seq_random 02 ? 16ef 16ef fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 16f0 16f0 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 16f1 16f1 fiu_load_var 1 hold_var; Flow C cc=True 0x32e0 fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32e0 0x32e0 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 16f2 16f2 fiu_fill_mode_src 0 ; Flow J cc=False 0x16ef fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 16ef 0x16ef seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 16f3 16f3 fiu_fill_mode_src 0 ; Flow C cc=True 0x32e0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32e0 0x32e0 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 16f4 16f4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR 16f5 16f5 ioc_load_wdr 0 ; Flow J 0x16f6 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 16f6 0x16f6 val_b_adr 07 GP07 16f6 16f6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 16f7 16f7 fiu_fill_mode_src 0 ; Flow C 0x2ab4 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 16f8 ; -------------------------------------------------------------------------------------- 16f8 ; Comes from: 16f8 ; 16e5 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 16f8 ; -------------------------------------------------------------------------------------- 16f8 16f8 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 09 GP09 val_a_adr 06 GP06 val_alu_func 1c DEC_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 16f9 16f9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x16fd fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 16fd 0x16fd typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 16fa 16fa fiu_mem_start a start_continue_if_false; Flow J cc=True 0x16f7 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 16f7 0x16f7 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 16fb 16fb fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 16fc 16fc fiu_fill_mode_src 0 ; Flow J 0x16f8 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 16f8 0x16f8 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 16fd 16fd seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 16fe 0x16fe seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 16fe 16fe seq_br_type a Unconditional Return; Flow R val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 16ff 16ff <halt> ; Flow R 1700 ; -------------------------------------------------------------------------------------- 1700 ; 0x2300-0x23ff Execute Variant_Record,Field_Type,fieldnum 1700 ; -------------------------------------------------------------------------------------- 1700 MACRO_Execute_Variant_Record,Field_Type,fieldnum: 1700 1700 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1700 dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1701 1701 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32d9 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1702 1702 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1703 0x1703 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_source 0 FIU_BUS 1703 1703 seq_br_type 7 Unconditional Call; Flow C 0x32e0 seq_branch_adr 32e0 0x32e0 seq_en_micro 0 seq_random 02 ? 1704 ; -------------------------------------------------------------------------------------- 1704 ; 0x2200-0x22ff Execute Variant_Record,Field_Constrain,fieldnum 1704 ; -------------------------------------------------------------------------------------- 1704 MACRO_Execute_Variant_Record,Field_Constrain,fieldnum: 1704 1704 dispatch_brk_class 8 ; Flow C cc=True 0x32de dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1704 dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 1705 1705 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR08:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 8 1706 1706 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x1709 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1709 0x1709 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 1707 1707 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1711 fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1711 0x1711 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1708 1708 seq_br_type 7 Unconditional Call; Flow C 0x32e0 seq_branch_adr 32e0 0x32e0 1709 1709 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x32e0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32e0 0x32e0 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 170a 170a fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x170c fiu_mem_start a start_continue_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 170c 0x170c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 170b 170b fiu_fill_mode_src 0 ; Flow J 0x170e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 170e 0x170e typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 170c 170c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 170d 170d fiu_fill_mode_src 0 ; Flow J 0x170e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 170e 0x170e typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 170e 170e seq_br_type 1 Branch True; Flow J cc=True 0x1711 seq_branch_adr 1711 0x1711 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B 170f 170f seq_b_timing 0 Early Condition; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 1710 1710 seq_br_type 7 Unconditional Call; Flow C 0x32e0 seq_branch_adr 32e0 0x32e0 1711 1711 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1718 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1718 0x1718 typ_c_adr 36 GP09 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 36 GP09 1712 1712 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1714 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1714 0x1714 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1713 1713 fiu_fill_mode_src 0 ; Flow J 0x1716 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1716 0x1716 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1714 1714 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1715 1715 fiu_fill_mode_src 0 ; Flow J 0x1716 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1716 0x1716 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1716 1716 seq_br_type 1 Branch True; Flow J cc=True 0x1718 seq_branch_adr 1718 0x1718 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1717 1717 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 1718 1718 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x1722 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 1722 0x1722 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 09 GP09 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1719 1719 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x171e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 171e 0x171e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 171a 171a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x171c seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 171c 0x171c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 171b 171b fiu_fill_mode_src 0 ; Flow J 0x171e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 171e 0x171e val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 171c 171c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 171d 171d fiu_fill_mode_src 0 ; Flow J 0x171e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 171e 0x171e val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 171e 171e fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x1721 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1721 0x1721 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 171f 171f seq_br_type 0 Branch False; Flow J cc=False 0x1721 seq_branch_adr 1721 0x1721 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 08 GP08 typ_c_lit 1 typ_frame c 1720 1720 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x29e5 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 29e5 0x29e5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 08 GP08 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1721 1721 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1722 1722 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x1721 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 1721 0x1721 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 08 GP08 typ_c_lit 1 typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1723 1723 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1721 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 1721 0x1721 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR08:00 typ_b_adr 08 GP08 typ_frame 8 1724 1724 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1725 1725 ioc_load_wdr 0 ; Flow J 0x1721 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1721 0x1721 seq_random 02 ? 1726 ; -------------------------------------------------------------------------------------- 1726 ; 0x2100-0x21ff Execute Variant_Record,Set_Bounds,fieldnum 1726 ; -------------------------------------------------------------------------------------- 1726 MACRO_Execute_Variant_Record,Set_Bounds,fieldnum: 1726 1726 dispatch_brk_class 8 ; Flow C cc=True 0x32de dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1726 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1727 1727 fiu_load_tar 1 hold_tar; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame a val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1728 1728 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32d9 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1729 1729 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32d9 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 val_rand 6 IMMEDIATE_OP 172a 172a fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x32d9 fiu_offs_lit 4f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 172b 172b fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1733 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1733 0x1733 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 172c 172c fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 172d 172d fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x172f fiu_mem_start a start_continue_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 172f 0x172f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3e GP01 val_c_source 0 FIU_BUS 172e 172e fiu_fill_mode_src 0 ; Flow J 0x1731 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1731 0x1731 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 172f 172f fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1730 1730 fiu_fill_mode_src 0 ; Flow J 0x1731 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1731 0x1731 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1731 1731 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1734 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1734 0x1734 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1732 1732 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 1733 1733 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1734 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1734 0x1734 seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1734 1734 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1735 1735 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 3f VR02:1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 val_rand c START_MULTIPLY 1736 1736 fiu_mem_start 2 start-rd; Flow J 0x173d ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 173d 0x173d seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1737 1737 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 1738 1738 ioc_fiubs 1 val ; Flow J cc=True 0x173b seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 173b 0x173b seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 1739 1739 seq_b_timing 1 Latch Condition; Flow J cc=True 0x173b seq_br_type 1 Branch True seq_branch_adr 173b 0x173b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 173a 173a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 173b 173b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x1757 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1757 0x1757 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 173c 173c fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 173d 173d val_alu_func 6 A_MINUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 173e 173e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 173f 173f fiu_mem_start 4 continue ioc_tvbs 1 typ+fiu typ_mar_cntl 6 INCREMENT_MAR val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1740 1740 fiu_load_var 1 hold_var; Flow C cc=False 0x32dc fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 1741 1741 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1742 1742 ioc_fiubs 0 fiu ; Flow J cc=True 0x1748 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1748 0x1748 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 20 TR05:00 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1743 1743 ioc_fiubs 1 val ; Flow C cc=False 0x32a2 seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 1744 1744 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 0e GP0e typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 1745 1745 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x1749 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1749 0x1749 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 0f GP0f val_a_adr 03 GP03 val_alu_func 7 INC_A val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1746 1746 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 1747 1747 seq_br_type 3 Unconditional Branch; Flow J 0x1749 seq_branch_adr 1749 0x1749 1748 1748 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x2ab4 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 1 INC_LOOP_COUNTER 1749 1749 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1757 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1757 0x1757 typ_mar_cntl b LOAD_MAR_DATA typ_rand d SET_PASS_PRIVACY_BIT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 174a 174a seq_b_timing 0 Early Condition; Flow J cc=False 0x1737 seq_br_type 0 Branch False seq_branch_adr 1737 0x1737 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 174b 174b fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1754 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1754 0x1754 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 07 GP07 val_alu_func 0 PASS_A val_b_adr 3f VR02:1f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 val_rand c START_MULTIPLY 174c 174c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 174d 174d fiu_load_var 1 hold_var; Flow C cc=False 0x32dc fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 174e 174e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x1757 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1757 0x1757 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 174f 174f fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1754 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1754 0x1754 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1750 1750 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x174d seq_br_type 0 Branch False seq_branch_adr 174d 0x174d seq_cond_sel 67 REFRESH_MACRO_EVENT 1751 1751 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 1752 1752 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 1753 1753 seq_br_type 3 Unconditional Branch; Flow J 0x174d seq_branch_adr 174d 0x174d 1754 1754 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 1755 1755 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 1756 1756 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1757 ; -------------------------------------------------------------------------------------- 1757 ; Comes from: 1757 ; 173b C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 1757 ; 1749 C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 1757 ; 174e C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 1757 ; -------------------------------------------------------------------------------------- 1757 1757 fiu_fill_mode_src 0 ; Flow J cc=False 0x175a fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 175a 0x175a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1758 1758 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1759 1759 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 175a 175a fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 175b 175b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 175c 175c fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 175d 175d ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 175e ; -------------------------------------------------------------------------------------- 175e ; 0x2000-0x20ff Execute Variant_Record,Set_Variant,fieldnum 175e ; -------------------------------------------------------------------------------------- 175e MACRO_Execute_Variant_Record,Set_Variant,fieldnum: 175e 175e dispatch_brk_class 8 ; Flow C cc=True 0x32d9 dispatch_csa_valid 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 175e dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 36 VR05:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 175f 175f fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32d9 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offs_lit 38 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1760 1760 fiu_fill_mode_src 0 ; Flow J cc=False 0x1768 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1768 0x1768 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1761 1761 fiu_fill_mode_src 0 ; Flow C cc=False 0x32d9 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 1762 1762 fiu_fill_mode_src 0 ; Flow C cc=False 0x32d9 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 35 TR02:15 typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A 1763 1763 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 1764 1764 ioc_load_wdr 0 ; Flow J cc=False 0x176f ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 176f 0x176f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1765 1765 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1766 1766 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 1767 1767 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 1768 1768 fiu_load_var 1 hold_var; Flow C cc=False 0x32d9 fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 1769 1769 fiu_fill_mode_src 0 ; Flow J cc=False 0x1766 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1766 0x1766 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 3c GP03 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 176a 176a fiu_fill_mode_src 0 ; Flow C cc=False 0x32d9 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 35 TR02:15 typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3c GP03 176b 176b fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 176c 176c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 176d 176d ioc_load_wdr 0 ; Flow J cc=False 0x176f ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 176f 0x176f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_b_adr 03 GP03 176e 176e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 176f 176f fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1770 1770 ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 1771 1771 fiu_vmux_sel 1 fill value; Flow C 0x2a5e ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2a5e 0x2a5e val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1772 1772 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1773 1773 <halt> ; Flow R 1774 ; -------------------------------------------------------------------------------------- 1774 ; 0x016e Execute Variant_Record,Not_Equal 1774 ; 0x016f Execute Variant_Record,Equal 1774 ; -------------------------------------------------------------------------------------- 1774 MACRO_Execute_Variant_Record,Equal: 1774 MACRO_Execute_Variant_Record,Not_Equal: 1774 1774 dispatch_brk_class 8 ; Flow J cc=True 0x1776 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1774 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 1776 0x1776 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1775 1775 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1776 1776 ioc_fiubs 1 val ioc_tvbs 1 typ+fiu typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1777 1777 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1779 seq_br_type 1 Branch True seq_branch_adr 1779 0x1779 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1778 1778 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1779 1779 fiu_mem_start 2 start-rd; Flow C 0x2484 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2484 0x2484 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_b_adr 08 GP08 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 177a 177a ioc_fiubs 1 val typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 177b 177b seq_br_type 7 Unconditional Call; Flow C 0x272c seq_branch_adr 272c 0x272c typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 177c 177c fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 177d 177d <halt> ; Flow R 177e ; -------------------------------------------------------------------------------------- 177e ; 0x016d Execute Variant_Record,Structure_Write 177e ; -------------------------------------------------------------------------------------- 177e MACRO_Execute_Variant_Record,Structure_Write: 177e 177e dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 177e dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 177f 177f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1de9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1de9 0x1de9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1780 ; -------------------------------------------------------------------------------------- 1780 ; 0x016c Execute Variant_Record,Is_Constrained 1780 ; -------------------------------------------------------------------------------------- 1780 MACRO_Execute_Variant_Record,Is_Constrained: 1780 1780 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1780 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 1781 1781 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1782 ; -------------------------------------------------------------------------------------- 1782 ; 0x015c Execute Variant_Record,Is_Constrained_Object 1782 ; -------------------------------------------------------------------------------------- 1782 MACRO_Execute_Variant_Record,Is_Constrained_Object: 1782 1782 dispatch_brk_class 8 ; Flow C 0x332e dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1782 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_frame 2 1783 1783 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1784 ; -------------------------------------------------------------------------------------- 1784 ; 0x015b Execute Variant_Record,Make_Constrained 1784 ; -------------------------------------------------------------------------------------- 1784 MACRO_Execute_Variant_Record,Make_Constrained: 1784 1784 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1784 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 21 TR0c:01 typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL 1785 1785 <halt> ; Flow R 1786 ; -------------------------------------------------------------------------------------- 1786 ; 0x016b Execute Variant_Record,Read_Variant 1786 ; -------------------------------------------------------------------------------------- 1786 MACRO_Execute_Variant_Record,Read_Variant: 1786 1786 dispatch_brk_class 8 ; Flow J cc=True 0x1789 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1786 dispatch_uses_tos 1 seq_br_type 1 Branch True seq_branch_adr 1789 0x1789 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 1787 1787 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x1789 seq_br_type 0 Branch False seq_branch_adr 1789 0x1789 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 1788 1788 fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1789 1789 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x1790 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1790 0x1790 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 3b TR07:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 178a 178a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x178c seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 178c 0x178c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 178b 178b fiu_fill_mode_src 0 ; Flow J 0x178e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 178e 0x178e val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 178c 178c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 178d 178d fiu_fill_mode_src 0 ; Flow J 0x178e fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 178e 0x178e val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 178e 178e fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 0 Early Condition seq_br_type d Dispatch False seq_branch_adr 178f 0x178f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 178f 178f seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_en_micro 0 seq_random 02 ? 1790 1790 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR05:16 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 1791 1791 <halt> ; Flow R 1792 ; -------------------------------------------------------------------------------------- 1792 ; 0x016a Execute Variant_Record,Indirects_Appended 1792 ; -------------------------------------------------------------------------------------- 1792 MACRO_Execute_Variant_Record,Indirects_Appended: 1792 1792 dispatch_brk_class 8 ; Flow C cc=False 0x32db dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1792 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_br_type 4 Call False seq_branch_adr 32db 0x32db seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 1f TOP - 1 typ_frame 1f 1793 1793 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32db fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 24 VR05:04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 1794 1794 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 2 typ seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_a_adr 21 TR02:01 typ_b_adr 1f TOP - 1 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1795 1795 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1798 fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1798 0x1798 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 1e TR02:01 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 1796 1796 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type c Dispatch True seq_branch_adr 1797 0x1797 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 1797 1797 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de seq_en_micro 0 seq_random 02 ? 1798 1798 fiu_load_var 1 hold_var; Flow J cc=True 0x179c fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 179c 0x179c typ_a_adr 22 TR01:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1799 1799 fiu_mem_start 3 start-wr ioc_adrbs 3 seq ioc_load_wdr 0 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 179a 179a ioc_fiubs 1 val ; Flow C cc=True 0x32de seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 179b 179b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 179c 179c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 179d 179d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 179e 179e fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32de fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 23 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 179f 179f fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_load_wdr 0 typ_c_adr 1d TR02:02 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 17a0 17a0 ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_b_adr 01 GP01 17a1 17a1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 17a2 ; -------------------------------------------------------------------------------------- 17a2 ; 0x0169 Execute Variant_Record,Read_Discriminant_Constraint 17a2 ; -------------------------------------------------------------------------------------- 17a2 MACRO_Execute_Variant_Record,Read_Discriminant_Constraint: 17a2 17a2 dispatch_brk_class 8 ; Flow C cc=True 0x32d9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 17a2 dispatch_uses_tos 1 fiu_len_fill_lit 79 zero-fill 0x39 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 19 X_XOR_B typ_b_adr 2d TR09:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 9 PASS_A_HIGH val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 17a3 17a3 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32d9 fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 17a4 17a4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B 17a5 17a5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32d9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 30 TR05:10 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 17a6 17a6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 17a7 17a7 typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL 17a8 17a8 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 17a9 17a9 <halt> ; Flow R 17aa ; -------------------------------------------------------------------------------------- 17aa ; 0x0168 Execute Variant_Record,Reference_Makes_Copy 17aa ; -------------------------------------------------------------------------------------- 17aa MACRO_Execute_Variant_Record,Reference_Makes_Copy: 17aa 17aa dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 17aa dispatch_uses_tos 1 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 17ab 17ab fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x17b0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 21 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 17b0 0x17b0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 17ac 17ac ioc_tvbs 2 fiu+val seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 17ad 17ad fiu_fill_mode_src 0 ; Flow J cc=False 0x17af fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 17af 0x17af val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 17ae 17ae seq_b_timing 0 Early Condition; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 17af 17af fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 17b0 17b0 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x17af fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 17af 0x17af 17b1 17b1 <halt> ; Flow R 17b2 ; -------------------------------------------------------------------------------------- 17b2 ; 0x0167 Execute Variant_Record,Structure_Query 17b2 ; -------------------------------------------------------------------------------------- 17b2 MACRO_Execute_Variant_Record,Structure_Query: 17b2 17b2 dispatch_brk_class 8 dispatch_csa_free 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 17b2 dispatch_uses_tos 1 typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 17b3 17b3 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x17b5 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 17b5 0x17b5 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 17b4 17b4 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x17b7 fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 17b7 0x17b7 typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 17b5 17b5 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 17b6 17b6 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 17b7 17b7 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 17b8 17b8 fiu_mem_start 6 start_rd_if_false; Flow C 0x210 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 17b9 17b9 ioc_fiubs 1 val ; Flow C cc=True 0x17c6 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 17c6 0x17c6 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1e A_AND_B val_b_adr 3f VR1e:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 1e val_rand 2 DEC_LOOP_COUNTER 17ba 17ba fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 22 VR08:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 17bb 17bb fiu_load_var 1 hold_var; Flow J cc=False 0x17b8 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 17b8 0x17b8 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 21 TR10:01 typ_frame 10 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 17bc 17bc fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x17c3 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 17c3 0x17c3 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 17bd 17bd fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x17c1 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 17c1 0x17c1 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 7 17be 17be fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x17c4 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 17c4 0x17c4 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17bf 17bf fiu_load_var 1 hold_var; Flow C cc=True 0x17c6 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 17c6 0x17c6 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 17 LOOP_COUNTER typ_rand d SET_PASS_PRIVACY_BIT 17c0 17c0 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x17be seq_br_type 1 Branch True seq_branch_adr 17be 0x17be seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 17c1 17c1 ioc_fiubs 0 fiu ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 2 17c2 17c2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 17c3 17c3 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 2f TOP val_c_source 0 FIU_BUS 17c4 17c4 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 17c5 17c5 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 17c6 ; -------------------------------------------------------------------------------------- 17c6 ; Comes from: 17c6 ; 17b9 C True from color 0x17b9 17c6 ; 17bf C True from color MACRO_Execute_Variant_Record,Structure_Query 17c6 ; -------------------------------------------------------------------------------------- 17c6 17c6 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 17c7 17c7 fiu_mem_start 2 start-rd; Flow J 0x332e ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 332e 0x332e typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A 17c8 ; -------------------------------------------------------------------------------------- 17c8 ; 0x0166 Execute Variant_Record,Component_Offset 17c8 ; -------------------------------------------------------------------------------------- 17c8 MACRO_Execute_Variant_Record,Component_Offset: 17c8 17c8 dispatch_brk_class 8 ; Flow C cc=False 0x32de dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17c8 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32de 0x32de seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 14 ZEROS typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 36 VR05:16 val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_frame 5 17c9 17c9 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 17ca 17ca fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32d9 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 17cb 17cb fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 17cc 0x17cc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 17cc 17cc seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de seq_en_micro 0 seq_random 02 ? 17cd 17cd <halt> ; Flow R 17ce ; -------------------------------------------------------------------------------------- 17ce ; 0x0165 Execute Variant_Record,Convert 17ce ; -------------------------------------------------------------------------------------- 17ce MACRO_Execute_Variant_Record,Convert: 17ce 17ce dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 17ce dispatch_uses_tos 1 ioc_fiubs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 17cf 17cf ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x17d2 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 17d2 0x17d2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 17d0 17d0 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2515 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2515 0x2515 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17d1 17d1 seq_b_timing 1 Latch Condition; Flow C cc=False 0x32a4 seq_br_type 4 Call False seq_branch_adr 32a4 0x32a4 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 17d2 17d2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x17d5 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 17d5 0x17d5 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 17d3 17d3 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17d4 17d4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 17d5 17d5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 26 TR06:06 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 6 17d6 17d6 fiu_load_tar 1 hold_tar; Flow C cc=True 0x17db fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 17db 0x17db seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 17d7 17d7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2484 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 2484 0x2484 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 08 GP08 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17d8 17d8 ioc_fiubs 1 val ; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 02 GP02 17d9 17d9 seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1e A_AND_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 17da 17da fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 2f TOP val_c_mux_sel 2 ALU 17db ; -------------------------------------------------------------------------------------- 17db ; Comes from: 17db ; 17d6 C True from color 0x0a32 17db ; -------------------------------------------------------------------------------------- 17db 17db seq_br_type 1 Branch True; Flow J cc=True 0x17de seq_branch_adr 17de 0x17de seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 02 ? val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 17dc 17dc ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 17dd 17dd seq_br_type 7 Unconditional Call; Flow C 0x32cc seq_branch_adr 32cc 0x32cc 17de 17de ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 17df 17df ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 17e0 ; -------------------------------------------------------------------------------------- 17e0 ; 0x0164 Execute Variant_Record,In_Type 17e0 ; -------------------------------------------------------------------------------------- 17e0 MACRO_Execute_Variant_Record,In_Type: 17e0 17e0 dispatch_brk_class 8 ; Flow J cc=True 0x17e2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17e0 seq_br_type 1 Branch True seq_branch_adr 17e2 0x17e2 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 17e1 17e1 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17e2 17e2 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2515 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 2515 0x2515 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17e3 17e3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 17e4 ; -------------------------------------------------------------------------------------- 17e4 ; 0x0163 Execute Variant_Record,Not_In_Type 17e4 ; -------------------------------------------------------------------------------------- 17e4 MACRO_Execute_Variant_Record,Not_In_Type: 17e4 17e4 dispatch_brk_class 8 ; Flow J cc=True 0x17e6 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17e4 seq_br_type 1 Branch True seq_branch_adr 17e6 0x17e6 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 17e5 17e5 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17e6 17e6 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2515 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 2515 0x2515 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17e7 17e7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 17e8 ; -------------------------------------------------------------------------------------- 17e8 ; 0x0162 Execute Variant_Record,Check_In_Type 17e8 ; -------------------------------------------------------------------------------------- 17e8 MACRO_Execute_Variant_Record,Check_In_Type: 17e8 17e8 dispatch_brk_class 8 ; Flow J cc=True 0x17ea dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17e8 seq_br_type 1 Branch True seq_branch_adr 17ea 0x17ea seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 17e9 17e9 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17ea 17ea fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2515 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 2515 0x2515 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17eb 17eb fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 17ec 0x17ec seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 17ec 17ec seq_br_type 7 Unconditional Call; Flow C 0x32a4 seq_branch_adr 32a4 0x32a4 seq_en_micro 0 seq_random 02 ? 17ed 17ed <halt> ; Flow R 17ee ; -------------------------------------------------------------------------------------- 17ee ; 0x0161 Execute Variant_Record,Check_In_Formal_Type 17ee ; -------------------------------------------------------------------------------------- 17ee MACRO_Execute_Variant_Record,Check_In_Formal_Type: 17ee 17ee dispatch_brk_class 8 ; Flow J cc=True 0x17f0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 17ee seq_br_type 1 Branch True seq_branch_adr 17f0 0x17f0 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 1 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 17ef 17ef fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 17f0 17f0 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2515 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 2515 0x2515 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17f1 17f1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a4 seq_br_type 5 Call True seq_branch_adr 32a4 0x32a4 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 35 TR02:15 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 17f2 17f2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 17f3 17f3 <halt> ; Flow R 17f4 ; -------------------------------------------------------------------------------------- 17f4 ; 0x0125 Execute Any,Set_Constraint 17f4 ; -------------------------------------------------------------------------------------- 17f4 MACRO_Execute_Any,Set_Constraint: 17f4 17f4 dispatch_brk_class 8 ; Flow J cc=False 0x1801 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 17f4 dispatch_uses_tos 1 seq_br_type 0 Branch False seq_branch_adr 1801 0x1801 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 17f5 17f5 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x17f8 fiu_mem_start 5 start_rd_if_true fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 17f8 0x17f8 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 17f6 17f6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x17fa fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 17fa 0x17fa seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 36 GP09 val_c_adr 36 GP09 17f7 17f7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x29e5 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 29e5 0x29e5 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 17f8 17f8 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 17f9 0x17f9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 17f9 17f9 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de seq_en_micro 0 seq_random 02 ? 17fa 17fa fiu_fill_mode_src 0 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 17fb 17fb fiu_mem_start a start_continue_if_false; Flow J cc=False 0x17fd seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 17fd 0x17fd seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 17fc 17fc fiu_fill_mode_src 0 ; Flow J 0x17ff fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 17ff 0x17ff val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 17fd 17fd fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 17fe 17fe fiu_fill_mode_src 0 ; Flow J 0x17ff fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 17ff 0x17ff val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 17ff 17ff seq_b_timing 0 Early Condition; Flow C cc=True 0x29e5 seq_br_type 5 Call True seq_branch_adr 29e5 0x29e5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 1800 1800 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1801 1801 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1802 0x1802 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 1802 1802 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 1803 1803 <halt> ; Flow R 1804 ; -------------------------------------------------------------------------------------- 1804 ; 0x3c00-0x3cff Execute Record,Field_Read,fieldnum 1804 ; -------------------------------------------------------------------------------------- 1804 MACRO_Execute_Record,Field_Read,fieldnum: 1804 1804 dispatch_brk_class 8 ; Flow C cc=True 0x32de dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1804 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 1805 1805 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x180e fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 180e 0x180e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 35 Validate_tos_optimizer+? typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1806 1806 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1808 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1808 0x1808 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1807 1807 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x180a fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 180a 0x180a seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1808 1808 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1809 1809 fiu_fill_mode_src 0 ; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 180a 0x180a seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 180a 180a fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 180b 0x180b seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 180b 180b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 180c ; -------------------------------------------------------------------------------------- 180c ; 0x017a Execute Record,Field_Read_Dynamic 180c ; -------------------------------------------------------------------------------------- 180c MACRO_Execute_Record,Field_Read_Dynamic: 180c 180c dispatch_brk_class 8 ; Flow C 0x1841 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 180c fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1841 0x1841 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_b_adr 10 TOP 180d 180d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x1806 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1806 0x1806 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 17 Validate_tos_optimizer+? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 180e 180e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 180f 180f <halt> ; Flow R 1810 ; -------------------------------------------------------------------------------------- 1810 ; 0x3800-0x38ff Execute Record,Field_Write,fieldnum 1810 ; -------------------------------------------------------------------------------------- 1810 MACRO_Execute_Record,Field_Write,fieldnum: 1810 1810 dispatch_brk_class 2 ; Flow C cc=True 0x32de dispatch_csa_valid 2 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1810 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 1811 1811 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d78 0x1d78 seq_int_reads 0 TYP VAL BUS seq_random 09 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1812 ; -------------------------------------------------------------------------------------- 1812 ; 0x0179 Execute Record,Field_Write_Dynamic 1812 ; -------------------------------------------------------------------------------------- 1812 MACRO_Execute_Record,Field_Write_Dynamic: 1812 1812 dispatch_brk_class 2 ; Flow C 0x1841 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1812 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1841 0x1841 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_b_adr 10 TOP 1813 1813 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d78 0x1d78 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1814 ; -------------------------------------------------------------------------------------- 1814 ; 0x3400-0x34ff Execute Record,Field_Reference,fieldnum 1814 ; -------------------------------------------------------------------------------------- 1814 MACRO_Execute_Record,Field_Reference,fieldnum: 1814 1814 dispatch_brk_class 8 ; Flow C cc=True 0x32de dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1814 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 1815 1815 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 3c Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1816 ; -------------------------------------------------------------------------------------- 1816 ; 0x0178 Execute Record,Field_Reference_Dynamic 1816 ; -------------------------------------------------------------------------------------- 1816 MACRO_Execute_Record,Field_Reference_Dynamic: 1816 1816 dispatch_brk_class 8 ; Flow C 0x1841 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1816 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1841 0x1841 seq_random 02 ? typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_b_adr 10 TOP 1817 1817 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1818 ; -------------------------------------------------------------------------------------- 1818 ; 0x3000-0x30ff Execute Record,Field_Type,fieldnum 1818 ; -------------------------------------------------------------------------------------- 1818 MACRO_Execute_Record,Field_Type,fieldnum: 1818 1818 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 3 TYPE READ, AT TOS PLUS FIELD NUMBER dispatch_uadr 1818 dispatch_uses_tos 1 ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand a PASS_B_HIGH val_b_adr 10 TOP 1819 1819 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 181a 0x181a seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 3c Load_save_offset+Validate_tos_optimizer+? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 181a 181a seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 181b 181b <halt> ; Flow R 181c ; -------------------------------------------------------------------------------------- 181c ; 0x0177 Execute Record,Field_Type_Dynamic 181c ; -------------------------------------------------------------------------------------- 181c MACRO_Execute_Record,Field_Type_Dynamic: 181c 181c dispatch_brk_class 8 ; Flow C 0x1846 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 181c fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1846 0x1846 seq_random 02 ? typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_b_adr 10 TOP 181d 181d fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 181e 0x181e seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 181e 181e seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 181f 181f <halt> ; Flow R 1820 ; -------------------------------------------------------------------------------------- 1820 ; 0x017e Execute Record,Not_Equal 1820 ; 0x017f Execute Record,Equal 1820 ; -------------------------------------------------------------------------------------- 1820 MACRO_Execute_Record,Equal: 1820 MACRO_Execute_Record,Not_Equal: 1820 1820 dispatch_brk_class 8 ; Flow C cc=False 0x1847 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1820 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 1847 0x1847 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1821 1821 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32de fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_lit 1 typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1822 1822 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x272c fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 272c 0x272c typ_a_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL 1823 1823 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1824 ; -------------------------------------------------------------------------------------- 1824 ; 0x017d Execute Record,Structure_Write 1824 ; -------------------------------------------------------------------------------------- 1824 MACRO_Execute_Record,Structure_Write: 1824 1824 dispatch_brk_class 2 ; Flow C cc=False 0x1847 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1824 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1847 0x1847 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1825 1825 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1826 1826 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1829 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1829 0x1829 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 1827 1827 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32db seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 22 VR02:02 val_frame 2 1828 1828 ioc_tvbs 5 seq+seq; Flow C cc=True 0x32db seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS 1829 1829 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 182a 182a seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1f1e seq_br_type 4 Call False seq_branch_adr 1f1e 0x1f1e seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 182b 182b fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 182c 0x182c seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 182c 182c seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 182d 182d <halt> ; Flow R 182e ; -------------------------------------------------------------------------------------- 182e ; 0x017c Execute Record,Component_Offset 182e ; -------------------------------------------------------------------------------------- 182e MACRO_Execute_Record,Component_Offset: 182e 182e dispatch_brk_class 8 ; Flow C cc=False 0x32de dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 182e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32de 0x32de seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 14 ZEROS typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 36 VR05:16 val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_frame 5 182f 182f fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1830 1830 <default> 1831 1831 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32d9 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1832 1832 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1833 0x1833 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1833 1833 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de seq_en_micro 0 seq_random 02 ? 1834 ; -------------------------------------------------------------------------------------- 1834 ; 0x017b Execute Record,Convert 1834 ; -------------------------------------------------------------------------------------- 1834 MACRO_Execute_Record,Convert: 1834 1834 dispatch_brk_class 4 ; Flow C cc=False 0x1847 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1834 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 1847 0x1847 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1835 1835 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_rand 8 SPARE_0x08 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1836 1836 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x183a fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 183a 0x183a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 7 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1837 1837 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1838 1838 seq_br_type 7 Unconditional Call; Flow C 0x1f1e seq_branch_adr 1f1e 0x1f1e seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1839 1839 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 183a 183a seq_br_type 1 Branch True; Flow J cc=True 0x183d seq_branch_adr 183d 0x183d seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 183b 183b ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 183c 183c seq_br_type 7 Unconditional Call; Flow C 0x32cc seq_branch_adr 32cc 0x32cc 183d 183d ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 183e 183e ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 183f 183f ioc_fiubs 1 val ; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1840 1840 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1841 ; -------------------------------------------------------------------------------------- 1841 ; Comes from: 1841 ; 180c C from color MACRO_Execute_Record,Field_Read,fieldnum 1841 ; 1812 C from color MACRO_Execute_Record,Field_Write_Dynamic 1841 ; 1816 C from color MACRO_Execute_Record,Field_Reference_Dynamic 1841 ; -------------------------------------------------------------------------------------- 1841 1841 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32de fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1842 1842 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32de seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 1843 1843 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1844 1844 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1845 0x1845 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 10 TOP val_alu_func 19 X_XOR_B 1845 1845 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 1846 ; -------------------------------------------------------------------------------------- 1846 ; Comes from: 1846 ; 181c C from color MACRO_Execute_Record,Field_Type_Dynamic 1846 ; -------------------------------------------------------------------------------------- 1846 1846 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1842 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1842 0x1842 typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL 1847 ; -------------------------------------------------------------------------------------- 1847 ; Comes from: 1847 ; 1820 C False from color 0x09ad 1847 ; 1824 C False from color MACRO_Execute_Record,Structure_Write 1847 ; 1834 C False from color 0x0a31 1847 ; -------------------------------------------------------------------------------------- 1847 1847 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand 8 SPARE_0x08 1848 1848 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1849 1849 <halt> ; Flow R 184a ; -------------------------------------------------------------------------------------- 184a ; 0x01de Execute Vector,Not_Equal 184a ; 0x01df Execute Vector,Equal 184a ; -------------------------------------------------------------------------------------- 184a MACRO_Execute_Vector,Equal: 184a MACRO_Execute_Vector,Not_Equal: 184a 184a dispatch_brk_class 8 ; Flow J cc=True 0x184c dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 184a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 184c 0x184c seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 184b 184b fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 184c 184c fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1857 ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 1857 0x1857 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 184d 184d fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 184e 184e fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 5 184f 184f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1851 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1851 0x1851 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1850 1850 fiu_fill_mode_src 0 ; Flow J 0x1853 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1853 0x1853 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1851 1851 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1852 1852 fiu_fill_mode_src 0 ; Flow J 0x1853 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1853 0x1853 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1853 1853 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1854 1854 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1858 seq_br_type 1 Branch True seq_branch_adr 1858 0x1858 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1855 1855 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1856 1856 seq_br_type 3 Unconditional Branch; Flow J 0x1858 seq_branch_adr 1858 0x1858 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1857 1857 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1858 1858 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1863 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 1863 0x1863 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1859 1859 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 185a 185a fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 185b 185b fiu_mem_start a start_continue_if_false; Flow J cc=False 0x185d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 185d 0x185d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 185c 185c fiu_fill_mode_src 0 ; Flow J 0x185f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 185f 0x185f val_c_adr 39 GP06 val_c_source 0 FIU_BUS 185d 185d fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 185e 185e fiu_fill_mode_src 0 ; Flow J 0x185f fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 185f 0x185f val_c_adr 39 GP06 val_c_source 0 FIU_BUS 185f 185f seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_rand c START_MULTIPLY 1860 1860 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1864 seq_br_type 1 Branch True seq_branch_adr 1864 0x1864 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1861 1861 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1862 1862 seq_br_type 3 Unconditional Branch; Flow J 0x1864 seq_branch_adr 1864 0x1864 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1863 1863 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1864 1864 ioc_fiubs 1 val ; Flow C cc=True 0x272c seq_br_type 5 Call True seq_branch_adr 272c 0x272c seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1865 1865 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 1866 0x1866 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1866 1866 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1867 0x1867 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1867 1867 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1869 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 1869 0x1869 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE 1868 1868 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1869 1869 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x186b ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 186b 0x186b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE 186a 186a fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 38 GP07 val_c_source 0 FIU_BUS 186b 186b fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 186c 0x186c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 186c 186c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 186d 186d <halt> ; Flow R 186e ; -------------------------------------------------------------------------------------- 186e ; 0x01c0 Execute Vector,Greater_Equal 186e ; -------------------------------------------------------------------------------------- 186e MACRO_Execute_Vector,Greater_Equal: 186e 186e dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 186e ioc_load_wdr 0 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 186f 186f fiu_mem_start 2 start-rd; Flow J 0x1872 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1872 MACRO_Execute_Vector,Less_Equal typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 20 TOP - 0x1 1870 ; -------------------------------------------------------------------------------------- 1870 ; 0x01c2 Execute Vector,Greater 1870 ; -------------------------------------------------------------------------------------- 1870 MACRO_Execute_Vector,Greater: 1870 1870 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1870 ioc_load_wdr 0 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 1871 1871 fiu_mem_start 2 start-rd; Flow J 0x1878 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1878 MACRO_Execute_Vector,Less typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 20 TOP - 0x1 1872 ; -------------------------------------------------------------------------------------- 1872 ; 0x01bf Execute Vector,Less_Equal 1872 ; -------------------------------------------------------------------------------------- 1872 MACRO_Execute_Vector,Less_Equal: 1872 1872 dispatch_brk_class 8 ; Flow C cc=False 0x1af3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1872 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1af3 0x1af3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1873 1873 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x187a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 187a 0x187a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 1874 1874 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1876 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1876 0x1876 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1875 1875 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x187a fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 187a 0x187a typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1876 1876 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1877 1877 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x187a fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 187a 0x187a typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1878 ; -------------------------------------------------------------------------------------- 1878 ; 0x01c1 Execute Vector,Less 1878 ; -------------------------------------------------------------------------------------- 1878 MACRO_Execute_Vector,Less: 1878 1878 dispatch_brk_class 8 ; Flow C cc=False 0x1af3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1878 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1af3 0x1af3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 13 ONES typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1879 1879 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1874 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1874 0x1874 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 187a 187a fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3b GP04 val_c_source 0 FIU_BUS 187b 187b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 4 continue fiu_offs_lit 40 typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 187c 187c fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 187d 187d fiu_fill_mode_src 0 ; Flow J cc=False 0x1882 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1882 0x1882 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 5 187e 187e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1880 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1880 0x1880 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 187f 187f fiu_fill_mode_src 0 ; Flow J 0x1882 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1882 0x1882 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1880 1880 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1881 1881 fiu_fill_mode_src 0 ; Flow J 0x1882 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1882 0x1882 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1882 1882 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1883 1883 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1884 1884 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x188a fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 188a 0x188a seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1885 1885 fiu_load_var 1 hold_var; Flow J cc=False 0x188d fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 188d 0x188d seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 11 TOP + 1 val_a_adr 05 GP05 val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 1886 1886 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=True 0x1888 fiu_len_fill_reg_ctl 1 len=literal, fill=literal ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1888 0x1888 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 typ_a_adr 3a TR02:1a typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1887 1887 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1888 1888 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x188e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 188e 0x188e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 3a TR02:1a typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 30 VR05:10 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 val_m_b_src 2 Bits 32…47 1889 1889 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x188d fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 188d 0x188d seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 20 VR00:00 188a 188a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 188b 188b fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 188c 188c fiu_fill_mode_src 0 ; Flow J cc=False 0x1892 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1892 0x1892 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_source 0 FIU_BUS 188d 188d fiu_mem_start 2 start-rd; Flow J cc=True 0x1893 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1893 0x1893 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 188e 188e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1894 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1894 0x1894 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 188f 188f fiu_fill_mode_src 0 ; Flow J cc=True 0x1896 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1896 0x1896 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1890 1890 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x188b seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 188b 0x188b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1891 1891 fiu_fill_mode_src 0 ; Flow J cc=True 0x188d fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 188d 0x188d seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1892 1892 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1889 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 1889 0x1889 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1893 1893 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1894 1894 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1895 1895 fiu_fill_mode_src 0 ; Flow J cc=False 0x1890 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1890 0x1890 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1896 1896 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 1897 1897 fiu_mem_start 2 start-rd; Flow J 0x1890 seq_br_type 3 Unconditional Branch seq_branch_adr 1890 0x1890 1898 ; -------------------------------------------------------------------------------------- 1898 ; 0x01dd Execute Vector,First 1898 ; -------------------------------------------------------------------------------------- 1898 MACRO_Execute_Vector,First: 1898 1898 dispatch_brk_class 8 ; Flow J cc=True 0x189d dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1898 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 189d 0x189d seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR0c:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 1899 1899 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x189b seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 189b 0x189b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 189a 189a fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 189b 189b fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 189c 189c fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 189d 189d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1899 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 40 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1899 0x1899 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 189e ; -------------------------------------------------------------------------------------- 189e ; 0x01dc Execute Vector,Last 189e ; -------------------------------------------------------------------------------------- 189e MACRO_Execute_Vector,Last: 189e 189e dispatch_brk_class 8 ; Flow J cc=True 0x18a7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 189e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 18a7 0x18a7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR0c:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 189f 189f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x18a2 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18a2 0x18a2 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 18a0 18a0 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 18a1 18a1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x18a5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 18a5 0x18a5 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18a2 18a2 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18a3 18a3 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 18a4 18a4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x18a5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 18a5 0x18a5 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18a5 18a5 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 18a6 0x18a6 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 18a6 18a6 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1899 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1899 0x1899 seq_en_micro 0 seq_random 02 ? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_frame 2 18a7 18a7 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 18a8 18a8 fiu_mem_start 4 continue typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 18a9 18a9 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 18aa 18aa fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x18ad fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18ad 0x18ad typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 18ab 18ab fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 18ac 0x18ac seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 18ac 18ac fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1899 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1899 0x1899 seq_en_micro 0 seq_random 02 ? typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE 18ad 18ad fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 7 18ae ; -------------------------------------------------------------------------------------- 18ae ; 0x01db Execute Vector,Length 18ae ; -------------------------------------------------------------------------------------- 18ae MACRO_Execute_Vector,Length: 18ae 18ae dispatch_brk_class 8 ; Flow J cc=True 0x1899 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 18ae fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 1899 0x1899 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 18af 18af fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1899 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1899 0x1899 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 18b0 ; -------------------------------------------------------------------------------------- 18b0 ; 0x01da Execute Vector,Bounds 18b0 ; -------------------------------------------------------------------------------------- 18b0 MACRO_Execute_Vector,Bounds: 18b0 18b0 dispatch_brk_class 8 ; Flow J cc=True 0x18b7 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 18b0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 18b7 0x18b7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR0c:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 18b1 18b1 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x18b4 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18b4 0x18b4 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 18b2 18b2 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 18b3 18b3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x18a5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 18a5 0x18a5 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18b4 18b4 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18b5 18b5 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 18b6 18b6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x18a5 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 18a5 0x18a5 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18b7 18b7 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 18b8 18b8 fiu_mem_start 4 continue typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 18b9 18b9 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 18ba 18ba ioc_tvbs c mem+mem+csa+dummy; Flow J 0x18aa seq_br_type 3 Unconditional Branch seq_branch_adr 18aa 0x18aa seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 18bb 18bb <halt> ; Flow R 18bc ; -------------------------------------------------------------------------------------- 18bc ; 0x01d9 Execute Vector,Reverse_Bounds 18bc ; -------------------------------------------------------------------------------------- 18bc MACRO_Execute_Vector,Reverse_Bounds: 18bc 18bc dispatch_brk_class 8 ; Flow J cc=True 0x18c5 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 18bc fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 18c5 0x18c5 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR0c:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_frame 2 18bd 18bd fiu_mem_start a start_continue_if_false; Flow J cc=False 0x18c0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18c0 0x18c0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 18be 18be fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 5 18bf 18bf fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x18c3 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 18c3 0x18c3 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18c0 18c0 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18c1 18c1 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 5 18c2 18c2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x18c3 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 18c3 0x18c3 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18c3 18c3 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 18c4 0x18c4 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 18c4 18c4 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x18cd fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 18cd 0x18cd typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_frame 2 18c5 18c5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 18c6 18c6 fiu_mem_start 4 continue typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 18c7 18c7 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 18c8 18c8 ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 18c9 18c9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x18cc fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18cc 0x18cc typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18ca 18ca fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 18cb 0x18cb seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 18cb 18cb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x18cd fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 18cd 0x18cd typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE 18cc 18cc fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 7 18cd 18cd fiu_mem_start a start_continue_if_false; Flow J cc=False 0x18cf seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18cf 0x18cf seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 18ce 18ce fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 18cf 18cf fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18d0 18d0 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 18d1 18d1 <halt> ; Flow R 18d2 ; -------------------------------------------------------------------------------------- 18d2 ; 0x01d8 Execute Vector,Element_Type 18d2 ; -------------------------------------------------------------------------------------- 18d2 MACRO_Execute_Vector,Element_Type: 18d2 18d2 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 18d2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 18d3 18d3 typ_a_adr 10 TOP typ_c_lit 0 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 18d4 18d4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 18d5 18d5 <halt> ; Flow R 18d6 ; -------------------------------------------------------------------------------------- 18d6 ; 0x01d7 Execute Vector,Field_Read 18d6 ; -------------------------------------------------------------------------------------- 18d6 MACRO_Execute_Vector,Field_Read: 18d6 18d6 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18d6 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18d7 18d7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x18e5 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18e5 0x18e5 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18d8 18d8 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x18e2 fiu_load_tar 1 hold_tar fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 18e2 0x18e2 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 18d9 18d9 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x18eb fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 18eb 0x18eb seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18da 18da fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18dc fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18dc 0x18dc seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 18db 18db fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x18de fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 18de 0x18de seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 18dc 18dc fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18dd 18dd fiu_fill_mode_src 0 ; Flow R cc=True fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 18de 0x18de seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4a) Heap_Access_Var seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 18de 18de seq_br_type 0 Branch False; Flow J cc=False 0x18e1 seq_branch_adr 18e1 0x18e1 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 18df 18df fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 18e0 0x18e0 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 18e0 18e0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 18e1 18e1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 18e2 18e2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18e3 18e3 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x18da fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18da 0x18da seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 18e4 18e4 fiu_load_oreg 1 hold_oreg; Flow J 0x18da fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 18da 0x18da seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18e5 18e5 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 18e6 18e6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18ec fiu_mem_start a start_continue_if_false fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 18ec 0x18ec seq_cond_sel 64 OFFSET_REGISTER_???? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 18e7 18e7 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18e8 18e8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x18ef fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18ef 0x18ef seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18e9 18e9 ioc_fiubs 1 val ; Flow J cc=False 0x18f2 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 18f2 0x18f2 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 18ea 18ea fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x18da fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 18da 0x18da seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18eb 18eb seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 18ec 18ec fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 18ed 18ed fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 18ee 18ee fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x18e9 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18e9 0x18e9 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18ef 18ef ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 18f0 18f0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18f1 18f1 fiu_load_oreg 1 hold_oreg; Flow J 0x18da fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 18da 0x18da seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18f2 18f2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18f3 18f3 fiu_load_oreg 1 hold_oreg; Flow J 0x18da fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 18da 0x18da seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18f4 ; -------------------------------------------------------------------------------------- 18f4 ; 0x018b Execute Subvector,Field_Read 18f4 ; -------------------------------------------------------------------------------------- 18f4 MACRO_Execute_Subvector,Field_Read: 18f4 18f4 dispatch_brk_class 8 ; Flow J 0x18d7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18f4 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 18d7 0x18d7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 2 typ_frame 4 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18f5 18f5 <halt> ; Flow R 18f6 ; -------------------------------------------------------------------------------------- 18f6 ; 0x01d6 Execute Vector,Field_Write 18f6 ; -------------------------------------------------------------------------------------- 18f6 MACRO_Execute_Vector,Field_Write: 18f6 18f6 dispatch_brk_class 2 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 18f6 dispatch_uses_tos 1 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 8 type_var seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 18f7 18f7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x18fe fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 18fe 0x18fe seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 18f8 18f8 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x18fb fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 18fb 0x18fb seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 18f9 18f9 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d78 0x1d78 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 18fa 18fa seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 18fb 18fb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 18fc 18fc fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1d78 0x1d78 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 18fd 18fd fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d78 0x1d78 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 18fe 18fe fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 18ff 18ff fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1905 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1905 0x1905 seq_cond_sel 64 OFFSET_REGISTER_???? typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1900 1900 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1901 1901 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1908 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1908 0x1908 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1902 1902 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x190b fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 190b 0x190b typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 01 GP01 val_rand c START_MULTIPLY 1903 1903 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d78 0x1d78 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1904 1904 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 1905 1905 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1906 1906 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1907 1907 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1902 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1902 0x1902 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1908 1908 ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 1909 1909 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 190a 190a fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d78 0x1d78 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 190b 190b seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand a PASS_B_HIGH 190c 190c fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d78 0x1d78 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 190d 190d <halt> ; Flow R 190e ; -------------------------------------------------------------------------------------- 190e ; 0x018a Execute Subvector,Field_Write 190e ; -------------------------------------------------------------------------------------- 190e MACRO_Execute_Subvector,Field_Write: 190e 190e dispatch_brk_class 2 ; Flow J 0x18f7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 190e dispatch_uses_tos 1 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 18f7 0x18f7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 2 typ_frame 4 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 190f 190f <halt> ; Flow R 1910 ; -------------------------------------------------------------------------------------- 1910 ; 0x01d5 Execute Vector,Field_Reference 1910 ; -------------------------------------------------------------------------------------- 1910 MACRO_Execute_Vector,Field_Reference: 1910 1910 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1910 dispatch_uses_tos 1 fiu_mem_start 4 continue seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 1911 1911 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1918 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1918 0x1918 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1912 1912 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1915 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1915 0x1915 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1913 1913 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 1914 0x1914 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1914 1914 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1915 1915 ioc_tvbs 2 fiu+val; Flow J cc=False 0x1914 seq_br_type 0 Branch False seq_branch_adr 1914 0x1914 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1916 1916 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1917 0x1917 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1917 1917 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1918 1918 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1919 1919 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1920 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1920 0x1920 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 191a 191a fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 191b 191b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1923 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1923 0x1923 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 191c 191c fiu_load_tar 1 hold_tar; Flow J cc=False 0x191e fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 191e 0x191e typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 191d 191d fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x1914 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 1914 0x1914 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 191e 191e seq_br_type 4 Call False; Flow C cc=False 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand a PASS_B_HIGH 191f 191f fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1920 1920 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1921 1921 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1922 1922 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x191c fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 191c 0x191c seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1923 1923 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 1924 1924 seq_br_type 4 Call False; Flow C cc=False 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 1925 1925 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1926 ; -------------------------------------------------------------------------------------- 1926 ; 0x0189 Execute Subvector,Field_Reference 1926 ; -------------------------------------------------------------------------------------- 1926 MACRO_Execute_Subvector,Field_Reference: 1926 1926 dispatch_brk_class 8 ; Flow J 0x1911 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1926 dispatch_uses_tos 1 fiu_mem_start 4 continue seq_br_type 3 Unconditional Branch seq_branch_adr 1911 0x1911 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 2 typ_frame 4 typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH 1927 1927 <halt> ; Flow R 1928 ; -------------------------------------------------------------------------------------- 1928 ; 0x01d4 Execute Vector,Structure_Write 1928 ; -------------------------------------------------------------------------------------- 1928 MACRO_Execute_Vector,Structure_Write: 1928 1928 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1928 dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1929 1929 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e1a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e1a 0x1e1a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 192a ; -------------------------------------------------------------------------------------- 192a ; 0x01d1 Execute Vector,Xor 192a ; 0x01d2 Execute Vector,Or 192a ; 0x01d3 Execute Vector,And 192a ; -------------------------------------------------------------------------------------- 192a MACRO_Execute_Vector,And: 192a MACRO_Execute_Vector,Or: 192a MACRO_Execute_Vector,Xor: 192a 192a dispatch_brk_class 8 ; Flow C cc=False 0x1af3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 192a dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1af3 0x1af3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 192b 192b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1930 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1930 0x1930 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 192c 192c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x192e seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 192e 0x192e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 192d 192d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1931 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1931 0x1931 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 192e 192e fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 192f 192f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1931 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1931 0x1931 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1930 1930 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1931 1931 fiu_mem_start 4 continue ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_frame 2 1932 1932 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1933 1933 fiu_fill_mode_src 0 ; Flow J cc=True 0x1935 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 60 fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1935 0x1935 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1934 1934 ioc_fiubs 2 typ ; Flow J 0x193f seq_br_type 3 Unconditional Branch seq_branch_adr 193f 0x193f val_a_adr 03 GP03 val_b_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 1935 1935 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1937 ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1937 0x1937 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_frame 2 1936 1936 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1939 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1939 0x1939 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1937 1937 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1938 1938 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1939 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1939 0x1939 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1939 1939 fiu_fill_mode_src 0 ; Flow J cc=False 0x193b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 193b 0x193b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 193a 193a fiu_fill_mode_src 0 ; Flow J 0x193d fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 193d 0x193d typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 193b 193b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 193c 193c fiu_fill_mode_src 0 ; Flow J 0x193d fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 193d 0x193d typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 193d 193d ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 193e 193e ioc_fiubs 2 typ ; Flow J 0x193f seq_br_type 3 Unconditional Branch seq_branch_adr 193f 0x193f typ_a_adr 03 GP03 val_a_adr 03 GP03 val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 193f 193f fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32a3 fiu_load_var 1 hold_var fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1940 1940 fiu_len_fill_lit 7d zero-fill 0x3d; Flow J cc=True 0x1943 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1943 0x1943 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1941 1941 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x194d seq_br_type f Unconditional Case Call seq_branch_adr 194d 0x194d seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1942 1942 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1943 1943 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x1948 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 1948 0x1948 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1944 1944 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1949 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1949 0x1949 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 2d VR05:0d val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 1945 1945 fiu_fill_mode_src 0 ; Flow J 0x1946 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1946 0x1946 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1946 1946 fiu_fill_mode_src 0 ; Flow J cc=False 0x194b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 194b 0x194b seq_cond_sel 65 CROSS_WORD_FIELD~ 1947 1947 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1948 1948 ioc_load_wdr 0 ; Flow J 0x1942 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1942 0x1942 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 1949 1949 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 194a 194a fiu_fill_mode_src 0 ; Flow J 0x1946 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1946 0x1946 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 194b 194b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 194c 194c fiu_fill_mode_src 0 ; Flow J 0x1948 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1948 0x1948 typ_mar_cntl 6 INCREMENT_MAR 194d ; -------------------------------------------------------------------------------------- 194d ; Comes from: 194d ; 1941 C #0x0 from color MACRO_Execute_Vector,And 194d ; -------------------------------------------------------------------------------------- 194d 194d seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 194e 194e seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 194f 194f seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 1950 1950 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 1951 1951 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x195d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 195d 0x195d typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 1952 1952 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1961 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1961 0x1961 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1953 1953 ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x1951 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 1951 0x1951 1954 1954 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 1955 1955 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x195d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 195d 0x195d typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 1956 1956 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1961 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1961 0x1961 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1957 1957 ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x1955 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 1955 0x1955 1958 1958 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 1959 1959 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x195d fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 195d 0x195d typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 01 GP01 195a 195a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1961 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1961 0x1961 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1e A_AND_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 195b 195b ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x1959 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 1959 0x1959 195c 195c seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d 195d ; -------------------------------------------------------------------------------------- 195d ; Comes from: 195d ; 1951 C from color 0x194d 195d ; 1955 C from color 0x1954 195d ; 1959 C from color 0x1958 195d ; -------------------------------------------------------------------------------------- 195d 195d fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1963 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1963 0x1963 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 195e 195e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 195f 195f fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1965 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1965 0x1965 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1960 1960 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ab4 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1961 ; -------------------------------------------------------------------------------------- 1961 ; Comes from: 1961 ; 1952 C from color 0x194d 1961 ; 1956 C from color 0x1954 1961 ; 195a C from color 0x1958 1961 ; -------------------------------------------------------------------------------------- 1961 1961 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1967 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1967 0x1967 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 1962 1962 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return 1963 1963 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1964 1964 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x195f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 195f 0x195f seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1965 1965 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1966 1966 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ab4 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1967 1967 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1968 1968 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 1969 1969 <halt> ; Flow R 196a ; -------------------------------------------------------------------------------------- 196a ; 0x01d0 Execute Vector,Complement 196a ; -------------------------------------------------------------------------------------- 196a MACRO_Execute_Vector,Complement: 196a 196a dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 196a dispatch_uses_tos 1 fiu_mem_start 4 continue ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 196b 196b fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3e GP01 val_c_source 0 FIU_BUS 196c 196c fiu_fill_mode_src 0 ; Flow J cc=True 0x196e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 60 fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 196e 0x196e seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 196d 196d ioc_fiubs 2 typ ; Flow J 0x1978 seq_br_type 3 Unconditional Branch seq_branch_adr 1978 0x1978 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 196e 196e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1970 ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1970 0x1970 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 21 VR02:01 val_frame 2 196f 196f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1972 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1972 0x1972 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1970 1970 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1971 1971 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1972 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1972 0x1972 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1972 1972 fiu_fill_mode_src 0 ; Flow J cc=False 0x1974 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1974 0x1974 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1973 1973 fiu_fill_mode_src 0 ; Flow J 0x1976 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1976 0x1976 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 1974 1974 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1975 1975 fiu_fill_mode_src 0 ; Flow J 0x1976 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1976 0x1976 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 1976 1976 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 1977 1977 ioc_fiubs 2 typ ; Flow J 0x1978 seq_br_type 3 Unconditional Branch seq_branch_adr 1978 0x1978 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 1978 1978 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1989 seq_br_type 1 Branch True seq_branch_adr 1989 0x1989 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1979 1979 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 197a 197a seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 197b 197b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x197e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 197e 0x197e seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B 197c 197c seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 197d 197d fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B 197e 197e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1985 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1985 0x1985 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 197f 197f fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1980 1980 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 10 NOT_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1981 1981 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1987 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1987 0x1987 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 1982 1982 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1983 1983 ioc_load_wdr 0 ; Flow J cc=False 0x197b ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 197b 0x197b 1984 1984 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1985 1985 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1986 1986 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1980 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1980 0x1980 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1987 1987 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1988 1988 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1983 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1983 0x1983 typ_mar_cntl 6 INCREMENT_MAR 1989 1989 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x198e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 198e 0x198e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 10 TOP typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 3d GP02 val_c_source 0 FIU_BUS 198a 198a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x198f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 198f 0x198f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 2d VR05:0d val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 198b 198b fiu_fill_mode_src 0 ; Flow J 0x198c fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 198c 0x198c typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 198c 198c fiu_fill_mode_src 0 ; Flow J cc=False 0x1991 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1991 0x1991 seq_cond_sel 65 CROSS_WORD_FIELD~ 198d 198d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 198e 198e ioc_load_wdr 0 ; Flow J 0x1984 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1984 0x1984 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 198f 198f fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1990 1990 fiu_fill_mode_src 0 ; Flow J 0x198c fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 198c 0x198c typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1991 1991 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1992 1992 fiu_fill_mode_src 0 ; Flow J 0x198e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 198e 0x198e typ_mar_cntl 6 INCREMENT_MAR 1993 1993 <halt> ; Flow R 1994 ; -------------------------------------------------------------------------------------- 1994 ; 0x01cf Execute Vector,Slice_Read 1994 ; -------------------------------------------------------------------------------------- 1994 MACRO_Execute_Vector,Slice_Read: 1994 1994 dispatch_brk_class 8 ; Flow C cc=True 0x32de dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1994 dispatch_uses_tos 1 fiu_mem_start 4 continue ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B val_b_adr 10 TOP 1995 1995 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1996 1996 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x19b6 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19b6 0x19b6 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 1997 1997 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x199a fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 199a 0x199a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1998 1998 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1999 1999 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 199a 199a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_frame 2 199b 199b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x19ad fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19ad 0x19ad seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 5 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 199c 199c ioc_fiubs 0 fiu ; Flow C cc=False 0x32cc ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 199d 199d ioc_fiubs 1 val ; Flow C cc=False 0x32a2 seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 05 GP05 val_rand c START_MULTIPLY 199e 199e ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 199f 199f fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 19a0 19a0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_var 1 hold_var fiu_rdata_src 0 rotator seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 19a1 19a1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x19aa fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19aa 0x19aa seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19a2 19a2 fiu_tivi_src c mar_0xc; Flow C cc=False 0x32dc ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 6 19a3 19a3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 19a4 19a4 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 19a5 19a5 fiu_mem_start 2 start-rd; Flow J cc=False 0x19a9 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 19a9 0x19a9 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 19a6 19a6 ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 19a7 19a7 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 19a8 19a8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 05 GP05 typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 19a9 19a9 ioc_fiubs 2 typ ; Flow C 0x32cc seq_br_type 7 Unconditional Call seq_branch_adr 32cc 0x32cc seq_en_micro 0 typ_a_adr 05 GP05 val_c_adr 1e VR02:01 val_c_source 0 FIU_BUS val_frame 2 19aa 19aa fiu_tivi_src c mar_0xc; Flow C cc=False 0x32dc ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 6 19ab 19ab fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 19ac 19ac fiu_fill_mode_src 0 ; Flow J 0x19a4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 19a4 0x19a4 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 19ad 19ad fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32cc fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 19ae 19ae fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19b2 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19b2 0x19b2 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 19af 19af fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 19b0 19b0 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_frame 2 19b1 19b1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x199d fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 199d 0x199d typ_a_adr 14 ZEROS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19b2 19b2 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19b3 19b3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy 19b4 19b4 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_frame 2 19b5 19b5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x199d fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 199d 0x199d typ_a_adr 14 ZEROS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19b6 19b6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32dc fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 30 TR05:10 typ_frame 5 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 6 19b7 19b7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32cc fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 19b8 19b8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 19b9 19b9 fiu_fill_mode_src 0 ; Flow J cc=False 0x19c0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19c0 0x19c0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 19ba 19ba fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 19bb 19bb fiu_fill_mode_src 0 ; Flow C cc=False 0x32dc fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 19bc 19bc fiu_fill_mode_src 0 ; Flow J cc=True 0x19c3 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 19c3 0x19c3 seq_cond_sel 64 OFFSET_REGISTER_???? 19bd 19bd fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 19be 19be ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 19bf 19bf fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 19c0 19c0 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 19c1 19c1 fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 19c2 19c2 fiu_fill_mode_src 0 ; Flow C cc=False 0x32dc fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 19c3 19c3 fiu_fill_mode_src 0 ; Flow J 0x19be fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 3 insert seq_br_type 3 Unconditional Branch seq_branch_adr 19be 0x19be seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 19c4 ; -------------------------------------------------------------------------------------- 19c4 ; 0x01ce Execute Vector,Slice_Write 19c4 ; -------------------------------------------------------------------------------------- 19c4 MACRO_Execute_Vector,Slice_Write: 19c4 19c4 dispatch_brk_class 2 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 19c4 dispatch_uses_tos 1 fiu_mem_start 4 continue ioc_fiubs 1 val seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 19c5 19c5 fiu_load_tar 1 hold_tar; Flow C cc=False 0x19ec fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 19ec 0x19ec seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 19c6 19c6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x19e7 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19e7 0x19e7 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_rand c START_MULTIPLY 19c7 19c7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x19ca fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19ca 0x19ca seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 19c8 19c8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 19c9 19c9 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 19ca 19ca fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x19d5 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19d5 0x19d5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19cb 19cb ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19cc 19cc ioc_fiubs 1 val ; Flow C cc=False 0x32a2 seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_rand c START_MULTIPLY 19cd 19cd ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 19ce 19ce fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 1d TOP - 3 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 19cf 19cf fiu_mem_start a start_continue_if_false seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 1d TOP - 3 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 19d0 19d0 ioc_load_wdr 0 ; Flow J cc=True 0x19de ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 19de 0x19de seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) seq_latch 1 typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 19d1 19d1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x19e9 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 19e9 0x19e9 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19d2 19d2 ioc_fiubs 1 val ; Flow C cc=True 0x32a3 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19d3 19d3 ioc_fiubs 1 val ; Flow C cc=True 0x1f1e seq_br_type 5 Call True seq_branch_adr 1f1e 0x1f1e seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 02 GP02 19d4 19d4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 19d5 19d5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 19d6 19d6 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19da seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19da 0x19da seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 19d7 19d7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 19d8 19d8 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 19d9 19d9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x19cc fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 19cc 0x19cc typ_a_adr 14 ZEROS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19da 19da fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19db 19db fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy 19dc 19dc fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 19dd 19dd fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x19cc fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 19cc 0x19cc typ_a_adr 14 ZEROS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19de 19de fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_c_adr 3a GP05 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1d TOP - 3 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 19df 19df fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19e3 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19e3 0x19e3 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 19e0 19e0 fiu_fill_mode_src 0 ; Flow C cc=False 0x19e9 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 19e9 0x19e9 seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19e1 19e1 ioc_fiubs 1 val ; Flow C cc=True 0x32a3 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 19e2 19e2 seq_br_type 3 Unconditional Branch; Flow J 0x19d3 seq_branch_adr 19d3 0x19d3 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 19e3 19e3 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19e4 19e4 fiu_fill_mode_src 0 ; Flow C cc=False 0x19e9 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 19e9 0x19e9 seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19e5 19e5 ioc_fiubs 1 val ; Flow C cc=True 0x32a3 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 19e6 19e6 seq_br_type 3 Unconditional Branch; Flow J 0x19d3 seq_branch_adr 19d3 0x19d3 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 19e7 19e7 ioc_fiubs 1 val ; Flow C cc=True 0x32de seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 19e8 19e8 seq_br_type 3 Unconditional Branch; Flow J 0x19ce seq_branch_adr 19ce 0x19ce val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand c START_MULTIPLY 19e9 ; -------------------------------------------------------------------------------------- 19e9 ; Comes from: 19e9 ; 19d1 C False from color MACRO_Execute_Vector,Slice_Write 19e9 ; 19e0 C False from color MACRO_Execute_Vector,Slice_Write 19e9 ; 19e4 C False from color MACRO_Execute_Vector,Slice_Write 19e9 ; -------------------------------------------------------------------------------------- 19e9 19e9 ioc_fiubs 1 val ; Flow C cc=True 0x32db seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 22 VR02:02 val_frame 2 19ea 19ea ioc_tvbs 5 seq+seq; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 19eb 0x19eb seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS 19eb 19eb seq_br_type 7 Unconditional Call; Flow C 0x32db seq_branch_adr 32db 0x32db 19ec ; -------------------------------------------------------------------------------------- 19ec ; Comes from: 19ec ; 19c5 C False from color MACRO_Execute_Vector,Slice_Write 19ec ; -------------------------------------------------------------------------------------- 19ec 19ec fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1d TOP - 3 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 19ed 19ed fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 19ee 19ee seq_br_type a Unconditional Return; Flow R 19ef 19ef <halt> ; Flow R 19f0 ; -------------------------------------------------------------------------------------- 19f0 ; 0x01cd Execute Vector,Slice_Reference 19f0 ; -------------------------------------------------------------------------------------- 19f0 MACRO_Execute_Vector,Slice_Reference: 19f0 19f0 dispatch_brk_class 2 ; Flow C cc=False 0x1af3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 19f0 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 1af3 0x1af3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 19f1 19f1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x19fa fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 19fa 0x19fa seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 19f2 19f2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32de fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 26 TR06:06 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 10 TOP 19f3 19f3 fiu_mem_start 4 continue ioc_tvbs 2 fiu+val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 19f4 19f4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x19f9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 19f9 0x19f9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 19f5 19f5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a3 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 19f6 19f6 ioc_tvbs 3 fiu+fiu typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 19f7 19f7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a3 seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 01 GP01 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 19f8 19f8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 19f9 19f9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 19fa ; -------------------------------------------------------------------------------------- 19fa ; Comes from: 19fa ; 19f1 C True from color MACRO_Execute_Vector,Slice_Reference 19fa ; -------------------------------------------------------------------------------------- 19fa 19fa fiu_mem_start a start_continue_if_false; Flow J cc=False 0x19fd seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 19fd 0x19fd seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 19fb 19fb fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 19fc 19fc fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 19fd 19fd fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 19fe 19fe fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 19ff 19ff fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 1a00 ; -------------------------------------------------------------------------------------- 1a00 ; 0x01cc Execute Vector,Catenate 1a00 ; -------------------------------------------------------------------------------------- 1a00 MACRO_Execute_Vector,Catenate: 1a00 1a00 dispatch_brk_class 8 ; Flow C cc=False 0x1af3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1a00 dispatch_uses_tos 1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 20 ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 1af3 0x1af3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1a01 1a01 fiu_fill_mode_src 0 ; Flow J cc=False 0x1a08 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1a08 0x1a08 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a02 1a02 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1a05 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a05 0x1a05 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 1a03 1a03 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 1a04 1a04 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1a09 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a09 0x1a09 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a05 1a05 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a06 1a06 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 1a07 1a07 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1a09 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a09 0x1a09 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a08 1a08 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a09 1a09 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 1a0a 1a0a fiu_mem_start a start_continue_if_false; Flow C cc=True 0x32a9 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT 1a0b 1a0b fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1a0c 1a0c fiu_fill_mode_src 0 ; Flow J cc=False 0x1a13 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 60 fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1a13 0x1a13 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 2c TR06:0c typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1a0d 1a0d fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1a10 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a10 0x1a10 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1a0e 1a0e fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 1a0f 1a0f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1a13 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a13 0x1a13 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 1a10 1a10 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a11 1a11 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 1a12 1a12 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1a13 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a13 0x1a13 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 1a13 1a13 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 2 typ ioc_fiubs 2 typ seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 1a14 1a14 fiu_load_var 1 hold_var; Flow J cc=True 0x1a16 fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a16 0x1a16 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1a15 1a15 seq_b_timing 1 Latch Condition; Flow C cc=False 0x32dc seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc 1a16 1a16 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 04 GP04 val_b_adr 05 GP05 val_rand c START_MULTIPLY 1a17 1a17 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 val_m_a_src 2 Bits 32…47 1a18 1a18 fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1a19 1a19 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1a28 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a28 0x1a28 seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 1a1a 1a1a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a2 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0e GP0e val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 1a1b 1a1b fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 1a1c 1a1c seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1a1d 1a1d ioc_fiubs 1 val typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 1a1e 1a1e fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a1f 1a1f fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A 1a20 1a20 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1a22 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a22 0x1a22 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 1a21 1a21 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1a24 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a24 0x1a24 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1a22 1a22 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1a23 1a23 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1a24 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a24 0x1a24 typ_mar_cntl 6 INCREMENT_MAR 1a24 1a24 ioc_load_wdr 0 ; Flow C 0x1f1e ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 seq_random 02 ? 1a25 1a25 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a26 1a26 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1f1e fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1a27 1a27 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1a28 1a28 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 1a29 1a29 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 1a2a 1a2a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1a1f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a1f 0x1a1f seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a2b 1a2b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1a2e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 1a2e 0x1a2e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE 1a2c 1a2c fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_frame 2 1a2d 1a2d fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1a2f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a2f 0x1a2f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1a2e 1a2e fiu_fill_mode_src 0 ; Flow J 0x1a32 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a32 0x1a32 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A 1a2f 1a2f fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a30 1a30 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1a31 1a31 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1a32 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1a32 0x1a32 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A 1a32 1a32 fiu_fill_mode_src 0 ; Flow J cc=False 0x1a39 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a39 0x1a39 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 1a33 1a33 fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1a34 1a34 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR01:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 1a35 1a35 fiu_fill_mode_src 0 ; Flow J cc=True 0x1a3c fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1a3c 0x1a3c seq_cond_sel 64 OFFSET_REGISTER_???? 1a36 1a36 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_mar_cntl 6 INCREMENT_MAR 1a37 1a37 ioc_fiubs 2 typ ; Flow C cc=True 0x32dc ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dc 0x32dc seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1a38 1a38 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1a39 1a39 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1a3a 1a3a fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1a3b 1a3b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR01:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 1a3c 1a3c fiu_fill_mode_src 0 ; Flow J 0x1a37 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 3 insert seq_br_type 3 Unconditional Branch seq_branch_adr 1a37 0x1a37 typ_mar_cntl 6 INCREMENT_MAR 1a3d 1a3d <halt> ; Flow R 1a3e ; -------------------------------------------------------------------------------------- 1a3e ; 0x01cb Execute Vector,Append 1a3e ; -------------------------------------------------------------------------------------- 1a3e MACRO_Execute_Vector,Append: 1a3e 1a3e dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1a3e fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a3f 1a3f fiu_mem_start 4 continue ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a40 1a40 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_mem_start a start_continue_if_false fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1a41 1a41 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32cc fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1a42 1a42 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3a GP05 val_c_source 0 FIU_BUS 1a43 1a43 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1a52 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a52 0x1a52 typ_c_adr 3c GP03 val_a_adr 03 GP03 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1a44 1a44 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a45 1a45 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x1a47 seq_br_type 1 Branch True seq_branch_adr 1a47 0x1a47 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a46 1a46 val_c_adr 3c GP03 1a47 1a47 ioc_tvbs 2 fiu+val; Flow C cc=False 0x32a2 seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 14 ZEROS typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B 1a48 1a48 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 1a49 1a49 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1a4a 1a4a fiu_fill_mode_src 0 ; Flow J cc=False 0x1a50 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a50 0x1a50 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1a4b 1a4b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32cc fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a4c 1a4c ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2c TR06:0c typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 6 1a4d 1a4d fiu_vmux_sel 1 fill value; Flow C cc=True 0x1f1e ioc_fiubs 0 fiu seq_br_type 5 Call True seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1a4e 1a4e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1a4f 1a4f fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d78 0x1d78 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 20 TOP - 0x1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1a50 1a50 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32cc fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a51 1a51 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1a4c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a4c 0x1a4c typ_mar_cntl 6 INCREMENT_MAR 1a52 1a52 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 35 TR07:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 1a53 1a53 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1a5c ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a5c 0x1a5c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1a54 1a54 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a55 1a55 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x1a5f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1a5f 0x1a5f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1a56 1a56 ioc_tvbs 1 typ+fiu typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1a57 1a57 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a2 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B 1a58 1a58 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1a59 1a59 ioc_fiubs 1 val ; Flow J cc=True 0x1a49 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a49 0x1a49 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 1a5a 1a5a seq_b_timing 1 Latch Condition; Flow J cc=True 0x1a49 seq_br_type 1 Branch True seq_branch_adr 1a49 0x1a49 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1a5b 1a5b seq_br_type 3 Unconditional Branch; Flow J 0x1a49 seq_branch_adr 1a49 0x1a49 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1a5c 1a5c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a5d 1a5d fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a5e 1a5e fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x1a56 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1a56 0x1a56 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1a5f 1a5f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator 1a60 1a60 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32dc seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_frame 6 1a61 1a61 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1a56 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a56 0x1a56 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 1a62 ; -------------------------------------------------------------------------------------- 1a62 ; 0x01ca Execute Vector,Prepend 1a62 ; -------------------------------------------------------------------------------------- 1a62 MACRO_Execute_Vector,Prepend: 1a62 1a62 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1a62 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a63 1a63 fiu_mem_start 4 continue ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a64 1a64 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_mem_start a start_continue_if_false fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1a65 1a65 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32cc fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1a66 1a66 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3a GP05 val_c_source 0 FIU_BUS 1a67 1a67 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1a74 fiu_len_fill_reg_ctl 1 len=literal, fill=literal seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a74 0x1a74 typ_c_adr 3c GP03 val_a_adr 07 GP07 val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a68 1a68 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32cc fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1a69 1a69 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32a2 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1a6a 1a6a fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 22 VR06:02 val_frame 6 1a6b 1a6b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1a6c 1a6c fiu_fill_mode_src 0 ; Flow J cc=False 0x1a72 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a72 0x1a72 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a6d 1a6d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32cc fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a6e 1a6e ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 2c TR06:0c typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 6 1a6f 1a6f fiu_vmux_sel 1 fill value; Flow C cc=True 0x1f1e ioc_fiubs 0 fiu seq_br_type 5 Call True seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1a70 1a70 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_b_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1a71 1a71 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d78 0x1d78 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 20 TOP - 0x1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1a72 1a72 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32cc fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a73 1a73 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1a6e fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1a6e 0x1a6e typ_mar_cntl 6 INCREMENT_MAR 1a74 1a74 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 1a75 1a75 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1a7c fiu_load_var 1 hold_var fiu_mem_start a start_continue_if_false fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a7c 0x1a7c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1a76 1a76 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1a77 1a77 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32a2 seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1a78 1a78 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1a79 1a79 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1a6a fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a6a 0x1a6a seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 1a7a 1a7a seq_b_timing 1 Latch Condition; Flow J cc=True 0x1a6a seq_br_type 1 Branch True seq_branch_adr 1a6a 0x1a6a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1a7b 1a7b seq_br_type 3 Unconditional Branch; Flow J 0x1a6a seq_branch_adr 1a6a 0x1a6a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1a7c 1a7c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a7d 1a7d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1a7e 1a7e fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1a77 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 1a77 0x1a77 1a7f ; -------------------------------------------------------------------------------------- 1a7f ; Comes from: 1a7f ; 1acc C True from color 0x0a2f 1a7f ; 1ad4 C True from color 0x0a2f 1a7f ; 1aea C True from color 0x0aa1 1a7f ; -------------------------------------------------------------------------------------- 1a7f 1a7f fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1a80 1a80 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1a82 seq_br_type 1 Branch True seq_branch_adr 1a82 0x1a82 1a81 1a81 fiu_fill_mode_src 0 ; Flow J 0x1a83 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a83 0x1a83 typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 1a82 1a82 fiu_fill_mode_src 0 ; Flow J 0x1a83 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1a83 0x1a83 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1a83 1a83 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1a85 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a85 0x1a85 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1a84 1a84 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1a85 1a85 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a86 1a86 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1a87 1a87 <halt> ; Flow R 1a88 ; -------------------------------------------------------------------------------------- 1a88 ; 0x01c7 Execute Vector,Convert 1a88 ; -------------------------------------------------------------------------------------- 1a88 MACRO_Execute_Vector,Convert: 1a88 1a88 dispatch_brk_class 4 ; Flow C cc=False 0x1af3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1a88 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1af3 0x1af3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1a89 1a89 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1a8a 1a8a seq_b_timing 1 Latch Condition; Flow J cc=True 0x1aa2 seq_br_type 1 Branch True seq_branch_adr 1aa2 0x1aa2 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1a8b 1a8b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1a95 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1a95 0x1a95 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1a8c 1a8c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_frame 2 1a8d 1a8d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 1a8e 1a8e fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1a8f 1a8f fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 1a90 1a90 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1a92 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1a92 0x1a92 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a91 1a91 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32cc seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1a92 1a92 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 3a GP05 typ_frame 2 1a93 1a93 ioc_fiubs 1 val ; Flow C cc=True 0x1f1e seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP 1a94 1a94 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1a95 ; -------------------------------------------------------------------------------------- 1a95 ; Comes from: 1a95 ; 1a8b C True from color 0x0a2f 1a95 ; 1aa2 C True from color 0x0a2f 1a95 ; 1acb C True from color 0x0a2f 1a95 ; -------------------------------------------------------------------------------------- 1a95 1a95 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1a98 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1a98 0x1a98 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1a96 1a96 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 5 1a97 1a97 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1a98 1a98 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1a99 1a99 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 5 1a9a 1a9a fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1a9b ; -------------------------------------------------------------------------------------- 1a9b ; Comes from: 1a9b ; 1abd C False from color 0x0a2f 1a9b ; -------------------------------------------------------------------------------------- 1a9b 1a9b fiu_mem_start 2 start-rd; Flow J 0x1aa0 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1aa0 0x1aa0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a9c ; -------------------------------------------------------------------------------------- 1a9c ; Comes from: 1a9c ; 1aa3 C False from color 0x0a2f 1a9c ; -------------------------------------------------------------------------------------- 1a9c 1a9c fiu_mem_start 2 start-rd; Flow C 0x1aa0 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1aa0 0x1aa0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a9d 1a9d fiu_mem_start 2 start-rd; Flow J 0x332e ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a9e ; -------------------------------------------------------------------------------------- 1a9e ; Comes from: 1a9e ; 1aa7 C False from color 0x0a2f 1a9e ; -------------------------------------------------------------------------------------- 1a9e 1a9e fiu_mem_start 2 start-rd; Flow C 0x1aa0 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1aa0 0x1aa0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1a9f 1a9f fiu_mem_start 2 start-rd; Flow J 0x332e ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1aa0 1aa0 <default> 1aa1 1aa1 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x32a2 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32a2 0x32a2 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 31 TR02:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 1aa2 1aa2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1a95 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1a95 0x1a95 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1aa3 1aa3 fiu_load_var 1 hold_var; Flow C cc=False 0x1a9c fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 1a9c 0x1a9c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B 1aa4 1aa4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1aa5 1aa5 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x1abc seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1abc 0x1abc typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1aa6 1aa6 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1aa7 1aa7 seq_br_type 4 Call False; Flow C cc=False 0x1a9e seq_branch_adr 1a9e 0x1a9e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3a GP05 typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 1aa8 1aa8 ioc_fiubs 1 val ; Flow C cc=True 0x32a9 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 1aa9 1aa9 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1aaa 1aaa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1aac fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1aac 0x1aac seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1aab 1aab ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32cc seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1aac 1aac fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 06 GP06 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_b_adr 04 GP04 1aad 1aad fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32cc fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1aae 1aae fiu_fill_mode_src 0 ; Flow J cc=False 0x1ab8 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ab8 0x1ab8 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 1aaf 1aaf fiu_fill_mode_src 0 ; Flow C cc=False 0x32dc fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_frame 6 1ab0 1ab0 ioc_load_wdr 0 ; Flow C cc=True 0x1f1e ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 1ab1 1ab1 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 1ab2 0x1ab2 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ab2 1ab2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1ab3 1ab3 fiu_fill_mode_src 0 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1ab4 1ab4 fiu_fill_mode_src 0 ; Flow J cc=False 0x1aba fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1aba 0x1aba seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR01:01 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 2d VR05:0d val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 1ab5 1ab5 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1ab6 1ab6 ioc_load_wdr 0 ; Flow C cc=True 0x32dc ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dc 0x32dc seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_rand 6 CHECK_CLASS_A_??_B 1ab7 1ab7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1ab8 1ab8 fiu_fill_mode_src 0 ; Flow C cc=False 0x32dc fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_frame 6 1ab9 1ab9 fiu_fill_mode_src 0 ; Flow J 0x1ab0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ab0 0x1ab0 typ_mar_cntl 6 INCREMENT_MAR 1aba 1aba fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 1abb 1abb fiu_fill_mode_src 0 ; Flow J 0x1ab6 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ab6 0x1ab6 typ_mar_cntl 6 INCREMENT_MAR 1abc 1abc fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1abd 1abd ioc_fiubs 2 typ ; Flow C cc=False 0x1a9b seq_br_type 4 Call False seq_branch_adr 1a9b 0x1a9b seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3a GP05 typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1abe 1abe ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1abf 1abf fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x1ac2 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1ac2 0x1ac2 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 1ac0 1ac0 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1ac1 1ac1 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1ac2 1ac2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1ac4 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1ac4 0x1ac4 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 08 Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ac3 1ac3 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32cc seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1ac4 1ac4 ioc_fiubs 1 val ; Flow J cc=True 0x1ac6 seq_br_type 1 Branch True seq_branch_adr 1ac6 0x1ac6 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 03 GP03 1ac5 1ac5 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 1ac6 1ac6 ioc_fiubs 1 val ; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 1ac7 1ac7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1ac8 ; -------------------------------------------------------------------------------------- 1ac8 ; 0x01c6 Execute Vector,Convert_To_Formal 1ac8 ; -------------------------------------------------------------------------------------- 1ac8 MACRO_Execute_Vector,Convert_To_Formal: 1ac8 1ac8 dispatch_brk_class 4 ; Flow C cc=False 0x1af3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1ac8 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1af3 0x1af3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1ac9 1ac9 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1aca 1aca seq_b_timing 1 Latch Condition; Flow J cc=True 0x1aa2 seq_br_type 1 Branch True seq_branch_adr 1aa2 0x1aa2 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1acb 1acb fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1a95 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1a95 0x1a95 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 1acc 1acc seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1a7f seq_br_type 5 Call True seq_branch_adr 1a7f 0x1a7f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 1acd 1acd fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_frame 2 1ace 1ace seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x1a8e seq_br_type 0 Branch False seq_branch_adr 1a8e 0x1a8e seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1acf 1acf seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 1ad0 ; -------------------------------------------------------------------------------------- 1ad0 ; 0x01c5 Execute Vector,In_Type 1ad0 ; -------------------------------------------------------------------------------------- 1ad0 MACRO_Execute_Vector,In_Type: 1ad0 1ad0 dispatch_brk_class 8 ; Flow C cc=False 0x1af3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1ad0 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1af3 0x1af3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1ad1 1ad1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ad2 1ad2 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x1ae1 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1ae1 0x1ae1 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 14 ZEROS val_b_adr 31 VR02:11 val_frame 2 1ad3 1ad3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1ad7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1ad7 0x1ad7 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1ad4 1ad4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1a7f seq_br_type 5 Call True seq_branch_adr 1a7f 0x1a7f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 1ad5 1ad5 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1ad6 0x1ad6 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 1ad6 1ad6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1ad7 ; -------------------------------------------------------------------------------------- 1ad7 ; Comes from: 1ad7 ; 1ad3 C True from color 0x0a2f 1ad7 ; 1ae1 C True from color 0x0a2f 1ad7 ; 1ae9 C True from color 0x0aa1 1ad7 ; 1aed C True from color 0x0aa1 1ad7 ; -------------------------------------------------------------------------------------- 1ad7 1ad7 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1ada seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ada 0x1ada seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1ad8 1ad8 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 1ad9 1ad9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1ada 1ada fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1adb 1adb fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 1adc 1adc fiu_len_fill_lit 5f zero-fill 0x1f; Flow R fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1add 1add <halt> ; Flow R 1ade ; -------------------------------------------------------------------------------------- 1ade ; 0x01c4 Execute Vector,Not_In_Type 1ade ; -------------------------------------------------------------------------------------- 1ade MACRO_Execute_Vector,Not_In_Type: 1ade 1ade dispatch_brk_class 8 ; Flow C cc=False 0x1af3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1ade dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1af3 0x1af3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1adf 1adf fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ae0 1ae0 fiu_tivi_src 4 fiu_var; Flow J cc=False 0x1ad3 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1ad3 0x1ad3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 14 ZEROS val_b_adr 39 VR02:19 val_frame 2 1ae1 1ae1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1ad7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1ad7 0x1ad7 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1ae2 1ae2 fiu_load_var 1 hold_var; Flow J cc=False 0x1ad6 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 1ad6 0x1ad6 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 02 ? typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 20 TOP - 0x1 1ae3 1ae3 fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1ae4 1ae4 ioc_tvbs 1 typ+fiu val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ae5 1ae5 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1ad6 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1ad6 0x1ad6 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 1ae6 ; -------------------------------------------------------------------------------------- 1ae6 ; 0x01c3 Execute Vector,Check_In_Type 1ae6 ; -------------------------------------------------------------------------------------- 1ae6 MACRO_Execute_Vector,Check_In_Type: 1ae6 1ae6 dispatch_brk_class 8 ; Flow C cc=False 0x1af3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1ae6 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 1af3 0x1af3 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c typ_rand 8 SPARE_0x08 1ae7 1ae7 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ae8 1ae8 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1aed seq_br_type 1 Branch True seq_branch_adr 1aed 0x1aed seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 1ae9 1ae9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1ad7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1ad7 0x1ad7 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1aea 1aea seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x1a7f seq_br_type 5 Call True seq_branch_adr 1a7f 0x1a7f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 1aeb 1aeb fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1aec 0x1aec seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 19 X_XOR_B val_b_adr 01 GP01 1aec 1aec seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 seq_en_micro 0 seq_random 02 ? 1aed 1aed fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1ad7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1ad7 0x1ad7 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 1aee 1aee fiu_load_var 1 hold_var; Flow C cc=False 0x32a2 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32a2 0x32a2 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 02 ? typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B 1aef 1aef fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1af0 1af0 ioc_tvbs 1 typ+fiu val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1af1 1af1 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1af2 0x1af2 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 1af2 1af2 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 1af3 ; -------------------------------------------------------------------------------------- 1af3 ; Comes from: 1af3 ; 1872 C False from color MACRO_Execute_Vector,Greater_Equal 1af3 ; 1878 C False from color MACRO_Execute_Vector,Greater_Equal 1af3 ; 192a C False from color MACRO_Execute_Vector,And 1af3 ; 19f0 C False from color MACRO_Execute_Vector,Slice_Reference 1af3 ; 1a00 C False from color MACRO_Execute_Vector,Catenate 1af3 ; 1a88 C False from color 0x0a2f 1af3 ; 1ac8 C False from color 0x0a2f 1af3 ; 1ad0 C False from color 0x0a2f 1af3 ; 1ade C False from color 0x0a2f 1af3 ; -------------------------------------------------------------------------------------- 1af3 1af3 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1af4 1af4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1af5 1af5 seq_br_type a Unconditional Return; Flow R 1af6 ; -------------------------------------------------------------------------------------- 1af6 ; 0x022f Execute Access,Equal 1af6 ; -------------------------------------------------------------------------------------- 1af6 MACRO_Execute_Access,Equal: 1af6 1af6 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1af6 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1af7 1af7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1af8 ; -------------------------------------------------------------------------------------- 1af8 ; 0x022e Execute Access,Not_Equal 1af8 ; -------------------------------------------------------------------------------------- 1af8 MACRO_Execute_Access,Not_Equal: 1af8 1af8 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1af8 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1af9 1af9 <halt> ; Flow R 1afa ; -------------------------------------------------------------------------------------- 1afa ; 0x022d Execute Access,Is_Null 1afa ; -------------------------------------------------------------------------------------- 1afa MACRO_Execute_Access,Is_Null: 1afa 1afa dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1afa fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 1afb 1afb <halt> ; Flow R 1afc ; -------------------------------------------------------------------------------------- 1afc ; 0x022c Execute Access,Not_Null 1afc ; -------------------------------------------------------------------------------------- 1afc MACRO_Execute_Access,Not_Null: 1afc 1afc dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1afc fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 1afd 1afd <halt> ; Flow R 1afe ; -------------------------------------------------------------------------------------- 1afe ; 0x022b Execute Access,Set_Null 1afe ; -------------------------------------------------------------------------------------- 1afe MACRO_Execute_Access,Set_Null: 1afe 1afe dispatch_brk_class 2 ; Flow J cc=True 0x1b02 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1afe fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1b02 0x1b02 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_frame 14 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1aff 1aff fiu_mem_start 5 start_rd_if_true; Flow C 0x32d7 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 1b00 1b00 fiu_load_tar 1 hold_tar; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 1b01 1b01 ioc_load_wdr 0 ; Flow J 0x1af7 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1af7 0x1af7 val_b_adr 39 VR02:19 val_frame 2 1b02 1b02 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x32a9 fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 10 TOP 1b03 1b03 fiu_load_mdr 1 hold_mdr; Flow J cc=False 0x1b05 fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b05 0x1b05 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 39 VR02:19 val_frame 2 1b04 1b04 fiu_fill_mode_src 0 ; Flow J 0x1b08 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1b08 0x1b08 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 1b05 1b05 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1b06 1b06 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1b07 1b07 fiu_load_var 1 hold_var; Flow J 0x1b08 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1b08 0x1b08 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1b08 1b08 ioc_load_wdr 0 ; Flow J 0x1af7 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1af7 0x1af7 1b09 1b09 <halt> ; Flow R 1b0a ; -------------------------------------------------------------------------------------- 1b0a ; 0x022a Execute Access,Element_Type 1b0a ; -------------------------------------------------------------------------------------- 1b0a MACRO_Execute_Access,Element_Type: 1b0a 1b0a dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b0a dispatch_uses_tos 1 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1b0b 1b0b fiu_load_tar 1 hold_tar; Flow J cc=False 0x1b0e fiu_mem_start 5 start_rd_if_true fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1b0e 0x1b0e seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE 1b0c 1b0c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 1b0d 1b0d fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator 1b0e 1b0e fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 1b0f 0x1b0f seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b0f 1b0f seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 seq_en_micro 0 seq_random 02 ? 1b10 ; -------------------------------------------------------------------------------------- 1b10 ; 0x0229 Execute Access,All_Read 1b10 ; -------------------------------------------------------------------------------------- 1b10 MACRO_Execute_Access,All_Read: 1b10 1b10 dispatch_brk_class 8 ; Flow C cc=True 0x32a1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b10 dispatch_uses_tos 1 ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a1 0x32a1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 20 VR07:00 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 7 1b11 1b11 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1b17 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1b17 0x1b17 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1b12 1b12 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 1b13 1b13 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1b15 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b15 0x1b15 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1b14 1b14 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x1b18 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 1b18 0x1b18 seq_random 04 Load_save_offset+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1b15 1b15 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1b16 1b16 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x1b18 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 1b18 0x1b18 seq_random 04 Load_save_offset+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1b17 1b17 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b18 1b18 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1b19 0x1b19 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b19 1b19 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1b1a ; -------------------------------------------------------------------------------------- 1b1a ; 0x0228 Execute Access,All_Write 1b1a ; -------------------------------------------------------------------------------------- 1b1a MACRO_Execute_Access,All_Write: 1b1a 1b1a dispatch_brk_class 2 ; Flow C cc=True 0x32a1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b1a dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a1 0x32a1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 10 TOP 1b1b 1b1b fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d78 0x1d78 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1b1c 1b1c fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1b1d 1b1d fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 1b1e 1b1e fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d78 0x1d78 1b1f 1b1f <halt> ; Flow R 1b20 ; -------------------------------------------------------------------------------------- 1b20 ; 0x0227 Execute Access,All_Reference 1b20 ; -------------------------------------------------------------------------------------- 1b20 MACRO_Execute_Access,All_Reference: 1b20 1b20 dispatch_brk_class 8 ; Flow C cc=True 0x32a1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b20 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a1 0x32a1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 1b21 1b21 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 1b22 ; -------------------------------------------------------------------------------------- 1b22 ; 0x0226 Execute Access,Convert 1b22 ; -------------------------------------------------------------------------------------- 1b22 MACRO_Execute_Access,Convert: 1b22 1b22 dispatch_brk_class 4 ; Flow J cc=True 0x1b24 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1b22 seq_br_type 1 Branch True seq_branch_adr 1b24 0x1b24 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand 8 SPARE_0x08 1b23 1b23 seq_br_type 7 Unconditional Call; Flow C 0x24ba seq_branch_adr 24ba 0x24ba seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b24 1b24 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1b3b ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1b3b 0x1b3b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 1b25 1b25 <halt> ; Flow R 1b26 ; -------------------------------------------------------------------------------------- 1b26 ; 0x0222 Execute Access,Convert_Reference 1b26 ; -------------------------------------------------------------------------------------- 1b26 MACRO_Execute_Access,Convert_Reference: 1b26 1b26 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1b26 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1b27 1b27 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1b A_OR_B val_b_adr 3e VR03:1e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 3 1b28 1b28 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 1b29 1b29 typ_a_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 14 typ_rand b CARRY IN = Q BIT FROM VAL 1b2a 1b2a fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1b2b 0x1b2b seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b2b 1b2b seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 typ_csa_cntl 3 POP_CSA 1b2c ; -------------------------------------------------------------------------------------- 1b2c ; 0x0225 Execute Access,In_Type 1b2c ; -------------------------------------------------------------------------------------- 1b2c MACRO_Execute_Access,In_Type: 1b2c 1b2c dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1b2c fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b2d 0x1b2d seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b2d 1b2d ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b2e 1b2e typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1b2f 1b2f seq_br_type 7 Unconditional Call; Flow C 0x24ba seq_branch_adr 24ba 0x24ba seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b30 1b30 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1b31 1b31 <halt> ; Flow R 1b32 ; -------------------------------------------------------------------------------------- 1b32 ; 0x0224 Execute Access,Not_In_Type 1b32 ; -------------------------------------------------------------------------------------- 1b32 MACRO_Execute_Access,Not_In_Type: 1b32 1b32 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1b32 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b33 0x1b33 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1b33 1b33 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1b34 1b34 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1b35 1b35 seq_br_type 7 Unconditional Call; Flow C 0x24ba seq_branch_adr 24ba 0x24ba seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b36 1b36 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b37 1b37 <halt> ; Flow R 1b38 ; -------------------------------------------------------------------------------------- 1b38 ; 0x0223 Execute Access,Check_In_Type 1b38 ; -------------------------------------------------------------------------------------- 1b38 MACRO_Execute_Access,Check_In_Type: 1b38 1b38 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1b38 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1b39 0x1b39 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 1b39 1b39 seq_br_type 7 Unconditional Call; Flow C 0x24ba seq_branch_adr 24ba 0x24ba seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1b3a 1b3a fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1b3b 0x1b3b seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 1f TOP - 1 1b3b 1b3b fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 seq_random 02 ? typ_a_adr 11 TOP + 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1b3c 1b3c ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a4 0x32a4 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c 1b3d 1b3d seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 1b3e ; -------------------------------------------------------------------------------------- 1b3e ; 0x0114 Execute Access,Size 1b3e ; -------------------------------------------------------------------------------------- 1b3e MACRO_Execute_Access,Size: 1b3e 1b3e dispatch_brk_class 8 ; Flow J cc=False 0x1b42 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b3e dispatch_uses_tos 1 seq_br_type 0 Branch False seq_branch_adr 1b42 0x1b42 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_frame 10 1b3f 1b3f fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1b40 1b40 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 1b41 1b41 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 38 VR02:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1b42 1b42 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 10 TOP 1b43 1b43 seq_br_type 3 Unconditional Branch; Flow J 0x1b3f seq_branch_adr 1b3f 0x1b3f typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL 1b44 ; -------------------------------------------------------------------------------------- 1b44 ; 0x0220 Execute Access,Deallocate 1b44 ; -------------------------------------------------------------------------------------- 1b44 MACRO_Execute_Access,Deallocate: 1b44 1b44 dispatch_brk_class 8 ; Flow J cc=True 0x1b4f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b44 dispatch_uses_tos 1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1b4f 0x1b4f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 1b45 1b45 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b46 1b46 ioc_fiubs 1 val typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1b47 1b47 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1b48 1b48 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x1b4f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1b4f 0x1b4f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 21 VR13:01 val_alu_func 1e A_AND_B val_b_adr 06 GP06 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 13 1b49 1b49 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1b4a 1b4a fiu_fill_mode_src 0 ; Flow J cc=False 0x1b50 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b50 0x1b50 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 06 GP06 1b4b 1b4b fiu_fill_mode_src 0 ; Flow J cc=False 0x1b55 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1b55 0x1b55 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 1b4c 1b4c ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1b4d 1b4d fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b4e 1b4e ioc_load_wdr 0 typ_b_adr 06 GP06 val_b_adr 06 GP06 1b4f 1b4f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1b50 1b50 fiu_fill_mode_src 0 ; Flow J cc=False 0x1b55 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1b55 0x1b55 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 1b51 1b51 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 1b52 1b52 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_c_adr 30 GP0f 1b53 1b53 ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_b_adr 0f GP0f 1b54 1b54 seq_br_type 3 Unconditional Branch; Flow J 0x1b4d seq_branch_adr 1b4d 0x1b4d val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1b55 1b55 fiu_mem_start 2 start-rd; Flow C 0x35a5 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35a5 0x35a5 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 1b56 1b56 fiu_mem_start 2 start-rd; Flow J cc=True 0x1b47 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1b47 0x1b47 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1b57 1b57 <halt> ; Flow R 1b58 ; -------------------------------------------------------------------------------------- 1b58 ; 0x0221 Execute Access,Allow_Deallocate 1b58 ; -------------------------------------------------------------------------------------- 1b58 MACRO_Execute_Access,Allow_Deallocate: 1b58 1b58 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b58 dispatch_uses_tos 1 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1b59 1b59 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b5a 1b5a fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1af7 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1af7 0x1af7 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1b5b 1b5b typ_c_adr 3d GP02 1b5c 1b5c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1b5d 1b5d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1af7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1af7 0x1af7 val_a_adr 21 VR13:01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 13 1b5e 1b5e ioc_tvbs 1 typ+fiu; Flow J cc=True 0x1af7 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1af7 0x1af7 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_c_adr 39 GP06 val_a_adr 31 VR02:11 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 1b5f 1b5f fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 59 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 01 GP01 1b60 1b60 ioc_load_wdr 0 ; Flow J 0x1af7 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1af7 0x1af7 typ_b_adr 06 GP06 1b61 1b61 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x32d9 seq_br_type 1 Branch True seq_branch_adr 32d9 0x32d9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 21 TR00:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 02 GP02 1b62 1b62 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32d9 seq_br_type 9 Return False seq_branch_adr 32d9 0x32d9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 02 GP02 typ_frame 11 1b63 1b63 <halt> ; Flow R 1b64 ; -------------------------------------------------------------------------------------- 1b64 ; 0x0080 QQUnknown InMicrocode 1b64 ; -------------------------------------------------------------------------------------- 1b64 MACRO_1b64_QQUnknown_InMicrocode: 1b64 1b64 dispatch_brk_class 0 ; Flow J cc=False 0x32db dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b64 dispatch_uses_tos 1 seq_br_type 0 Branch False seq_branch_adr 32db 0x32db seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1b65 1b65 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x332e fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1b66 1b66 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 1b67 1b67 ioc_fiubs 2 typ ; Flow J cc=True 0x32db ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32db 0x32db seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b68 1b68 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val typ_b_adr 01 GP01 val_b_adr 01 GP01 1b69 1b69 ioc_load_wdr 0 ; Flow J 0x1af7 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1af7 0x1af7 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1b6a ; -------------------------------------------------------------------------------------- 1b6a ; 0x0082 QQUnknown InMicrocode 1b6a ; -------------------------------------------------------------------------------------- 1b6a MACRO_1b6a_QQUnknown_InMicrocode: 1b6a 1b6a dispatch_brk_class 0 ; Flow J cc=False 0x32dc dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b6a dispatch_uses_tos 1 seq_br_type 0 Branch False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1b6b 1b6b fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1b6c 1b6c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1b6d 1b6d fiu_mem_start 3 start-wr; Flow J cc=True 0x32d9 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32d9 0x32d9 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1b6e 1b6e ioc_load_wdr 0 ; Flow J 0x1af7 seq_br_type 3 Unconditional Branch seq_branch_adr 1af7 0x1af7 typ_csa_cntl 3 POP_CSA 1b6f 1b6f <halt> ; Flow R 1b70 ; -------------------------------------------------------------------------------------- 1b70 ; 0x0081 QQUnknown InMicrocode 1b70 ; -------------------------------------------------------------------------------------- 1b70 MACRO_1b70_QQUnknown_InMicrocode: 1b70 1b70 dispatch_brk_class 0 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1b70 dispatch_uses_tos 1 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1b71 1b71 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 1b72 1b72 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1b73 1b73 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1b74 ; -------------------------------------------------------------------------------------- 1b74 ; 0x01fe Execute Array,Not_Equal 1b74 ; 0x01ff Execute Array,Equal 1b74 ; -------------------------------------------------------------------------------------- 1b74 MACRO_Execute_Array,Equal: 1b74 MACRO_Execute_Array,Not_Equal: 1b74 1b74 dispatch_brk_class 8 ; Flow J cc=True 0x1b76 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1b74 fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 1b76 0x1b76 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1b75 1b75 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1b76 1b76 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1b77 1b77 seq_br_type 2 Push (branch address); Flow J 0x1b78 seq_branch_adr 1ba5 0x1ba5 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1b78 1b78 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=False 0x1b90 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1b90 0x1b90 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1b79 1b79 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1b7a 1b7a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1b7b 1b7b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1b7c 1b7c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1b83 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b83 0x1b83 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b7d 1b7d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b7e 1b7e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x1ba0 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 1ba0 0x1ba0 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1b7f 1b7f fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1b87 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 1b87 0x1b87 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 1b80 1b80 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1b81 1b81 seq_br_type 1 Branch True; Flow J cc=True 0x22e4 seq_branch_adr 22e4 0x22e4 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1b82 1b82 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b83 1b83 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1b84 1b84 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b85 1b85 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x1ba0 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 1ba0 0x1ba0 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1b86 1b86 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1b80 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 1b80 0x1b80 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 1b87 1b87 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1b8a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1b8a 0x1b8a typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1b88 1b88 seq_br_type 1 Branch True; Flow J cc=True 0x22ec seq_branch_adr 22ec 0x22ec seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1b89 1b89 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b8a ; -------------------------------------------------------------------------------------- 1b8a ; Comes from: 1b8a ; 1b87 C from color 0x09aa 1b8a ; 1b98 C from color 0x09aa 1b8a ; -------------------------------------------------------------------------------------- 1b8a 1b8a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1b8d ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1b8d 0x1b8d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR 1b8b 1b8b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b8c 1b8c fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1b9b fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1b9b 0x1b9b seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1b8d 1b8d fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1b8e 1b8e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1b8f 1b8f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1b9b fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1b9b 0x1b9b seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1b90 1b90 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1b91 1b91 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1b92 1b92 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1b96 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 1b96 0x1b96 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 1b93 1b93 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1b94 1b94 seq_br_type 1 Branch True; Flow J cc=True 0x22de seq_branch_adr 22de 0x22de seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 1b95 1b95 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b96 1b96 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1b97 1b97 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1b98 1b98 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1b8a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 1b8a 0x1b8a typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1b99 1b99 seq_br_type 1 Branch True; Flow J cc=True 0x22da seq_branch_adr 22da 0x22da seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 06 GP06 1b9a 1b9a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1b9b 1b9b seq_br_type 0 Branch False; Flow J cc=False 0x1b9d seq_branch_adr 1b9d 0x1b9d seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_rand c START_MULTIPLY 1b9c 1b9c seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1b9d 1b9d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1b9e 1b9e seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1b9f 0x1b9f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1b9f 1b9f seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1ba0 ; -------------------------------------------------------------------------------------- 1ba0 ; Comes from: 1ba0 ; 1b7e C from color 0x09aa 1ba0 ; 1b85 C from color 0x09aa 1ba0 ; -------------------------------------------------------------------------------------- 1ba0 1ba0 seq_br_type 0 Branch False; Flow J cc=False 0x1ba2 seq_branch_adr 1ba2 0x1ba2 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_rand c START_MULTIPLY 1ba1 1ba1 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1ba2 1ba2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1ba3 1ba3 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1ba4 0x1ba4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1ba4 1ba4 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1ba5 1ba5 seq_b_timing 1 Latch Condition; Flow J cc=False 0x1ba8 seq_br_type 0 Branch False seq_branch_adr 1ba8 0x1ba8 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1ba6 1ba6 ioc_fiubs 1 val ; Flow C 0x272c seq_br_type 7 Unconditional Call seq_branch_adr 272c 0x272c seq_random 02 ? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 07 GP07 1ba7 1ba7 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 1ba8 1ba8 seq_br_type 7 Unconditional Call; Flow C 0x1bae seq_branch_adr 1bae 0x1bae typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1ba9 1ba9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1bab seq_br_type 1 Branch True seq_branch_adr 1bab 0x1bab seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1baa 1baa seq_br_type 7 Unconditional Call; Flow C 0x1bae seq_branch_adr 1bae 0x1bae typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 30 GP0f val_c_mux_sel 2 ALU 1bab 1bab seq_random 02 ? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1bac 1bac fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1bad 0x1bad seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1bad 1bad fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1bae ; -------------------------------------------------------------------------------------- 1bae ; Comes from: 1bae ; 1ba8 C from color 0x1ba5 1bae ; 1baa C from color 0x1ba5 1bae ; -------------------------------------------------------------------------------------- 1bae 1bae ioc_fiubs 2 typ ; Flow J cc=False 0x2286 seq_br_type 0 Branch False seq_branch_adr 2286 0x2286 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_b_adr 07 GP07 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1baf 1baf ioc_fiubs 1 val ; Flow J 0x228e seq_br_type 3 Unconditional Branch seq_branch_adr 228e 0x228e seq_en_micro 0 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 1bb0 ; -------------------------------------------------------------------------------------- 1bb0 ; Comes from: 1bb0 ; 1bc8 C from color MACRO_Execute_Array,First 1bb0 ; 1bca C from color MACRO_Execute_Array,Last 1bb0 ; 1bcc C from color MACRO_Execute_Array,Length 1bb0 ; 1bce C from color MACRO_Execute_Array,Last 1bb0 ; 1bd0 C from color MACRO_Execute_Array,First 1bb0 ; -------------------------------------------------------------------------------------- 1bb0 1bb0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1bbc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bbc 0x1bbc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 10 TOP 1bb1 1bb1 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1bb2 1bb2 fiu_len_fill_lit 77 zero-fill 0x37; Flow C cc=True 0x32d9 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 1bb3 1bb3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1bb4 1bb4 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x1bb6 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bb6 0x1bb6 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1c DEC_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1bb5 1bb5 fiu_tivi_src c mar_0xc; Flow R ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1bb6 1bb6 fiu_len_fill_lit 79 zero-fill 0x39 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_b_adr 04 GP04 1bb7 1bb7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1bb8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1bb8 0x1bb8 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 1bb8 1bb8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1bba seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1bba 0x1bba seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1bb9 1bb9 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return seq_random 02 ? typ_csa_cntl 3 POP_CSA val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1bba 1bba fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1bbb 1bbb fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return seq_random 02 ? typ_csa_cntl 3 POP_CSA val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1bbc 1bbc fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1bb1 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bb1 0x1bb1 typ_a_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 04 GP04 val_b_adr 3f VR02:1f val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 1bbd 1bbd fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32d9 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP 1bbe 1bbe fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1bc0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1bc0 0x1bc0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 5 1bbf 1bbf fiu_fill_mode_src 0 ; Flow J 0x1bc2 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1bc2 0x1bc2 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1bc0 1bc0 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1bc1 1bc1 fiu_fill_mode_src 0 ; Flow J 0x1bc2 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1bc2 0x1bc2 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1bc2 1bc2 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x1bc4 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1bc4 0x1bc4 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1bc3 1bc3 fiu_tivi_src c mar_0xc; Flow R ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_random 02 ? typ_csa_cntl 3 POP_CSA val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1bc4 1bc4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1bc5 1bc5 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1bc6 1bc6 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x1bb8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1bb8 0x1bb8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 1bc7 1bc7 <halt> ; Flow R 1bc8 ; -------------------------------------------------------------------------------------- 1bc8 ; 0x01fd Execute Array,First 1bc8 ; -------------------------------------------------------------------------------------- 1bc8 MACRO_Execute_Array,First: 1bc8 1bc8 dispatch_brk_class 8 ; Flow C 0x1bb0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1bc8 dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1bb0 0x1bb0 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1bc9 1bc9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1bca ; -------------------------------------------------------------------------------------- 1bca ; 0x01fc Execute Array,Last 1bca ; -------------------------------------------------------------------------------------- 1bca MACRO_Execute_Array,Last: 1bca 1bca dispatch_brk_class 8 ; Flow C 0x1bb0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1bca dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1bb0 0x1bb0 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1bcb 1bcb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1bcc ; -------------------------------------------------------------------------------------- 1bcc ; 0x01fb Execute Array,Length 1bcc ; -------------------------------------------------------------------------------------- 1bcc MACRO_Execute_Array,Length: 1bcc 1bcc dispatch_brk_class 8 ; Flow C 0x1bb0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1bcc dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1bb0 0x1bb0 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1bcd 1bcd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1bce ; -------------------------------------------------------------------------------------- 1bce ; 0x01fa Execute Array,Bounds 1bce ; -------------------------------------------------------------------------------------- 1bce MACRO_Execute_Array,Bounds: 1bce 1bce dispatch_brk_class 8 ; Flow C 0x1bb0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1bce dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1bb0 0x1bb0 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1bcf 1bcf seq_br_type 3 Unconditional Branch; Flow J 0x1bcb seq_branch_adr 1bcb 0x1bcb typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1bd0 ; -------------------------------------------------------------------------------------- 1bd0 ; 0x01f9 Execute Array,Reverse_Bounds 1bd0 ; -------------------------------------------------------------------------------------- 1bd0 MACRO_Execute_Array,Reverse_Bounds: 1bd0 1bd0 dispatch_brk_class 8 ; Flow C 0x1bb0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1bd0 dispatch_uses_tos 1 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1bb0 0x1bb0 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 1c DEC_A val_b_adr 1f TOP - 1 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1bd1 1bd1 seq_br_type 3 Unconditional Branch; Flow J 0x1bc9 seq_branch_adr 1bc9 0x1bc9 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 1bd2 ; -------------------------------------------------------------------------------------- 1bd2 ; 0x01f8 Execute Array,Element_Type 1bd2 ; -------------------------------------------------------------------------------------- 1bd2 MACRO_Execute_Array,Element_Type: 1bd2 1bd2 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1bd2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bd3 1bd3 typ_a_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL 1bd4 1bd4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1bd5 1bd5 <halt> ; Flow R 1bd6 ; -------------------------------------------------------------------------------------- 1bd6 ; 0x01ed Execute Array,In_Type 1bd6 ; -------------------------------------------------------------------------------------- 1bd6 MACRO_Execute_Array,In_Type: 1bd6 1bd6 dispatch_brk_class 8 ; Flow C cc=False 0x1c03 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1bd6 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1c03 0x1c03 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bd7 1bd7 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1bd8 1bd8 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1bde fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bde 0x1bde seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1bd9 1bd9 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bdc seq_br_type 1 Branch True seq_branch_adr 1bdc 0x1bdc 1bda 1bda seq_br_type 7 Unconditional Call; Flow C 0x22c6 seq_branch_adr 22c6 0x22c6 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bdb 1bdb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1bdc 1bdc ioc_fiubs 1 val ; Flow C 0x22bc seq_br_type 7 Unconditional Call seq_branch_adr 22bc 0x22bc typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bdd 1bdd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1bde 1bde seq_b_timing 1 Latch Condition; Flow J cc=True 0x1be1 seq_br_type 1 Branch True seq_branch_adr 1be1 0x1be1 1bdf 1bdf seq_br_type 7 Unconditional Call; Flow C 0x2292 seq_branch_adr 2292 0x2292 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1be0 1be0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1be1 1be1 ioc_fiubs 1 val ; Flow C 0x229d seq_br_type 7 Unconditional Call seq_branch_adr 229d 0x229d typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1be2 1be2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1be3 1be3 <halt> ; Flow R 1be4 ; -------------------------------------------------------------------------------------- 1be4 ; 0x01ec Execute Array,Not_In_Type 1be4 ; -------------------------------------------------------------------------------------- 1be4 MACRO_Execute_Array,Not_In_Type: 1be4 1be4 dispatch_brk_class 8 ; Flow C cc=False 0x1c03 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1be4 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1c03 0x1c03 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1be5 1be5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1be6 1be6 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1bec fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bec 0x1bec seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1be7 1be7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bea seq_br_type 1 Branch True seq_branch_adr 1bea 0x1bea 1be8 1be8 seq_br_type 7 Unconditional Call; Flow C 0x22c6 seq_branch_adr 22c6 0x22c6 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1be9 1be9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1bea 1bea ioc_fiubs 1 val ; Flow C 0x22bc seq_br_type 7 Unconditional Call seq_branch_adr 22bc 0x22bc typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1beb 1beb fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1bec 1bec seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bef seq_br_type 1 Branch True seq_branch_adr 1bef 0x1bef 1bed 1bed seq_br_type 7 Unconditional Call; Flow C 0x2292 seq_branch_adr 2292 0x2292 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bee 1bee fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1bef 1bef ioc_fiubs 1 val ; Flow C 0x229d seq_br_type 7 Unconditional Call seq_branch_adr 229d 0x229d typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bf0 1bf0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 1bf1 1bf1 <halt> ; Flow R 1bf2 ; -------------------------------------------------------------------------------------- 1bf2 ; 0x01eb Execute Array,Check_In_Type 1bf2 ; -------------------------------------------------------------------------------------- 1bf2 MACRO_Execute_Array,Check_In_Type: 1bf2 1bf2 dispatch_brk_class 8 ; Flow C cc=False 0x1c03 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1bf2 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1c03 0x1c03 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1bf3 1bf3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1bf4 1bf4 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1bfc fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1bfc 0x1bfc seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1bf5 1bf5 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1bf9 seq_br_type 1 Branch True seq_branch_adr 1bf9 0x1bf9 1bf6 1bf6 seq_br_type 7 Unconditional Call; Flow C 0x22c6 seq_branch_adr 22c6 0x22c6 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bf7 1bf7 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1bf8 0x1bf8 seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1bf8 1bf8 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 seq_en_micro 0 seq_random 02 ? 1bf9 1bf9 ioc_fiubs 1 val ; Flow C 0x22bc seq_br_type 7 Unconditional Call seq_branch_adr 22bc 0x22bc typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1bfa 1bfa fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1bfb 0x1bfb seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1bfb 1bfb seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 seq_en_micro 0 seq_random 02 ? 1bfc 1bfc seq_b_timing 1 Latch Condition; Flow J cc=True 0x1c00 seq_br_type 1 Branch True seq_branch_adr 1c00 0x1c00 1bfd 1bfd seq_br_type 7 Unconditional Call; Flow C 0x2292 seq_branch_adr 2292 0x2292 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1bfe 1bfe fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1bff 0x1bff seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1bff 1bff seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 seq_en_micro 0 seq_random 02 ? 1c00 1c00 ioc_fiubs 1 val ; Flow C 0x229d seq_br_type 7 Unconditional Call seq_branch_adr 229d 0x229d typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1c01 1c01 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 1c02 0x1c02 seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1c02 1c02 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 seq_en_micro 0 seq_random 02 ? 1c03 ; -------------------------------------------------------------------------------------- 1c03 ; Comes from: 1c03 ; 1bd6 C False from color 0x0a78 1c03 ; 1be4 C False from color 0x0a8c 1c03 ; -------------------------------------------------------------------------------------- 1c03 1c03 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c04 1c04 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c05 1c05 <halt> ; Flow R 1c06 ; -------------------------------------------------------------------------------------- 1c06 ; 0x01ef Execute Array,Convert 1c06 ; -------------------------------------------------------------------------------------- 1c06 MACRO_Execute_Array,Convert: 1c06 1c06 dispatch_brk_class 4 ; Flow J cc=True 0x1c08 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c06 seq_br_type 1 Branch True seq_branch_adr 1c08 0x1c08 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1c07 1c07 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c08 1c08 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c09 1c09 ioc_fiubs 2 typ ; Flow J cc=True 0x1c1f seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c1f 0x1c1f seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c0a 1c0a fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1c0f fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c0f 0x1c0f typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1c0b 1c0b seq_br_type 7 Unconditional Call; Flow C 0x22de seq_branch_adr 22de 0x22de typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1c0c 1c0c fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1c17 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c17 0x1c17 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c0d 1c0d ioc_fiubs 2 typ ; Flow C 0x2286 seq_br_type 7 Unconditional Call seq_branch_adr 2286 0x2286 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1c0e 1c0e seq_br_type 3 Unconditional Branch; Flow J 0x1c14 seq_branch_adr 1c14 0x1c14 1c0f 1c0f ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1c10 1c10 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1c11 1c11 ioc_fiubs 1 val ; Flow C 0x22da seq_br_type 7 Unconditional Call seq_branch_adr 22da 0x22da typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c12 1c12 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1c17 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c17 0x1c17 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 1c13 1c13 ioc_fiubs 2 typ ; Flow C 0x228e seq_br_type 7 Unconditional Call seq_branch_adr 228e 0x228e typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1c14 1c14 ioc_fiubs 2 typ ; Flow C cc=True 0x32a2 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 1c15 1c15 seq_br_type 7 Unconditional Call; Flow C 0x2286 seq_branch_adr 2286 0x2286 1c16 1c16 fiu_mem_start 2 start-rd; Flow C cc=True 0x32a2 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1c17 1c17 ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_frame 2 1c18 1c18 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1c19 1c19 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 1c1a 1c1a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1c1c fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c1c 0x1c1c seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c1b 1c1b ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32d2 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32d2 0x32d2 val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1c1c 1c1c seq_br_type 4 Call False; Flow C cc=False 0x32cc seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 37 GP08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 1c1d 1c1d ioc_fiubs 1 val ; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP 1c1e 1c1e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c1f 1c1f fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1c20 1c20 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1c24 seq_br_type 1 Branch True seq_branch_adr 1c24 0x1c24 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 3f VR02:1f val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 val_rand c START_MULTIPLY 1c21 1c21 seq_br_type 7 Unconditional Call; Flow C 0x2292 seq_branch_adr 2292 0x2292 seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1c22 1c22 fiu_mem_start 2 start-rd; Flow J cc=True 0x1c27 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c27 0x1c27 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1c23 1c23 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 1c24 1c24 seq_br_type 2 Push (branch address); Flow J 0x1c25 seq_branch_adr 1c57 0x1c57 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1c25 1c25 ioc_fiubs 1 val ; Flow C 0x229d seq_br_type 7 Unconditional Call seq_branch_adr 229d 0x229d typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 1c26 1c26 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x32a2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 32a2 0x32a2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1c27 1c27 <default> 1c28 1c28 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c29 1c29 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1c2a 1c2a ioc_fiubs 1 val ; Flow C cc=True 0x32a9 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 1c2b 1c2b fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c2c 1c2c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1c2e fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c2e 0x1c2e seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c2d 1c2d ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32cc seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1c2e 1c2e fiu_mem_start 2 start-rd; Flow C cc=False 0x32cc ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_rand 2 DEC_LOOP_COUNTER 1c2f 1c2f fiu_mem_start 4 continue typ_c_adr 37 GP08 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c30 1c30 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1c31 1c31 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1c32 1c32 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 07 GP07 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_frame 6 1c33 1c33 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c34 1c34 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c45 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c45 0x1c45 seq_cond_sel 65 CROSS_WORD_FIELD~ 1c35 1c35 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c36 1c36 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 1c37 1c37 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 1c38 1c38 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c47 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c47 0x1c47 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 06 GP06 1c39 1c39 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c3a 1c3a ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 1c3b 1c3b fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 1c3c 1c3c fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1c30 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c30 0x1c30 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR 1c3d 1c3d fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1c3e 1c3e fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 07 GP07 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_frame 6 1c3f 1c3f fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c40 1c40 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c49 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c49 0x1c49 seq_cond_sel 65 CROSS_WORD_FIELD~ 1c41 1c41 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c4b fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1c4b 0x1c4b typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c42 1c42 ioc_load_wdr 0 ; Flow C cc=True 0x32cc ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 1c43 1c43 seq_br_type 7 Unconditional Call; Flow C 0x1f1e seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 1c44 1c44 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c45 1c45 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c46 1c46 fiu_fill_mode_src 0 ; Flow J 0x1c36 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c36 0x1c36 typ_mar_cntl 6 INCREMENT_MAR 1c47 1c47 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c48 1c48 fiu_fill_mode_src 0 ; Flow J 0x1c3a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c3a 0x1c3a typ_mar_cntl 6 INCREMENT_MAR 1c49 1c49 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c4a 1c4a fiu_fill_mode_src 0 ; Flow J cc=True 0x1c42 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c42 0x1c42 typ_mar_cntl 6 INCREMENT_MAR 1c4b 1c4b ioc_load_wdr 0 ; Flow J 0x1c4d ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c4d 0x1c4d val_a_adr 04 GP04 val_alu_func 1c DEC_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1c4c 1c4c ioc_load_wdr 0 ; Flow J cc=True 0x1c42 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1c42 0x1c42 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_rand 2 DEC_LOOP_COUNTER 1c4d 1c4d fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 1c4e 1c4e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32dc fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 6 1c4f 1c4f fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 07 GP07 val_frame 6 1c50 1c50 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 1c51 1c51 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c54 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c54 0x1c54 seq_cond_sel 65 CROSS_WORD_FIELD~ 1c52 1c52 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c4c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c4c 0x1c4c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 2 DEC_LOOP_COUNTER 1c53 1c53 ioc_load_wdr 0 ; Flow J 0x1c42 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c42 0x1c42 val_rand 2 DEC_LOOP_COUNTER 1c54 1c54 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1c55 1c55 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c4c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c4c 0x1c4c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 1c56 1c56 ioc_load_wdr 0 ; Flow J 0x1c42 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1c42 0x1c42 val_rand 2 DEC_LOOP_COUNTER 1c57 1c57 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1c5b seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1c5b 0x1c5b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1c58 1c58 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1c59 1c59 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c5a 1c5a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1c5d fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1c5d 0x1c5d typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1c5b 1c5b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c5c 1c5c fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1c5d 1c5d seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 1c5e 1c5e fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 1c5f 1c5f fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x1c62 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 1c62 0x1c62 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 6 CONTROL TOP typ_c_adr 37 GP08 val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1c60 1c60 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1c65 seq_br_type 1 Branch True seq_branch_adr 1c65 0x1c65 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c61 1c61 seq_br_type 3 Unconditional Branch; Flow J 0x1c6a seq_branch_adr 1c6a 0x1c6a 1c62 1c62 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1c63 1c63 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1c64 1c64 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1c6a seq_br_type 1 Branch True seq_branch_adr 1c6a 0x1c6a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1c65 1c65 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1c67 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c67 0x1c67 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 08 Validate_tos_optimizer+? typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1c66 1c66 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x32cc seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 1c67 1c67 ioc_fiubs 1 val ; Flow C cc=False 0x32cc seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP 1c68 1c68 ioc_fiubs 1 val ; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 1c69 1c69 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 1c6a 1c6a val_a_adr 04 GP04 val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 1c6b 1c6b seq_br_type 3 Unconditional Branch; Flow J 0x1c65 seq_branch_adr 1c65 0x1c65 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c6c ; -------------------------------------------------------------------------------------- 1c6c ; 0x01ee Execute Array,Convert_To_Formal 1c6c ; -------------------------------------------------------------------------------------- 1c6c MACRO_Execute_Array,Convert_To_Formal: 1c6c 1c6c dispatch_brk_class 4 ; Flow J cc=True 0x1c6e dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c6c seq_br_type 1 Branch True seq_branch_adr 1c6e 0x1c6e seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame 1c typ_rand 8 SPARE_0x08 1c6d 1c6d fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c6e 1c6e fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c6f 1c6f seq_b_timing 1 Latch Condition; Flow J cc=True 0x1c1f seq_br_type 1 Branch True seq_branch_adr 1c1f 0x1c1f seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c70 1c70 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x1c74 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c74 0x1c74 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1c71 1c71 seq_br_type 7 Unconditional Call; Flow C 0x22c6 seq_branch_adr 22c6 0x22c6 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1c72 1c72 fiu_mem_start 2 start-rd; Flow J cc=True 0x1c17 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c17 0x1c17 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c73 1c73 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 1c74 1c74 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1c75 1c75 seq_br_type 2 Push (branch address); Flow J 0x1c76 seq_branch_adr 1c17 0x1c17 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1c76 1c76 ioc_fiubs 1 val ; Flow C 0x22bc seq_br_type 7 Unconditional Call seq_branch_adr 22bc 0x22bc typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c77 1c77 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x32a2 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 32a2 0x32a2 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1c78 ; -------------------------------------------------------------------------------------- 1c78 ; 0x01f4 Execute Array,Structure_Write 1c78 ; -------------------------------------------------------------------------------------- 1c78 MACRO_Execute_Array,Structure_Write: 1c78 1c78 dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 1c78 dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1c typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c79 1c79 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e7a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e7a 0x1e7a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1c7a ; -------------------------------------------------------------------------------------- 1c7a ; Comes from: 1c7a ; 1c9a C from color MACRO_Execute_Array,Field_Read 1c7a ; 1ca2 C from color MACRO_Execute_Array,Field_Read 1c7a ; 1ca6 C from color MACRO_Execute_Array,Field_Write 1c7a ; 1caa C from color MACRO_Execute_Array,Field_Write 1c7a ; 1cac C from color MACRO_Execute_Array,Field_Reference 1c7a ; 1cae C from color MACRO_Execute_Subarray,Field_Reference 1c7a ; -------------------------------------------------------------------------------------- 1c7a 1c7a fiu_mem_start 4 continue; Flow J cc=True 0x1c88 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1c88 0x1c88 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1c7b 1c7b fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c7c 1c7c fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=False 0x1c83 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 41 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1c83 0x1c83 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1c7d 1c7d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1c7e 1c7e fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c7f 1c7f fiu_mem_start 4 continue; Flow C cc=True 0x1c85 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1c85 0x1c85 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 1c80 1c80 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1c7c fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c7c 0x1c7c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c81 1c81 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=False 0x1c83 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1c83 0x1c83 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1c82 1c82 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32a2 seq_br_type 9 Return False seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1c83 ; -------------------------------------------------------------------------------------- 1c83 ; Comes from: 1c83 ; 1c7c C False from color 0x0000 1c83 ; 1c81 C False from color 0x0000 1c83 ; 1c8e C False from color 0x0000 1c83 ; -------------------------------------------------------------------------------------- 1c83 1c83 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1c84 1c84 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1c85 ; -------------------------------------------------------------------------------------- 1c85 ; Comes from: 1c85 ; 1c7f C True from color 0x0000 1c85 ; -------------------------------------------------------------------------------------- 1c85 1c85 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 1c86 1c86 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1c87 1c87 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 1c88 1c88 fiu_len_fill_lit 45 zero-fill 0x5 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 41 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_b_adr 10 TOP 1c89 1c89 fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1c8a 1c8a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1c95 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c95 0x1c95 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_frame 2 1c8b 1c8b fiu_fill_mode_src 0 ; Flow J cc=True 0x1c97 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1c97 0x1c97 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1c8c 1c8c fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x1c91 fiu_mem_start a start_continue_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c91 0x1c91 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1c8d 1c8d fiu_fill_mode_src 0 ; Flow C 0x2ab4 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c8e 1c8e fiu_mem_start 2 start-rd; Flow C cc=False 0x1c83 ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 1c83 0x1c83 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1c8f 1c8f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1c90 1c90 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1c8a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1c8a 0x1c8a typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 1c91 1c91 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1c92 1c92 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c8e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1c8e 0x1c8e seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c93 1c93 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 1c94 1c94 seq_br_type 3 Unconditional Branch; Flow J 0x1c8e seq_branch_adr 1c8e 0x1c8e 1c95 1c95 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1c96 1c96 fiu_fill_mode_src 0 ; Flow J cc=False 0x1c8c fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c8c 0x1c8c seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1c97 1c97 fiu_len_fill_lit 1f sign-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 1c98 1c98 seq_br_type 3 Unconditional Branch; Flow J 0x1c81 seq_branch_adr 1c81 0x1c81 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1c99 1c99 <halt> ; Flow R 1c9a ; -------------------------------------------------------------------------------------- 1c9a ; 0x01f7 Execute Array,Field_Read 1c9a ; -------------------------------------------------------------------------------------- 1c9a MACRO_Execute_Array,Field_Read: 1c9a 1c9a dispatch_brk_class 8 ; Flow C 0x1c7a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1c9a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c7a 0x1c7a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1c9b 1c9b fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x1ca4 fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 1ca4 0x1ca4 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 1c9c 1c9c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1c9e fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1c9e 0x1c9e seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR 1c9d 1c9d fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x1ca0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1ca0 0x1ca0 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1c9e 1c9e fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1c9f 1c9f fiu_fill_mode_src 0 ; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1ca0 0x1ca0 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 3b GP04 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1ca0 1ca0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1ca1 0x1ca1 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 04 GP04 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1ca1 1ca1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 04 GP04 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 1ca2 ; -------------------------------------------------------------------------------------- 1ca2 ; 0x018f Execute Subarray,Field_Read 1ca2 ; -------------------------------------------------------------------------------------- 1ca2 MACRO_Execute_Subarray,Field_Read: 1ca2 1ca2 dispatch_brk_class 8 ; Flow C 0x1c7a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ca2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c7a 0x1c7a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ca3 1ca3 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x1c9c fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 1c9c 0x1c9c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x07) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 1ca4 1ca4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1ca5 1ca5 <halt> ; Flow R 1ca6 ; -------------------------------------------------------------------------------------- 1ca6 ; 0x01f6 Execute Array,Field_Write 1ca6 ; -------------------------------------------------------------------------------------- 1ca6 MACRO_Execute_Array,Field_Write: 1ca6 1ca6 dispatch_brk_class 2 ; Flow C 0x1c7a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ca6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c7a 0x1c7a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ca7 1ca7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1ca8 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1ca8 0x1ca8 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1ca8 1ca8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 2e TOP + 1 1ca9 1ca9 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d78 0x1d78 seq_en_micro 0 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1caa ; -------------------------------------------------------------------------------------- 1caa ; 0x018e Execute Subarray,Field_Write 1caa ; -------------------------------------------------------------------------------------- 1caa MACRO_Execute_Subarray,Field_Write: 1caa 1caa dispatch_brk_class 2 ; Flow C 0x1c7a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1caa fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c7a 0x1c7a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1cab 1cab fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1ca8 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1ca8 0x1ca8 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1cac ; -------------------------------------------------------------------------------------- 1cac ; 0x01f5 Execute Array,Field_Reference 1cac ; -------------------------------------------------------------------------------------- 1cac MACRO_Execute_Array,Field_Reference: 1cac 1cac dispatch_brk_class 8 ; Flow C 0x1c7a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cac fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c7a 0x1c7a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1cad 1cad fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1cae ; -------------------------------------------------------------------------------------- 1cae ; 0x018d Execute Subarray,Field_Reference 1cae ; -------------------------------------------------------------------------------------- 1cae MACRO_Execute_Subarray,Field_Reference: 1cae 1cae dispatch_brk_class 8 ; Flow C 0x1c7a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cae fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 1c7a 0x1c7a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1caf 1caf fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR05:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1cb0 ; -------------------------------------------------------------------------------------- 1cb0 ; 0x01f3 Execute Array,Subarray 1cb0 ; -------------------------------------------------------------------------------------- 1cb0 MACRO_Execute_Array,Subarray: 1cb0 1cb0 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cb0 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1cb1 1cb1 seq_b_timing 1 Latch Condition; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 20 TR1c:00 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1cb2 1cb2 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x32d9 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 typ_a_adr 39 TR02:19 typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1cb3 1cb3 ioc_tvbs 5 seq+seq; Flow C cc=False 0x32d9 seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1cb4 1cb4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 1cb5 1cb5 fiu_mem_start 4 continue typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 1cb6 1cb6 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 1cb7 1cb7 fiu_load_tar 1 hold_tar; Flow C 0x332e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1cb8 1cb8 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1cb9 1cb9 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 07 GP07 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1cba 1cba ioc_fiubs 1 val ; Flow C cc=False 0x1cc2 seq_br_type 4 Call False seq_branch_adr 1cc2 0x1cc2 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_rand c START_MULTIPLY 1cbb 1cbb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 07 GP07 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1cbc 1cbc fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1cb5 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1cb5 0x1cb5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_mar_cntl d LOAD_MAR_TYPE 1cbd 1cbd ioc_adrbs 2 typ ioc_fiubs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 seq_random 18 Load_control_top+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 1cbe 1cbe seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 1cbf 1cbf seq_b_timing 1 Latch Condition; Flow J cc=True 0x1cc1 seq_br_type 1 Branch True seq_branch_adr 1cc1 0x1cc1 typ_csa_cntl 3 POP_CSA 1cc0 1cc0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1b A_OR_B typ_b_adr 36 TR11:16 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1cc1 1cc1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1b A_OR_B typ_b_adr 35 TR11:15 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1cc2 ; -------------------------------------------------------------------------------------- 1cc2 ; Comes from: 1cc2 ; 1cba C False from color MACRO_Execute_Array,Subarray 1cc2 ; -------------------------------------------------------------------------------------- 1cc2 1cc2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1cc3 1cc3 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1cc4 ; -------------------------------------------------------------------------------------- 1cc4 ; 0xc000-0xc1ff Store llvl,ldelta 1cc4 ; Comes from: 1cc4 ; 1ccb C from color 0x1cc9 1cc4 ; -------------------------------------------------------------------------------------- 1cc4 MACRO_Store_llvl,ldelta: 1cc4 1cc4 dispatch_brk_class 2 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1cc4 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1cc5 1cc5 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x1d3c fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d3c 0x1d3c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x05) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1cc6 1cc6 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1d3d ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 1d3d 0x1d3d seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1cc7 1cc7 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 2 typ_frame 1e 1cc8 1cc8 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x14) Deletion_Key typ_b_adr 03 GP03 typ_frame 14 1cc9 1cc9 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 1cca ; -------------------------------------------------------------------------------------- 1cca ; 0x009b Action Store_Dynamic 1cca ; -------------------------------------------------------------------------------------- 1cca MACRO_Action_Store_Dynamic: 1cca 1cca dispatch_brk_class 2 ; Flow C 0x2ca0 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1cca seq_br_type 7 Unconditional Call seq_branch_adr 2ca0 0x2ca0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 1ccb 1ccb fiu_mem_start 2 start-rd; Flow C 0x1cc4 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1cc4 MACRO_Store_llvl,ldelta 1ccc ; -------------------------------------------------------------------------------------- 1ccc ; 0xc200-0xdfff Store llvl,ldelta 1ccc ; -------------------------------------------------------------------------------------- 1ccc MACRO_Store_llvl,ldelta: 1ccc 1ccc dispatch_brk_class 2 ; Flow J cc=True 0x1cd3 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1ccc fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1cd3 0x1cd3 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1ccd 1ccd fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x1d3c fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d3c 0x1d3c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1cce 1cce fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1d3d ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 1d3d 0x1d3d seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1ccf 1ccf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1d40 seq_br_type 1 Branch True seq_branch_adr 1d40 0x1d40 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_c_lit 2 typ_frame 1e 1cd0 1cd0 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 1cd1 1cd1 <halt> ; Flow R 1cd2 ; -------------------------------------------------------------------------------------- 1cd2 ; 0xa200-0xbfff Store_Unchecked llvl,ldelta 1cd2 ; -------------------------------------------------------------------------------------- 1cd2 MACRO_Store_Unchecked_llvl,ldelta: 1cd2 1cd2 dispatch_brk_class 2 ; Flow J cc=True 0x1ccd dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 1cd2 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1ccd 0x1ccd seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3f TR05:1f typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1cd3 1cd3 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=False 0x1ccd fiu_mem_start 7 start_wr_if_true fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1ccd 0x1ccd seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 1 RESTORE_RDR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1cd4 1cd4 ioc_load_wdr 0 ; Flow J cc=True 0x1cd5 ; Flow J cc=#0x0 0x1cd5 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 1cd5 0x1cd5 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 10 TOP 1cd5 1cd5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1cd6 1cd6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1cd7 1cd7 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1cdd ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1cdd 0x1cdd seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1cd8 1cd8 seq_br_type 3 Unconditional Branch; Flow J 0x1cdd seq_branch_adr 1cdd 0x1cdd typ_csa_cntl 3 POP_CSA 1cd9 1cd9 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1cda 1cda seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1cdb 1cdb seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1cdc 1cdc fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1cdd 0x1cdd seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1cdd 1cdd fiu_mem_start 3 start-wr; Flow C 0x332e ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 typ_b_adr 03 GP03 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 03 GP03 1cde 1cde seq_br_type 3 Unconditional Branch; Flow J 0x1ccd seq_branch_adr 1ccd 0x1ccd typ_b_adr 03 GP03 typ_mar_cntl 1 RESTORE_RDR val_b_adr 03 GP03 1cdf 1cdf <halt> ; Flow R 1ce0 ; -------------------------------------------------------------------------------------- 1ce0 ; 0x0059 Store_Top Discrete,At_Offset_1 1ce0 ; -------------------------------------------------------------------------------------- 1ce0 MACRO_Store_Top_Discrete,At_Offset_1: 1ce0 1ce0 dispatch_brk_class 2 ; Flow C 0x1d0f dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ce0 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1d0f 0x1d0f seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1ce1 1ce1 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 1ce2 ; -------------------------------------------------------------------------------------- 1ce2 ; 0x005a Store_Top Discrete,At_Offset_2 1ce2 ; -------------------------------------------------------------------------------------- 1ce2 MACRO_Store_Top_Discrete,At_Offset_2: 1ce2 1ce2 dispatch_brk_class 2 ; Flow C 0x1d0f dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1ce2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1d0f 0x1d0f seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1ce3 1ce3 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 21 TOP - 0x2 1ce4 ; -------------------------------------------------------------------------------------- 1ce4 ; 0x005b Store_Top Discrete,At_Offset_3 1ce4 ; -------------------------------------------------------------------------------------- 1ce4 MACRO_Store_Top_Discrete,At_Offset_3: 1ce4 1ce4 dispatch_brk_class 2 ; Flow C 0x1d0f dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1ce4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1d0f 0x1d0f seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1d TOP - 3 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1ce5 1ce5 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR06:07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 22 TOP - 0x3 1ce6 ; -------------------------------------------------------------------------------------- 1ce6 ; 0x005c Store_Top Discrete,At_Offset_4 1ce6 ; -------------------------------------------------------------------------------------- 1ce6 MACRO_Store_Top_Discrete,At_Offset_4: 1ce6 1ce6 dispatch_brk_class 2 ; Flow C 0x1d0f dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1ce6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1d0f 0x1d0f seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1c TOP - 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1c TOP - 4 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1ce7 1ce7 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 1ce8 ; -------------------------------------------------------------------------------------- 1ce8 ; 0x005d Store_Top Discrete,At_Offset_5 1ce8 ; -------------------------------------------------------------------------------------- 1ce8 MACRO_Store_Top_Discrete,At_Offset_5: 1ce8 1ce8 dispatch_brk_class 2 ; Flow C 0x1d0f dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1ce8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1d0f 0x1d0f seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1b TOP - 5 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1b TOP - 5 val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1ce9 1ce9 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 24 TOP - 0x5 1cea ; -------------------------------------------------------------------------------------- 1cea ; 0x005e Store_Top Discrete,At_Offset_6 1cea ; -------------------------------------------------------------------------------------- 1cea MACRO_Store_Top_Discrete,At_Offset_6: 1cea 1cea dispatch_brk_class 2 ; Flow C 0x1d0f dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cea fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1d0f 0x1d0f seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1a TOP - 6 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1a TOP - 6 val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1ceb 1ceb fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 3c TR06:1c typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 25 TOP - 0x6 1cec ; -------------------------------------------------------------------------------------- 1cec ; 0x0051 Store_Top_Unchecked Discrete,At_Offset_1 1cec ; -------------------------------------------------------------------------------------- 1cec MACRO_Store_Top_Unchecked_Discrete,At_Offset_1: 1cec 1cec dispatch_brk_class 2 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cec fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1ced 1ced <halt> ; Flow R 1cee ; -------------------------------------------------------------------------------------- 1cee ; 0x0052 Store_Top_Unchecked Discrete,At_Offset_2 1cee ; -------------------------------------------------------------------------------------- 1cee MACRO_Store_Top_Unchecked_Discrete,At_Offset_2: 1cee 1cee dispatch_brk_class 2 ; Flow R dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1cee fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1cef 1cef <halt> ; Flow R 1cf0 ; -------------------------------------------------------------------------------------- 1cf0 ; 0x0053 Store_Top_Unchecked Discrete,At_Offset_3 1cf0 ; -------------------------------------------------------------------------------------- 1cf0 MACRO_Store_Top_Unchecked_Discrete,At_Offset_3: 1cf0 1cf0 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1cf0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1cf1 1cf1 <halt> ; Flow R 1cf2 ; -------------------------------------------------------------------------------------- 1cf2 ; 0x0054 Store_Top_Unchecked Discrete,At_Offset_4 1cf2 ; -------------------------------------------------------------------------------------- 1cf2 MACRO_Store_Top_Unchecked_Discrete,At_Offset_4: 1cf2 1cf2 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1cf2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1c TOP - 4 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1cf3 1cf3 <halt> ; Flow R 1cf4 ; -------------------------------------------------------------------------------------- 1cf4 ; 0x0055 Store_Top_Unchecked Discrete,At_Offset_5 1cf4 ; -------------------------------------------------------------------------------------- 1cf4 MACRO_Store_Top_Unchecked_Discrete,At_Offset_5: 1cf4 1cf4 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1cf4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1b TOP - 5 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1cf5 1cf5 <halt> ; Flow R 1cf6 ; -------------------------------------------------------------------------------------- 1cf6 ; 0x0056 Store_Top_Unchecked Discrete,At_Offset_6 1cf6 ; -------------------------------------------------------------------------------------- 1cf6 MACRO_Store_Top_Unchecked_Discrete,At_Offset_6: 1cf6 1cf6 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1cf6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1a TOP - 6 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1cf7 1cf7 <halt> ; Flow R 1cf8 ; -------------------------------------------------------------------------------------- 1cf8 ; 0x0049 Store_Top Float,At_Offset_1 1cf8 ; -------------------------------------------------------------------------------------- 1cf8 MACRO_Store_Top_Float,At_Offset_1: 1cf8 1cf8 dispatch_brk_class 2 ; Flow C 0x1d12 dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1cf8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1d12 0x1d12 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1cf9 1cf9 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 1cfa ; -------------------------------------------------------------------------------------- 1cfa ; 0x004a Store_Top Float,At_Offset_2 1cfa ; -------------------------------------------------------------------------------------- 1cfa MACRO_Store_Top_Float,At_Offset_2: 1cfa 1cfa dispatch_brk_class 2 ; Flow C 0x1d12 dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1cfa fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1d12 0x1d12 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1cfb 1cfb fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 21 TOP - 0x2 1cfc ; -------------------------------------------------------------------------------------- 1cfc ; 0x004b Store_Top Float,At_Offset_3 1cfc ; -------------------------------------------------------------------------------------- 1cfc MACRO_Store_Top_Float,At_Offset_3: 1cfc 1cfc dispatch_brk_class 2 ; Flow C 0x1d12 dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1cfc fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1d12 0x1d12 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1d TOP - 3 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1cfd 1cfd fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR06:07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 22 TOP - 0x3 1cfe ; -------------------------------------------------------------------------------------- 1cfe ; 0x004c Store_Top Float,At_Offset_4 1cfe ; -------------------------------------------------------------------------------------- 1cfe MACRO_Store_Top_Float,At_Offset_4: 1cfe 1cfe dispatch_brk_class 2 ; Flow C 0x1d12 dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1cfe fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1d12 0x1d12 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1c TOP - 4 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1c TOP - 4 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1cff 1cff fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 1d00 ; -------------------------------------------------------------------------------------- 1d00 ; 0x004d Store_Top Float,At_Offset_5 1d00 ; -------------------------------------------------------------------------------------- 1d00 MACRO_Store_Top_Float,At_Offset_5: 1d00 1d00 dispatch_brk_class 2 ; Flow C 0x1d12 dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1d00 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1d12 0x1d12 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1b TOP - 5 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1b TOP - 5 val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1d01 1d01 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 24 TOP - 0x5 1d02 ; -------------------------------------------------------------------------------------- 1d02 ; 0x004e Store_Top Float,At_Offset_6 1d02 ; -------------------------------------------------------------------------------------- 1d02 MACRO_Store_Top_Float,At_Offset_6: 1d02 1d02 dispatch_brk_class 2 ; Flow C 0x1d12 dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1d02 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 1d12 0x1d12 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 1a TOP - 6 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1a TOP - 6 val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1d03 1d03 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_int_reads 6 CONTROL TOP typ_a_adr 3c TR06:1c typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 25 TOP - 0x6 1d04 ; -------------------------------------------------------------------------------------- 1d04 ; 0x0041 Store_Top_Unchecked Float,At_Offset_1 1d04 ; -------------------------------------------------------------------------------------- 1d04 MACRO_Store_Top_Unchecked_Float,At_Offset_1: 1d04 1d04 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1d04 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1d05 1d05 <halt> ; Flow R 1d06 ; -------------------------------------------------------------------------------------- 1d06 ; 0x0042 Store_Top_Unchecked Float,At_Offset_2 1d06 ; -------------------------------------------------------------------------------------- 1d06 MACRO_Store_Top_Unchecked_Float,At_Offset_2: 1d06 1d06 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1d06 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1d07 1d07 <halt> ; Flow R 1d08 ; -------------------------------------------------------------------------------------- 1d08 ; 0x0043 Store_Top_Unchecked Float,At_Offset_3 1d08 ; -------------------------------------------------------------------------------------- 1d08 MACRO_Store_Top_Unchecked_Float,At_Offset_3: 1d08 1d08 dispatch_brk_class 2 ; Flow R dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1d08 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1d09 1d09 <halt> ; Flow R 1d0a ; -------------------------------------------------------------------------------------- 1d0a ; 0x0044 Store_Top_Unchecked Float,At_Offset_4 1d0a ; -------------------------------------------------------------------------------------- 1d0a MACRO_Store_Top_Unchecked_Float,At_Offset_4: 1d0a 1d0a dispatch_brk_class 2 ; Flow R dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1d0a fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1c TOP - 4 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1d0b 1d0b <halt> ; Flow R 1d0c ; -------------------------------------------------------------------------------------- 1d0c ; 0x0045 Store_Top_Unchecked Float,At_Offset_5 1d0c ; -------------------------------------------------------------------------------------- 1d0c MACRO_Store_Top_Unchecked_Float,At_Offset_5: 1d0c 1d0c dispatch_brk_class 2 ; Flow R dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1d0c fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1b TOP - 5 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1d0d 1d0d <halt> ; Flow R 1d0e ; -------------------------------------------------------------------------------------- 1d0e ; 0x0046 Store_Top_Unchecked Float,At_Offset_6 1d0e ; -------------------------------------------------------------------------------------- 1d0e MACRO_Store_Top_Unchecked_Float,At_Offset_6: 1d0e 1d0e dispatch_brk_class 2 ; Flow R dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1d0e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1a TOP - 6 typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1d0f ; -------------------------------------------------------------------------------------- 1d0f ; Comes from: 1d0f ; 1ce0 C from color MACRO_Store_llvl,ldelta 1d0f ; 1ce2 C from color MACRO_Store_llvl,ldelta 1d0f ; 1ce4 C from color MACRO_Store_llvl,ldelta 1d0f ; 1ce6 C from color MACRO_Store_llvl,ldelta 1d0f ; 1ce8 C from color MACRO_Store_llvl,ldelta 1d0f ; 1cea C from color MACRO_Store_llvl,ldelta 1d0f ; -------------------------------------------------------------------------------------- 1d0f 1d0f ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP 1d10 1d10 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1d11 0x1d11 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1d11 1d11 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 1d12 ; -------------------------------------------------------------------------------------- 1d12 ; Comes from: 1d12 ; 1cf8 C from color MACRO_Store_llvl,ldelta 1d12 ; 1cfa C from color MACRO_Store_llvl,ldelta 1d12 ; 1cfc C from color MACRO_Store_llvl,ldelta 1d12 ; 1cfe C from color MACRO_Store_llvl,ldelta 1d12 ; 1d00 C from color MACRO_Store_llvl,ldelta 1d12 ; 1d02 C from color MACRO_Store_llvl,ldelta 1d12 ; -------------------------------------------------------------------------------------- 1d12 1d12 ioc_fiubs 1 val ; Flow J cc=False 0x1d10 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1d10 0x1d10 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d13 1d13 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1d11 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1d11 0x1d11 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA 1d14 1d14 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1d11 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 1d11 0x1d11 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1d15 1d15 <halt> ; Flow R 1d16 ; -------------------------------------------------------------------------------------- 1d16 ; 0x0039 Store_Top Access,At_Offset_1 1d16 ; -------------------------------------------------------------------------------------- 1d16 MACRO_Store_Top_Access,At_Offset_1: 1d16 1d16 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1d16 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1d17 0x1d17 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1d17 1d17 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR02:12 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP 1d18 ; -------------------------------------------------------------------------------------- 1d18 ; 0x003a Store_Top Access,At_Offset_2 1d18 ; -------------------------------------------------------------------------------------- 1d18 MACRO_Store_Top_Access,At_Offset_2: 1d18 1d18 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1d18 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1d19 0x1d19 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1d19 1d19 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 1d1a ; -------------------------------------------------------------------------------------- 1d1a ; 0x003b Store_Top Access,At_Offset_3 1d1a ; -------------------------------------------------------------------------------------- 1d1a MACRO_Store_Top_Access,At_Offset_3: 1d1a 1d1a dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1d1a fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1d1b 0x1d1b seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1d1b 1d1b fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 21 TOP - 0x2 1d1c ; -------------------------------------------------------------------------------------- 1d1c ; 0x003c Store_Top Access,At_Offset_4 1d1c ; -------------------------------------------------------------------------------------- 1d1c MACRO_Store_Top_Access,At_Offset_4: 1d1c 1d1c dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1d1c fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1d1d 0x1d1d seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1c TOP - 4 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1c TOP - 4 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1d1d 1d1d fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR06:07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 22 TOP - 0x3 1d1e ; -------------------------------------------------------------------------------------- 1d1e ; 0x003d Store_Top Access,At_Offset_5 1d1e ; -------------------------------------------------------------------------------------- 1d1e MACRO_Store_Top_Access,At_Offset_5: 1d1e 1d1e dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1d1e fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1d1f 0x1d1f seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1b TOP - 5 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1b TOP - 5 val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1d1f 1d1f fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 1d20 ; -------------------------------------------------------------------------------------- 1d20 ; 0x003e Store_Top Access,At_Offset_6 1d20 ; -------------------------------------------------------------------------------------- 1d20 MACRO_Store_Top_Access,At_Offset_6: 1d20 1d20 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1d20 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1d21 0x1d21 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1a TOP - 6 typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1a TOP - 6 val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1d21 1d21 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 24 TOP - 0x5 1d22 ; -------------------------------------------------------------------------------------- 1d22 ; 0x0031 Store_Top Heap_Access,At_Offset_1 1d22 ; -------------------------------------------------------------------------------------- 1d22 MACRO_Store_Top_Heap_Access,At_Offset_1: 1d22 1d22 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1d22 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1d23 0x1d23 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 1d23 1d23 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR02:12 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP 1d24 ; -------------------------------------------------------------------------------------- 1d24 ; 0x0032 Store_Top Heap_Access,At_Offset_2 1d24 ; -------------------------------------------------------------------------------------- 1d24 MACRO_Store_Top_Heap_Access,At_Offset_2: 1d24 1d24 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1d24 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1d25 0x1d25 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 1d25 1d25 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 1d26 ; -------------------------------------------------------------------------------------- 1d26 ; 0x0033 Store_Top Heap_Access,At_Offset_3 1d26 ; -------------------------------------------------------------------------------------- 1d26 MACRO_Store_Top_Heap_Access,At_Offset_3: 1d26 1d26 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 1d26 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1d27 0x1d27 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1d TOP - 3 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 1d27 1d27 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 21 TOP - 0x2 1d28 ; -------------------------------------------------------------------------------------- 1d28 ; 0x0034 Store_Top Heap_Access,At_Offset_4 1d28 ; -------------------------------------------------------------------------------------- 1d28 MACRO_Store_Top_Heap_Access,At_Offset_4: 1d28 1d28 dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 1d28 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1d29 0x1d29 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1c TOP - 4 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1c TOP - 4 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 1d29 1d29 fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 27 TR06:07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 22 TOP - 0x3 1d2a ; -------------------------------------------------------------------------------------- 1d2a ; 0x0035 Store_Top Heap_Access,At_Offset_5 1d2a ; -------------------------------------------------------------------------------------- 1d2a MACRO_Store_Top_Heap_Access,At_Offset_5: 1d2a 1d2a dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1d2a fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1d2b 0x1d2b seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1b TOP - 5 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1b TOP - 5 val_c_adr 24 TOP - 0x5 val_c_mux_sel 2 ALU 1d2b 1d2b fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 1d2c ; -------------------------------------------------------------------------------------- 1d2c ; 0x0036 Store_Top Heap_Access,At_Offset_6 1d2c ; -------------------------------------------------------------------------------------- 1d2c MACRO_Store_Top_Heap_Access,At_Offset_6: 1d2c 1d2c dispatch_brk_class 2 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 1d2c fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type c Dispatch True seq_branch_adr 1d2d 0x1d2d seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1a TOP - 6 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1a TOP - 6 val_c_adr 25 TOP - 0x6 val_c_mux_sel 2 ALU 1d2d 1d2d fiu_mem_start 2 start-rd; Flow J 0x1ccc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ccc MACRO_Store_llvl,ldelta seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 35 TR09:15 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 24 TOP - 0x5 1d2e ; -------------------------------------------------------------------------------------- 1d2e ; 0x1a00-0x1aff Execute Package,Field_Write,fieldnum 1d2e ; -------------------------------------------------------------------------------------- 1d2e MACRO_Execute_Package,Field_Write,fieldnum: 1d2e 1d2e dispatch_brk_class 2 dispatch_csa_valid 2 dispatch_mem_strt 6 CONTROL READ, AT VALUE_ITEM.NAME PLUS FIELD NUMBER dispatch_uadr 1d2e dispatch_uses_tos 1 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu typ_a_adr 10 TOP typ_c_lit 1 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1d2f 1d2f ioc_random 17 force type bus receivers; Flow J cc=False 0x1d31 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1d31 0x1d31 seq_cond_sel 79 IOC.PFR seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1d30 1d30 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x1d3c fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d3c 0x1d3c typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 16 CSA/VAL_BUS 1d31 1d31 seq_br_type 0 Branch False; Flow J cc=False 0x1d3a seq_branch_adr 1d3a 0x1d3a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 03 GP03 1d32 1d32 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x1d3c fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d3c 0x1d3c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 1d33 1d33 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1d3d ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 1d3d 0x1d3d seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d34 1d34 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 1d35 1d35 <halt> ; Flow R 1d36 ; -------------------------------------------------------------------------------------- 1d36 ; 0x0097 Execute Package,Field_Write_Dynamic 1d36 ; -------------------------------------------------------------------------------------- 1d36 MACRO_Execute_Package,Field_Write_Dynamic: 1d36 1d36 dispatch_brk_class 2 ; Flow C 0x32d7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 1d36 fiu_len_fill_lit 58 zero-fill 0x18 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_a_adr 10 TOP val_b_adr 1f TOP - 1 1d37 1d37 fiu_mem_start 2 start-rd; Flow C cc=True 0x32de ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3e VR05:1e val_frame 5 1d38 1d38 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1d39 1d39 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x1d32 seq_br_type 3 Unconditional Branch seq_branch_adr 1d32 0x1d32 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1d3a 1d3a fiu_tivi_src 2 tar_fiu; Flow C cc=True 0x32da ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32da 0x32da seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR05:04 typ_frame 5 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR05:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 1d3b 1d3b seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_en_micro 0 1d3c ; -------------------------------------------------------------------------------------- 1d3c ; Comes from: 1d3c ; 1cc5 C from color MACRO_Store_llvl,ldelta 1d3c ; 1ccd C from color MACRO_Store_llvl,ldelta 1d3c ; 1d30 C from color MACRO_Execute_Package,Field_Write,fieldnum 1d3c ; 1d32 C from color MACRO_Execute_Package,Field_Write,fieldnum 1d3c ; -------------------------------------------------------------------------------------- 1d3c 1d3c ioc_fiubs 1 val ; Flow J cc=True 0x1d3d ; Flow J cc=#0x0 0x1d58 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 1d58 0x1d58 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1d3d 1d3d val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1d3e 1d3e fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x1d3c fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d3c 0x1d3c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1d3f 1d3f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d40 1d40 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1d46 seq_br_type 1 Branch True seq_branch_adr 1d46 0x1d46 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_frame 1 1d41 1d41 fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x1d44 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 1d44 0x1d44 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 1d42 1d42 ioc_load_wdr 0 typ_b_adr 10 TOP val_b_adr 10 TOP 1d43 1d43 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1d44 1d44 fiu_mem_start 8 start_wr_if_false; Flow J cc=False 0x1d42 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d42 0x1d42 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 1d45 1d45 seq_br_type 7 Unconditional Call; Flow C 0x32da seq_branch_adr 32da 0x32da 1d46 1d46 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1d42 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d42 0x1d42 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 10 TOP typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 1d47 1d47 fiu_mem_start 8 start_wr_if_false; Flow J cc=False 0x1d42 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d42 0x1d42 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 10 TOP typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS 1d48 1d48 fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x1d42 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 1d42 0x1d42 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 1d49 1d49 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x1d4c fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 71 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1d4c 0x1d4c seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_frame e typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 1d4a 1d4a fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x1d56 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1d56 0x1d56 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 1d4b 1d4b seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 1d4c 1d4c fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1d4d 1d4d fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator 1d4e 1d4e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 10 TOP val_b_adr 01 GP01 1d4f 1d4f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 1d50 1d50 ioc_load_wdr 0 ; Flow J 0x1d43 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1d43 0x1d43 val_b_adr 10 TOP 1d51 1d51 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1d52 1d52 ioc_load_wdr 0 ; Flow J cc=True 0x1d57 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1d57 0x1d57 val_b_adr 06 GP06 1d53 1d53 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x1d56 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1d56 0x1d56 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 1d54 1d54 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 1d55 1d55 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1d56 1d56 seq_br_type 3 Unconditional Branch; Flow J 0x1d51 seq_branch_adr 1d51 0x1d51 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 05 GP05 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1d57 1d57 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1d4f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1d4f 0x1d4f typ_a_adr 10 TOP 1d58 1d58 fiu_mem_start 3 start-wr; Flow J 0x1d8c ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d8c 0x1d8c typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d59 1d59 fiu_mem_start 2 start-rd; Flow J 0x1d93 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d93 0x1d93 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d5a 1d5a fiu_mem_start 3 start-wr; Flow J 0x1da0 ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1da0 0x1da0 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d5b 1d5b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1da7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1da7 0x1da7 seq_random 02 ? typ_a_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d5c 1d5c fiu_mem_start 7 start_wr_if_true; Flow J 0x1db8 ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1db8 0x1db8 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 10 TOP 1d5d 1d5d fiu_mem_start 2 start-rd; Flow J 0x1dc3 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1dc3 0x1dc3 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d5e 1d5e seq_br_type 7 Unconditional Call; Flow C 0x32db seq_branch_adr 32db 0x32db 1d5f 1d5f seq_br_type 7 Unconditional Call; Flow C 0x32db seq_branch_adr 32db 0x32db 1d60 1d60 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d61 1d61 seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c 1d62 1d62 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d63 1d63 seq_br_type 7 Unconditional Call; Flow C 0x329c seq_branch_adr 329c 0x329c 1d64 1d64 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d65 1d65 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d66 1d66 fiu_mem_start 7 start_wr_if_true; Flow J 0x1dbd ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1dbd 0x1dbd seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 10 TOP 1d67 1d67 fiu_mem_start 2 start-rd; Flow J 0x1dce ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1dce 0x1dce typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d68 1d68 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d69 1d69 fiu_mem_start 2 start-rd; Flow J 0x1de2 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1de2 0x1de2 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d6a 1d6a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d6b 1d6b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1de9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1de9 0x1de9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d6c 1d6c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d6d 1d6d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d6e 1d6e seq_br_type 7 Unconditional Call; Flow C 0x32db seq_branch_adr 32db 0x32db 1d6f 1d6f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d70 1d70 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d71 1d71 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d72 1d72 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d73 1d73 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e1a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e1a 0x1e1a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d74 1d74 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d75 1d75 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e3e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e3e 0x1e3e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d76 1d76 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d77 1d77 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e7a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e7a 0x1e7a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 1d78 ; -------------------------------------------------------------------------------------- 1d78 ; Comes from: 1d78 ; 0aaa C from color MACRO_Execute_Any,Write_Unchecked 1d78 ; 0aad C from color 0x0aac 1d78 ; 0c2b C from color MACRO_Execute_Heap_Access,All_Write 1d78 ; 0c2e C from color 0x0c2c 1d78 ; 152d C from color MACRO_Execute_Matrix,Field_Write 1d78 ; 1534 C from color MACRO_Execute_Matrix,Field_Write 1d78 ; 1537 C from color MACRO_Execute_Matrix,Field_Write 1d78 ; 1657 C from color 0x098b 1d78 ; 165e C from color 0x165a 1d78 ; 1664 C from color 0x165f 1d78 ; 1676 C from color 0x166c 1d78 ; 1811 C from color MACRO_Execute_Record,Field_Write,fieldnum 1d78 ; 1813 C from color MACRO_Execute_Record,Field_Write_Dynamic 1d78 ; 18f9 C from color MACRO_Execute_Vector,Field_Write 1d78 ; 18fc C from color MACRO_Execute_Vector,Field_Write 1d78 ; 18fd C from color 0x18fd 1d78 ; 1903 C from color MACRO_Execute_Vector,Field_Write 1d78 ; 190a C from color MACRO_Execute_Vector,Field_Write 1d78 ; 190c C from color MACRO_Execute_Vector,Field_Write 1d78 ; 1a4f C from color MACRO_Execute_Vector,Append 1d78 ; 1a71 C from color MACRO_Execute_Vector,Prepend 1d78 ; 1b1b C from color MACRO_Execute_Access,All_Write 1d78 ; 1b1e C from color 0x1b1c 1d78 ; 1ca9 C from color MACRO_Execute_Array,Field_Write 1d78 ; 3616 C from color 0x3611 1d78 ; -------------------------------------------------------------------------------------- 1d78 1d78 ioc_fiubs 1 val ; Flow J cc=True 0x1d79 ; Flow J cc=#0x0 0x1d79 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 1d79 0x1d79 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1d79 1d79 fiu_load_oreg 1 hold_oreg; Flow J 0x1d95 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d95 0x1d95 typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d7a 1d7a fiu_load_oreg 1 hold_oreg; Flow J 0x1da7 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1da7 0x1da7 typ_a_adr 1f TOP - 1 typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 03 GP03 1d7b 1d7b fiu_load_oreg 1 hold_oreg; Flow J 0x1dc7 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1dc7 0x1dc7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 03 GP03 1d7c 1d7c seq_br_type 7 Unconditional Call; Flow C 0x32db seq_branch_adr 32db 0x32db 1d7d 1d7d seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d7e 1d7e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d7f 1d7f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d80 1d80 fiu_load_oreg 1 hold_oreg; Flow J 0x1dd0 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1dd0 0x1dd0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1d81 1d81 fiu_mem_start 2 start-rd; Flow J 0x1de2 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1de2 0x1de2 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d82 1d82 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1de9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1de9 0x1de9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d83 1d83 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d84 1d84 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d85 1d85 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1d86 1d86 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e1a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e1a 0x1e1a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d87 1d87 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e3e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e3e 0x1e3e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d88 1d88 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e7a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e7a 0x1e7a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d89 ; -------------------------------------------------------------------------------------- 1d89 ; Comes from: 1d89 ; 1de6 C False from color 0x1d69 1d89 ; 1e3f C False from color MACRO_Execute_Matrix,Structure_Write 1d89 ; 1e53 C False from color MACRO_Execute_Matrix,Structure_Write 1d89 ; -------------------------------------------------------------------------------------- 1d89 1d89 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1d8a 0x1d8a seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1d8a 1d8a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32db seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 22 VR02:02 val_frame 2 1d8b 1d8b ioc_tvbs 5 seq+seq; Flow R cc=False ; Flow J cc=True 0x32db seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS 1d8c 1d8c ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_c_adr 3b GP04 val_c_adr 3b GP04 1d8d 1d8d fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1d8e 0x1d8e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1d8e 1d8e fiu_mem_start 3 start-wr; Flow C 0x332e ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_b_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 03 GP03 1d8f 1d8f fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1d90 1d90 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 1d91 1d91 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x329e seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 1d92 1d92 seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 1d93 1d93 ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1d94 1d94 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1d95 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1d95 0x1d95 seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d95 1d95 fiu_fill_mode_src 0 ; Flow J cc=False 0x1d98 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1d98 0x1d98 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3b GP04 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3b GP04 1d96 1d96 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d97 1d97 ioc_load_wdr 0 ; Flow J 0x1d9c ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1d9c 0x1d9c seq_random 02 ? typ_c_adr 3e GP01 typ_csa_cntl 3 POP_CSA val_c_adr 3e GP01 1d98 1d98 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1d99 1d99 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3e GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 1d9a 1d9a fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3a GP05 1d9b 1d9b ioc_load_wdr 0 ; Flow J 0x1d9c ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1d9c 0x1d9c typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 1d9c 1d9c fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1d9d 0x1d9d seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1d9d 1d9d fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1d9e 1d9e fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1d8f ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1d8f 0x1d8f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 1d9f 1d9f ioc_load_wdr 0 ; Flow J 0x1d8f seq_br_type 3 Unconditional Branch seq_branch_adr 1d8f 0x1d8f typ_b_adr 05 GP05 val_b_adr 05 GP05 1da0 1da0 ioc_load_wdr 0 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 seq_random 02 ? typ_b_adr 03 GP03 typ_c_adr 3b GP04 val_alu_func 1a PASS_B val_c_adr 3b GP04 1da1 1da1 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1da3 seq_br_type 1 Branch True seq_branch_adr 1da3 0x1da3 typ_csa_cntl 3 POP_CSA 1da2 1da2 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x1da5 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1da5 0x1da5 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1da3 1da3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1da5 seq_br_type 1 Branch True seq_branch_adr 1da5 0x1da5 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 1da4 1da4 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1da5 0x1da5 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 1da5 1da5 fiu_mem_start 3 start-wr; Flow C 0x332e ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_b_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 03 GP03 1da6 1da6 seq_br_type 7 Unconditional Call; Flow C 0x329e seq_branch_adr 329e 0x329e 1da7 1da7 fiu_fill_mode_src 0 ; Flow J cc=False 0x1dad fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1dad 0x1dad seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_c_adr 3b GP04 1da8 1da8 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1da9 1da9 ioc_load_wdr 0 ; Flow J cc=True 0x1dab ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1dab 0x1dab seq_random 02 ? typ_c_adr 3e GP01 typ_csa_cntl 3 POP_CSA val_c_adr 3e GP01 1daa 1daa fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x1db4 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1db4 0x1db4 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1dab 1dab seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1db4 seq_br_type 1 Branch True seq_branch_adr 1db4 0x1db4 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA 1dac 1dac fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x1db4 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1db4 0x1db4 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 1dad 1dad fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ typ_c_adr 3b GP04 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1dae 1dae fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3e GP01 1daf 1daf fiu_mem_start 4 continue; Flow J cc=True 0x1db2 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1db2 0x1db2 seq_random 02 ? typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3a GP05 1db0 1db0 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 1db1 1db1 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x1db4 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1db4 0x1db4 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 04 GP04 1db2 1db2 ioc_load_wdr 0 ; Flow J cc=True 0x1db4 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1db4 0x1db4 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 1db3 1db3 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1db4 0x1db4 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 1db4 1db4 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1db5 1db5 fiu_mem_start a start_continue_if_false ioc_load_wdr 0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 1db6 1db6 ioc_load_wdr 0 ; Flow C 0x329e seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_b_adr 05 GP05 val_b_adr 05 GP05 1db7 1db7 seq_br_type 7 Unconditional Call; Flow C 0x329e seq_branch_adr 329e 0x329e 1db8 1db8 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1dbc seq_br_type 1 Branch True seq_branch_adr 1dbc 0x1dbc seq_random 02 ? val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1db9 1db9 seq_br_type 7 Unconditional Call; Flow C 0x24ba seq_branch_adr 24ba 0x24ba seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1dba 1dba fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x1dc0 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1dc0 0x1dc0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1dbb 1dbb ioc_load_wdr 0 typ_b_adr 03 GP03 val_b_adr 10 TOP 1dbc 1dbc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1dbd 1dbd seq_b_timing 1 Latch Condition; Flow J cc=True 0x1dbc seq_br_type 1 Branch True seq_branch_adr 1dbc 0x1dbc seq_random 02 ? val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1dbe 1dbe seq_br_type 7 Unconditional Call; Flow C 0x24c4 seq_branch_adr 24c4 0x24c4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1dbf 1dbf fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x1dbb ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1dbb 0x1dbb typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A 1dc0 1dc0 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1dc1 1dc1 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a4 0x32a4 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame c 1dc2 1dc2 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 1dc3 1dc3 typ_a_adr 10 TOP typ_frame 10 typ_rand b CARRY IN = Q BIT FROM VAL 1dc4 1dc4 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1dc7 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1dc7 0x1dc7 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1dc5 1dc5 fiu_load_tar 1 hold_tar; Flow C 0x24ba fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 24ba 0x24ba seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1dc6 1dc6 fiu_len_fill_reg_ctl 2 ; Flow J cc=False 0x1dc0 fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1dc0 0x1dc0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1dc7 1dc7 fiu_fill_mode_src 0 ; Flow J cc=False 0x1dcb fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1dcb 0x1dcb seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 1dc8 1dc8 fiu_fill_mode_src 0 ; Flow J cc=False 0x1dc5 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1dc5 0x1dc5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1dc9 1dc9 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA 1dca 1dca fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1dcb 1dcb fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1dcc 1dcc fiu_fill_mode_src 0 ; Flow J cc=False 0x1dc5 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1dc5 0x1dc5 typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1dcd 1dcd fiu_load_var 1 hold_var; Flow J 0x1dc9 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1dc9 0x1dc9 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1dce 1dce fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS val_a_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1dcf 1dcf fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J 0x1dd0 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1dd0 0x1dd0 seq_random 02 ? typ_a_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 03 GP03 1dd0 1dd0 fiu_fill_mode_src 0 ; Flow J cc=False 0x1dd3 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1dd3 0x1dd3 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 1dd1 1dd1 fiu_fill_mode_src 0 ; Flow C cc=True 0x1dde fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1dde 0x1dde typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1dd2 1dd2 ioc_load_wdr 0 ; Flow J 0x1dd7 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1dd7 0x1dd7 seq_random 02 ? typ_c_adr 3b GP04 typ_csa_cntl 3 POP_CSA val_c_adr 3b GP04 1dd3 1dd3 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1dd4 1dd4 fiu_fill_mode_src 0 ; Flow C cc=True 0x1dde fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1dde 0x1dde typ_c_adr 3b GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3b GP04 1dd5 1dd5 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3a GP05 1dd6 1dd6 ioc_load_wdr 0 ; Flow J 0x1dd7 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1dd7 0x1dd7 typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 1dd7 1dd7 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1dd8 0x1dd8 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1dd8 1dd8 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1dd9 1dd9 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1ddb ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1ddb 0x1ddb seq_cond_sel 65 CROSS_WORD_FIELD~ typ_b_adr 04 GP04 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 1dda 1dda ioc_load_wdr 0 ; Flow J 0x1ddb seq_br_type 3 Unconditional Branch seq_branch_adr 1ddb 0x1ddb typ_b_adr 05 GP05 val_b_adr 05 GP05 1ddb 1ddb fiu_load_tar 1 hold_tar; Flow C 0x24c4 fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 24c4 0x24c4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1ddc 1ddc fiu_len_fill_reg_ctl 2 ; Flow J cc=False 0x1dc0 ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1dc0 0x1dc0 typ_b_adr 1f TOP - 1 1ddd 1ddd fiu_load_oreg 1 hold_oreg; Flow J 0x1dd0 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 1dd0 0x1dd0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1dde ; -------------------------------------------------------------------------------------- 1dde ; Comes from: 1dde ; 1dd1 C True from color 0x1d5c 1dde ; 1dd4 C True from color 0x1d5c 1dde ; -------------------------------------------------------------------------------------- 1dde 1dde fiu_tivi_src c mar_0xc; Flow C cc=False 0x32e1 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32e1 0x32e1 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1ddf 1ddf fiu_fill_mode_src 0 ; Flow J cc=False 0x1de1 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1de1 0x1de1 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 1f TOP - 1 1de0 1de0 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert ioc_adrbs 1 val seq_br_type a Unconditional Return typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1de1 1de1 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_adrbs 1 val seq_br_type a Unconditional Return typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 1de2 1de2 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1de6 seq_br_type 1 Branch True seq_branch_adr 1de6 0x1de6 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_lit 1 typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1de3 1de3 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1de4 1de4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1de5 1de5 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1de6 1de6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d89 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d89 0x1d89 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 1de7 1de7 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x1f1e seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 1de8 1de8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1de9 1de9 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1dec seq_br_type 1 Branch True seq_branch_adr 1dec 0x1dec seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_lit 1 typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 39 GP06 1dea 1dea fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1deb 1deb fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1dec 1dec fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d89 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d89 0x1d89 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1ded 1ded fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1df6 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1df6 0x1df6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 06 GP06 typ_c_adr 38 GP07 1dee 1dee ioc_tvbs 2 fiu+val; Flow J cc=True 0x1df3 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1df3 0x1df3 typ_a_adr 20 TR08:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1def 1def seq_br_type 7 Unconditional Call; Flow C 0x272c seq_branch_adr 272c 0x272c typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1df0 1df0 ioc_fiubs 1 val ; Flow C cc=True 0x32a4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a4 0x32a4 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1df1 1df1 seq_br_type 7 Unconditional Call; Flow C 0x2488 seq_branch_adr 2488 0x2488 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 1df2 1df2 ioc_fiubs 1 val ; Flow J 0x1df6 seq_br_type 3 Unconditional Branch seq_branch_adr 1df6 0x1df6 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 1df3 1df3 fiu_load_oreg 1 hold_oreg; Flow C 0x2515 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2515 0x2515 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1df4 1df4 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x1df7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1df7 0x1df7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 1df5 1df5 seq_br_type 7 Unconditional Call; Flow C 0x32a4 seq_branch_adr 32a4 0x32a4 1df6 1df6 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 1df7 1df7 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e03 seq_br_type 1 Branch True seq_branch_adr 1e03 0x1e03 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 06 GP06 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 7 INC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1df8 1df8 fiu_fill_mode_src 0 ; Flow J cc=True 0x1e05 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e05 0x1e05 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 1df9 1df9 ioc_fiubs 1 val ; Flow J cc=False 0x1e00 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1e00 0x1e00 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 1dfa 1dfa fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1dfb 1dfb seq_b_timing 0 Early Condition; Flow J cc=True 0x1e00 seq_br_type 1 Branch True seq_branch_adr 1e00 0x1e00 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 1dfc 1dfc fiu_mem_start 2 start-rd; Flow C 0x2484 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2484 0x2484 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1dfd 1dfd ioc_fiubs 1 val ; Flow J cc=True 0x1e00 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1e00 0x1e00 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1dfe 1dfe seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e00 seq_br_type 1 Branch True seq_branch_adr 1e00 0x1e00 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 03 GP03 1dff 1dff seq_br_type 7 Unconditional Call; Flow C 0x2a5e seq_branch_adr 2a5e 0x2a5e typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1e00 1e00 typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1e01 1e01 seq_br_type 7 Unconditional Call; Flow C 0x1f1e seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_csa_cntl 3 POP_CSA typ_frame 5 1e02 1e02 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e03 1e03 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1e04 1e04 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e05 1e05 ioc_fiubs 1 val ; Flow J cc=False 0x1e0f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1e0f 0x1e0f seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 1e06 1e06 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 06 GP06 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e07 1e07 seq_b_timing 0 Early Condition; Flow J cc=True 0x1e0c seq_br_type 1 Branch True seq_branch_adr 1e0c 0x1e0c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 1e08 1e08 fiu_mem_start 2 start-rd; Flow C 0x2484 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2484 0x2484 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1e09 1e09 ioc_fiubs 1 val ; Flow J cc=False 0x1dfe seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1dfe 0x1dfe seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 06 GP06 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 1e0a 1e0a seq_br_type 1 Branch True; Flow J cc=True 0x1e00 seq_branch_adr 1e00 0x1e00 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1e0b 1e0b seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 1e0c 1e0c ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x1e11 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e11 0x1e11 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 1e0d 1e0d seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e11 seq_br_type 1 Branch True seq_branch_adr 1e11 0x1e11 1e0e 1e0e seq_br_type 3 Unconditional Branch; Flow J 0x1e01 seq_branch_adr 1e01 0x1e01 typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 1e0f 1e0f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e10 1e10 seq_b_timing 0 Early Condition; Flow J cc=True 0x1e14 seq_br_type 1 Branch True seq_branch_adr 1e14 0x1e14 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 1e11 1e11 fiu_mem_start 2 start-rd; Flow C 0x2484 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2484 0x2484 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1e12 1e12 seq_br_type 1 Branch True; Flow J cc=True 0x1e00 seq_branch_adr 1e00 0x1e00 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1e13 1e13 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 1e14 1e14 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x1e17 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1e17 0x1e17 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 1e15 1e15 fiu_mem_start 2 start-rd; Flow C 0x2484 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2484 0x2484 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1e16 1e16 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1e17 1e17 seq_br_type 7 Unconditional Call; Flow C 0x2488 seq_branch_adr 2488 0x2488 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 1e18 1e18 seq_br_type 1 Branch True; Flow J cc=True 0x1e00 seq_branch_adr 1e00 0x1e00 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 07 GP07 1e19 1e19 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 1e1a 1e1a ioc_fiubs 0 fiu ; Flow J cc=True 0x1e32 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e32 0x1e32 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_adr 3a GP05 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1e1b 1e1b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d89 fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d89 0x1d89 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 1e1c 1e1c ioc_tvbs 2 fiu+val; Flow C cc=False 0x1f1e seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_csa_cntl 3 POP_CSA typ_frame 5 1e1d 1e1d fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1e1e 0x1e1e seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e1e 1e1e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 03 GP03 1e1f 1e1f fiu_mem_start 2 start-rd; Flow J cc=True 0x1e23 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e23 0x1e23 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 11 TOP + 1 typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_csa_cntl 2 PUSH_CSA typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e20 1e20 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e2f seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e2f 0x1e2f typ_mar_cntl 6 INCREMENT_MAR 1e21 1e21 <default> 1e22 1e22 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e2d fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e2d 0x1e2d typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 1e23 1e23 fiu_mem_start 4 continue typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 1e24 1e24 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 1e25 1e25 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e26 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e26 0x1e26 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e26 1e26 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1e2b seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1e2b 0x1e2b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e27 1e27 fiu_fill_mode_src 0 ; Flow J cc=False 0x1e2d fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1e2d 0x1e2d seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS 1e28 1e28 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 1e29 1e29 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x1f1e seq_br_type 4 Call False seq_branch_adr 1f1e 0x1f1e seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1e2a 1e2a fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x32a3 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 32a3 0x32a3 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e2b 1e2b fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e2c 1e2c fiu_fill_mode_src 0 ; Flow J cc=True 0x1e28 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1e28 0x1e28 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 10 TOP typ_b_adr 03 GP03 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS 1e2d 1e2d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a3 seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 1e2e 1e2e fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e2f 1e2f seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 1e30 1e30 seq_br_type 5 Call True; Flow C cc=True 0x1f1e seq_branch_adr 1f1e 0x1f1e seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1e31 1e31 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e32 1e32 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d89 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d89 0x1d89 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e33 1e33 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x1e26 fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1e26 0x1e26 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_random 02 ? typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1e34 1e34 fiu_fill_mode_src 0 ; Flow J cc=True 0x1e38 fiu_length_src 0 length_register fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e38 0x1e38 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1e35 1e35 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_c_adr 38 GP07 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1e36 1e36 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e37 1e37 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e38 1e38 ioc_fiubs 2 typ typ_a_adr 04 GP04 typ_c_adr 38 GP07 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1e39 1e39 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1e3a 1e3a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1e26 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e26 0x1e26 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 1e3b 1e3b seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e3d seq_br_type 1 Branch True seq_branch_adr 1e3d 0x1e3d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1e3c 1e3c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1e3d 1e3d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e26 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1e26 0x1e26 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA 1e3e 1e3e ioc_fiubs 0 fiu ; Flow J cc=True 0x1e53 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e53 0x1e53 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 14 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 1e3f 1e3f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d89 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d89 0x1d89 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 1e40 1e40 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x1e48 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1e48 0x1e48 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE 1e41 1e41 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e4a seq_br_type 1 Branch True seq_branch_adr 1e4a 0x1e4a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 1f TOP - 1 1e42 1e42 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1e45 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1e45 0x1e45 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 1e43 1e43 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x332e fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1e44 1e44 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e71 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e71 0x1e71 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1e45 1e45 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1e46 1e46 seq_br_type 5 Call True; Flow C cc=True 0x1f1e seq_branch_adr 1f1e 0x1f1e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1e47 1e47 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e48 1e48 ioc_tvbs 2 fiu+val; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 1e49 1e49 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e4a 1e4a fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e4b 1e4b fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e4e seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e4e 0x1e4e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 1e4c 1e4c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e4d 1e4d fiu_fill_mode_src 0 ; Flow J 0x1e4f fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e4f 0x1e4f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 1e4e 1e4e fiu_fill_mode_src 0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 4 1e4f 1e4f fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e52 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e52 0x1e52 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e50 1e50 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e51 1e51 fiu_fill_mode_src 0 ; Flow J 0x1e71 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e71 0x1e71 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1e52 1e52 fiu_fill_mode_src 0 ; Flow J 0x1e71 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e71 0x1e71 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1e53 1e53 fiu_load_tar 1 hold_tar; Flow C cc=False 0x1d89 fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d89 0x1d89 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 1e54 1e54 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 27 TR09:07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e55 1e55 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e58 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e58 0x1e58 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e56 1e56 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e57 1e57 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e59 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e59 0x1e59 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 1e58 1e58 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 1e59 1e59 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e5c seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1e5c 0x1e5c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e5a 1e5a fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e5b 1e5b fiu_fill_mode_src 0 ; Flow J 0x1e5d fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e5d 0x1e5d seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e5c 1e5c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e5d 1e5d fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1e61 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e61 0x1e61 typ_mar_cntl 6 INCREMENT_MAR 1e5e 1e5e fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 1e5f 1e5f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x332e fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1e60 1e60 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e71 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e71 0x1e71 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 1e61 1e61 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e62 1e62 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1e6c seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1e6c 0x1e6c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 1e63 1e63 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 2 1e64 1e64 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 1e65 1e65 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1e6f seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1e6f 0x1e6f seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e66 1e66 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1e67 1e67 ioc_fiubs 1 val ; Flow J cc=True 0x1e6b seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e6b 0x1e6b seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 1e68 1e68 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e6a seq_br_type 1 Branch True seq_branch_adr 1e6a 0x1e6a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1e69 1e69 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1e6a 1e6a ioc_fiubs 1 val ; Flow J 0x1e71 seq_br_type 3 Unconditional Branch seq_branch_adr 1e71 0x1e71 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 1e6b 1e6b seq_br_type 3 Unconditional Branch; Flow J 0x1e71 seq_branch_adr 1e71 0x1e71 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 1e6c 1e6c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e6d 1e6d fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 2 1e6e 1e6e fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1e65 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e65 0x1e65 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 1e6f 1e6f fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1e70 1e70 fiu_fill_mode_src 0 ; Flow J 0x1e67 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1e67 0x1e67 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1e71 1e71 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1e76 seq_br_type 1 Branch True seq_branch_adr 1e76 0x1e76 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 1e72 1e72 fiu_mem_start 2 start-rd; Flow C cc=False 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 326f 0x326f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e73 1e73 ioc_tvbs 2 fiu+val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 1e74 1e74 seq_br_type 5 Call True; Flow C cc=True 0x1f1e seq_branch_adr 1f1e 0x1f1e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1e75 1e75 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e76 1e76 fiu_mem_start 2 start-rd; Flow C cc=False 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 326f 0x326f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e77 1e77 seq_br_type 4 Call False; Flow C cc=False 0x32a3 seq_branch_adr 32a3 0x32a3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 06 GP06 typ_alu_func 0 PASS_A val_a_adr 06 GP06 val_alu_func 0 PASS_A 1e78 1e78 seq_br_type 4 Call False; Flow C cc=False 0x32a3 seq_branch_adr 32a3 0x32a3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 02 ? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 3 POP_CSA val_a_adr 04 GP04 val_alu_func 0 PASS_A 1e79 1e79 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1e7a 1e7a seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e8d seq_br_type 1 Branch True seq_branch_adr 1e8d 0x1e8d seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_c_lit 0 typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 03 GP03 1e7b 1e7b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1d89 fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d89 0x1d89 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 1e7c 1e7c fiu_mem_start 2 start-rd; Flow J cc=False 0x1ea9 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1ea9 0x1ea9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 01 GP01 1e7d 1e7d seq_b_timing 1 Latch Condition; Flow J cc=True 0x1e85 seq_br_type 1 Branch True seq_branch_adr 1e85 0x1e85 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 1e7e 1e7e fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=False 0x1eab fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1eab 0x1eab typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e7f 1e7f seq_br_type 7 Unconditional Call; Flow C 0x22de seq_branch_adr 22de 0x22de typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1e80 1e80 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1ea9 seq_br_type 1 Branch True seq_branch_adr 1ea9 0x1ea9 1e81 1e81 ioc_fiubs 2 typ ; Flow C 0x2286 seq_br_type 7 Unconditional Call seq_branch_adr 2286 0x2286 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e82 1e82 ioc_fiubs 2 typ ; Flow C cc=True 0x32a3 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 1e83 1e83 seq_br_type 7 Unconditional Call; Flow C 0x2286 seq_branch_adr 2286 0x2286 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1e84 1e84 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32a3 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a3 0x32a3 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1e85 1e85 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=False 0x1eab fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1eab 0x1eab typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e86 1e86 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1e87 1e87 seq_br_type 7 Unconditional Call; Flow C 0x22da seq_branch_adr 22da 0x22da seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1e88 1e88 ioc_fiubs 1 val ; Flow J cc=True 0x1ea9 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1ea9 0x1ea9 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1e89 1e89 ioc_fiubs 2 typ ; Flow C 0x228e seq_br_type 7 Unconditional Call seq_branch_adr 228e 0x228e typ_a_adr 17 LOOP_COUNTER val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e8a 1e8a ioc_fiubs 2 typ ; Flow C cc=True 0x32a3 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 1e8b 1e8b seq_br_type 7 Unconditional Call; Flow C 0x2286 seq_branch_adr 2286 0x2286 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1e8c 1e8c fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32a3 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a3 0x32a3 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1e8d 1e8d fiu_load_tar 1 hold_tar; Flow C cc=False 0x1d89 fiu_tivi_src 8 type_var ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1d89 0x1d89 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 22 TR01:02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_frame 1 val_a_adr 03 GP03 1e8e 1e8e fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1e8f 1e8f fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e90 1e90 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 1e91 1e91 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1e9a ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1e9a 0x1e9a seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 1e92 1e92 ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS 1e93 1e93 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x1eab fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 1eab 0x1eab seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 1e94 1e94 seq_br_type 7 Unconditional Call; Flow C 0x22e4 seq_branch_adr 22e4 0x22e4 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1e95 1e95 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1ea9 seq_br_type 1 Branch True seq_branch_adr 1ea9 0x1ea9 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1e96 1e96 ioc_fiubs 2 typ ; Flow C 0x2286 seq_br_type 7 Unconditional Call seq_branch_adr 2286 0x2286 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e97 1e97 ioc_fiubs 1 val ; Flow C cc=True 0x32a3 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 04 GP04 1e98 1e98 ioc_fiubs 2 typ ; Flow C 0x228e seq_br_type 7 Unconditional Call seq_branch_adr 228e 0x228e seq_random 02 ? typ_a_adr 17 LOOP_COUNTER typ_csa_cntl 3 POP_CSA val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1e99 1e99 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32a3 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a3 0x32a3 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1e9a 1e9a ioc_fiubs 1 val ; Flow C 0x22ec seq_br_type 7 Unconditional Call seq_branch_adr 22ec 0x22ec typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1e9b 1e9b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1ead fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1ead 0x1ead typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_b_adr 1f TOP - 1 1e9c 1e9c fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 1e9d 1e9d fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1ea2 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ea2 0x1ea2 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1e9e 1e9e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1e9f 1e9f fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1ea0 1ea0 seq_br_type 4 Call False; Flow C cc=False 0x1ea5 seq_branch_adr 1ea5 0x1ea5 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 07 GP07 val_rand c START_MULTIPLY 1ea1 1ea1 ioc_fiubs 1 val ; Flow J 0x1ea9 seq_br_type 3 Unconditional Branch seq_branch_adr 1ea9 0x1ea9 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 1ea2 1ea2 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1ea3 1ea3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 1ea4 1ea4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x1ea0 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1ea0 0x1ea0 val_c_adr 38 GP07 val_c_source 0 FIU_BUS 1ea5 1ea5 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 1ea6 1ea6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1ea7 1ea7 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 1ea8 1ea8 ioc_fiubs 1 val ; Flow J 0x1ea9 seq_br_type 3 Unconditional Branch seq_branch_adr 1ea9 0x1ea9 seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 1ea9 1ea9 ioc_tvbs 2 fiu+val; Flow C 0x1f1e seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 1eaa 1eaa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1eab ; -------------------------------------------------------------------------------------- 1eab ; Comes from: 1eab ; 1e7e C False from color 0x0000 1eab ; 1e85 C False from color 0x0000 1eab ; 1e93 C False from color 0x0000 1eab ; -------------------------------------------------------------------------------------- 1eab 1eab fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1eac 1eac seq_br_type a Unconditional Return; Flow R 1ead 1ead ioc_fiubs 2 typ ; Flow C 0x228e ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 228e 0x228e typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1eae 1eae ioc_fiubs 1 val ; Flow C cc=True 0x32a3 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a3 0x32a3 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 04 GP04 1eaf 1eaf ioc_fiubs 2 typ ; Flow C 0x228e seq_br_type 7 Unconditional Call seq_branch_adr 228e 0x228e seq_random 02 ? typ_a_adr 17 LOOP_COUNTER typ_csa_cntl 3 POP_CSA val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1eb0 1eb0 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32a3 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a3 0x32a3 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 1eb1 1eb1 <halt> ; Flow R 1eb2 ; -------------------------------------------------------------------------------------- 1eb2 ; 0x032d Declare_Type Record,Defined 1eb2 ; -------------------------------------------------------------------------------------- 1eb2 MACRO_Declare_Type_Record,Defined: 1eb2 1eb2 dispatch_brk_class 4 ; Flow J 0x1eb3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1eb2 fiu_len_fill_lit 00 sign-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1eb3 0x1eb3 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1eb3 1eb3 fiu_len_fill_lit 78 zero-fill 0x38; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_frame 1c val_a_adr 10 TOP val_b_adr 1f TOP - 1 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1eb4 1eb4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32d9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 1eb5 1eb5 ioc_tvbs 2 fiu+val typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 3b VR07:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 1eb6 1eb6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 1eb7 1eb7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x26e8 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 26e8 0x26e8 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_b_adr 39 VR02:19 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 1eb8 1eb8 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 3d TR08:1d typ_alu_func 1e A_AND_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 8 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 10 TOP 1eb9 1eb9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1ebd fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 1ebd 0x1ebd seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 typ_rand d SET_PASS_PRIVACY_BIT 1eba 1eba fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x1ec1 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1ec1 0x1ec1 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 1ebb 1ebb ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 03 GP03 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1ebc 1ebc fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 22 TR08:02 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 1ebd ; -------------------------------------------------------------------------------------- 1ebd ; Comes from: 1ebd ; 1eb9 C False from color 0x1eb4 1ebd ; 1ede C False from color 0x1ed6 1ebd ; -------------------------------------------------------------------------------------- 1ebd 1ebd seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1ebe 0x1ebe seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 1ebe 1ebe seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1ebf 0x1ebf seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR00:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 1ebf 1ebf seq_br_type a Unconditional Return; Flow R typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR01:02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 1ec0 ; -------------------------------------------------------------------------------------- 1ec0 ; 0x0327 Declare_Type Record,Defined_Incomplete 1ec0 ; -------------------------------------------------------------------------------------- 1ec0 MACRO_Declare_Type_Record,Defined_Incomplete: 1ec0 1ec0 dispatch_brk_class 4 ; Flow J 0x1eb3 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ec0 fiu_len_fill_lit 00 sign-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1eb3 0x1eb3 seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1ec1 ; -------------------------------------------------------------------------------------- 1ec1 ; Comes from: 1ec1 ; 1eba C True from color 0x1eb4 1ec1 ; 1edf C True from color 0x1ed6 1ec1 ; -------------------------------------------------------------------------------------- 1ec1 1ec1 fiu_mem_start 8 start_wr_if_false; Flow R cc=False fiu_tivi_src c mar_0xc ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 1ec2 0x1ec2 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 1ec2 1ec2 fiu_len_fill_lit 5a zero-fill 0x1a; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 22 TR02:02 typ_frame 2 val_a_adr 3b VR02:1b val_alu_func 1d A_AND_NOT_B val_frame 2 1ec3 1ec3 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 0210 0x0210 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 31 TR09:11 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 1ec4 ; -------------------------------------------------------------------------------------- 1ec4 ; 0x032e Declare_Type Record,Defined,Visible 1ec4 ; -------------------------------------------------------------------------------------- 1ec4 MACRO_Declare_Type_Record,Defined,Visible: 1ec4 1ec4 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ec4 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 1ec5 1ec5 fiu_len_fill_lit 00 sign-fill 0x0; Flow J 0x1eb3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1eb3 0x1eb3 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 1ec6 ; -------------------------------------------------------------------------------------- 1ec6 ; 0x0328 Declare_Type Record,Defined_Incomplete,Visible 1ec6 ; -------------------------------------------------------------------------------------- 1ec6 MACRO_Declare_Type_Record,Defined_Incomplete,Visible: 1ec6 1ec6 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ec6 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 1ec7 1ec7 fiu_len_fill_lit 00 sign-fill 0x0; Flow J 0x1eb3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1eb3 0x1eb3 seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 1ec8 ; -------------------------------------------------------------------------------------- 1ec8 ; 0x032a Declare_Type Record,Incomplete 1ec8 ; -------------------------------------------------------------------------------------- 1ec8 MACRO_Declare_Type_Record,Incomplete: 1ec8 1ec8 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ec8 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offs_lit 44 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1ec9 1ec9 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 22 TR02:02 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 1eca 1eca fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 3b VR02:1b val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 1ecb 1ecb fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32d9 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 1ecc 1ecc fiu_mem_start a start_continue_if_false; Flow J cc=True 0x1ecf fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1ecf 0x1ecf seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 24 TR09:04 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 val_rand 2 DEC_LOOP_COUNTER 1ecd 1ecd ioc_load_wdr 0 ; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 1ece 1ece fiu_mem_start 8 start_wr_if_false; Flow J cc=False 0x1ecd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ecd 0x1ecd seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand 2 DEC_LOOP_COUNTER 1ecf 1ecf fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 1ed0 1ed0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 1ed1 1ed1 <halt> ; Flow R 1ed2 ; -------------------------------------------------------------------------------------- 1ed2 ; 0x032b Declare_Type Record,Incomplete,Visible 1ed2 ; -------------------------------------------------------------------------------------- 1ed2 MACRO_Declare_Type_Record,Incomplete,Visible: 1ed2 1ed2 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1ed2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 1ed3 1ed3 fiu_load_oreg 1 hold_oreg; Flow J 0x1ec9 fiu_offs_lit 44 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1ec9 0x1ec9 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1ed4 ; -------------------------------------------------------------------------------------- 1ed4 ; 0x0326 Complete_Type Record,By_Defining 1ed4 ; -------------------------------------------------------------------------------------- 1ed4 MACRO_Complete_Type_Record,By_Defining: 1ed4 1ed4 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ed4 fiu_mem_start 2 start-rd fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 3f VR1e:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 1e 1ed5 1ed5 ioc_load_wdr 0 ; Flow C 0x32d7 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1c val_a_adr 3b VR07:1b val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 1ed6 1ed6 fiu_len_fill_lit 00 sign-fill 0x0; Flow C cc=True 0x32a9 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_b_adr 16 CSA/VAL_BUS 1ed7 1ed7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3c GP03 val_c_source 0 FIU_BUS 1ed8 1ed8 ioc_fiubs 1 val ; Flow C cc=True 0x32d9 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 6 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 1ed9 1ed9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1eda 1eda fiu_len_fill_lit 5a zero-fill 0x1a fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand c WRITE_OUTER_FRAME val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 val_rand c START_MULTIPLY 1edb 1edb fiu_load_tar 1 hold_tar; Flow C cc=False 0x32db fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32db 0x32db seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 04 GP04 typ_b_adr 05 GP05 val_a_adr 16 PRODUCT 1edc 1edc ioc_tvbs 3 fiu+fiu; Flow C 0x26e8 seq_br_type 7 Unconditional Call seq_branch_adr 26e8 0x26e8 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1edd 1edd fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 3d TR08:1d typ_alu_func 1e A_AND_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 8 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 04 GP04 1ede 1ede fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1ebd fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 1ebd 0x1ebd seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 7 FINISH_POP_DOWN typ_rand d SET_PASS_PRIVACY_BIT 1edf 1edf fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x1ec1 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1ec1 0x1ec1 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 1ee0 1ee0 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 03 GP03 1ee1 1ee1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 1ee2 ; -------------------------------------------------------------------------------------- 1ee2 ; 0x0325 Complete_Type Record,By_Renaming 1ee2 ; -------------------------------------------------------------------------------------- 1ee2 MACRO_Complete_Type_Record,By_Renaming: 1ee2 1ee2 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1ee2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1ee3 1ee3 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 1ee4 1ee4 fiu_mem_start 2 start-rd; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 1ee5 1ee5 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT 1ee6 1ee6 fiu_len_fill_lit 5a zero-fill 0x1a fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 1ee7 1ee7 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32d9 fiu_mem_start 2 start-rd fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 4 1ee8 1ee8 seq_br_type 4 Call False; Flow C cc=False 0x32db seq_branch_adr 32db 0x32db seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 01 GP01 typ_b_adr 02 GP02 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1ee9 1ee9 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A val_rand 1 INC_LOOP_COUNTER 1eea 1eea ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1eeb 1eeb fiu_mem_start 3 start-wr; Flow J cc=True 0x1ef1 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 1ef1 0x1ef1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A 1eec 1eec seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 1eed 1eed fiu_mem_start 2 start-rd; Flow J 0x1eea ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1eea 0x1eea typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 1eee ; -------------------------------------------------------------------------------------- 1eee ; 0x0324 Complete_Type Record,By_Component_Completion 1eee ; -------------------------------------------------------------------------------------- 1eee MACRO_Complete_Type_Record,By_Component_Completion: 1eee 1eee dispatch_brk_class 4 ; Flow C 0x332e dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1eee fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 1eef 1eef fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 10 TOP typ_c_adr 3a GP05 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_rand a PASS_B_HIGH val_a_adr 35 VR09:15 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 9 1ef0 1ef0 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x1ef1 ; Flow J cc=#0x0 0x1ef1 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 1ef1 0x1ef1 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1ef1 1ef1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1ef2 1ef2 fiu_tivi_src c mar_0xc; Flow J 0x1ef5 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1ef5 0x1ef5 typ_a_adr 2b TR02:0b typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1ef3 1ef3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1ef4 1ef4 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 1ef5 1ef5 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x1f03 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1f03 0x1f03 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1ef6 1ef6 val_alu_func 1 A_PLUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 2 DEC_LOOP_COUNTER 1ef7 1ef7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 3d VR06:1d val_alu_func 1b A_OR_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 6 1ef8 1ef8 ioc_load_wdr 0 ; Flow J cc=False 0x1efd seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1efd 0x1efd typ_b_adr 03 GP03 val_b_adr 03 GP03 1ef9 1ef9 fiu_load_tar 1 hold_tar; Flow C cc=True 0x1f00 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1f00 0x1f00 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A 1efa 1efa ioc_tvbs 2 fiu+val; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 3d TR08:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 1efb 1efb ioc_fiubs 1 val ; Flow J cc=True 0x1ef5 ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 1ef5 0x1ef5 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1efc 1efc ioc_fiubs 1 val ; Flow J 0x1ef5 seq_br_type 3 Unconditional Branch seq_branch_adr 1ef5 0x1ef5 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1efd 1efd fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 1efe 1efe seq_b_timing 1 Latch Condition; Flow C cc=True 0x1f00 seq_br_type 5 Call True seq_branch_adr 1f00 0x1f00 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1eff 1eff fiu_mem_start 3 start-wr; Flow J 0x1efa ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1efa 0x1efa typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 03 GP03 1f00 ; -------------------------------------------------------------------------------------- 1f00 ; Comes from: 1f00 ; 1ef9 C True from color MACRO_Complete_Type_Record,By_Renaming 1f00 ; 1efe C True from color MACRO_Complete_Type_Record,By_Renaming 1f00 ; -------------------------------------------------------------------------------------- 1f00 1f00 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 1f01 1f01 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 1f02 0x1f02 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func a PASS_A_ELSE_PASS_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 1f02 1f02 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32a9 seq_br_type 9 Return False seq_branch_adr 32a9 0x32a9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49) Float_Var typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 9 1f03 1f03 ioc_fiubs 1 val seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1f04 1f04 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 1f05 1f05 ioc_load_wdr 0 ; Flow J 0x1ef1 seq_br_type 3 Unconditional Branch seq_branch_adr 1ef1 0x1ef1 typ_b_adr 02 GP02 val_b_adr 02 GP02 1f06 ; -------------------------------------------------------------------------------------- 1f06 ; 0x0321 Declare_Variable Record,Visible 1f06 ; -------------------------------------------------------------------------------------- 1f06 MACRO_Declare_Variable_Record,Visible: 1f06 1f06 dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1f06 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 31 VR02:11 val_frame 2 1f07 1f07 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1f1d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 1f1d 0x1f1d seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1f08 1f08 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 1f09 0x1f09 seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) seq_random 04 Load_save_offset+? typ_a_adr 28 TR07:08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1f09 1f09 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x1f11 ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1f11 0x1f11 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_c_adr 3b GP04 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3b GP04 val_frame 2 1f0a 1f0a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x1f0d seq_br_type 1 Branch True seq_branch_adr 1f0d 0x1f0d seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 04 GP04 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 04 GP04 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 1f0b 1f0b ioc_fiubs 1 val ; Flow C 0x2a5e seq_br_type 7 Unconditional Call seq_branch_adr 2a5e 0x2a5e typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 1f0c 1f0c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1f0d 1f0d fiu_tivi_src c mar_0xc; Flow J cc=False 0x1f10 ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 1f10 0x1f10 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 1f0e 1f0e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2a5e seq_br_type 5 Call True seq_branch_adr 2a5e 0x2a5e seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 21 TR00:01 val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1f0f 1f0f fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 1f10 0x1f10 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1f10 1f10 seq_br_type 7 Unconditional Call; Flow C 0x32cc seq_branch_adr 32cc 0x32cc seq_en_micro 0 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1f11 1f11 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 1f12 1f12 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d2 seq_br_type 5 Call True seq_branch_adr 32d2 0x32d2 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 19 X_XOR_B val_b_adr 04 GP04 val_frame 2 val_rand 9 PASS_A_HIGH 1f13 1f13 seq_br_type 7 Unconditional Call; Flow C 0x32cc seq_branch_adr 32cc 0x32cc seq_en_micro 0 1f14 ; -------------------------------------------------------------------------------------- 1f14 ; 0x0322 Declare_Variable Record 1f14 ; -------------------------------------------------------------------------------------- 1f14 MACRO_Declare_Variable_Record: 1f14 1f14 dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1f14 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 39 VR02:19 val_frame 2 1f15 1f15 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1f08 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1f08 0x1f08 seq_int_reads 6 CONTROL TOP val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1f16 ; -------------------------------------------------------------------------------------- 1f16 ; 0x0320 Declare_Variable Record,Duplicate 1f16 ; -------------------------------------------------------------------------------------- 1f16 MACRO_Declare_Variable_Record,Duplicate: 1f16 1f16 dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 1f16 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f17 1f17 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1f18 1f18 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x1f1b fiu_load_tar 1 hold_tar fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1f1b 0x1f1b seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2a TR07:0a typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 7 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1f19 1f19 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x32a9 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_frame 2 1f1a 1f1a fiu_tivi_src c mar_0xc; Flow C cc=False 0x32cc ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1f1b 1f1b ioc_fiubs 1 val ; Flow C 0x1f1e ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 1f1e 0x1f1e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_csa_cntl 2 PUSH_CSA typ_frame 5 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 1f1c 1f1c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 1f1d 1f1d seq_br_type 7 Unconditional Call; Flow C 0x32da seq_branch_adr 32da 0x32da seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 1f1e ; -------------------------------------------------------------------------------------- 1f1e ; Comes from: 1f1e ; 076e C from color 0x0767 1f1e ; 0d36 C from color 0x0000 1f1e ; 118e C from color 0x1147 1f1e ; 1198 C from color 0x1194 1f1e ; 11c2 C from color 0x114d 1f1e ; 11c8 C from color 0x114d 1f1e ; 11f5 C from color 0x114d 1f1e ; 1201 C from color 0x114d 1f1e ; 1344 C from color 0x133f 1f1e ; 1375 C from color 0x0000 1f1e ; 138e C from color 0x0000 1f1e ; 1592 C from color 0x0000 1f1e ; 15d4 C from color 0x0000 1f1e ; 15f6 C from color 0x0000 1f1e ; 17d8 C from color 0x0a32 1f1e ; 182a C False from color MACRO_Execute_Record,Structure_Write 1f1e ; 1838 C from color 0x0a31 1f1e ; 183f C from color 0x0a31 1f1e ; 19a7 C from color MACRO_Execute_Vector,Slice_Read 1f1e ; 19d3 C True from color MACRO_Execute_Vector,Slice_Write 1f1e ; 1a24 C from color MACRO_Execute_Vector,Catenate 1f1e ; 1a26 C from color MACRO_Execute_Vector,Catenate 1f1e ; 1a4d C True from color MACRO_Execute_Vector,Append 1f1e ; 1a6f C True from color MACRO_Execute_Vector,Prepend 1f1e ; 1a93 C True from color 0x0a2f 1f1e ; 1ab0 C True from color 0x0a2f 1f1e ; 1ac6 C from color 0x0a2f 1f1e ; 1c1d C from color 0x0000 1f1e ; 1c43 C from color 0x0000 1f1e ; 1c68 C from color 0x1c57 1f1e ; 1de7 C True from color 0x1d69 1f1e ; 1e01 C from color 0x0000 1f1e ; 1e1c C False from color 0x0000 1f1e ; 1e29 C False from color 0x0000 1f1e ; 1e30 C True from color 0x0000 1f1e ; 1e46 C True from color MACRO_Execute_Matrix,Structure_Write 1f1e ; 1e48 C from color MACRO_Execute_Matrix,Structure_Write 1f1e ; 1e74 C True from color MACRO_Execute_Matrix,Structure_Write 1f1e ; 1ea9 C from color 0x0000 1f1e ; 1f1b C from color 0x1f17 1f1e ; 363e C True from color 0x108b 1f1e ; -------------------------------------------------------------------------------------- 1f1e 1f1e fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x1f7c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1f7c 0x1f7c seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f1f 1f1f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x1f2a fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f2a 0x1f2a seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 01 GP01 1f20 1f20 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x1f25 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1f25 0x1f25 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR 1f21 1f21 fiu_fill_mode_src 0 ; Flow J 0x1f22 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f22 0x1f22 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f22 1f22 fiu_fill_mode_src 0 ; Flow J cc=False 0x1f27 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1f27 0x1f27 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 1f23 1f23 fiu_fill_mode_src 0 ; Flow J 0x1f24 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f24 0x1f24 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f24 1f24 ioc_load_wdr 0 ; Flow C 0x2ab4 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1f25 1f25 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1f26 1f26 fiu_fill_mode_src 0 ; Flow J 0x1f22 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f22 0x1f22 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f27 1f27 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 1f28 1f28 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1f29 1f29 fiu_load_var 1 hold_var; Flow J 0x1f24 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f24 0x1f24 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 1f2a 1f2a fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1f33 fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1f33 0x1f33 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f2b 1f2b fiu_load_tar 1 hold_tar; Flow J cc=True 0x1f4e fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f4e 0x1f4e typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B 1f2c 1f2c fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1f2d 1f2d fiu_fill_mode_src 0 ; Flow J cc=True 0x1f37 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 1f37 0x1f37 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f2e 1f2e fiu_mem_start 2 start-rd; Flow J 0x1f2f ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 1f2f 0x1f2f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1f2f 1f2f seq_br_type 3 Unconditional Branch; Flow J 0x1f1e seq_branch_adr 1f1e 0x1f1e seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 1f30 1f30 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f31 1f31 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x1f20 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f20 0x1f20 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 35 TR02:15 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 01 GP01 1f32 1f32 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x1f2b fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 1f2b 0x1f2b seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 1f33 1f33 fiu_load_tar 1 hold_tar; Flow J cc=True 0x1f51 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f51 0x1f51 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_latch 1 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 1f34 1f34 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1f36 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f36 0x1f36 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 seq_latch 1 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 1f35 1f35 seq_br_type 0 Branch False; Flow J cc=False 0x1f2f seq_branch_adr 1f2f 0x1f2f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 1f36 1f36 fiu_fill_mode_src 0 ; Flow J 0x1f37 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f37 0x1f37 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f37 1f37 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x1f3b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 9 start_continue_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f3b 0x1f3b typ_mar_cntl 6 INCREMENT_MAR 1f38 1f38 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 1f39 1f39 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 1f3a 1f3a fiu_fill_mode_src 0 ; Flow J 0x1f24 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f24 0x1f24 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f3b 1f3b fiu_load_tar 1 hold_tar; Flow J cc=False 0x1f41 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1f41 0x1f41 seq_cond_sel 64 OFFSET_REGISTER_???? 1f3c 1f3c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1f46 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 1f46 0x1f46 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 1f3d 1f3d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 1f3e 1f3e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f3f 1f3f fiu_fill_mode_src 0 ; Flow J 0x1f40 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f40 0x1f40 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f40 1f40 fiu_mem_start 4 continue; Flow J 0x1f24 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 1f24 0x1f24 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP 1f41 1f41 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1f46 fiu_length_src 0 length_register fiu_op_sel 2 insert first ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 1f46 0x1f46 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1f42 1f42 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 1 insert last fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 seq_latch 1 typ_alu_func 0 PASS_A 1f43 1f43 fiu_fill_mode_src 0 ; Flow J cc=True 0x1f45 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f45 0x1f45 seq_en_micro 0 typ_c_adr 3f GP00 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f44 1f44 fiu_fill_mode_src 0 ; Flow J 0x1f40 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f40 0x1f40 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f45 1f45 fiu_fill_mode_src 0 ; Flow J 0x1f40 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f40 0x1f40 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f46 1f46 fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x1f4b ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 1f4b 0x1f4b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 31 GP0e typ_mar_cntl 1 RESTORE_RDR val_c_adr 31 GP0e 1f47 1f47 seq_en_micro 0 1f48 1f48 fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x1f4b ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 1f4b 0x1f4b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f49 1f49 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 1f4a 1f4a ioc_adrbs 2 typ ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1f4b 0x1f4b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA 1f4b 1f4b fiu_mem_start 3 start-wr; Flow C 0x332e ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_mar_cntl b LOAD_MAR_DATA val_b_adr 0e GP0e 1f4c 1f4c fiu_mem_start 2 start-rd; Flow C 0x332e fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 1f4d 1f4d fiu_mem_start 3 start-wr; Flow J 0x1f2f ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f2f 0x1f2f seq_random 06 Pop_stack+? 1f4e 1f4e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1f4f 1f4f fiu_fill_mode_src 0 ; Flow J cc=True 0x1f57 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f57 0x1f57 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f50 1f50 fiu_load_oreg 1 hold_oreg; Flow J 0x1f54 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f54 0x1f54 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA 1f51 1f51 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 1f52 1f52 seq_b_timing 1 Latch Condition; Flow J cc=True 0x1f59 seq_br_type 1 Branch True seq_branch_adr 1f59 0x1f59 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 1f53 1f53 fiu_fill_mode_src 0 ; Flow J 0x1f54 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f54 0x1f54 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f54 1f54 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 1f55 1f55 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1f56 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f56 0x1f56 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f56 1f56 ioc_load_wdr 0 ; Flow J 0x1f5e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f5e 0x1f5e seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1f57 1f57 fiu_fill_mode_src 0 ; Flow J cc=True 0x1f5e fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f5e 0x1f5e seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1f58 1f58 fiu_fill_mode_src 0 ; Flow J 0x1f5b fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f5b 0x1f5b typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA 1f59 1f59 fiu_fill_mode_src 0 ; Flow J cc=True 0x1f5e fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 1f5e 0x1f5e seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 1f5a 1f5a fiu_fill_mode_src 0 ; Flow J 0x1f5b fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1f5b 0x1f5b typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA 1f5b 1f5b fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 1f5c 1f5c fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A 1f5d 1f5d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1f56 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f56 0x1f56 typ_a_adr 17 LOOP_COUNTER typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1f5e 1f5e fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x1f30 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f30 0x1f30 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f5f 1f5f fiu_mem_start 4 continue; Flow J cc=False 0x1f6e seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1f6e 0x1f6e seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1f60 1f60 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f61 1f61 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1f6b fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f6b 0x1f6b typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f62 1f62 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1f63 1f63 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32cc seq_br_type 5 Call True seq_branch_adr 32cc 0x32cc seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 27 TR02:07 typ_frame 2 1f64 1f64 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f65 1f65 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1f68 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1f68 0x1f68 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f66 1f66 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 1f67 1f67 fiu_mem_start 2 start-rd; Flow C 0x332e seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e 1f68 1f68 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1f6a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f6a 0x1f6a typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f69 1f69 fiu_load_oreg 1 hold_oreg; Flow J 0x1f64 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f64 0x1f64 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f6a 1f6a ioc_load_wdr 0 ; Flow J 0x1f30 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f30 0x1f30 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f6b 1f6b ioc_load_wdr 0 ; Flow J cc=False 0x1f30 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1f30 0x1f30 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 1f6c 1f6c seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 1f6d 1f6d seq_br_type 3 Unconditional Branch; Flow J 0x1f30 seq_branch_adr 1f30 0x1f30 1f6e 1f6e fiu_load_var 1 hold_var; Flow J cc=False 0x1f79 fiu_tivi_src 1 tar_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f79 0x1f79 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1f6f 1f6f fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f70 1f70 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f71 1f71 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32cc seq_br_type 5 Call True seq_branch_adr 32cc 0x32cc seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 27 TR02:07 typ_frame 2 1f72 1f72 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1f76 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1f76 0x1f76 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f73 1f73 fiu_load_oreg 1 hold_oreg; Flow C 0x2ab4 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f74 1f74 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f75 1f75 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x1f72 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f72 0x1f72 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f76 1f76 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ab4 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f77 1f77 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 1f78 1f78 ioc_load_wdr 0 ; Flow J 0x1f30 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f30 0x1f30 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1f79 1f79 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ab4 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1f7a 1f7a fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 1f7b 1f7b ioc_load_wdr 0 ; Flow J 0x1f30 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 1f30 0x1f30 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 1f7c ; -------------------------------------------------------------------------------------- 1f7c ; Comes from: 1f7c ; 1f1e C True from color 0x098b 1f7c ; -------------------------------------------------------------------------------------- 1f7c 1f7c fiu_tivi_src 4 fiu_var; Flow R cc=False ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 1f7d 0x1f7d seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 01 GP01 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 1f7d 1f7d fiu_len_fill_lit 49 zero-fill 0x9; Flow R fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1f7e 1f7e fiu_len_fill_lit 49 zero-fill 0x9 fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 1f7f 1f7f seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 1f80 0x1f80 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 20 TR00:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 1f80 1f80 seq_br_type 7 Unconditional Call; Flow C 0x32f3 seq_branch_adr 32f3 0x32f3 1f81 1f81 <halt> ; Flow R 1f82 ; -------------------------------------------------------------------------------------- 1f82 ; 0x03d1 Declare_Type Access,Constrained 1f82 ; -------------------------------------------------------------------------------------- 1f82 MACRO_Declare_Type_Access,Constrained: 1f82 1f82 dispatch_brk_class 4 ; Flow J 0x1f8a dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1f82 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f8a 0x1f8a typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR00:00 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1f83 1f83 <halt> ; Flow R 1f84 ; -------------------------------------------------------------------------------------- 1f84 ; 0x03d2 Declare_Type Access,Constrained,Visible 1f84 ; -------------------------------------------------------------------------------------- 1f84 MACRO_Declare_Type_Access,Constrained,Visible: 1f84 1f84 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1f84 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 1f85 1f85 fiu_mem_start 2 start-rd; Flow J 0x1f8a ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f8a 0x1f8a typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1f86 ; -------------------------------------------------------------------------------------- 1f86 ; 0x03ab Declare_Type Heap_Access,Constrained 1f86 ; -------------------------------------------------------------------------------------- 1f86 MACRO_Declare_Type_Heap_Access,Constrained: 1f86 1f86 dispatch_brk_class 4 ; Flow J 0x1f8b dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1f86 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f8b 0x1f8b typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR00:00 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1f87 1f87 <halt> ; Flow R 1f88 ; -------------------------------------------------------------------------------------- 1f88 ; 0x03ac Declare_Type Heap_Access,Constrained,Visible 1f88 ; -------------------------------------------------------------------------------------- 1f88 MACRO_Declare_Type_Heap_Access,Constrained,Visible: 1f88 1f88 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 1f88 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 1f89 1f89 fiu_mem_start 2 start-rd; Flow J 0x1f8b ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f8b 0x1f8b typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1f8a 1f8a fiu_load_tar 1 hold_tar; Flow J 0x1f8c fiu_mem_start 4 continue fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1f8c 0x1f8c seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_b_adr 3d VR02:1d val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 1f8b 1f8b fiu_load_tar 1 hold_tar; Flow J 0x1f8c fiu_mem_start 4 continue fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 1f8c 0x1f8c seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_b_adr 39 VR07:19 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 7 1f8c 1f8c fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1f8d 1f8d fiu_load_tar 1 hold_tar; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1f8e 1f8e ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 1f8f 1f8f fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x32d9 fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_a_adr 01 GP01 typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_lit 2 typ_frame b typ_rand 9 PASS_A_HIGH 1f90 1f90 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x1f96 seq_br_type f Unconditional Case Call seq_branch_adr 1f96 0x1f96 seq_en_micro 0 typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 1f91 1f91 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE 1f92 1f92 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 1f93 1f93 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 1f TOP - 1 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 1f94 1f94 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_b_adr 01 GP01 1f95 1f95 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 1f96 ; -------------------------------------------------------------------------------------- 1f96 ; Comes from: 1f96 ; 1f90 C #0x0 from color MACRO_Declare_Type_Access,Constrained 1f96 ; -------------------------------------------------------------------------------------- 1f96 1f96 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1f97 1f97 fiu_mem_start 2 start-rd; Flow J 0x1f9e ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1f9e 0x1f9e typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1f98 1f98 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1f99 1f99 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1f9a 1f9a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 1f9b 1f9b seq_br_type 3 Unconditional Branch; Flow J 0x1fa3 seq_branch_adr 1fa3 0x1fa3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 1f9c 1f9c seq_br_type 3 Unconditional Branch; Flow J 0x1fa3 seq_branch_adr 1fa3 0x1fa3 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 1f9d 1f9d fiu_mem_start 2 start-rd; Flow J 0x1fab ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1fab 0x1fab seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 1f9e 1f9e ioc_fiubs 1 val typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 1f9f 1f9f fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32d9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 1fa0 1fa0 <default> 1fa1 1fa1 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32d9 seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 1fa2 1fa2 fiu_mem_start 2 start-rd; Flow J 0x3274 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3274 0x3274 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1fa3 1fa3 ioc_fiubs 1 val ; Flow C cc=False 0x32d9 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 1fa4 1fa4 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1fa5 0x1fa5 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 01 GP01 1fa5 1fa5 fiu_mem_start 2 start-rd; Flow C 0x3274 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3274 0x3274 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 01 GP01 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1fa6 1fa6 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 1fa7 1fa7 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 1fa8 1fa8 seq_br_type 7 Unconditional Call; Flow C 0x2292 seq_branch_adr 2292 0x2292 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 1fa9 1fa9 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1faa 0x1faa typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 1faa 1faa seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 1fab 1fab <default> 1fac 1fac fiu_len_fill_lit 45 zero-fill 0x5; Flow J 0x1fa3 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 1fa3 0x1fa3 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1fad 1fad <halt> ; Flow R 1fae ; -------------------------------------------------------------------------------------- 1fae ; 0x0341 Complete_Type Array,By_Constraining 1fae ; -------------------------------------------------------------------------------------- 1fae MACRO_Complete_Type_Array,By_Constraining: 1fae 1fae dispatch_brk_class 4 ; Flow C cc=True 0x32db dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 1fae fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1faf 1faf fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 1fb0 1fb0 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR 1fb1 1fb1 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x1fb6 fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1fb6 0x1fb6 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 0 typ_frame 1c typ_rand 9 PASS_A_HIGH val_c_adr 3f GP00 val_c_source 0 FIU_BUS 1fb2 1fb2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 1fb3 1fb3 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32db seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 1fb4 1fb4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x1fbb seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 1fbb 0x1fbb seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 1fb5 1fb5 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1fb6 1fb6 fiu_len_fill_lit 45 zero-fill 0x5 fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 1fb7 1fb7 <default> 1fb8 1fb8 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1fb9 1fb9 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1fba 0x1fba seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 0f GP0f 1fba 1fba seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 1fbb 1fbb fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_lit 0 typ_frame c typ_mar_cntl d LOAD_MAR_TYPE 1fbc 1fbc fiu_mem_start 4 continue; Flow J cc=False 0x1fda fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1fda 0x1fda typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 1d TOP - 3 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1fbd 1fbd fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 1fbe 1fbe fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x1fc9 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 1fc9 0x1fc9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1fbf 1fbf fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1fd7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1fd7 0x1fd7 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1fc0 1fc0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a2 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1fc1 1fc1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x1fd0 fiu_load_var 1 hold_var fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 1fd0 0x1fd0 seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1fc2 1fc2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 02 ? typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 1fc3 1fc3 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1d TOP - 3 1fc4 1fc4 ioc_load_wdr 0 ; Flow C cc=True 0x32a2 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 1fc5 1fc5 seq_b_timing 0 Early Condition; Flow C cc=False 0x1fc7 seq_br_type 4 Call False seq_branch_adr 1fc7 0x1fc7 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_csa_cntl 3 POP_CSA 1fc6 1fc6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1fc7 ; -------------------------------------------------------------------------------------- 1fc7 ; Comes from: 1fc7 ; 1fc5 C False from color MACRO_Complete_Type_Array,By_Constraining 1fc7 ; -------------------------------------------------------------------------------------- 1fc7 1fc7 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1fc8 1fc8 fiu_tivi_src 4 fiu_var; Flow R ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return val_a_adr 06 GP06 val_b_adr 37 VR06:17 val_frame 6 1fc9 ; -------------------------------------------------------------------------------------- 1fc9 ; Comes from: 1fc9 ; 1fbe C True from color MACRO_Complete_Type_Array,By_Constraining 1fc9 ; -------------------------------------------------------------------------------------- 1fc9 1fc9 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 1fca 1fca fiu_mem_start 4 continue; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 1fcb 0x1fcb seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2d TR05:0d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 1fcb 1fcb seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1fcc ; -------------------------------------------------------------------------------------- 1fcc ; Comes from: 1fcc ; 1fdc C True from color MACRO_Complete_Type_Array,By_Constraining 1fcc ; -------------------------------------------------------------------------------------- 1fcc 1fcc <default> 1fcd 1fcd fiu_mem_start 2 start-rd; Flow J 0x1fca ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 1fca 0x1fca typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 1fce ; -------------------------------------------------------------------------------------- 1fce ; Comes from: 1fce ; 200b C True from color MACRO_Complete_Type_Array,By_Constraining 1fce ; -------------------------------------------------------------------------------------- 1fce 1fce seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1fcf 0x1fcf seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 2d TR05:0d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 5 1fcf 1fcf seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 1fd0 ; -------------------------------------------------------------------------------------- 1fd0 ; Comes from: 1fd0 ; 1fc1 C False from color MACRO_Complete_Type_Array,By_Constraining 1fd0 ; -------------------------------------------------------------------------------------- 1fd0 1fd0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1fd1 1fd1 ioc_fiubs 0 fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 1fd2 1fd2 seq_b_timing 1 Latch Condition; Flow C cc=False 0x1fd5 seq_br_type 4 Call False seq_branch_adr 1fd5 0x1fd5 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1fd3 1fd3 seq_br_type 4 Call False; Flow C cc=False 0x1fd6 seq_branch_adr 1fd6 0x1fd6 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 1fd4 1fd4 fiu_load_var 1 hold_var; Flow R fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return seq_en_micro 0 val_b_adr 0e GP0e 1fd5 ; -------------------------------------------------------------------------------------- 1fd5 ; Comes from: 1fd5 ; 1fd2 C False from color 0x1fce 1fd5 ; -------------------------------------------------------------------------------------- 1fd5 1fd5 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 1fd6 0x1fd6 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_m_b_src 2 Bits 32…47 1fd6 ; -------------------------------------------------------------------------------------- 1fd6 ; Comes from: 1fd6 ; 1fd3 C False from color 0x1fce 1fd6 ; -------------------------------------------------------------------------------------- 1fd6 1fd6 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 1fd7 ; -------------------------------------------------------------------------------------- 1fd7 ; Comes from: 1fd7 ; 1fbf C False from color MACRO_Complete_Type_Array,By_Constraining 1fd7 ; -------------------------------------------------------------------------------------- 1fd7 1fd7 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1fd8 1fd8 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1fd9 1fd9 seq_br_type a Unconditional Return; Flow R val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1fda 1fda fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1fdb 1fdb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x200b fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 200b 0x200b seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 37 VR06:17 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 6 1fdc 1fdc fiu_mem_start 4 continue; Flow C cc=True 0x1fcc ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1fcc 0x1fcc seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1b TOP - 5 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 1fdd 1fdd fiu_mem_start 4 continue; Flow C cc=True 0x1ff5 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 1ff5 0x1ff5 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 1fde 1fde fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1ff8 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 1ff8 0x1ff8 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1fdf 1fdf fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a2 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 1fe0 1fe0 seq_b_timing 1 Latch Condition; Flow C cc=False 0x1ffc seq_br_type 4 Call False seq_branch_adr 1ffc 0x1ffc seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1b A_OR_B val_b_adr 3d VR08:1d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 1fe1 1fe1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS 1fe2 1fe2 ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2f TR07:0f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 1fe3 1fe3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 1fe4 1fe4 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 03 GP03 val_a_adr 1c TOP - 4 val_alu_func 6 A_MINUS_B val_b_adr 1b TOP - 5 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1fe5 1fe5 val_a_adr 05 GP05 val_alu_func 7 INC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 1fe6 1fe6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 1b TOP - 5 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1c TOP - 4 1fe7 1fe7 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x2004 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2004 0x2004 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 1fe8 1fe8 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 1fe9 1fe9 ioc_fiubs 1 val seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 1fea 1fea fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x2006 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2006 0x2006 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 1feb 1feb fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_load_wdr 0 seq_random 02 ? typ_a_adr 04 GP04 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 1fec 1fec fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 05 GP05 val_b_adr 1b TOP - 5 1fed 1fed fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 1fee 1fee fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x1ff2 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 1ff2 0x1ff2 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 1fef 1fef ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA 1ff0 1ff0 typ_csa_cntl 3 POP_CSA 1ff1 1ff1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1ff2 1ff2 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 1ff3 1ff3 ioc_load_wdr 0 typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA val_b_adr 06 GP06 1ff4 1ff4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 1ff5 ; -------------------------------------------------------------------------------------- 1ff5 ; Comes from: 1ff5 ; 1fdd C True from color MACRO_Complete_Type_Array,By_Constraining 1ff5 ; -------------------------------------------------------------------------------------- 1ff5 1ff5 seq_br_type 4 Call False; Flow C cc=False 0x32a2 seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1c TOP - 4 val_alu_func 6 A_MINUS_B val_b_adr 1b TOP - 5 1ff6 1ff6 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 1ff7 1ff7 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 1ff8 1ff8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 25 TR11:05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 1ff9 1ff9 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 1ffa 1ffa fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3d GP02 val_c_mux_sel 2 ALU 1ffb 1ffb seq_br_type 3 Unconditional Branch; Flow J 0x1fe1 seq_branch_adr 1fe1 0x1fe1 val_a_adr 3d VR08:1d val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 1ffc ; -------------------------------------------------------------------------------------- 1ffc ; Comes from: 1ffc ; 1fe0 C False from color MACRO_Complete_Type_Array,By_Constraining 1ffc ; -------------------------------------------------------------------------------------- 1ffc 1ffc val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 1ffd 1ffd fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 1ffe 1ffe seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 1fff 1fff seq_b_timing 1 Latch Condition; Flow C cc=False 0x2002 seq_br_type 4 Call False seq_branch_adr 2002 0x2002 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2000 2000 seq_br_type 4 Call False; Flow C cc=False 0x2003 seq_branch_adr 2003 0x2003 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 2001 2001 seq_br_type a Unconditional Return; Flow R val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3d VR08:1d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 2002 ; -------------------------------------------------------------------------------------- 2002 ; Comes from: 2002 ; 1fff C False from color 0x1ffc 2002 ; -------------------------------------------------------------------------------------- 2002 2002 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2003 0x2003 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_m_b_src 2 Bits 32…47 2003 ; -------------------------------------------------------------------------------------- 2003 ; Comes from: 2003 ; 2000 C False from color 0x1ffc 2003 ; -------------------------------------------------------------------------------------- 2003 2003 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 2004 ; -------------------------------------------------------------------------------------- 2004 ; Comes from: 2004 ; 1fe7 C False from color MACRO_Complete_Type_Array,By_Constraining 2004 ; -------------------------------------------------------------------------------------- 2004 2004 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2005 2005 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 1c TOP - 4 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2006 ; -------------------------------------------------------------------------------------- 2006 ; Comes from: 2006 ; 1fea C False from color MACRO_Complete_Type_Array,By_Constraining 2006 ; -------------------------------------------------------------------------------------- 2006 2006 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2007 2007 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2008 2008 seq_br_type 4 Call False; Flow C cc=False 0x200a seq_branch_adr 200a 0x200a seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 2009 2009 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return 200a ; -------------------------------------------------------------------------------------- 200a ; Comes from: 200a ; 2008 C False from color 0x2006 200a ; -------------------------------------------------------------------------------------- 200a 200a seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 200b 200b seq_b_timing 1 Latch Condition; Flow C cc=True 0x1fce seq_br_type 5 Call True seq_branch_adr 1fce 0x1fce 200c 200c fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 200d 200d fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 38 TR05:18 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 200e 200e typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 38 TR05:18 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 200f 200f fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 2010 2010 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 22 VR09:02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 9 2011 2011 fiu_load_tar 1 hold_tar; Flow J cc=True 0x201a fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 201a 0x201a seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 21 VR09:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2012 2012 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2013 2013 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 4 val_rand c START_MULTIPLY 2014 2014 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 22 VR09:02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 9 2015 2015 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2016 2016 ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 2017 2017 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2018 2018 ioc_tvbs 2 fiu+val typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 2019 2019 fiu_load_tar 1 hold_tar; Flow J 0x201a fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 201a 0x201a typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 201a 201a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2030 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2030 0x2030 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 201b 201b fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 val_rand 2 DEC_LOOP_COUNTER 201c 201c ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 201d 201d ioc_tvbs c mem+mem+csa+dummy typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 201e 201e fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 201f 201f seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2020 2020 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 2021 2021 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x202f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 202f 0x202f seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2022 2022 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a2 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 2023 2023 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 2024 2024 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 2025 2025 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 06 GP06 2026 2026 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR07:11 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 7 val_b_adr 01 GP01 2027 2027 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2b TR08:0b typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 2028 2028 ioc_fiubs 2 typ ; Flow J cc=True 0x201a seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 201a 0x201a seq_en_micro 0 typ_a_adr 06 GP06 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2029 2029 seq_br_type 0 Branch False; Flow J cc=False 0x202e seq_branch_adr 202e 0x202e seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 202a 202a seq_br_type 0 Branch False; Flow J cc=False 0x202e seq_branch_adr 202e 0x202e seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 202b 202b seq_br_type 0 Branch False; Flow J cc=False 0x202e seq_branch_adr 202e 0x202e seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 202c 202c seq_br_type 0 Branch False; Flow J cc=False 0x202e seq_branch_adr 202e 0x202e seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 202d 202d seq_br_type 1 Branch True; Flow J cc=True 0x201a seq_branch_adr 201a 0x201a seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_rand e PRODUCT_LEFT_32 202e 202e ioc_fiubs 2 typ ; Flow J 0x201a seq_br_type 3 Unconditional Branch seq_branch_adr 201a 0x201a typ_a_adr 06 GP06 val_alu_func 13 ONES val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 202f 202f seq_br_type 3 Unconditional Branch; Flow J 0x2024 seq_branch_adr 2024 0x2024 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2030 2030 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2031 2031 ioc_load_wdr 0 ; Flow C cc=False 0x2035 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 2035 0x2035 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 02 ? typ_b_adr 01 GP01 val_b_adr 0f GP0f 2032 2032 ioc_adrbs 1 val ioc_fiubs 1 val seq_random 0f Load_control_top+? typ_csa_cntl 1 START_POP_DOWN val_a_adr 05 GP05 val_alu_func 0 PASS_A 2033 2033 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 2034 2034 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2035 ; -------------------------------------------------------------------------------------- 2035 ; Comes from: 2035 ; 2031 C False from color MACRO_Complete_Type_Array,By_Constraining 2035 ; -------------------------------------------------------------------------------------- 2035 2035 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2036 2036 ioc_fiubs 1 val ; Flow J 0x2247 seq_br_type 3 Unconditional Branch seq_branch_adr 2247 0x2247 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 2037 2037 <halt> ; Flow R 2038 ; -------------------------------------------------------------------------------------- 2038 ; 0x0343 Complete_Type Array,By_Defining 2038 ; -------------------------------------------------------------------------------------- 2038 MACRO_Complete_Type_Array,By_Defining: 2038 2038 dispatch_brk_class 4 ; Flow C cc=True 0x32db dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2038 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2039 2039 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 203a 203a fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR 203b 203b fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x32d7 fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_b_adr 10 TOP typ_c_lit 2 typ_frame a val_c_adr 37 GP08 val_c_source 0 FIU_BUS 203c 203c fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3b GP04 val_c_source 0 FIU_BUS 203d 203d fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 203e 203e ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32db seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 203f 203f ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 2040 2040 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x32d7 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2041 2041 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20d8 seq_br_type f Unconditional Case Call seq_branch_adr 20d8 0x20d8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2042 2042 ioc_tvbs 2 fiu+val; Flow J cc=False 0x2047 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2047 0x2047 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 2043 2043 seq_br_type 2 Push (branch address); Flow J 0x2044 seq_branch_adr 2047 0x2047 typ_alu_func 1b A_OR_B typ_b_adr 31 TR09:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 2044 2044 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2045 0x2045 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_frame b 2045 2045 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x20e8 seq_br_type 1 Branch True seq_branch_adr 20e8 0x20e8 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 1e TOP - 2 typ_b_adr 2d TR09:0d typ_frame 9 2046 2046 seq_br_type 3 Unconditional Branch; Flow J 0x20eb seq_branch_adr 20eb 0x20eb 2047 2047 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2064 seq_br_type 1 Branch True seq_branch_adr 2064 0x2064 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_rand 2 DEC_LOOP_COUNTER 2048 2048 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3e VR08:1e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 2049 2049 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 204a 204a seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 204b 204b seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2053 seq_br_type 1 Branch True seq_branch_adr 2053 0x2053 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 204c 204c seq_b_timing 1 Latch Condition; Flow C cc=False 0x32a8 seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 204d 204d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a8 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 204e 204e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2056 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2056 0x2056 seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 204f 204f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2050 2050 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2051 2051 fiu_mem_start 3 start-wr; Flow J cc=True 0x2056 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 2056 0x2056 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 2052 2052 fiu_mem_start 3 start-wr; Flow J 0x2056 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2056 0x2056 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2053 2053 ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2054 2054 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2055 2055 fiu_mem_start 3 start-wr; Flow J 0x2056 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2056 0x2056 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2056 2056 fiu_mem_start 4 continue; Flow C 0x32d7 ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2057 2057 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 0 PASS_A 2058 2058 fiu_load_var 1 hold_var; Flow J cc=True 0x205c fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 205c 0x205c typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 1d TOP - 3 2059 2059 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA 205a 205a typ_csa_cntl 3 POP_CSA 205b 205b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 205c 205c fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 205d 205d fiu_tivi_src 4 fiu_var; Flow J 0x205e ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 205a 0x205a val_a_adr 10 TOP val_b_adr 37 VR06:17 val_frame 6 205e 205e seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 205f 0x205f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 18 NOT_A_AND_B typ_b_adr 23 TR01:03 typ_frame 1 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 205f 205f fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2060 2060 <default> 2061 2061 fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 3b VR02:1b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2062 2062 ioc_load_wdr 0 ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2063 0x2063 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_alu_func 19 X_XOR_B typ_b_adr 0f GP0f val_b_adr 0f GP0f 2063 2063 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2064 2064 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 2065 2065 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2066 2066 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x206f seq_br_type 1 Branch True seq_branch_adr 206f 0x206f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 2067 2067 seq_b_timing 1 Latch Condition; Flow C cc=False 0x32a8 seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2068 2068 ioc_fiubs 1 val ; Flow C cc=False 0x32a8 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 2069 2069 seq_b_timing 1 Latch Condition; Flow J cc=True 0x206e seq_br_type 1 Branch True seq_branch_adr 206e 0x206e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 206a 206a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 206b 206b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 206c 206c seq_br_type 1 Branch True; Flow J cc=True 0x206e seq_branch_adr 206e 0x206e seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 206d 206d seq_br_type 3 Unconditional Branch; Flow J 0x206e seq_branch_adr 206e 0x206e val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 206e 206e seq_br_type 3 Unconditional Branch; Flow J 0x2071 seq_branch_adr 2071 0x2071 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_rand 1 INC_LOOP_COUNTER 206f 206f ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 3e VR05:1e val_frame 5 2070 2070 seq_br_type 3 Unconditional Branch; Flow J 0x206e seq_branch_adr 206e 0x206e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2071 2071 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_tar 1 hold_tar fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 17 LOOP_COUNTER val_rand 1 INC_LOOP_COUNTER 2072 2072 fiu_len_fill_lit 4d zero-fill 0xd; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_b_adr 04 GP04 val_rand 2 DEC_LOOP_COUNTER 2073 2073 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 33 VR06:13 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2074 2074 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32cb fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32cb 0x32cb seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1e TOP - 2 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2075 2075 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1c TOP - 4 2076 2076 ioc_load_wdr 0 ; Flow J 0x2077 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2077 0x2077 val_a_adr 32 VR06:12 val_alu_func 18 NOT_A_AND_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2077 2077 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2078 2078 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 31 VR06:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2079 2079 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 207a 207a ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 207b 207b seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x207d seq_br_type 0 Branch False seq_branch_adr 207d 0x207d seq_cond_sel 67 REFRESH_MACRO_EVENT 207c 207c seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 207d 207d seq_br_type 0 Branch False; Flow J cc=False 0x2089 seq_branch_adr 2089 0x2089 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 207e 207e seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 207f 207f seq_b_timing 1 Latch Condition; Flow C cc=False 0x32a8 seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2080 2080 ioc_fiubs 1 val ; Flow C cc=False 0x32a8 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 2081 2081 seq_en_micro 0 2082 2082 fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x2087 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2087 0x2087 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 2083 2083 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2084 2084 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2085 2085 fiu_mem_start 3 start-wr; Flow J cc=True 0x2087 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 2087 0x2087 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 2086 2086 fiu_mem_start 3 start-wr; Flow J 0x2087 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2087 0x2087 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2087 2087 fiu_mem_start 4 continue; Flow J 0x2088 ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 2077 0x2077 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 val_rand 2 DEC_LOOP_COUNTER 2088 2088 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x208c ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 208c 0x208c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_b_adr 01 GP01 2089 2089 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 208a 208a ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 3e VR05:1e val_frame 5 208b 208b fiu_mem_start 3 start-wr; Flow J 0x2087 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2087 0x2087 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_mux_sel 2 ALU 208c 208c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 04 GP04 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 208d 208d fiu_len_fill_lit 45 zero-fill 0x5; Flow C 0x32d7 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_b_adr 1f TOP - 1 208e 208e ioc_load_wdr 0 ; Flow C cc=False 0x2092 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 2092 0x2092 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 208f 208f ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 18 Load_control_top+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2090 2090 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 2091 2091 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2092 ; -------------------------------------------------------------------------------------- 2092 ; Comes from: 2092 ; 208e C False from color 0x208e 2092 ; -------------------------------------------------------------------------------------- 2092 2092 val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2093 2093 ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2094 2094 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 03 GP03 2095 2095 ioc_tvbs 1 typ+fiu val_a_adr 2d VR04:0d val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand c START_MULTIPLY 2096 2096 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 2097 2097 ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2098 2098 fiu_load_tar 1 hold_tar; Flow J 0x2099 fiu_tivi_src 8 type_var seq_br_type 2 Push (branch address) seq_branch_adr 209a 0x209a typ_b_adr 01 GP01 2099 2099 seq_br_type 3 Unconditional Branch; Flow J 0x205e seq_branch_adr 205e 0x205e 209a 209a seq_br_type 3 Unconditional Branch; Flow J 0x2247 seq_branch_adr 2247 0x2247 209b 209b <halt> ; Flow R 209c ; -------------------------------------------------------------------------------------- 209c ; 0x0355 Declare_Type Array,Defined_Incomplete 209c ; -------------------------------------------------------------------------------------- 209c MACRO_Declare_Type_Array,Defined_Incomplete: 209c 209c dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 209c fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3b GP04 val_c_mux_sel 2 ALU 209d 209d seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x209f seq_br_type f Unconditional Case Call seq_branch_adr 209f 0x209f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 209e 209e seq_br_type 7 Unconditional Call; Flow C 0x20fc seq_branch_adr 20fc MACRO_Declare_Type_Array,Defined 209f ; -------------------------------------------------------------------------------------- 209f ; Comes from: 209f ; 209d C #0x0 from color 0x209d 209f ; 20ce C #0x0 from color 0x20ce 209f ; 20d1 C #0x0 from color 0x20d1 209f ; 20d6 C #0x0 from color 0x20d6 209f ; -------------------------------------------------------------------------------------- 209f 209f ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x20b4 seq_br_type 9 Return False seq_branch_adr 20b4 0x20b4 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20a0 20a0 seq_br_type a Unconditional Return; Flow R 20a1 20a1 seq_br_type a Unconditional Return; Flow R 20a2 20a2 seq_br_type a Unconditional Return; Flow R 20a3 20a3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20a4 20a4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20a5 20a5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20a6 20a6 seq_br_type a Unconditional Return; Flow R 20a7 20a7 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x20b4 seq_br_type 9 Return False seq_branch_adr 20b4 0x20b4 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20a8 20a8 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x20af seq_br_type 9 Return False seq_branch_adr 20af 0x20af seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20a9 20a9 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20aa 20aa seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20ab 20ab seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20ac 20ac ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x20b2 seq_br_type 9 Return False seq_branch_adr 20b2 0x20b2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20ad 20ad ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x20b2 seq_br_type 9 Return False seq_branch_adr 20b2 0x20b2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20ae 20ae ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x20b2 seq_br_type 9 Return False seq_branch_adr 20b2 0x20b2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 36 TR12:16 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20af 20af fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x20b4 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 20b4 0x20b4 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_mar_cntl d LOAD_MAR_TYPE 20b0 20b0 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x20b4 seq_br_type 1 Branch True seq_branch_adr 20b4 0x20b4 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 20b1 20b1 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 20b2 20b2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x20b4 seq_br_type 0 Branch False seq_branch_adr 20b4 0x20b4 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 1e TOP - 2 20b3 20b3 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 20b4 20b4 seq_b_timing 1 Latch Condition; Flow J cc=False 0x20b6 seq_br_type 0 Branch False seq_branch_adr 20b6 0x20b6 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 30 VR05:10 val_frame 5 val_rand 2 DEC_LOOP_COUNTER 20b5 20b5 seq_br_type 3 Unconditional Branch; Flow J 0x20ed seq_branch_adr 20ed 0x20ed typ_a_adr 20 TR05:00 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 20b6 20b6 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3e VR08:1e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 20b7 20b7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 20b8 20b8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20b9 20b9 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x20c1 seq_br_type 1 Branch True seq_branch_adr 20c1 0x20c1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 20ba 20ba seq_b_timing 1 Latch Condition; Flow C cc=False 0x32a8 seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20bb 20bb fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a8 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 20bc 20bc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x20c4 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 20c4 0x20c4 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 20bd 20bd seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20be 20be seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20bf 20bf fiu_mem_start 3 start-wr; Flow J cc=True 0x20c4 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 20c4 0x20c4 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 20c0 20c0 fiu_mem_start 3 start-wr; Flow J 0x20c4 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 20c4 0x20c4 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 20c1 20c1 ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_source 0 FIU_BUS 20c2 20c2 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 20c3 20c3 fiu_mem_start 3 start-wr; Flow J 0x20c4 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 20c4 0x20c4 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 20c4 20c4 fiu_mem_start 4 continue; Flow C 0x32d7 ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 20c5 20c5 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 3b VR02:1b val_frame 2 20c6 20c6 fiu_load_var 1 hold_var; Flow J cc=True 0x20c9 fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 20c9 0x20c9 typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 1d TOP - 3 20c7 20c7 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 33 VR05:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 20c8 20c8 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 20c9 20c9 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 33 VR05:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 20ca 20ca fiu_tivi_src 4 fiu_var; Flow J 0x20c8 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 20c8 0x20c8 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_b_adr 37 VR06:17 val_frame 6 20cb 20cb <halt> ; Flow R 20cc ; -------------------------------------------------------------------------------------- 20cc ; 0x0356 Declare_Type Array,Defined_Incomplete,Visible 20cc ; -------------------------------------------------------------------------------------- 20cc MACRO_Declare_Type_Array,Defined_Incomplete,Visible: 20cc 20cc dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 20cc seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 20cd 20cd fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x32d7 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR06:02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 20ce 20ce seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x209f seq_br_type f Unconditional Case Call seq_branch_adr 209f 0x209f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 20cf 20cf seq_br_type 7 Unconditional Call; Flow C 0x2144 seq_branch_adr 2144 MACRO_Declare_Type_Array,Defined,Visible 20d0 ; -------------------------------------------------------------------------------------- 20d0 ; 0x0348 Declare_Type Array,Defined_Incomplete,Bounds_With_Object 20d0 ; -------------------------------------------------------------------------------------- 20d0 MACRO_Declare_Type_Array,Defined_Incomplete,Bounds_With_Object: 20d0 20d0 dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 20d0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR00:00 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 20d1 20d1 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x209f seq_br_type f Unconditional Case Call seq_branch_adr 209f 0x209f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 20d2 20d2 seq_br_type 7 Unconditional Call; Flow C 0x214a seq_branch_adr 214a MACRO_Declare_Type_Array,Defined,Bounds_With_Object 20d3 20d3 <halt> ; Flow R 20d4 ; -------------------------------------------------------------------------------------- 20d4 ; 0x0349 Declare_Type Array,Defined_Incomplete,Visible,Bounds_With_Object 20d4 ; -------------------------------------------------------------------------------------- 20d4 MACRO_Declare_Type_Array,Defined_Incomplete,Visible,Bounds_With_Object: 20d4 20d4 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 20d4 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 20d5 20d5 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x32d7 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 20d6 20d6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x209f seq_br_type f Unconditional Case Call seq_branch_adr 209f 0x209f seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 20d7 20d7 seq_br_type 7 Unconditional Call; Flow C 0x214e seq_branch_adr 214e MACRO_Declare_Type_Array,Defined,Visible,Bounds_With_Object 20d8 ; -------------------------------------------------------------------------------------- 20d8 ; Comes from: 20d8 ; 2041 C #0x0 from color 0x2041 20d8 ; 20fd C #0x0 from color 0x20fd 20d8 ; 2146 C #0x0 from color 0x2146 20d8 ; 214b C #0x0 from color 0x214b 20d8 ; 2150 C #0x0 from color 0x2150 20d8 ; -------------------------------------------------------------------------------------- 20d8 20d8 fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20d9 20d9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20da 20da fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20db 20db fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20dc 20dc seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20dd 20dd seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20de 20de seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20df 20df fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 20e0 20e0 fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20e1 20e1 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x20e8 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 20e8 0x20e8 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20e2 20e2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20e3 20e3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20e4 20e4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 20e5 20e5 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x20eb fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 20eb 0x20eb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20e6 20e6 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x20eb fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 20eb 0x20eb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20e7 20e7 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x20eb fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 20eb 0x20eb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 28 TR13:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3d VR06:1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 20e8 20e8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 20e9 0x20e9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 1a PASS_B typ_b_adr 1e TOP - 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS 20e9 20e9 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 20ea 0x20ea seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 20ea 20ea seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 20eb 20eb fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 20ec 0x20ec seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 1e TOP - 2 val_a_adr 14 ZEROS 20ec 20ec seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 20ed 20ed fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32dc fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32dc 0x32dc typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 20ee 20ee seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20ef 20ef seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x20f9 seq_br_type 1 Branch True seq_branch_adr 20f9 0x20f9 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 20f0 20f0 seq_b_timing 1 Latch Condition; Flow C cc=False 0x32a8 seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 20f1 20f1 ioc_fiubs 1 val ; Flow C cc=False 0x32a8 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 20f2 20f2 ioc_tvbs 5 seq+seq; Flow J cc=True 0x20f7 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 20f7 0x20f7 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 20f3 20f3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20f4 20f4 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 20f5 20f5 seq_br_type 1 Branch True; Flow J cc=True 0x20f7 seq_branch_adr 20f7 0x20f7 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 20f6 20f6 seq_br_type 3 Unconditional Branch; Flow J 0x20f7 seq_branch_adr 20f7 0x20f7 val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 20f7 20f7 seq_b_timing 0 Early Condition; Flow J cc=True 0x2117 seq_br_type 1 Branch True seq_branch_adr 2117 0x2117 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 34 VR05:14 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 val_rand 1 INC_LOOP_COUNTER 20f8 20f8 seq_br_type 3 Unconditional Branch; Flow J 0x2117 seq_branch_adr 2117 0x2117 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 35 VR05:15 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 20f9 20f9 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT 20fa 20fa ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 3e VR05:1e val_frame 5 20fb 20fb seq_br_type 3 Unconditional Branch; Flow J 0x20f7 seq_branch_adr 20f7 0x20f7 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_mux_sel 2 ALU 20fc ; -------------------------------------------------------------------------------------- 20fc ; 0x035d Declare_Type Array,Defined 20fc ; Comes from: 20fc ; 209e C from color 0x2042 20fc ; -------------------------------------------------------------------------------------- 20fc MACRO_Declare_Type_Array,Defined: 20fc 20fc dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 20fc fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3b GP04 val_c_mux_sel 2 ALU 20fd 20fd seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20d8 seq_br_type f Unconditional Case Call seq_branch_adr 20d8 0x20d8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 20fe 20fe ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 20ff 20ff seq_b_timing 1 Latch Condition; Flow J cc=True 0x20ed seq_br_type 1 Branch True seq_branch_adr 20ed 0x20ed seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 30 VR05:10 val_frame 5 val_rand 2 DEC_LOOP_COUNTER 2100 2100 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3e VR08:1e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 2101 2101 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 1d TOP - 3 typ_b_adr 1c TOP - 4 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS 2102 2102 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2103 2103 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x210d seq_br_type 1 Branch True seq_branch_adr 210d 0x210d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 2104 2104 seq_b_timing 1 Latch Condition; Flow C cc=False 0x210b seq_br_type 4 Call False seq_branch_adr 210b 0x210b seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2105 2105 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a8 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 2106 2106 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2110 fiu_mem_start 7 start_wr_if_true fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2110 0x2110 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 2107 2107 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2108 2108 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2109 2109 fiu_mem_start 3 start-wr; Flow J cc=True 0x2110 ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 2110 0x2110 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 210a 210a fiu_mem_start 3 start-wr; Flow J 0x2110 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2110 0x2110 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 210b ; -------------------------------------------------------------------------------------- 210b ; Comes from: 210b ; 2104 C False from color 0x2042 210b ; -------------------------------------------------------------------------------------- 210b 210b seq_br_type 1 Branch True; Flow J cc=True 0x32a8 seq_branch_adr 32a8 0x32a8 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1b A_OR_B typ_b_adr 31 TR02:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 210c 210c seq_br_type a Unconditional Return; Flow R val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 210d 210d ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_source 0 FIU_BUS 210e 210e typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 210f 210f fiu_mem_start 3 start-wr; Flow J 0x2110 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2110 0x2110 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2110 2110 fiu_mem_start 4 continue; Flow C 0x32d7 ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2111 2111 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 0 PASS_A 2112 2112 fiu_load_var 1 hold_var; Flow J cc=True 0x2115 fiu_mem_start 4 continue fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2115 0x2115 typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 1d TOP - 3 2113 2113 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 33 VR05:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 2114 2114 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2115 2115 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 33 VR05:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 2116 2116 fiu_tivi_src 4 fiu_var; Flow J 0x2114 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2114 0x2114 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_b_adr 37 VR06:17 val_frame 6 2117 2117 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_tar 1 hold_tar fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 36 TR06:16 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 17 LOOP_COUNTER val_rand 1 INC_LOOP_COUNTER 2118 2118 fiu_len_fill_lit 4d zero-fill 0xd; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_b_adr 10 TOP val_rand 2 DEC_LOOP_COUNTER 2119 2119 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 33 VR06:13 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 211a 211a fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x32cb fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32cb 0x32cb seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 1e TOP - 2 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 211b 211b fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1c TOP - 4 211c 211c ioc_load_wdr 0 ; Flow J 0x211d ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 211d 0x211d val_a_adr 32 VR06:12 val_alu_func 18 NOT_A_AND_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 211d 211d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 211e 211e fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 31 VR06:11 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 211f 211f ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2120 2120 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2121 2121 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2123 seq_br_type 0 Branch False seq_branch_adr 2123 0x2123 seq_cond_sel 67 REFRESH_MACRO_EVENT 2122 2122 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 2123 2123 seq_br_type 0 Branch False; Flow J cc=False 0x212f seq_branch_adr 212f 0x212f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 2124 2124 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2125 2125 seq_b_timing 1 Latch Condition; Flow C cc=False 0x32a8 seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 val_a_adr 03 GP03 val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2126 2126 ioc_fiubs 1 val ; Flow C cc=False 0x32a8 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_rand c START_MULTIPLY 2127 2127 seq_en_micro 0 2128 2128 fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x212d ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 212d 0x212d seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 2129 2129 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 212a 212a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 212b 212b fiu_mem_start 3 start-wr; Flow J cc=True 0x212d ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 212d 0x212d seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 212c 212c fiu_mem_start 3 start-wr; Flow J 0x212d ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 212d 0x212d typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 13 ONES val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 212d 212d fiu_mem_start 4 continue; Flow J 0x212e ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 211d 0x211d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 val_rand 2 DEC_LOOP_COUNTER 212e 212e ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x2132 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 2132 0x2132 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_b_adr 01 GP01 212f 212f typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2130 2130 ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 3e VR05:1e val_frame 5 2131 2131 fiu_mem_start 3 start-wr; Flow J 0x212d ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 212d 0x212d typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2132 2132 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2136 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2136 0x2136 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 10 TOP val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2133 2133 fiu_len_fill_lit 45 zero-fill 0x5; Flow C 0x32d7 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_b_adr 1f TOP - 1 2134 2134 ioc_load_wdr 0 ; Flow C cc=False 0x213d seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 213d 0x213d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 2135 2135 ioc_adrbs 2 typ ; Flow J 0x2139 ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2139 0x2139 seq_random 18 Load_control_top+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2136 2136 fiu_len_fill_lit 45 zero-fill 0x5; Flow C 0x32d7 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_b_adr 1f TOP - 1 2137 2137 ioc_load_wdr 0 ; Flow C cc=False 0x213d seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 213d 0x213d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_b_adr 3b VR02:1b val_frame 2 2138 2138 ioc_adrbs 2 typ ; Flow J 0x2139 ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2139 0x2139 seq_random 18 Load_control_top+? typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2139 2139 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 213a 213a fiu_mem_start 3 start-wr fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 213b 213b fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val val_a_adr 04 GP04 val_b_adr 39 VR02:19 val_frame 2 213c 213c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 213d ; -------------------------------------------------------------------------------------- 213d ; Comes from: 213d ; 2134 C False from color 0x2134 213d ; 2137 C False from color 0x2134 213d ; -------------------------------------------------------------------------------------- 213d 213d val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 213e 213e ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 213f 213f fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 03 GP03 2140 2140 ioc_tvbs 1 typ+fiu val_a_adr 2d VR04:0d val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand c START_MULTIPLY 2141 2141 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 2142 2142 ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2143 2143 fiu_load_tar 1 hold_tar; Flow J 0x2247 fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 2247 0x2247 typ_b_adr 01 GP01 2144 ; -------------------------------------------------------------------------------------- 2144 ; 0x035e Declare_Type Array,Defined,Visible 2144 ; Comes from: 2144 ; 20cf C from color 0x20cf 2144 ; -------------------------------------------------------------------------------------- 2144 MACRO_Declare_Type_Array,Defined,Visible: 2144 2144 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2144 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2145 2145 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x32d7 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR06:02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 2146 2146 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20d8 seq_br_type f Unconditional Case Call seq_branch_adr 20d8 0x20d8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2147 2147 ioc_tvbs 2 fiu+val; Flow J cc=False 0x20ff seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 20ff 0x20ff seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2148 2148 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 2149 2149 <halt> ; Flow R 214a ; -------------------------------------------------------------------------------------- 214a ; 0x0350 Declare_Type Array,Defined,Bounds_With_Object 214a ; Comes from: 214a ; 20d2 C from color 0x20d2 214a ; -------------------------------------------------------------------------------------- 214a MACRO_Declare_Type_Array,Defined,Bounds_With_Object: 214a 214a dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 214a fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR00:00 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 214b 214b seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20d8 seq_br_type f Unconditional Case Call seq_branch_adr 20d8 0x20d8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 214c 214c ioc_tvbs 2 fiu+val; Flow J cc=False 0x20ff seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 20ff 0x20ff seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 214d 214d seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 214e ; -------------------------------------------------------------------------------------- 214e ; 0x0351 Declare_Type Array,Defined,Visible,Bounds_With_Object 214e ; Comes from: 214e ; 20d7 C from color 0x20d7 214e ; -------------------------------------------------------------------------------------- 214e MACRO_Declare_Type_Array,Defined,Visible,Bounds_With_Object: 214e 214e dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 214e seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 214f 214f fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x32d7 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2150 2150 seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x20d8 seq_br_type f Unconditional Case Call seq_branch_adr 20d8 0x20d8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2151 2151 ioc_tvbs 2 fiu+val; Flow J cc=False 0x20ff seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 20ff 0x20ff seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2152 2152 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 2153 2153 <halt> ; Flow R 2154 ; -------------------------------------------------------------------------------------- 2154 ; 0x035b Declare_Type Array,Constrained 2154 ; -------------------------------------------------------------------------------------- 2154 MACRO_Declare_Type_Array,Constrained: 2154 2154 dispatch_brk_class 4 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 2154 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS 2155 2155 fiu_mem_start 4 continue; Flow J cc=False 0x2176 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2176 0x2176 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2156 2156 fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 2157 2157 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2165 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2165 0x2165 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2158 2158 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2173 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2173 0x2173 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 24 TR07:04 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2159 2159 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2162 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2162 0x2162 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 215a 215a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x216c fiu_load_var 1 hold_var fiu_mem_start 9 start_continue_if_true fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 216c 0x216c seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR02:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 215b 215b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 04 GP04 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU 215c 215c fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1e TOP - 2 215d 215d ioc_load_wdr 0 ; Flow C cc=True 0x2164 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2164 0x2164 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 215e 215e fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 0 Early Condition seq_br_type c Dispatch True seq_branch_adr 215f 0x215f seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 215f 215f fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 2160 2160 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 21 TR10:01 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 06 GP06 val_b_adr 37 VR06:17 val_frame 6 2161 2161 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2162 ; -------------------------------------------------------------------------------------- 2162 ; Comes from: 2162 ; 2159 C True from color MACRO_Declare_Type_Array,Constrained 2162 ; -------------------------------------------------------------------------------------- 2162 2162 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x32a2 seq_br_type 1 Branch True seq_branch_adr 32a2 0x32a2 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_random 05 ? typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 31 TR02:11 typ_frame 2 2163 2163 fiu_mem_start 3 start-wr; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2164 ; -------------------------------------------------------------------------------------- 2164 ; Comes from: 2164 ; 215d C True from color MACRO_Declare_Type_Array,Constrained 2164 ; -------------------------------------------------------------------------------------- 2164 2164 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32a2 seq_br_type 9 Return False seq_branch_adr 32a2 0x32a2 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 31 TR02:11 typ_frame 2 2165 ; -------------------------------------------------------------------------------------- 2165 ; Comes from: 2165 ; 2157 C True from color MACRO_Declare_Type_Array,Constrained 2165 ; -------------------------------------------------------------------------------------- 2165 2165 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2166 2166 fiu_mem_start 4 continue; Flow R cc=False ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2167 0x2167 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 2d TR05:0d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2167 2167 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 2168 ; -------------------------------------------------------------------------------------- 2168 ; Comes from: 2168 ; 2178 C True from color MACRO_Declare_Type_Array,Constrained 2168 ; -------------------------------------------------------------------------------------- 2168 2168 <default> 2169 2169 fiu_mem_start 2 start-rd; Flow J 0x2166 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2166 0x2166 typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 216a ; -------------------------------------------------------------------------------------- 216a ; Comes from: 216a ; 21a7 C True from color MACRO_Declare_Type_Array,Constrained 216a ; -------------------------------------------------------------------------------------- 216a 216a ioc_tvbs 5 seq+seq; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 216b 0x216b seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 2d TR05:0d typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_frame 5 val_a_adr 25 VR05:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 216b 216b seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 216c ; -------------------------------------------------------------------------------------- 216c ; Comes from: 216c ; 215a C False from color MACRO_Declare_Type_Array,Constrained 216c ; -------------------------------------------------------------------------------------- 216c 216c fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 216d 216d ioc_fiubs 0 fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 216e 216e seq_b_timing 1 Latch Condition; Flow C cc=False 0x2171 seq_br_type 4 Call False seq_branch_adr 2171 0x2171 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 216f 216f seq_br_type 4 Call False; Flow C cc=False 0x2172 seq_branch_adr 2172 0x2172 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2170 2170 fiu_load_var 1 hold_var; Flow R fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return seq_en_micro 0 val_b_adr 0e GP0e 2171 ; -------------------------------------------------------------------------------------- 2171 ; Comes from: 2171 ; 216e C False from color 0x216a 2171 ; -------------------------------------------------------------------------------------- 2171 2171 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2172 0x2172 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_m_b_src 2 Bits 32…47 2172 ; -------------------------------------------------------------------------------------- 2172 ; Comes from: 2172 ; 216f C False from color 0x216a 2172 ; -------------------------------------------------------------------------------------- 2172 2172 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 2173 ; -------------------------------------------------------------------------------------- 2173 ; Comes from: 2173 ; 2158 C False from color MACRO_Declare_Type_Array,Constrained 2173 ; -------------------------------------------------------------------------------------- 2173 2173 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2174 2174 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2175 2175 seq_br_type a Unconditional Return; Flow R val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2176 2176 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 10 TOP typ_c_lit 0 typ_frame 14 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2177 2177 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x21a7 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 21a7 0x21a7 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 37 VR06:17 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 6 2178 2178 fiu_mem_start 4 continue; Flow C cc=True 0x2168 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2168 0x2168 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1c TOP - 4 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2179 2179 fiu_mem_start 4 continue; Flow C cc=True 0x2191 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2191 0x2191 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 217a 217a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2194 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2194 0x2194 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2d TR07:0d typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 217b 217b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a2 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 217c 217c seq_b_timing 1 Latch Condition; Flow C cc=False 0x2198 seq_br_type 4 Call False seq_branch_adr 2198 0x2198 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1b A_OR_B val_b_adr 3d VR08:1d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 217d 217d fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS 217e 217e ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2f TR07:0f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 217f 217f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 2180 2180 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 03 GP03 val_a_adr 1d TOP - 3 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2181 2181 val_a_adr 05 GP05 val_alu_func 7 INC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2182 2182 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 1c TOP - 4 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1d TOP - 3 2183 2183 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x21a0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 21a0 0x21a0 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 2184 2184 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 2185 2185 ioc_fiubs 1 val seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 05 GP05 val_rand c START_MULTIPLY 2186 2186 fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x21a2 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 21a2 0x21a2 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 05 GP05 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 2187 2187 fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 04 GP04 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2188 2188 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_mar_cntl 6 INCREMENT_MAR val_a_adr 05 GP05 val_b_adr 1c TOP - 4 2189 2189 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 218a 218a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x218d fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 218d 0x218d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 218b 218b ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 218c 218c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 218d 218d fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 218e 218e ioc_load_wdr 0 typ_b_adr 06 GP06 val_b_adr 06 GP06 218f 218f typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 2190 2190 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2191 ; -------------------------------------------------------------------------------------- 2191 ; Comes from: 2191 ; 2179 C True from color MACRO_Declare_Type_Array,Constrained 2191 ; -------------------------------------------------------------------------------------- 2191 2191 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1c TOP - 4 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1d TOP - 3 2192 2192 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 2193 2193 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 2194 2194 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 25 TR11:05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2195 2195 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2196 2196 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2197 2197 seq_br_type 3 Unconditional Branch; Flow J 0x217d seq_branch_adr 217d 0x217d val_a_adr 3d VR08:1d val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 2198 ; -------------------------------------------------------------------------------------- 2198 ; Comes from: 2198 ; 217c C False from color MACRO_Declare_Type_Array,Constrained 2198 ; -------------------------------------------------------------------------------------- 2198 2198 val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2199 2199 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 219a 219a seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 seq_latch 1 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_m_a_src 2 Bits 32…47 val_rand c START_MULTIPLY 219b 219b seq_b_timing 1 Latch Condition; Flow C cc=False 0x219e seq_br_type 4 Call False seq_branch_adr 219e 0x219e seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 219c 219c seq_br_type 4 Call False; Flow C cc=False 0x219f seq_branch_adr 219f 0x219f seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 219d 219d seq_br_type a Unconditional Return; Flow R val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3d VR08:1d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 219e ; -------------------------------------------------------------------------------------- 219e ; Comes from: 219e ; 219b C False from color 0x2198 219e ; -------------------------------------------------------------------------------------- 219e 219e seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 219f 0x219f seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_m_b_src 2 Bits 32…47 219f ; -------------------------------------------------------------------------------------- 219f ; Comes from: 219f ; 219c C False from color 0x2198 219f ; -------------------------------------------------------------------------------------- 219f 219f seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_m_b_src 2 Bits 32…47 21a0 ; -------------------------------------------------------------------------------------- 21a0 ; Comes from: 21a0 ; 2183 C False from color MACRO_Declare_Type_Array,Constrained 21a0 ; -------------------------------------------------------------------------------------- 21a0 21a0 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 21a1 21a1 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 1d TOP - 3 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 21a2 ; -------------------------------------------------------------------------------------- 21a2 ; Comes from: 21a2 ; 2186 C False from color MACRO_Declare_Type_Array,Constrained 21a2 ; -------------------------------------------------------------------------------------- 21a2 21a2 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 21a3 21a3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 21a4 21a4 seq_br_type 4 Call False; Flow C cc=False 0x21a6 seq_branch_adr 21a6 0x21a6 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 21a5 21a5 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return 21a6 ; -------------------------------------------------------------------------------------- 21a6 ; Comes from: 21a6 ; 21a4 C False from color 0x21a2 21a6 ; -------------------------------------------------------------------------------------- 21a6 21a6 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 21a7 21a7 ioc_fiubs 0 fiu ; Flow C cc=True 0x216a seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 216a 0x216a typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 21a8 21a8 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 33 TR02:13 typ_alu_func 1a PASS_B typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 21a9 21a9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1 A_PLUS_B typ_b_adr 33 TR02:13 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 21aa 21aa typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 38 TR05:18 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 22 VR09:02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 9 21ab 21ab fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU 21ac 21ac typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 32 TR08:12 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 8 21ad 21ad fiu_load_tar 1 hold_tar; Flow J cc=True 0x21b7 fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 21b7 0x21b7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 21 VR09:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 21ae 21ae fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 21af 21af val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 4 val_rand c START_MULTIPLY 21b0 21b0 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 22 VR09:02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 9 21b1 21b1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 3a GP05 val_c_mux_sel 2 ALU 21b2 21b2 ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 21b3 21b3 ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 21b4 21b4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 21b5 21b5 ioc_tvbs 2 fiu+val typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 21b6 21b6 fiu_load_tar 1 hold_tar; Flow J 0x21b7 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 21b7 0x21b7 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 21b7 21b7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x21cf fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 21cf 0x21cf seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 21b8 21b8 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 4 val_rand 2 DEC_LOOP_COUNTER 21b9 21b9 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 21ba 21ba ioc_tvbs c mem+mem+csa+dummy typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 21bb 21bb fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 21bc 21bc seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x21bf seq_br_type 0 Branch False seq_branch_adr 21bf 0x21bf seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 21bd 21bd seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 21be 21be fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 21bf 21bf seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 21c0 21c0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x21ce fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 21ce 0x21ce seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 21c1 21c1 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32a2 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 21c2 21c2 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a2 seq_br_type 5 Call True seq_branch_adr 32a2 0x32a2 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 21c3 21c3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 21c4 21c4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_b_adr 06 GP06 21c5 21c5 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR07:11 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 7 val_b_adr 01 GP01 21c6 21c6 seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2b TR08:0b typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 21c7 21c7 ioc_fiubs 2 typ ; Flow J cc=True 0x21b7 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 21b7 0x21b7 seq_en_micro 0 typ_a_adr 06 GP06 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 21c8 21c8 seq_br_type 0 Branch False; Flow J cc=False 0x21cd seq_branch_adr 21cd 0x21cd seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 21c9 21c9 seq_br_type 0 Branch False; Flow J cc=False 0x21cd seq_branch_adr 21cd 0x21cd seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 21ca 21ca seq_br_type 0 Branch False; Flow J cc=False 0x21cd seq_branch_adr 21cd 0x21cd seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 21cb 21cb seq_br_type 0 Branch False; Flow J cc=False 0x21cd seq_branch_adr 21cd 0x21cd seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 21cc 21cc seq_br_type 1 Branch True; Flow J cc=True 0x21b7 seq_branch_adr 21b7 0x21b7 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_rand e PRODUCT_LEFT_32 21cd 21cd ioc_fiubs 2 typ ; Flow J 0x21b7 seq_br_type 3 Unconditional Branch seq_branch_adr 21b7 0x21b7 typ_a_adr 06 GP06 val_alu_func 13 ONES val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 21ce 21ce seq_br_type 3 Unconditional Branch; Flow J 0x21c3 seq_branch_adr 21c3 0x21c3 typ_a_adr 3b TR07:1b typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 21cf 21cf fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 21d0 21d0 ioc_load_wdr 0 ; Flow C cc=False 0x21d6 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 21d6 0x21d6 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 01 GP01 val_b_adr 0f GP0f 21d1 21d1 ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 2 val_a_adr 05 GP05 val_alu_func 0 PASS_A 21d2 21d2 seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 21d3 21d3 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 21d4 21d4 ioc_load_wdr 0 val_b_adr 39 VR02:19 val_frame 2 21d5 21d5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 21d6 ; -------------------------------------------------------------------------------------- 21d6 ; Comes from: 21d6 ; 21d0 C False from color MACRO_Declare_Type_Array,Constrained 21d6 ; -------------------------------------------------------------------------------------- 21d6 21d6 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 21d7 21d7 ioc_fiubs 1 val typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 21d8 21d8 val_a_adr 17 LOOP_COUNTER val_alu_func 7 INC_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU 21d9 21d9 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0e GP0e 21da 21da ioc_tvbs 1 typ+fiu val_a_adr 2d VR04:0d val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand c START_MULTIPLY 21db 21db ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 21dc 21dc seq_br_type 3 Unconditional Branch; Flow J 0x2247 seq_branch_adr 2247 0x2247 seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 21dd 21dd <halt> ; Flow R 21de ; -------------------------------------------------------------------------------------- 21de ; 0x034e Declare_Type Array,Constrained,Bounds_With_Object 21de ; -------------------------------------------------------------------------------------- 21de MACRO_Declare_Type_Array,Constrained,Bounds_With_Object: 21de 21de dispatch_brk_class 4 ; Flow J 0x2155 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21de fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2155 0x2155 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR00:00 21df 21df <halt> ; Flow R 21e0 ; -------------------------------------------------------------------------------------- 21e0 ; 0x035c Declare_Type Array,Constrained,Visible 21e0 ; -------------------------------------------------------------------------------------- 21e0 MACRO_Declare_Type_Array,Constrained,Visible: 21e0 21e0 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21e0 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 21e1 21e1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2155 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2155 0x2155 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR06:02 val_frame 6 21e2 ; -------------------------------------------------------------------------------------- 21e2 ; 0x034f Declare_Type Array,Constrained,Visible,Bounds_With_Object 21e2 ; -------------------------------------------------------------------------------------- 21e2 MACRO_Declare_Type_Array,Constrained,Visible,Bounds_With_Object: 21e2 21e2 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21e2 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 21e3 21e3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2155 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2155 0x2155 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR00:02 21e4 ; -------------------------------------------------------------------------------------- 21e4 ; 0x0353 Declare_Type Array,Constrained_Incomplete 21e4 ; -------------------------------------------------------------------------------------- 21e4 MACRO_Declare_Type_Array,Constrained_Incomplete: 21e4 21e4 dispatch_brk_class 4 ; Flow J 0x2155 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21e4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2155 0x2155 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS 21e5 21e5 <halt> ; Flow R 21e6 ; -------------------------------------------------------------------------------------- 21e6 ; 0x0346 Declare_Type Array,Constrained_Incomplete,Bounds_With_Object 21e6 ; -------------------------------------------------------------------------------------- 21e6 MACRO_Declare_Type_Array,Constrained_Incomplete,Bounds_With_Object: 21e6 21e6 dispatch_brk_class 4 ; Flow J 0x2155 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21e6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2155 0x2155 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 20 VR00:00 21e7 21e7 <halt> ; Flow R 21e8 ; -------------------------------------------------------------------------------------- 21e8 ; 0x0354 Declare_Type Array,Constrained_Incomplete,Visible 21e8 ; -------------------------------------------------------------------------------------- 21e8 MACRO_Declare_Type_Array,Constrained_Incomplete,Visible: 21e8 21e8 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21e8 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 21e9 21e9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2155 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2155 0x2155 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR06:02 val_frame 6 21ea ; -------------------------------------------------------------------------------------- 21ea ; 0x0347 Declare_Type Array,Constrained_Incomplete,Visible,Bounds_With_Object 21ea ; -------------------------------------------------------------------------------------- 21ea MACRO_Declare_Type_Array,Constrained_Incomplete,Visible,Bounds_With_Object: 21ea 21ea dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 21ea seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 21eb 21eb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2155 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2155 0x2155 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR0c:00 typ_c_adr 38 GP07 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 22 VR00:02 21ec ; -------------------------------------------------------------------------------------- 21ec ; 0x03a3 Complete_Type Heap_Access,By_Defining 21ec ; -------------------------------------------------------------------------------------- 21ec MACRO_Complete_Type_Heap_Access,By_Defining: 21ec 21ec dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 21ec fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 21ed 21ed ioc_fiubs 0 fiu ; Flow C cc=True 0x32db ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 21ee 21ee fiu_load_tar 1 hold_tar; Flow C cc=False 0x32d9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR09:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 9 21ef 21ef fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3a GP05 val_c_source 0 FIU_BUS 21f0 21f0 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2244 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2244 0x2244 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 21f1 21f1 fiu_mem_start 6 start_rd_if_false; Flow C 0x32d7 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 21f2 21f2 seq_b_timing 3 Late Condition, Hint False; Flow C 0x32d7 seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_frame 1c 21f3 21f3 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 26 TR06:06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 21f4 21f4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=#0x0 0x21f9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 21f9 0x21f9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_b_adr 1e TOP - 2 typ_c_lit 1 typ_frame c 21f5 21f5 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 1f TOP - 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 21f6 21f6 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1e TOP - 2 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 21f7 21f7 ioc_load_wdr 0 typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA val_b_adr 39 VR02:19 val_frame 2 21f8 21f8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 21f9 ; -------------------------------------------------------------------------------------- 21f9 ; Comes from: 21f9 ; 21f4 C #0x0 from color 0x21f3 21f9 ; -------------------------------------------------------------------------------------- 21f9 21f9 fiu_mem_start 8 start_wr_if_false; Flow R cc=False ; Flow J cc=True 0x21ff ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 21ff 0x21ff typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21fa 21fa fiu_mem_start 8 start_wr_if_false; Flow R cc=False ; Flow J cc=True 0x21ff ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 21ff 0x21ff typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21fb 21fb fiu_mem_start 8 start_wr_if_false; Flow R cc=False ; Flow J cc=True 0x21ff ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 21ff 0x21ff typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21fc 21fc seq_br_type 3 Unconditional Branch; Flow J 0x21fd seq_branch_adr 21fd 0x21fd typ_c_adr 3b GP04 21fd 21fd seq_br_type 4 Call False; Flow C cc=False 0x32d9 seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 04 GP04 21fe 21fe fiu_mem_start 8 start_wr_if_false; Flow R cc=False ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 21ff 0x21ff typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 21ff 21ff typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 2200 2200 fiu_mem_start 3 start-wr; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 2201 2201 <halt> ; Flow R 2202 ; -------------------------------------------------------------------------------------- 2202 ; 0x03a2 Complete_Type Heap_Access,By_Renaming 2202 ; -------------------------------------------------------------------------------------- 2202 MACRO_Complete_Type_Heap_Access,By_Renaming: 2202 2202 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2202 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2203 2203 ioc_fiubs 0 fiu ; Flow C cc=True 0x32db ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2204 2204 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32d9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2205 2205 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2206 2206 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x2244 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2244 0x2244 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_c_adr 3e GP01 2207 2207 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 2b VR06:0b val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2208 2208 fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 2209 2209 fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 220a 220a fiu_load_tar 1 hold_tar; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 220b 220b fiu_len_fill_lit 41 zero-fill 0x1 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 220c 220c fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 35 VR07:15 val_c_adr 3b GP04 val_frame 7 220d 220d fiu_mem_start 4 continue ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 220e 220e fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 220f 220f ioc_load_wdr 0 typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA val_b_adr 04 GP04 2210 2210 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2211 2211 <halt> ; Flow R 2212 ; -------------------------------------------------------------------------------------- 2212 ; 0x03a1 Complete_Type Heap_Access,By_Constraining 2212 ; -------------------------------------------------------------------------------------- 2212 MACRO_Complete_Type_Heap_Access,By_Constraining: 2212 2212 dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2212 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2213 2213 ioc_fiubs 0 fiu ; Flow C cc=True 0x32db ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2214 2214 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32d9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 10 TOP typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2215 2215 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2216 2216 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2244 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2244 0x2244 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 22 TR01:02 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 2217 2217 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR01:00 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 2218 2218 fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 2219 2219 fiu_mem_start 4 continue ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 221a 221a fiu_load_tar 1 hold_tar; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 221b 221b ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1e TOP - 2 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 221c 221c fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=True 0x32d9 fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_frame b 221d 221d ioc_fiubs 0 fiu ; Flow C cc=#0x0 0x2223 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2223 0x2223 seq_en_micro 0 typ_a_adr 1e TOP - 2 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 221e 221e fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 35 VR07:15 val_frame 7 221f 221f fiu_mem_start 4 continue ioc_load_wdr 0 seq_random 02 ? typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 03 GP03 2220 2220 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 04 GP04 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 2221 2221 ioc_load_wdr 0 typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA val_b_adr 05 GP05 2222 2222 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2223 ; -------------------------------------------------------------------------------------- 2223 ; Comes from: 2223 ; 221d C #0x0 from color 0x2035 2223 ; -------------------------------------------------------------------------------------- 2223 2223 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2224 2224 fiu_mem_start 2 start-rd; Flow J 0x222b ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 222b 0x222b typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2225 2225 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2226 2226 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2227 2227 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2228 2228 seq_br_type 3 Unconditional Branch; Flow J 0x2230 seq_branch_adr 2230 0x2230 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 05 GP05 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2229 2229 seq_br_type 3 Unconditional Branch; Flow J 0x2230 seq_branch_adr 2230 0x2230 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 05 GP05 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 222a 222a fiu_mem_start 2 start-rd; Flow J 0x2238 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2238 0x2238 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 222b 222b <default> 222c 222c fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32d9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1e TOP - 2 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 222d 222d <default> 222e 222e ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32d9 seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 222f 222f fiu_mem_start 2 start-rd; Flow J 0x3274 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3274 0x3274 typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2230 2230 seq_b_timing 1 Latch Condition; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 2231 2231 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2232 0x2232 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1e TOP - 2 typ_b_adr 05 GP05 2232 2232 fiu_mem_start 2 start-rd; Flow C 0x3274 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3274 0x3274 typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 05 GP05 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2233 2233 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 2234 2234 typ_a_adr 1e TOP - 2 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2235 2235 seq_br_type 7 Unconditional Call; Flow C 0x2292 seq_branch_adr 2292 0x2292 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 2236 2236 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2237 0x2237 typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 2237 2237 seq_br_type 7 Unconditional Call; Flow C 0x32a2 seq_branch_adr 32a2 0x32a2 2238 2238 <default> 2239 2239 fiu_len_fill_lit 45 zero-fill 0x5; Flow J 0x2230 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2230 0x2230 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 223a ; -------------------------------------------------------------------------------------- 223a ; 0x03a0 Complete_Type Heap_Access,By_Component_Completion 223a ; -------------------------------------------------------------------------------------- 223a MACRO_Complete_Type_Heap_Access,By_Component_Completion: 223a 223a dispatch_brk_class 4 ; Flow C cc=True 0x32db dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 223a fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 223b 223b fiu_mem_start 4 continue typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 223c 223c ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 223d 223d fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 223e 223e fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 223f 223f seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x2240 seq_br_type f Unconditional Case Call seq_branch_adr 2240 0x2240 seq_en_micro 0 2240 ; -------------------------------------------------------------------------------------- 2240 ; Comes from: 2240 ; 223f C #0x0 from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 2240 ; -------------------------------------------------------------------------------------- 2240 2240 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2241 2241 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2242 2242 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2243 2243 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 2244 2244 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2245 2245 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32db seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 2246 2246 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 2247 2247 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 2248 2248 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 2249 2249 fiu_mem_start 4 continue typ_a_adr 25 TR11:05 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR 224a 224a ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2254 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2254 0x2254 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 224b 224b fiu_load_var 1 hold_var; Flow J cc=True 0x224d fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 224d 0x224d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 224c 224c ioc_fiubs 0 fiu typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 224d 224d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 224e 224e fiu_mem_start 4 continue typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 37 VR06:17 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 6 224f 224f ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2250 2250 fiu_load_var 1 hold_var; Flow J cc=True 0x2252 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2252 0x2252 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2251 2251 ioc_fiubs 0 fiu val_c_adr 37 GP08 val_c_source 0 FIU_BUS 2252 2252 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2253 2253 ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x2247 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2247 0x2247 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 08 GP08 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 08 GP08 2254 2254 fiu_load_var 1 hold_var; Flow J cc=True 0x2256 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2256 0x2256 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2255 2255 ioc_fiubs 0 fiu typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 2256 2256 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2257 2257 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 08 GP08 val_b_adr 37 VR06:17 val_frame 6 2258 ; -------------------------------------------------------------------------------------- 2258 ; Comes from: 2258 ; 1127 C from color 0x1107 2258 ; 11ff C from color 0x114d 2258 ; 1265 C from color 0x1231 2258 ; 126e C from color 0x1231 2258 ; -------------------------------------------------------------------------------------- 2258 2258 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 2259 2259 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 225a 225a fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 225b 225b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2ab4 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_c_adr 36 GP09 val_c_source 0 FIU_BUS 225c 225c fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 08 GP08 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 08 GP08 val_frame 6 225d 225d fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 225e 225e fiu_fill_mode_src 0 ; Flow J cc=False 0x226d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 226d 0x226d seq_cond_sel 65 CROSS_WORD_FIELD~ 225f 225f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2260 2260 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 2261 2261 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA 2262 2262 fiu_fill_mode_src 0 ; Flow J cc=False 0x226f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 226f 0x226f seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 09 GP09 2263 2263 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2264 2264 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2265 2265 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 2266 2266 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x225a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 225a 0x225a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR 2267 2267 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 2268 2268 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 08 GP08 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 08 GP08 val_frame 6 2269 2269 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 226a 226a fiu_fill_mode_src 0 ; Flow J cc=False 0x2271 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2271 0x2271 seq_cond_sel 65 CROSS_WORD_FIELD~ 226b 226b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 226c 226c ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 226d 226d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 226e 226e fiu_fill_mode_src 0 ; Flow J 0x2260 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2260 0x2260 typ_mar_cntl 6 INCREMENT_MAR 226f 226f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2270 2270 fiu_fill_mode_src 0 ; Flow J 0x2264 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2264 0x2264 typ_mar_cntl 6 INCREMENT_MAR 2271 2271 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2272 2272 fiu_fill_mode_src 0 ; Flow J 0x226c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 226c 0x226c typ_mar_cntl 6 INCREMENT_MAR 2273 2273 ioc_load_wdr 0 ; Flow C 0x2ab4 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2274 2274 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2275 2275 fiu_fill_mode_src 0 ; Flow J cc=False 0x2283 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2283 0x2283 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 09 GP09 2276 2276 fiu_fill_mode_src 0 ; Flow J cc=True 0x226c fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 226c 0x226c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 2 DEC_LOOP_COUNTER 2277 2277 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2278 ; -------------------------------------------------------------------------------------- 2278 ; Comes from: 2278 ; 112a C True from color 0x1107 2278 ; 1204 C from color 0x114d 2278 ; 126f C from color 0x1231 2278 ; -------------------------------------------------------------------------------------- 2278 2278 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2279 2279 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 10 227a 227a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32dc fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_source 0 FIU_BUS val_frame 6 227b 227b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32dc fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 08 GP08 val_c_adr 36 GP09 val_c_source 0 FIU_BUS val_frame 6 227c 227c fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 227d 227d fiu_fill_mode_src 0 ; Flow J cc=False 0x2280 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2280 0x2280 seq_cond_sel 65 CROSS_WORD_FIELD~ val_a_adr 08 GP08 227e 227e fiu_fill_mode_src 0 ; Flow J cc=False 0x2273 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2273 0x2273 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 2 DEC_LOOP_COUNTER 227f 227f ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2280 2280 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2281 2281 fiu_fill_mode_src 0 ; Flow J cc=False 0x2273 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2273 0x2273 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 2282 2282 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2283 2283 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2284 2284 fiu_fill_mode_src 0 ; Flow J cc=False 0x2277 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2277 0x2277 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 2285 2285 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2286 ; -------------------------------------------------------------------------------------- 2286 ; Comes from: 2286 ; 1123 C from color 0x1107 2286 ; 11eb C from color 0x114d 2286 ; 1c0d C from color 0x0000 2286 ; 1c15 C from color 0x0000 2286 ; 1e81 C from color 0x0000 2286 ; 1e83 C from color 0x0000 2286 ; 1e8b C from color 0x0000 2286 ; 1e96 C from color 0x0000 2286 ; -------------------------------------------------------------------------------------- 2286 2286 val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2287 2287 fiu_mem_start 2 start-rd; Flow J cc=False 0x228a ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 228a 0x228a seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 2288 2288 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 2289 2289 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 228a 228a seq_b_timing 0 Early Condition; Flow J cc=True 0x228d seq_br_type 1 Branch True seq_branch_adr 228d 0x228d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 228b 228b ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2287 seq_br_type 1 Branch True seq_branch_adr 2287 0x2287 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 228c 228c seq_br_type a Unconditional Return; Flow R val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 228d 228d ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x228c seq_br_type 8 Return True seq_branch_adr 228c 0x228c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 228e ; -------------------------------------------------------------------------------------- 228e ; Comes from: 228e ; 1c13 C from color 0x0000 228e ; 1e89 C from color 0x0000 228e ; 1e98 C from color 0x0000 228e ; 1ead C from color 0x0000 228e ; 1eaf C from color 0x0000 228e ; -------------------------------------------------------------------------------------- 228e 228e seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 228f 228f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x22f3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 22f3 0x22f3 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_rand 2 DEC_LOOP_COUNTER 2290 2290 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x228c seq_br_type 1 Branch True seq_branch_adr 228c 0x228c seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 2291 2291 seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x228e seq_br_type 8 Return True seq_branch_adr 228e 0x228e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 13 ONES val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2292 ; -------------------------------------------------------------------------------------- 2292 ; Comes from: 2292 ; 0506 C from color 0x04fa 2292 ; 11f8 C from color 0x114d 2292 ; 1260 C from color 0x1231 2292 ; 1bdf C from color 0x0a78 2292 ; 1bed C from color 0x0a8c 2292 ; 1bfd C from color 0x0aa0 2292 ; 1c21 C from color 0x0000 2292 ; 1fa8 C from color 0x1f9b 2292 ; 2235 C from color 0x2228 2292 ; -------------------------------------------------------------------------------------- 2292 2292 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2293 0x2293 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 2293 2293 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_rand 2 DEC_LOOP_COUNTER 2294 2294 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x22d8 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 22d8 0x22d8 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2295 2295 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2296 2296 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x229b seq_br_type 0 Branch False seq_branch_adr 229b 0x229b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2297 2297 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x229c fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 229c 0x229c seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2298 2298 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2299 2299 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 229a 229a seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x2292 seq_br_type 8 Return True seq_branch_adr 2292 0x2292 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 09 GP09 229b 229b ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 229c 0x229c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 229c 229c seq_br_type 3 Unconditional Branch; Flow J 0x2292 seq_branch_adr 2292 0x2292 typ_alu_func 13 ONES typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 229d ; -------------------------------------------------------------------------------------- 229d ; Comes from: 229d ; 11ee C from color 0x114d 229d ; 1be1 C from color 0x0a78 229d ; 1bef C from color 0x0a8c 229d ; 1c00 C from color 0x0aa0 229d ; 1c25 C from color 0x0000 229d ; -------------------------------------------------------------------------------------- 229d 229d fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 229e 0x229e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 229e 229e fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 229f 229f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x22d2 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 22d2 0x22d2 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 22a0 22a0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x22a4 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 22a4 0x22a4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 09 GP09 val_alu_func 5 DEC_A_MINUS_B val_b_adr 08 GP08 22a1 22a1 ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 22a2 22a2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x22a5 seq_br_type 1 Branch True seq_branch_adr 22a5 0x22a5 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 22a3 22a3 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x229d seq_br_type 8 Return True seq_branch_adr 229d 0x229d seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 09 GP09 22a4 22a4 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 22a5 0x22a5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 08 GP08 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 22a5 22a5 seq_br_type 3 Unconditional Branch; Flow J 0x229d seq_branch_adr 229d 0x229d typ_alu_func 13 ONES typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 22a6 ; -------------------------------------------------------------------------------------- 22a6 ; Comes from: 22a6 ; 22ae C from color 0x22ae 22a6 ; 22b0 C from color 0x22b0 22a6 ; -------------------------------------------------------------------------------------- 22a6 22a6 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 22a7 22a7 seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU 22a8 22a8 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0e GP0e val_alu_func 1d A_AND_NOT_B val_b_adr 31 VR02:11 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 22a9 22a9 seq_en_micro 0 val_a_adr 0e GP0e val_b_adr 32 VR02:12 val_frame 2 val_rand c START_MULTIPLY 22aa 22aa fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0f GP0f typ_alu_func 1e A_AND_B typ_b_adr 20 TR05:00 typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f 22ab 22ab seq_b_timing 1 Latch Condition; Flow J cc=True 0x22ad seq_br_type 1 Branch True seq_branch_adr 22ad 0x22ad 22ac 22ac fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return 22ad 22ad fiu_load_var 1 hold_var; Flow R fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return 22ae ; -------------------------------------------------------------------------------------- 22ae ; Comes from: 22ae ; 22c4 C from color 0x22bc 22ae ; 22d0 C from color 0x22c6 22ae ; -------------------------------------------------------------------------------------- 22ae 22ae fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x22a6 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 22a6 0x22a6 typ_b_adr 06 GP06 val_a_adr 17 LOOP_COUNTER val_b_adr 2e VR04:0e val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 4 val_rand c START_MULTIPLY 22af 22af ioc_fiubs 0 fiu ; Flow R seq_br_type a Unconditional Return typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 22b0 ; -------------------------------------------------------------------------------------- 22b0 ; Comes from: 22b0 ; 22cf C from color 0x22c6 22b0 ; -------------------------------------------------------------------------------------- 22b0 22b0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x22a6 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 22a6 0x22a6 typ_b_adr 07 GP07 val_a_adr 17 LOOP_COUNTER val_b_adr 2e VR04:0e val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 4 val_rand c START_MULTIPLY 22b1 22b1 ioc_fiubs 0 fiu ; Flow R seq_br_type a Unconditional Return typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22b2 ; -------------------------------------------------------------------------------------- 22b2 ; Comes from: 22b2 ; 22c3 C from color 0x22bc 22b2 ; -------------------------------------------------------------------------------------- 22b2 22b2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val typ_b_adr 07 GP07 val_a_adr 17 LOOP_COUNTER val_b_adr 3f VR02:1f val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 22b3 22b3 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 22b4 22b4 seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU 22b5 22b5 seq_en_micro 0 val_a_adr 0e GP0e val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 22b6 22b6 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU 22b7 22b7 fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_frame 5 22b8 22b8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x22ba seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22ba 0x22ba seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 22b9 22b9 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22ba 22ba fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 22bb 22bb fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22bc ; -------------------------------------------------------------------------------------- 22bc ; Comes from: 22bc ; 11c4 C from color 0x114d 22bc ; 1bdc C from color 0x0a78 22bc ; 1bea C from color 0x0a8c 22bc ; 1bf9 C from color 0x0aa0 22bc ; 1c76 C from color 0x0000 22bc ; -------------------------------------------------------------------------------------- 22bc 22bc ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 22bd 22bd fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22be 0x22be seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22be 22be fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22bf 22bf fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 22c0 22c0 fiu_load_oreg 1 hold_oreg; Flow C 0x22d2 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 22d2 0x22d2 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 22c1 22c1 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 22c2 0x22c2 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 08 GP08 22c2 22c2 seq_br_type 1 Branch True; Flow J cc=True 0x22bd seq_branch_adr 22bd 0x22bd seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 22c3 22c3 ioc_fiubs 2 typ ; Flow C 0x22b2 seq_br_type 7 Unconditional Call seq_branch_adr 22b2 0x22b2 typ_a_adr 17 LOOP_COUNTER val_c_adr 37 GP08 val_c_source 0 FIU_BUS 22c4 22c4 ioc_fiubs 2 typ ; Flow C 0x22ae seq_br_type 7 Unconditional Call seq_branch_adr 22ae 0x22ae typ_a_adr 17 LOOP_COUNTER val_c_adr 37 GP08 val_c_source 0 FIU_BUS 22c5 22c5 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22bd seq_branch_adr 22bd 0x22bd seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22c6 ; -------------------------------------------------------------------------------------- 22c6 ; Comes from: 22c6 ; 11e8 C from color 0x114d 22c6 ; 1bda C from color 0x0a78 22c6 ; 1be8 C from color 0x0a8c 22c6 ; 1bf6 C from color 0x0aa0 22c6 ; 1c71 C from color 0x0000 22c6 ; -------------------------------------------------------------------------------------- 22c6 22c6 ioc_fiubs 1 val typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 22c7 22c7 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22c8 0x22c8 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22c8 22c8 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_rand 2 DEC_LOOP_COUNTER 22c9 22c9 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 22ca 22ca fiu_mem_start 2 start-rd; Flow C cc=True 0x22d8 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 22d8 0x22d8 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 22cb 22cb seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU 22cc 22cc fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 22cd 22cd seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 22ce 0x22ce seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 08 GP08 22ce 22ce seq_br_type 1 Branch True; Flow J cc=True 0x22c7 seq_branch_adr 22c7 0x22c7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 22cf 22cf ioc_fiubs 2 typ ; Flow C 0x22b0 seq_br_type 7 Unconditional Call seq_branch_adr 22b0 0x22b0 typ_a_adr 17 LOOP_COUNTER val_c_adr 37 GP08 val_c_source 0 FIU_BUS 22d0 22d0 ioc_fiubs 2 typ ; Flow C 0x22ae seq_br_type 7 Unconditional Call seq_branch_adr 22ae 0x22ae typ_a_adr 17 LOOP_COUNTER val_c_adr 37 GP08 val_c_source 0 FIU_BUS 22d1 22d1 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22c7 seq_branch_adr 22c7 0x22c7 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22d2 ; -------------------------------------------------------------------------------------- 22d2 ; Comes from: 22d2 ; 229f C from color 0x229d 22d2 ; 22c0 C from color 0x22bc 22d2 ; -------------------------------------------------------------------------------------- 22d2 22d2 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x22d5 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22d5 0x22d5 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 22d3 22d3 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 22d4 22d4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2ab4 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22d5 22d5 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 22d6 22d6 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 37 GP08 val_c_source 0 FIU_BUS 22d7 22d7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2ab4 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22d8 ; -------------------------------------------------------------------------------------- 22d8 ; Comes from: 22d8 ; 2294 C True from color 0x2292 22d8 ; 22ca C True from color 0x22c6 22d8 ; 22e0 C True from color 0x09aa 22d8 ; -------------------------------------------------------------------------------------- 22d8 22d8 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 22d9 22d9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 22da ; -------------------------------------------------------------------------------------- 22da ; Comes from: 22da ; 1c11 C from color 0x0000 22da ; 1e87 C from color 0x0000 22da ; -------------------------------------------------------------------------------------- 22da 22da fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22db 0x22db seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22db 22db seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22dc 22dc fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x22f3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 22f3 0x22f3 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA 22dd 22dd seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22da seq_branch_adr 22da 0x22da seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22de ; -------------------------------------------------------------------------------------- 22de ; Comes from: 22de ; 1c0b C from color 0x0000 22de ; 1e7f C from color 0x0000 22de ; -------------------------------------------------------------------------------------- 22de 22de fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22df 0x22df seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22df 22df seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22e0 22e0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x22d8 fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 22d8 0x22d8 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 22e1 22e1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 22e2 22e2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22e3 22e3 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22de seq_branch_adr 22de 0x22de seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22e4 ; -------------------------------------------------------------------------------------- 22e4 ; Comes from: 22e4 ; 1e94 C from color 0x0000 22e4 ; -------------------------------------------------------------------------------------- 22e4 22e4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22e5 0x22e5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22e5 22e5 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x22ea seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22ea 0x22ea seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 22e6 22e6 fiu_len_fill_lit 5f zero-fill 0x1f fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22e7 22e7 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 22e8 22e8 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2ab4 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22e9 22e9 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22e4 seq_branch_adr 22e4 0x22e4 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22ea 22ea fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22eb 22eb fiu_fill_mode_src 0 ; Flow J 0x22e7 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 22e7 0x22e7 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 22ec ; -------------------------------------------------------------------------------------- 22ec ; Comes from: 22ec ; 1e9a C from color 0x0000 22ec ; -------------------------------------------------------------------------------------- 22ec 22ec fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 22ed 0x22ed seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 22ed 22ed fiu_mem_start a start_continue_if_false; Flow J cc=False 0x22f0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22f0 0x22f0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 22ee 22ee fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x22f3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 22f3 0x22f3 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22ef 22ef seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22ec seq_branch_adr 22ec 0x22ec seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22f0 22f0 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 22f1 22f1 fiu_fill_mode_src 0 ; Flow C 0x22f3 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 22f3 0x22f3 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA 22f2 22f2 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x22ec seq_branch_adr 22ec 0x22ec seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 19 X_XOR_B typ_b_adr 08 GP08 22f3 ; -------------------------------------------------------------------------------------- 22f3 ; Comes from: 22f3 ; 228f C from color 0x1bae 22f3 ; 22dc C from color 0x09aa 22f3 ; 22ee C from color 0x09aa 22f3 ; 22f1 C from color 0x09aa 22f3 ; -------------------------------------------------------------------------------------- 22f3 22f3 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x22f5 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 22f5 0x22f5 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 22f4 22f4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2ab4 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22f5 22f5 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 22f6 22f6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2ab4 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 22f7 22f7 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 5 val_rand a PASS_B_HIGH 22f8 22f8 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 3d VR06:1d val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 22f9 22f9 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x231d fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 231d 0x231d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR00:01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 22fa 22fa fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=#0x0 0x22fd fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 22fd 0x22fd seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 0e GP0e val_rand a PASS_B_HIGH 22fb 22fb fiu_mem_start 3 start-wr fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 22fc 22fc ioc_load_wdr 0 ; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR05:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 39 VR02:19 val_frame 2 22fd ; -------------------------------------------------------------------------------------- 22fd ; Comes from: 22fd ; 22fa C #0x0 from color 0x0000 22fd ; -------------------------------------------------------------------------------------- 22fd 22fd seq_br_type 3 Unconditional Branch; Flow J 0x3432 seq_branch_adr 3432 0x3432 seq_en_micro 0 seq_random 05 ? typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 22fe 22fe seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 22ff 22ff seq_br_type 3 Unconditional Branch; Flow J 0x2301 seq_branch_adr 2301 0x2301 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 06 Pop_stack+? 2300 2300 seq_br_type 3 Unconditional Branch; Flow J 0x2301 seq_branch_adr 2301 0x2301 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 seq_random 06 Pop_stack+? 2301 2301 seq_br_type 0 Branch False; Flow J cc=False 0x231f seq_branch_adr 231f 0x231f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 2302 2302 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 2303 2303 ioc_tvbs 2 fiu+val; Flow C cc=True 0x2309 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2309 0x2309 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 2304 2304 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2305 0x2305 seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 0b GP0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 2305 2305 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 0e GP0e val_frame 5 val_rand a PASS_B_HIGH 2306 2306 ioc_load_wdr 0 seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 0f GP0f val_b_adr 0f GP0f 2307 2307 ioc_adrbs 2 typ ; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_mar_cntl c LOAD_MAR_QUEUE 2308 2308 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 2309 2309 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2308 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2308 0x2308 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 05 GP05 val_alu_func 0 PASS_A val_b_adr 0e GP0e val_rand a PASS_B_HIGH 230a 230a ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS 230b 230b seq_br_type 0 Branch False; Flow J cc=False 0x231e seq_branch_adr 231e 0x231e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 230c 230c fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR val_a_adr 3a VR12:1a val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 12 230d 230d fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 24 VR05:04 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 5 230e 230e ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2314 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2314 0x2314 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0c GP0c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 230f 230f fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x231e fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 231e 0x231e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_mar_cntl 1 RESTORE_RDR 2310 2310 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x230e fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 230e 0x230e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0d GP0d val_alu_func 1c DEC_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU 2311 2311 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x231e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 4c fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 231e 0x231e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 2312 2312 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 2313 2313 fiu_load_tar 1 hold_tar; Flow C 0x2ab4 fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_b_adr 05 GP05 typ_mar_cntl c LOAD_MAR_QUEUE 2314 2314 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x231e fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 231e 0x231e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_a_adr 0c GP0c 2315 2315 fiu_mem_start 3 start-wr ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 7 2316 2316 ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 0d GP0d val_a_adr 21 VR07:01 val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 7 2317 2317 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x231c fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 231c 0x231c seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 0d GP0d val_alu_func 0 PASS_A val_b_adr 0e GP0e val_rand a PASS_B_HIGH 2318 2318 fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2319 2319 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x231e fiu_load_tar 1 hold_tar fiu_mem_start 7 start_wr_if_true fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 231e 0x231e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 231a 231a ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_random 06 Pop_stack+? val_b_adr 0d GP0d 231b 231b ioc_adrbs 2 typ ; Flow R seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_mar_cntl c LOAD_MAR_QUEUE 231c ; -------------------------------------------------------------------------------------- 231c ; Comes from: 231c ; 2317 C True from color 0x0000 231c ; -------------------------------------------------------------------------------------- 231c 231c seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 1 231d 231d fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x231f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 231f 0x231f seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS 231e 231e seq_br_type 3 Unconditional Branch; Flow J 0x231f seq_branch_adr 231f 0x231f seq_en_micro 0 seq_random 06 Pop_stack+? 231f 231f fiu_mem_start 2 start-rd; Flow C 0x332e fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2320 2320 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x22f7 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 22f7 0x22f7 typ_a_adr 05 GP05 typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 05 GP05 val_alu_func 0 PASS_A 2321 2321 <halt> ; Flow R 2322 ; -------------------------------------------------------------------------------------- 2322 ; 0x0358 Declare_Type Array,Incomplete 2322 ; -------------------------------------------------------------------------------------- 2322 MACRO_Declare_Type_Array,Incomplete: 2322 2322 dispatch_brk_class 4 ; Flow J 0x2323 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2322 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2323 0x2323 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2323 2323 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 30 VR05:10 val_frame 5 val_rand 2 DEC_LOOP_COUNTER 2324 2324 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 41 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 17 LOOP_COUNTER val_rand 1 INC_LOOP_COUNTER 2325 2325 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 3b VR02:1b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2326 2326 fiu_len_fill_lit 53 zero-fill 0x13 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2327 2327 fiu_mem_start 4 continue fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 3b VR02:1b val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2328 2328 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J 0x2329 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2329 0x2329 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 24 TR09:04 typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 val_rand 2 DEC_LOOP_COUNTER 2329 2329 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x232d fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 232d 0x232d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS 232a 232a fiu_mem_start 4 continue; Flow J cc=False 0x2329 ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2329 0x2329 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_latch 1 typ_b_adr 32 TR02:12 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 28 VR11:08 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 11 val_rand 2 DEC_LOOP_COUNTER 232b 232b seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 232c 232c fiu_mem_start 3 start-wr; Flow J 0x2329 seq_br_type 3 Unconditional Branch seq_branch_adr 2329 0x2329 232d 232d seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 232e 232e fiu_mem_start 3 start-wr val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 32 VR06:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 232f 232f fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 28 VR11:08 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 11 val_rand 2 DEC_LOOP_COUNTER 2330 2330 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2330 fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2330 0x2330 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 37 VR06:17 val_frame 6 2331 2331 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 29 VR11:09 val_frame 11 2332 2332 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 2333 0x2333 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2333 2333 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 2334 0x2334 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2334 2334 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 2335 2335 <halt> ; Flow R 2336 ; -------------------------------------------------------------------------------------- 2336 ; 0x0359 Declare_Type Array,Incomplete,Visible 2336 ; -------------------------------------------------------------------------------------- 2336 MACRO_Declare_Type_Array,Incomplete,Visible: 2336 2336 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2336 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2337 2337 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2323 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2323 0x2323 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 2338 ; -------------------------------------------------------------------------------------- 2338 ; 0x034b Declare_Type Array,Incomplete,Bounds_With_Object 2338 ; -------------------------------------------------------------------------------------- 2338 MACRO_Declare_Type_Array,Incomplete,Bounds_With_Object: 2338 2338 dispatch_brk_class 4 ; Flow J 0x2323 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2338 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2323 0x2323 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2339 2339 <halt> ; Flow R 233a ; -------------------------------------------------------------------------------------- 233a ; 0x034c Declare_Type Array,Incomplete,Visible,Bounds_With_Object 233a ; -------------------------------------------------------------------------------------- 233a MACRO_Declare_Type_Array,Incomplete,Visible,Bounds_With_Object: 233a 233a dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 233a seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 233b 233b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2323 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2323 0x2323 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR00:02 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 233c ; -------------------------------------------------------------------------------------- 233c ; 0x0340 Complete_Type Array,By_Component_Completion 233c ; -------------------------------------------------------------------------------------- 233c MACRO_Complete_Type_Array,By_Component_Completion: 233c 233c dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 233c fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_lit 2 typ_frame a typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 233d 233d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS 233e 233e fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 233f 233f seq_b_timing 0 Early Condition; Flow J cc=True 0x2340 ; Flow J cc=#0x0 0x2340 seq_br_type b Case False seq_branch_adr 2340 0x2340 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3e GP01 2340 2340 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2341 2341 fiu_len_fill_lit 45 zero-fill 0x5; Flow J 0x2344 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2344 0x2344 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2342 2342 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2343 2343 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 2344 2344 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 3f GP00 2345 2345 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 2b VR06:0b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2346 2346 ioc_tvbs 2 fiu+val typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1e A_AND_B val_b_adr 2d VR11:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 2347 2347 val_alu_func 1b A_OR_B val_b_adr 33 VR06:13 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 2348 2348 seq_br_type 3 Unconditional Branch; Flow J 0x2349 seq_branch_adr 2349 0x2349 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 2349 2349 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 234a 234a ioc_load_wdr 0 234b 234b fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 234c 234c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ab4 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 234d 234d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 12 VAL.ALU_MIDDLE_ZERO(late) seq_latch 1 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_rand c START_MULTIPLY 234e 234e seq_b_timing 1 Latch Condition; Flow J cc=True 0x2354 seq_br_type 1 Branch True seq_branch_adr 2354 0x2354 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand a PASS_B_HIGH 234f 234f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2350 2350 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2351 2351 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2353 seq_br_type 1 Branch True seq_branch_adr 2353 0x2353 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A 2352 2352 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2354 seq_br_type 1 Branch True seq_branch_adr 2354 0x2354 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2353 2353 ioc_tvbs 1 typ+fiu; Flow J 0x2354 seq_br_type 3 Unconditional Branch seq_branch_adr 2354 0x2354 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 2354 2354 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2358 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2358 0x2358 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2355 2355 <default> 2356 2356 ioc_tvbs c mem+mem+csa+dummy val_a_adr 2b VR06:0b val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 val_rand 2 DEC_LOOP_COUNTER 2357 2357 seq_br_type 3 Unconditional Branch; Flow J 0x2349 seq_branch_adr 2349 0x2349 val_alu_func 1b A_OR_B val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2358 2358 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 3b fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 01 GP01 2359 2359 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert 235a 235a fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 235b 235b ioc_load_wdr 0 ; Flow J 0x2340 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2340 0x2340 val_b_adr 02 GP02 235c ; -------------------------------------------------------------------------------------- 235c ; 0x0342 Complete_Type Array,By_Renaming 235c ; -------------------------------------------------------------------------------------- 235c MACRO_Complete_Type_Array,By_Renaming: 235c 235c dispatch_brk_class 4 ; Flow C cc=True 0x32db dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 235c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 38 GP07 val_c_source 0 FIU_BUS 235d 235d fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 235e 235e fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR 235f 235f fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x32d7 fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 2 typ_frame a typ_rand 9 PASS_A_HIGH val_c_adr 39 GP06 val_c_source 0 FIU_BUS 2360 2360 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 2361 2361 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand e CHECK_CLASS_SYSTEM_B 2362 2362 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=True 0x32db fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2363 2363 fiu_mem_start 2 start-rd; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2364 2364 fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2365 2365 fiu_mem_start 4 continue; Flow C cc=True 0x32a9 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR 2366 2366 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 2367 2367 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 2368 2368 fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 2369 2369 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 236a 236a fiu_mem_start 4 continue typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 236b 236b ioc_load_wdr 0 ; Flow J cc=True 0x2371 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2371 0x2371 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 35 TR07:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 236c 236c fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS 236d 236d fiu_load_oreg 1 hold_oreg fiu_mem_start 4 continue fiu_offs_lit 40 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 236e 236e ioc_load_wdr 0 ; Flow J cc=False 0x2369 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2369 0x2369 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 05 GP05 typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 05 GP05 236f 236f seq_b_timing 1 Latch Condition; Flow C cc=True 0x2374 seq_br_type 5 Call True seq_branch_adr 2374 0x2374 typ_csa_cntl 3 POP_CSA 2370 2370 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2371 2371 fiu_mem_start 3 start-wr; Flow J cc=False 0x2373 fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2373 0x2373 seq_cond_sel 64 OFFSET_REGISTER_???? seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2372 2372 fiu_load_oreg 1 hold_oreg; Flow J 0x236e fiu_mem_start 4 continue fiu_offs_lit 40 seq_br_type 3 Unconditional Branch seq_branch_adr 236e 0x236e typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2373 2373 fiu_mem_start 4 continue; Flow J 0x236e seq_br_type 3 Unconditional Branch seq_branch_adr 236e 0x236e seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2374 ; -------------------------------------------------------------------------------------- 2374 ; Comes from: 2374 ; 236f C True from color 0x2360 2374 ; -------------------------------------------------------------------------------------- 2374 2374 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2375 2375 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2376 2376 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 2377 2377 seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x2374 seq_br_type 8 Return True seq_branch_adr 2374 0x2374 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2378 ; -------------------------------------------------------------------------------------- 2378 ; 0x0305 Complete_Type Variant_Record,By_Constraining_Incomplete 2378 ; -------------------------------------------------------------------------------------- 2378 MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete: 2378 2378 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2378 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 28 TR08:08 typ_alu_func 1 A_PLUS_B typ_b_adr 1f TOP - 1 typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 9 PASS_A_HIGH 2379 2379 fiu_mem_start 4 continue ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 237a 237a fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 237b 237b fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 2f TR13:0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 13 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU 237c 237c ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 237d 237d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 39 VR13:19 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 13 237e 237e fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 2 start-rd fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 36 VR05:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 237f 237f fiu_mem_start 4 continue typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2380 2380 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 24 TR09:04 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 2381 2381 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2382 2382 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32d9 seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 39 VR13:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 2383 2383 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2384 2384 seq_b_timing 0 Early Condition; Flow J cc=True 0x2388 seq_br_type 1 Branch True seq_branch_adr 2388 0x2388 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 07 GP07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2385 2385 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2387 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 2387 0x2387 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1e TOP - 2 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 2386 2386 seq_br_type 3 Unconditional Branch; Flow J 0x2388 seq_branch_adr 2388 0x2388 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2387 2387 ioc_tvbs 2 fiu+val; Flow C cc=False 0x32dd seq_br_type 4 Call False seq_branch_adr 32dd 0x32dd seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2388 2388 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val val_a_adr 17 LOOP_COUNTER 2389 2389 seq_br_type 7 Unconditional Call; Flow C 0x24b2 seq_branch_adr 24b2 0x24b2 typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 36 GP09 val_c_mux_sel 2 ALU 238a 238a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 238b 238b fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 238c 238c ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 3c GP03 val_c_mux_sel 2 ALU 238d 238d typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 238e 238e fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER typ_rand d SET_PASS_PRIVACY_BIT 238f 238f fiu_len_fill_lit 78 zero-fill 0x38; Flow C 0x239e fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 239e 0x239e typ_a_adr 14 ZEROS 2390 2390 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 2391 2391 fiu_mem_start 4 continue typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2392 2392 ioc_load_wdr 0 ; Flow C 0x23a1 seq_br_type 7 Unconditional Call seq_branch_adr 23a1 0x23a1 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2393 2393 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value 2394 2394 ioc_tvbs 1 typ+fiu val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2395 2395 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_en_micro 0 2396 2396 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 2397 2397 ioc_fiubs 0 fiu ; Flow J 0x2398 seq_br_type 2 Push (branch address) seq_branch_adr 2399 0x2399 seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 2398 2398 seq_br_type 3 Unconditional Branch; Flow J 0x23b1 seq_branch_adr 23b1 0x23b1 seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2399 2399 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 239a 239a ioc_load_wdr 0 239b 239b ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 06 GP06 239c 239c seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN 239d 239d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 239e ; -------------------------------------------------------------------------------------- 239e ; Comes from: 239e ; 238f C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 239e ; -------------------------------------------------------------------------------------- 239e 239e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value typ_b_adr 22 TR02:02 typ_frame 2 239f 239f fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 23a0 23a0 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 0f GP0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU 23a1 ; -------------------------------------------------------------------------------------- 23a1 ; Comes from: 23a1 ; 2392 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 23a1 ; -------------------------------------------------------------------------------------- 23a1 23a1 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 23a2 0x23a2 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 23a2 23a2 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 23a3 23a3 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 23a4 23a4 ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 23a5 23a5 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x241f ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 241f 0x241f seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 23a6 23a6 <default> 23a7 23a7 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x329e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 23a8 23a8 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 23a9 23a9 seq_b_timing 1 Latch Condition; Flow J cc=True 0x23ac seq_br_type 1 Branch True seq_branch_adr 23ac 0x23ac seq_cond_sel 56 SEQ.LATCHED_COND seq_latch 1 23aa 23aa fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 23ab 23ab ioc_load_wdr 0 ; Flow J 0x23a1 seq_br_type 3 Unconditional Branch seq_branch_adr 23a1 0x23a1 typ_b_adr 2b TR08:0b typ_frame 8 val_b_adr 05 GP05 23ac 23ac fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 23ad 23ad <default> 23ae 23ae fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 23af 23af ioc_load_wdr 0 ; Flow J 0x23a1 seq_br_type 3 Unconditional Branch seq_branch_adr 23a1 0x23a1 seq_en_micro 0 typ_b_adr 06 GP06 val_b_adr 0f GP0f 23b0 23b0 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 23b1 23b1 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 23b2 0x23b2 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 23b2 23b2 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 23b3 23b3 fiu_mem_start 3 start-wr; Flow J 0x23b0 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 23b0 0x23b0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 23b4 23b4 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 23b5 23b5 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 23b6 0x23b6 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 23b6 23b6 seq_br_type 2 Push (branch address); Flow J 0x23b7 seq_branch_adr 23b4 0x23b4 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 23b7 23b7 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x23bc fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 23bc 0x23bc val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 23b8 23b8 seq_br_type 7 Unconditional Call; Flow C 0x23c0 seq_branch_adr 23c0 0x23c0 23b9 23b9 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 23ba 23ba seq_br_type 3 Unconditional Branch; Flow J 0x23b1 seq_branch_adr 23b1 0x23b1 23bb 23bb fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 23bc 23bc fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x23be ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 23be 0x23be seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 3b VR08:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 8 val_rand 2 DEC_LOOP_COUNTER 23bd 23bd ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x23bb seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 23bb 0x23bb seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 2d TR09:0d typ_frame 9 val_b_adr 0f GP0f 23be ; -------------------------------------------------------------------------------------- 23be ; Comes from: 23be ; 23bc C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 23be ; -------------------------------------------------------------------------------------- 23be 23be seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 23bf 23bf fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return seq_en_micro 0 23c0 ; -------------------------------------------------------------------------------------- 23c0 ; Comes from: 23c0 ; 23b8 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 23c0 ; 23eb C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 23c0 ; 240f C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 23c0 ; 241a C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 23c0 ; -------------------------------------------------------------------------------------- 23c0 23c0 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 23c1 23c1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 28 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var 23c2 23c2 ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 23c3 23c3 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 23c4 23c4 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 23c5 0x23c5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 23c5 23c5 seq_br_type 2 Push (branch address); Flow J 0x23c6 seq_branch_adr 23c3 0x23c3 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 23c6 23c6 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 23c7 23c7 seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 23c8 0x23c8 23c8 23c8 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_c_adr 3a GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3a GP05 val_frame 4 23c9 23c9 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 05 GP05 typ_c_lit 1 typ_frame c val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 23ca 23ca ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32dd seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 9 PASS_A_HIGH val_a_adr 01 GP01 val_alu_func 1c DEC_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 23cb 23cb fiu_mem_start 2 start-rd; Flow J cc=True 0x23df ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 23df 0x23df typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 23cc 23cc typ_a_adr 09 GP09 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 23cd 23cd fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 23ce 23ce fiu_load_tar 1 hold_tar; Flow C 0x326f fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 23cf 23cf fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 23d0 23d0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 30 GP0f val_c_source 0 FIU_BUS 23d1 23d1 ioc_load_wdr 0 ; Flow C cc=True 0x32dd ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 23d2 23d2 fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f 23d3 23d3 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x23d7 seq_br_type 1 Branch True seq_branch_adr 23d7 0x23d7 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 23d4 23d4 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 23d5 23d5 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU 23d6 23d6 fiu_load_var 1 hold_var; Flow J 0x23e3 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 23e3 0x23e3 seq_en_micro 0 val_a_adr 0f GP0f 23d7 23d7 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x23dd ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 23dd 0x23dd seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 0f GP0f 23d8 23d8 fiu_mem_start 4 continue typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 23d9 23d9 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x23dc seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 23dc 0x23dc seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 23da 23da ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x23d7 seq_br_type 1 Branch True seq_branch_adr 23d7 0x23d7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_frame 6 23db 23db seq_br_type 3 Unconditional Branch; Flow J 0x23d4 seq_branch_adr 23d4 0x23d4 seq_en_micro 0 23dc 23dc fiu_len_fill_lit 7d zero-fill 0x3d; Flow J 0x23e3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 23e3 0x23e3 seq_en_micro 0 23dd ; -------------------------------------------------------------------------------------- 23dd ; Comes from: 23dd ; 23d7 C True from color 0x23c4 23dd ; -------------------------------------------------------------------------------------- 23dd 23dd seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 23de 23de fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 23df 23df fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 23e0 23e0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 23e1 23e1 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32d9 seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 23e2 23e2 fiu_load_tar 1 hold_tar; Flow C 0x326f fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 23e3 23e3 ioc_tvbs 1 typ+fiu val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 23e4 23e4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x23e7 seq_br_type 5 Call True seq_branch_adr 23e7 0x23e7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 3b VR02:1b val_frame 2 23e5 23e5 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 05 GP05 23e6 23e6 seq_br_type a Unconditional Return; Flow R 23e7 ; -------------------------------------------------------------------------------------- 23e7 ; Comes from: 23e7 ; 23e4 C True from color 0x23c4 23e7 ; -------------------------------------------------------------------------------------- 23e7 23e7 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 23e8 23e8 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 23e9 0x23e9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 23e9 23e9 seq_br_type 2 Push (branch address); Flow J 0x23ea seq_branch_adr 23e8 0x23e8 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 23ea 23ea fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x23bc fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 23bc 0x23bc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 7 23eb 23eb seq_br_type 7 Unconditional Call; Flow C 0x23c0 seq_branch_adr 23c0 0x23c0 23ec 23ec fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 23ed 23ed seq_b_timing 1 Latch Condition; Flow J cc=True 0x23c3 seq_br_type 1 Branch True seq_branch_adr 23c3 0x23c3 23ee 23ee typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 1 INC_LOOP_COUNTER 23ef 23ef seq_br_type 3 Unconditional Branch; Flow J 0x23c3 seq_branch_adr 23c3 0x23c3 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 23f0 ; -------------------------------------------------------------------------------------- 23f0 ; 0x0304 Complete_Type Variant_Record,By_Completing_Constraint 23f0 ; -------------------------------------------------------------------------------------- 23f0 MACRO_Complete_Type_Variant_Record,By_Completing_Constraint: 23f0 23f0 dispatch_brk_class 4 ; Flow C cc=True 0x32db dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 23f0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 3c GP03 val_c_source 0 FIU_BUS 23f1 23f1 fiu_mem_start 4 continue typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 4 23f2 23f2 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 23f3 23f3 fiu_load_tar 1 hold_tar; Flow C cc=False 0x32d9 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 23f4 23f4 fiu_len_fill_lit 53 zero-fill 0x13 fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 30 GP0f val_c_source 0 FIU_BUS 23f5 23f5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32db fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 23f6 23f6 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_mem_start 2 start-rd fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 23f7 23f7 fiu_mem_start 4 continue; Flow C cc=True 0x32d9 ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 30 TR05:10 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 23f8 23f8 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL 23f9 23f9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 23fa 23fa ioc_tvbs 2 fiu+val typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 23fb 23fb seq_br_type 7 Unconditional Call; Flow C 0x24b2 seq_branch_adr 24b2 0x24b2 val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 23fc 23fc fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val val_b_adr 09 GP09 23fd 23fd fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 23fe 23fe fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 23ff 23ff fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2400 2400 ioc_tvbs 2 fiu+val; Flow J cc=True 0x2412 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2412 0x2412 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 2401 2401 fiu_load_var 1 hold_var; Flow C 0x23b1 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 23b1 0x23b1 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2402 2402 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value 2403 2403 ioc_fiubs 0 fiu ; Flow C 0x240c seq_br_type 7 Unconditional Call seq_branch_adr 240c 0x240c typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2404 2404 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 08 GP08 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 2405 2405 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 2406 2406 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 2407 2407 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 01 GP01 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 2408 2408 ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 10 TOP val_c_adr 38 GP07 val_c_source 0 FIU_BUS 2409 2409 ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 06 GP06 240a 240a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x25de seq_br_type 1 Branch True seq_branch_adr 25de 0x25de seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 30 TR05:10 typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 5 240b 240b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 240c 240c fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 240d 0x240d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 240d 240d seq_br_type 2 Push (branch address); Flow J 0x240e seq_branch_adr 240c 0x240c seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 240e 240e fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x23bc fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 23bc 0x23bc val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 240f 240f seq_br_type 7 Unconditional Call; Flow C 0x23c0 seq_branch_adr 23c0 0x23c0 2410 2410 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 2411 2411 seq_br_type 3 Unconditional Branch; Flow J 0x23b1 seq_branch_adr 23b1 0x23b1 2412 2412 fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x2413 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 2404 0x2404 typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2413 2413 ioc_tvbs 1 typ+fiu val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2414 2414 fiu_load_var 1 hold_var; Flow C 0x23c3 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 23c3 0x23c3 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2415 2415 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value 2416 2416 ioc_fiubs 0 fiu ; Flow J 0x2417 seq_br_type 3 Unconditional Branch seq_branch_adr 2417 0x2417 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 4 2417 2417 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2418 0x2418 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 2418 2418 seq_br_type 2 Push (branch address); Flow J 0x2419 seq_branch_adr 23e8 0x23e8 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 2419 2419 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x23bc fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 23bc 0x23bc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 7 241a 241a seq_br_type 7 Unconditional Call; Flow C 0x23c0 seq_branch_adr 23c0 0x23c0 241b 241b fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 241c 241c seq_b_timing 1 Latch Condition; Flow J cc=True 0x23c3 seq_br_type 1 Branch True seq_branch_adr 23c3 0x23c3 241d 241d typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 1 INC_LOOP_COUNTER 241e 241e seq_br_type 3 Unconditional Branch; Flow J 0x23c3 seq_branch_adr 23c3 0x23c3 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 241f ; -------------------------------------------------------------------------------------- 241f ; Comes from: 241f ; 23a5 C True from color 0x23a1 241f ; -------------------------------------------------------------------------------------- 241f 241f seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 2420 2420 fiu_mem_start 2 start-rd; Flow R seq_br_type a Unconditional Return 2421 2421 <halt> ; Flow R 2422 ; -------------------------------------------------------------------------------------- 2422 ; 0x031c Declare_Type Variant_Record,Constrained,Visible 2422 ; -------------------------------------------------------------------------------------- 2422 MACRO_Declare_Type_Variant_Record,Constrained,Visible: 2422 2422 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2422 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2423 2423 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2425 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2425 0x2425 seq_int_reads 6 CONTROL TOP typ_a_adr 28 TR08:08 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 9 PASS_A_HIGH val_a_adr 22 VR06:02 val_frame 6 2424 ; -------------------------------------------------------------------------------------- 2424 ; 0x031b Declare_Type Variant_Record,Constrained 2424 ; -------------------------------------------------------------------------------------- 2424 MACRO_Declare_Type_Variant_Record,Constrained: 2424 2424 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2424 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 28 TR08:08 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 9 PASS_A_HIGH val_a_adr 39 VR02:19 val_frame 2 2425 2425 fiu_mem_start 4 continue ioc_fiubs 0 fiu typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME 2426 2426 fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 29 TR08:09 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2427 2427 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2428 2428 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2429 2429 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 36 VR05:16 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 242a 242a seq_b_timing 0 Early Condition; Flow J cc=True 0x242e seq_br_type 1 Branch True seq_branch_adr 242e 0x242e seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 242b 242b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x242d fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 242d 0x242d seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 242c 242c seq_br_type 3 Unconditional Branch; Flow J 0x242e seq_branch_adr 242e 0x242e val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 242d 242d ioc_tvbs 2 fiu+val; Flow C cc=False 0x32dd seq_br_type 4 Call False seq_branch_adr 32dd 0x32dd seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 242e 242e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 val_a_adr 17 LOOP_COUNTER 242f 242f seq_br_type 7 Unconditional Call; Flow C 0x24b2 seq_branch_adr 24b2 0x24b2 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2430 2430 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2431 2431 fiu_len_fill_lit 78 zero-fill 0x38 fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2432 2432 ioc_fiubs 0 fiu ; Flow J cc=True 0x2450 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2450 0x2450 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2433 2433 seq_br_type 7 Unconditional Call; Flow C 0x243b seq_branch_adr 243b 0x243b typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2434 2434 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 2435 2435 ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2436 2436 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 2437 2437 ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 06 GP06 2438 2438 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3e TR02:1e typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 2439 2439 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 06 GP06 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 243a 243a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 243b ; -------------------------------------------------------------------------------------- 243b ; Comes from: 243b ; 2433 C from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 243b ; 2451 C from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 243b ; -------------------------------------------------------------------------------------- 243b 243b fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 17 LOOP_COUNTER typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 243c 243c fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 14 ZEROS val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 243d 243d fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 243e 243e fiu_mem_start a start_continue_if_false typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 243f 243f fiu_load_var 1 hold_var; Flow C 0x2445 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 2445 0x2445 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_b_adr 02 GP02 2440 2440 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2441 2441 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 31 GP0e val_c_source 0 FIU_BUS 2442 2442 seq_br_type 7 Unconditional Call; Flow C 0x2454 seq_branch_adr 2454 0x2454 seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0f GP0f val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2443 2443 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value 2444 2444 ioc_fiubs 0 fiu ; Flow J 0x2476 seq_br_type 3 Unconditional Branch seq_branch_adr 2476 0x2476 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2445 ; -------------------------------------------------------------------------------------- 2445 ; Comes from: 2445 ; 243f C from color 0x243b 2445 ; -------------------------------------------------------------------------------------- 2445 2445 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2446 0x2446 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2446 2446 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2447 2447 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2448 2448 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 2449 2449 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x329e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 06 GP06 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 244a 244a fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x2482 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2482 0x2482 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 244b 244b seq_b_timing 1 Latch Condition; Flow J cc=True 0x244e seq_br_type 1 Branch True seq_branch_adr 244e 0x244e seq_cond_sel 56 SEQ.LATCHED_COND seq_latch 1 typ_a_adr 2b TR08:0b typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 8 244c 244c fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE 244d 244d ioc_load_wdr 0 ; Flow J 0x2445 seq_br_type 3 Unconditional Branch seq_branch_adr 2445 0x2445 typ_b_adr 06 GP06 val_b_adr 05 GP05 244e 244e fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 244f 244f fiu_mem_start 3 start-wr; Flow J 0x244d ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 244d 0x244d typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2450 2450 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2451 2451 ioc_tvbs 1 typ+fiu; Flow C 0x243b seq_br_type 7 Unconditional Call seq_branch_adr 243b 0x243b typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2452 2452 fiu_mem_start 3 start-wr; Flow C cc=True 0x32dd ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 0 PASS_A 2453 2453 ioc_load_wdr 0 ; Flow J 0x2434 seq_br_type 3 Unconditional Branch seq_branch_adr 2434 0x2434 typ_b_adr 01 GP01 val_b_adr 02 GP02 2454 ; -------------------------------------------------------------------------------------- 2454 ; Comes from: 2454 ; 2442 C from color 0x243b 2454 ; -------------------------------------------------------------------------------------- 2454 2454 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2455 0x2455 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2455 2455 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 2456 2456 fiu_load_var 1 hold_var; Flow C cc=True 0x2482 fiu_mem_start 8 start_wr_if_false fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2482 0x2482 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2457 2457 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2454 seq_br_type 1 Branch True seq_branch_adr 2454 0x2454 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3a GP05 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_frame 7 2458 2458 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 05 GP05 typ_c_lit 1 typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 2459 2459 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32dd seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 9 PASS_A_HIGH val_a_adr 01 GP01 val_alu_func 1c DEC_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 245a 245a fiu_mem_start 2 start-rd; Flow J cc=True 0x246e ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 246e 0x246e typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 245b 245b typ_a_adr 09 GP09 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 245c 245c fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 245d 245d fiu_load_tar 1 hold_tar; Flow C 0x326f fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 245e 245e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 245f 245f fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2460 2460 ioc_load_wdr 0 ; Flow C cc=True 0x32dd ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2461 2461 fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f 2462 2462 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2466 seq_br_type 1 Branch True seq_branch_adr 2466 0x2466 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 2463 2463 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 2464 2464 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2465 2465 fiu_load_var 1 hold_var; Flow J 0x2472 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2472 0x2472 seq_en_micro 0 val_a_adr 0f GP0f 2466 2466 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x246c ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 246c 0x246c seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 0f GP0f 2467 2467 fiu_mem_start 4 continue typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2468 2468 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x246b seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 246b 0x246b seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 2469 2469 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2466 seq_br_type 1 Branch True seq_branch_adr 2466 0x2466 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_frame 6 246a 246a seq_br_type 3 Unconditional Branch; Flow J 0x2463 seq_branch_adr 2463 0x2463 seq_en_micro 0 246b 246b fiu_len_fill_lit 7d zero-fill 0x3d; Flow J 0x2472 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2472 0x2472 seq_en_micro 0 246c ; -------------------------------------------------------------------------------------- 246c ; Comes from: 246c ; 2466 C True from color 0x0000 246c ; -------------------------------------------------------------------------------------- 246c 246c seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 246d 246d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 246e 246e fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 246f 246f fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 2470 2470 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x32d9 seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 2471 2471 fiu_load_tar 1 hold_tar; Flow C 0x326f fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2472 2472 ioc_tvbs 1 typ+fiu; Flow J 0x2473 seq_br_type 2 Push (branch address) seq_branch_adr 2454 0x2454 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2473 2473 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2475 seq_br_type 5 Call True seq_branch_adr 2475 0x2475 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 3b VR02:1b val_frame 2 2474 2474 fiu_mem_start 3 start-wr; Flow J 0x332e ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 332e 0x332e typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 05 GP05 2475 ; -------------------------------------------------------------------------------------- 2475 ; Comes from: 2475 ; 2473 C True from color 0x0000 2475 ; -------------------------------------------------------------------------------------- 2475 2475 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2476 2476 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2477 0x2477 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 2477 2477 seq_br_type 2 Push (branch address); Flow J 0x2478 seq_branch_adr 2476 0x2476 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 10 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 2478 2478 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x2480 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2480 0x2480 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 7 2479 2479 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 51 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 247a 247a fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_offs_lit 28 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 247b 247b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2482 fiu_mem_start 8 start_wr_if_false fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2482 0x2482 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 247c 247c seq_b_timing 1 Latch Condition; Flow J cc=True 0x2454 seq_br_type 1 Branch True seq_branch_adr 2454 0x2454 247d 247d typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 1 INC_LOOP_COUNTER 247e 247e seq_br_type 3 Unconditional Branch; Flow J 0x2454 seq_branch_adr 2454 0x2454 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 247f 247f fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2480 2480 fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x2482 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2482 0x2482 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 3b VR08:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 8 val_rand 2 DEC_LOOP_COUNTER 2481 2481 ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x247f seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 247f 0x247f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 2d TR09:0d typ_frame 9 val_b_adr 0f GP0f 2482 ; -------------------------------------------------------------------------------------- 2482 ; Comes from: 2482 ; 244a C True from color 0x2445 2482 ; 2456 C True from color 0x0000 2482 ; 247b C True from color 0x0000 2482 ; 2480 C True from color 0x243b 2482 ; -------------------------------------------------------------------------------------- 2482 2482 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 2483 2483 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return seq_en_micro 0 2484 ; -------------------------------------------------------------------------------------- 2484 ; Comes from: 2484 ; 09f5 C from color MACRO_Execute_Any,Size 2484 ; 1343 C from color 0x133f 2484 ; 1779 C from color 0x09ae 2484 ; 17d7 C from color 0x0a32 2484 ; 3634 C from color 0x108b 2484 ; -------------------------------------------------------------------------------------- 2484 2484 fiu_mem_start 9 start_continue_if_true; Flow J cc=False 0x2487 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2487 0x2487 typ_mar_cntl 6 INCREMENT_MAR 2485 2485 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2486 2486 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x2488 seq_br_type 8 Return True seq_branch_adr 2488 0x2488 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2487 2487 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x32a9 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2488 ; -------------------------------------------------------------------------------------- 2488 ; Comes from: 2488 ; 119f C from color 0x119b 2488 ; 16d2 C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 2488 ; 16e8 C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 2488 ; -------------------------------------------------------------------------------------- 2488 2488 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x248f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 38 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 248f 0x248f seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 09 GP09 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 2489 2489 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x248c ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 248c 0x248c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 08 GP08 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 248a 248a fiu_fill_mode_src 0 ; Flow J cc=False 0x24b7 fiu_length_src 0 length_register fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24b7 0x24b7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 248b 248b seq_br_type 3 Unconditional Branch; Flow J 0x2487 seq_branch_adr 2487 0x2487 248c 248c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 248d 248d fiu_fill_mode_src 0 ; Flow J cc=False 0x24b7 fiu_length_src 0 length_register fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24b7 0x24b7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 248e 248e seq_br_type 3 Unconditional Branch; Flow J 0x2487 seq_branch_adr 2487 0x2487 248f 248f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 09 GP09 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2490 2490 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu typ_a_adr 09 GP09 typ_alu_func 1e A_AND_B typ_b_adr 3b TR07:1b typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2491 2491 fiu_len_fill_lit 78 zero-fill 0x38; Flow C 0x2ab4 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2492 2492 seq_b_timing 0 Early Condition; Flow J cc=True 0x249f seq_br_type 1 Branch True seq_branch_adr 249f 0x249f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 2493 2493 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x249f ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 249f 0x249f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 2494 2494 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x24b0 seq_br_type 5 Call True seq_branch_adr 24b0 0x24b0 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 08 GP08 typ_alu_func 7 INC_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2495 2495 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x2493 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2493 0x2493 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2496 2496 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2497 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 2493 0x2493 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 2497 2497 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x249a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 249a 0x249a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2498 2498 fiu_fill_mode_src 0 ; Flow J 0x249c fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 249c 0x249c typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2499 2499 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x2498 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2498 0x2498 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 249a 249a fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 249b 249b fiu_fill_mode_src 0 ; Flow J 0x249c fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 249c 0x249c typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 249c 249c seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 249d 0x249d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 0f GP0f typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU 249d 249d seq_b_timing 1 Latch Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 249e 0x249e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 0f GP0f typ_rand 5 CHECK_CLASS_B_LIT 249e 249e seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x32de seq_br_type 8 Return True seq_branch_adr 32de 0x32de seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 249f 249f fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 24a0 0x24a0 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 24a0 24a0 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24a2 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24a2 0x24a2 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 08 GP08 typ_alu_func 7 INC_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP 24a1 24a1 fiu_fill_mode_src 0 ; Flow J 0x24a4 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 24a4 0x24a4 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 24a2 24a2 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 24a3 24a3 fiu_fill_mode_src 0 ; Flow J 0x24a4 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 24a4 0x24a4 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 24a4 24a4 fiu_mem_start 2 start-rd; Flow J cc=False 0x24a6 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 24a6 0x24a6 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 3b TR07:1b typ_frame 7 val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 24a5 24a5 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32d9 seq_branch_adr 32d9 0x32d9 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 3b TR07:1b typ_frame 7 24a6 24a6 seq_b_timing 0 Early Condition; Flow J cc=True 0x24a9 seq_br_type 1 Branch True seq_branch_adr 24a9 0x24a9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 24a7 24a7 fiu_len_fill_lit 4d zero-fill 0xd; Flow C 0x2ab4 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 24a8 24a8 fiu_mem_start 2 start-rd; Flow J 0x24a6 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 24a6 0x24a6 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_rand 2 DEC_LOOP_COUNTER 24a9 24a9 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=False 0x24ae fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 24ae 0x24ae seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 2a VR08:0a val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 8 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 24aa 24aa fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_rand d SET_PASS_PRIVACY_BIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 24ab 24ab fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 24ac 0x24ac seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 24ac 24ac seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x24b0 seq_br_type 5 Call True seq_branch_adr 24b0 0x24b0 seq_cond_sel 67 REFRESH_MACRO_EVENT 24ad 24ad fiu_load_tar 1 hold_tar; Flow J cc=True 0x24aa fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 24aa 0x24aa seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 2a VR08:0a val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 8 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 24ae 24ae fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2499 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2499 0x2499 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f 24af 24af fiu_mem_start 6 start_rd_if_false; Flow R cc=True ; Flow J cc=False 0x24ac ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 24ac 0x24ac seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl d LOAD_MAR_TYPE 24b0 ; -------------------------------------------------------------------------------------- 24b0 ; Comes from: 24b0 ; 2494 C True from color 0x0000 24b0 ; 24ac C True from color 0x0000 24b0 ; -------------------------------------------------------------------------------------- 24b0 24b0 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 24b1 24b1 fiu_mem_start 2 start-rd; Flow J 0x332e seq_br_type 3 Unconditional Branch seq_branch_adr 332e 0x332e 24b2 ; -------------------------------------------------------------------------------------- 24b2 ; Comes from: 24b2 ; 1313 C from color 0x1307 24b2 ; 2389 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 24b2 ; 23fb C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 24b2 ; 242f C from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 24b2 ; -------------------------------------------------------------------------------------- 24b2 24b2 fiu_len_fill_lit 7a zero-fill 0x3a; Flow J cc=True 0x24b6 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24b6 0x24b6 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 08 GP08 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 24b3 24b3 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 24b4 24b4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x332e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 24b5 24b5 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x32d9 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 32d9 0x32d9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_c_adr 3d GP02 val_c_source 0 FIU_BUS 24b6 24b6 seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 09 GP09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24b7 24b7 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 08 GP08 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 24b8 24b8 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 24b9 0x24b9 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 09 GP09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24b9 24b9 seq_br_type 3 Unconditional Branch; Flow J 0x24b5 seq_branch_adr 24b5 0x24b5 24ba ; -------------------------------------------------------------------------------------- 24ba ; Comes from: 24ba ; 1170 C from color 0x113f 24ba ; 1b23 C from color 0x0a33 24ba ; 1b2f C from color 0x0a7d 24ba ; 1b35 C from color 0x0a91 24ba ; 1b39 C from color 0x0a33 24ba ; 1db9 C from color 0x1d5c 24ba ; 1dc5 C from color 0x1d5c 24ba ; -------------------------------------------------------------------------------------- 24ba 24ba fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 24bb 24bb fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 24bc 0x24bc typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24bc 24bc <default> 24bd 24bd fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 24be 24be ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 0 PASS_A val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 24bf 24bf ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 24c0 0x24c0 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 24c0 24c0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A 24c1 24c1 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x24ca ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 24ca 0x24ca seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_b_adr 09 GP09 typ_c_lit 2 typ_frame a typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 24c2 24c2 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x2512 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 2512 0x2512 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE 24c3 24c3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 24c4 ; -------------------------------------------------------------------------------------- 24c4 ; Comes from: 24c4 ; 0c33 C from color 0x0a35 24c4 ; 0c3f C from color 0x0a7e 24c4 ; 0c45 C from color 0x0a92 24c4 ; 0c49 C from color 0x0a35 24c4 ; 117a C from color 0x113f 24c4 ; 1dbe C from color 0x1d5c 24c4 ; 1ddb C from color 0x1d5c 24c4 ; -------------------------------------------------------------------------------------- 24c4 24c4 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 24c5 24c5 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 24c6 0x24c6 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24c6 24c6 <default> 24c7 24c7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 24c8 24c8 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 0 PASS_A val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 24c9 24c9 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x24c0 seq_br_type 8 Return True seq_branch_adr 24c0 0x24c0 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 09 GP09 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 24ca 24ca fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=False 0x24cd fiu_mem_start 5 start_rd_if_true fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 24cd 0x24cd seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 24cb 24cb fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x24f6 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 24f6 0x24f6 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 24cc 24cc ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x24f6 seq_br_type 1 Branch True seq_branch_adr 24f6 0x24f6 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 09 GP09 typ_b_adr 16 CSA/VAL_BUS 24cd 24cd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x24de seq_br_type 1 Branch True seq_branch_adr 24de 0x24de seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 08 GP08 24ce 24ce fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 24cf 0x24cf seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24cf 24cf typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 24d0 24d0 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x2510 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2510 0x2510 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 24d1 24d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x24d3 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24d3 0x24d3 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 24d2 24d2 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x24ce seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 24ce 0x24ce seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24d3 24d3 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 24d4 0x24d4 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24d4 24d4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 17 LOOP_COUNTER val_b_adr 2c VR12:0c val_frame 12 val_rand c START_MULTIPLY 24d5 24d5 fiu_load_oreg 1 hold_oreg seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 24d6 24d6 fiu_len_fill_lit 4b zero-fill 0xb fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 24d7 24d7 ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU 24d8 24d8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS 24d9 24d9 typ_a_adr 09 GP09 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 24da 24da fiu_fill_mode_src 0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 24db 24db <default> 24dc 24dc fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 24dd 24dd seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x24ce seq_branch_adr 24ce 0x24ce seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 0f GP0f 24de 24de fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 24df 0x24df seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 20 TR05:00 typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 24df 24df fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24e4 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24e4 0x24e4 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 24e0 24e0 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 24e1 24e1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x2510 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2510 0x2510 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 24e2 24e2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x24e9 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24e9 0x24e9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 24e3 24e3 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x24de seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 24de 0x24de seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24e4 24e4 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 24e5 24e5 fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 24e6 24e6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x2510 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2510 0x2510 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 24e7 24e7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x24e9 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24e9 0x24e9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 24e8 24e8 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x24de seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 24de 0x24de seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24e9 24e9 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 24ea 0x24ea seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 24ea 24ea fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 17 LOOP_COUNTER val_b_adr 32 VR02:12 val_frame 2 val_rand c START_MULTIPLY 24eb 24eb ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 39 TR02:19 typ_alu_func 18 NOT_A_AND_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 24ec 24ec fiu_len_fill_lit 4a zero-fill 0xa fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 17 LOOP_COUNTER val_b_adr 2c VR12:0c val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 12 val_rand c START_MULTIPLY 24ed 24ed fiu_len_fill_lit 4b zero-fill 0xb fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU 24ee 24ee fiu_len_fill_lit 1f sign-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B 24ef 24ef fiu_mem_start a start_continue_if_false; Flow J cc=False 0x24f1 ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 24f1 0x24f1 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT 24f0 24f0 fiu_fill_mode_src 0 ; Flow J 0x24f3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 24f3 0x24f3 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 24f1 24f1 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 24f2 24f2 fiu_fill_mode_src 0 ; Flow J 0x24f3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 24f3 0x24f3 typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 3f GP00 val_c_source 0 FIU_BUS 24f3 24f3 typ_c_adr 36 GP09 24f4 24f4 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f val_c_source 0 FIU_BUS 24f5 24f5 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x24de seq_branch_adr 24de 0x24de seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 19 X_XOR_B val_b_adr 0f GP0f 24f6 24f6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2501 seq_br_type 1 Branch True seq_branch_adr 2501 0x2501 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 08 GP08 24f7 24f7 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 24f8 0x24f8 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 24f8 24f8 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 24f9 24f9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x2510 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2510 0x2510 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 24fa 24fa fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x24f7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 24f7 0x24f7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 24fb 24fb ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 24fc 0x24fc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 24fc 24fc fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 24fd 24fd ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 24fe 24fe fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_b_adr 09 GP09 24ff 24ff seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x24f7 seq_br_type 8 Return True seq_branch_adr 24f7 0x24f7 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f 2500 2500 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2501 0x2501 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f 2501 2501 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x250a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 250a 0x250a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 2502 2502 fiu_load_var 1 hold_var; Flow J cc=True 0x2508 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2508 0x2508 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 09 GP09 2503 2503 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2504 0x2504 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2504 2504 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2505 2505 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2506 2506 fiu_load_var 1 hold_var; Flow J cc=False 0x2500 fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2500 0x2500 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_b_adr 09 GP09 2507 2507 seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x2509 seq_br_type 8 Return True seq_branch_adr 2509 0x2509 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f 2508 2508 seq_b_timing 0 Early Condition; Flow J cc=False 0x2501 seq_br_type 0 Branch False seq_branch_adr 2501 0x2501 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU 2509 2509 seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 250a ; -------------------------------------------------------------------------------------- 250a ; Comes from: 250a ; 2501 C from color 0x24ba 250a ; -------------------------------------------------------------------------------------- 250a 250a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x250d seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 250d 0x250d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_mux_sel 2 ALU 250b 250b fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 250c 250c fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x2510 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2510 0x2510 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 250d 250d fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 250e 250e fiu_len_fill_lit 1f sign-fill 0x1f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 250f 250f fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2510 0x2510 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 2510 ; -------------------------------------------------------------------------------------- 2510 ; Comes from: 2510 ; 24d0 C True from color 0x24ba 2510 ; 24e1 C True from color 0x24ba 2510 ; 24e6 C True from color 0x24ba 2510 ; 24f9 C True from color 0x24ba 2510 ; -------------------------------------------------------------------------------------- 2510 2510 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 2511 2511 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2512 2512 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 2513 2513 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x2517 fiu_mem_start 5 start_rd_if_true fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2517 0x2517 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 4 2514 2514 fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2515 ; -------------------------------------------------------------------------------------- 2515 ; Comes from: 2515 ; 119c C from color 0x119b 2515 ; 17d0 C True from color 0x0a32 2515 ; 17e2 C True from color 0x0a7c 2515 ; 17e6 C True from color 0x0a90 2515 ; 17ea C True from color MACRO_Execute_Variant_Record,Check_In_Type 2515 ; 17f0 C True from color 0x0aa4 2515 ; 1df3 C from color 0x0000 2515 ; -------------------------------------------------------------------------------------- 2515 2515 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 2516 2516 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32de fiu_mem_start 5 start_rd_if_true fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32de 0x32de seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 4 2517 2517 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x252d fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 252d 0x252d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2518 2518 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2519 2519 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2520 ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2520 0x2520 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 2 DEC_LOOP_COUNTER 251a 251a fiu_fill_mode_src 0 ; Flow J cc=True 0x2522 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2522 0x2522 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_source 0 FIU_BUS 251b 251b seq_b_timing 0 Early Condition; Flow J cc=True 0x2524 seq_br_type 1 Branch True seq_branch_adr 2524 0x2524 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 251c 251c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 251d 251d ioc_tvbs 1 typ+fiu; Flow J cc=True 0x252c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 252c 0x252c seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 251e 251e fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 251f 251f fiu_mem_start a start_continue_if_false; Flow J cc=True 0x251a seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 251a 0x251a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_rand 2 DEC_LOOP_COUNTER 2520 2520 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2521 2521 fiu_fill_mode_src 0 ; Flow J cc=False 0x251b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 251b 0x251b seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_source 0 FIU_BUS 2522 2522 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 2523 2523 fiu_mem_start 2 start-rd; Flow J 0x251b ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 251b 0x251b typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A 2524 2524 fiu_fill_mode_src 0 ; Flow J cc=True 0x2529 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2529 0x2529 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 20 TR01:00 typ_alu_func 18 NOT_A_AND_B typ_frame 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2525 2525 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x252a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 252a 0x252a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2526 2526 fiu_fill_mode_src 0 ; Flow J cc=True 0x252c fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 252c 0x252c seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B 2527 2527 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 2528 0x2528 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 08 GP08 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2528 2528 seq_br_type 7 Unconditional Call; Flow C 0x32a4 seq_branch_adr 32a4 0x32a4 2529 2529 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 08 GP08 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 252a 252a fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 252b 252b fiu_fill_mode_src 0 ; Flow J cc=True 0x2527 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2527 0x2527 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B 252c 252c fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 252d 252d fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x2530 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2530 0x2530 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 20 TR01:00 typ_alu_func 18 NOT_A_AND_B typ_frame 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_frame 2 252e 252e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2531 ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2531 0x2531 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_source 0 FIU_BUS 252f 252f fiu_fill_mode_src 0 ; Flow J 0x2527 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2527 0x2527 2530 2530 fiu_load_var 1 hold_var; Flow R fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 31 VR02:11 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2531 2531 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2532 2532 fiu_fill_mode_src 0 ; Flow J 0x2527 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2527 0x2527 2533 2533 <halt> ; Flow R 2534 ; -------------------------------------------------------------------------------------- 2534 ; 0x0319 Declare_Type Variant_Record,Incomplete,Visible 2534 ; -------------------------------------------------------------------------------------- 2534 MACRO_Declare_Type_Variant_Record,Incomplete,Visible: 2534 2534 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2534 ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR06:02 val_frame 6 2535 2535 seq_br_type 3 Unconditional Branch; Flow J 0x2537 seq_branch_adr 2537 0x2537 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1b A_OR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2536 ; -------------------------------------------------------------------------------------- 2536 ; 0x0318 Declare_Type Variant_Record,Incomplete 2536 ; -------------------------------------------------------------------------------------- 2536 MACRO_Declare_Type_Variant_Record,Incomplete: 2536 2536 dispatch_brk_class 4 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2536 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1b A_OR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2537 2537 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x2539 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 2539 0x2539 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 3b VR02:1b val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_frame 2 2538 2538 fiu_tivi_src 4 fiu_var; Flow C cc=True 0x32dd ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1d TOP - 3 val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 2539 2539 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32dd fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2d TR09:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 253a 253a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32dd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 253b 253b fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32dd fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 3a GP05 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 253c 253c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32dd fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 37 TR05:17 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 02 GP02 val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR05:16 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_frame 5 253d 253d fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 1d TOP - 3 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 253e 253e ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 26 VR05:06 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 20 VR05:00 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 253f 253f fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x2542 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2542 0x2542 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 3e VR03:1e val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 3 2540 2540 fiu_tivi_src 6 fiu_fiu; Flow C 0x2ab4 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 20 TR08:00 typ_frame 8 2541 2541 fiu_mem_start 3 start-wr; Flow J cc=True 0x2540 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2540 0x2540 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 3e VR03:1e val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 3 2542 2542 fiu_len_fill_lit 53 zero-fill 0x13 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_alu_func 13 ONES val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2543 2543 ioc_load_wdr 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 2c TR09:0c typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2544 2544 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 38 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS typ_b_adr 21 TR00:01 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 1d TOP - 3 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2545 2545 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x2546 fiu_load_tar 1 hold_tar fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2546 0x2546 typ_a_adr 05 GP05 val_b_adr 05 GP05 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2546 2546 fiu_load_var 1 hold_var; Flow J cc=True 0x254c fiu_mem_start 6 start_rd_if_false fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 254c 0x254c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 05 GP05 typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 06 GP06 val_rand 2 DEC_LOOP_COUNTER 2547 2547 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 3c VR07:1c val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 7 2548 2548 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x332e fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2549 2549 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 254a 254a fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2ab4 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 06 GP06 val_b_adr 02 GP02 254b 254b ioc_tvbs 1 typ+fiu; Flow J 0x2546 seq_br_type 3 Unconditional Branch seq_branch_adr 2546 0x2546 val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 254c 254c ioc_adrbs 1 val ioc_fiubs 1 val seq_random 18 Load_control_top+? typ_csa_cntl 1 START_POP_DOWN val_a_adr 04 GP04 val_alu_func 0 PASS_A 254d 254d fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2550 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2550 0x2550 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 254e 254e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 254f 254f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2550 ; -------------------------------------------------------------------------------------- 2550 ; Comes from: 2550 ; 254d C from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 2550 ; 255e C from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 2550 ; -------------------------------------------------------------------------------------- 2550 2550 fiu_load_oreg 1 hold_oreg; Flow C 0x2ab4 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 21 TR02:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3e TR02:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 2551 2551 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x2550 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2550 0x2550 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 2552 ; -------------------------------------------------------------------------------------- 2552 ; 0x0312 Declare_Type Variant_Record,Constrained_Incomplete,Visible 2552 ; -------------------------------------------------------------------------------------- 2552 MACRO_Declare_Type_Variant_Record,Constrained_Incomplete,Visible: 2552 2552 dispatch_brk_class 4 ; Flow C cc=False 0x32a9 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2552 ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR06:02 val_frame 6 2553 2553 seq_br_type 3 Unconditional Branch; Flow J 0x2555 seq_branch_adr 2555 0x2555 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2554 ; -------------------------------------------------------------------------------------- 2554 ; 0x0311 Declare_Type Variant_Record,Constrained_Incomplete 2554 ; -------------------------------------------------------------------------------------- 2554 MACRO_Declare_Type_Variant_Record,Constrained_Incomplete: 2554 2554 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2554 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2555 2555 fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=True 0x32dd fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 2556 2556 ioc_fiubs 0 fiu ; Flow C cc=True 0x32dd seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2d TR09:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2557 2557 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32dd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 2558 2558 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x255b fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 255b 0x255b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 2559 2559 fiu_tivi_src 6 fiu_fiu; Flow C 0x2ab4 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 2b TR08:0b typ_frame 8 val_rand 2 DEC_LOOP_COUNTER 255a 255a fiu_mem_start 3 start-wr; Flow J cc=False 0x2559 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2559 0x2559 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 255b 255b fiu_len_fill_lit 53 zero-fill 0x13 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_alu_func 13 ONES val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 255c 255c fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_mdr 1 hold_mdr fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 24 TR09:04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 0 NO_OP val_a_adr 10 TOP 255d 255d fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 3b VR02:1b val_b_adr 1f TOP - 1 val_frame 2 255e 255e fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x2550 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 58 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2550 0x2550 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 27 TR08:07 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 255f 255f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x254f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 3 Unconditional Branch seq_branch_adr 254f 0x254f seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2560 ; -------------------------------------------------------------------------------------- 2560 ; 0x0307 Complete_Type Variant_Record,By_Defining 2560 ; -------------------------------------------------------------------------------------- 2560 MACRO_Complete_Type_Variant_Record,By_Defining: 2560 2560 dispatch_brk_class 4 ; Flow C 0x332e dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 2560 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 22 TR02:02 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2561 2561 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=True 0x32a9 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 14 ZEROS val_b_adr 16 CSA/VAL_BUS 2562 2562 fiu_mem_start 4 continue; Flow C cc=True 0x32db ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 2563 2563 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32dd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 21 TR06:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 5 2564 2564 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32d9 fiu_load_tar 1 hold_tar fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 07 GP07 typ_alu_func 19 X_XOR_B typ_b_adr 2e TR09:0e typ_frame 9 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2565 2565 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32db seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2566 2566 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32d9 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 21 TR00:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2567 2567 fiu_tivi_src 1 tar_val; Flow J cc=True 0x25a5 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 25a5 0x25a5 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_a_adr 1e TOP - 2 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 1f TOP - 1 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2568 2568 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 1d TOP - 3 typ_frame 1c val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2569 2569 ioc_fiubs 0 fiu ; Flow C cc=True 0x32dd seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 0f GP0f val_c_adr 3c GP03 val_c_source 0 FIU_BUS 256a 256a fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_source 0 FIU_BUS 256b 256b seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 37 TR05:17 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 256c 256c ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 256d 256d seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 256e 256e seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 256f 256f ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 2570 2570 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2571 2571 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 51 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_b_adr 01 GP01 2572 2572 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2573 2573 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_adrbs 2 typ ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_b_adr 0e GP0e val_c_adr 3f GP00 2574 2574 ioc_fiubs 0 fiu ; Flow C 0x26e8 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 26e8 0x26e8 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 1d TOP - 3 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_b_adr 1d TOP - 3 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2575 2575 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2576 2576 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2577 2577 seq_b_timing 0 Early Condition; Flow J cc=False 0x2579 seq_br_type 0 Branch False seq_branch_adr 2579 0x2579 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_alu_func 1b A_OR_B val_b_adr 22 VR08:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 2578 2578 seq_br_type 3 Unconditional Branch; Flow J 0x257a seq_branch_adr 257a 0x257a val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2579 2579 seq_br_type 3 Unconditional Branch; Flow J 0x257a seq_branch_adr 257a 0x257a typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 257a 257a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 22 VR07:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 257b 257b ioc_tvbs 1 typ+fiu; Flow J cc=True 0x258d seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 258d 0x258d seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 257c 257c ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 257d 257d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32dd seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 257e 257e fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32dd fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 257f 257f ioc_tvbs 1 typ+fiu; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2580 2580 seq_br_type 7 Unconditional Call; Flow C 0x26e8 seq_branch_adr 26e8 0x26e8 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2581 2581 fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 2582 2582 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2585 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2585 0x2585 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 2583 2583 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x257a seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 257a 0x257a seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2584 2584 ioc_fiubs 0 fiu ; Flow J 0x257a seq_br_type 3 Unconditional Branch seq_branch_adr 257a 0x257a val_c_adr 37 GP08 val_c_source 0 FIU_BUS 2585 ; -------------------------------------------------------------------------------------- 2585 ; Comes from: 2585 ; 2582 C #0x0 from color 0x2580 2585 ; 25d7 C #0x0 from color 0x25cd 2585 ; 2640 C #0x0 from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2585 ; -------------------------------------------------------------------------------------- 2585 2585 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 30 VR02:10 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2586 2586 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 2587 2587 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2588 2588 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2586 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2586 0x2586 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2589 2589 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 258a 258a fiu_mem_start 3 start-wr; Flow J 0x2586 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2586 0x2586 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 258b 258b fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 258c 258c fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x2586 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2586 0x2586 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 258d 258d ioc_tvbs 5 seq+seq; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 258e 258e seq_b_timing 0 Early Condition; Flow C cc=False 0x259c seq_br_type 4 Call False seq_branch_adr 259c 0x259c seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_rand d SET_PASS_PRIVACY_BIT 258f 258f seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32dd seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2590 2590 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 2591 2591 fiu_tivi_src c mar_0xc; Flow C cc=True 0x259a ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 259a 0x259a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 2592 2592 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR05:00 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 2593 2593 seq_b_timing 0 Early Condition; Flow C cc=False 0x25a3 seq_br_type 4 Call False seq_branch_adr 25a3 0x25a3 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 2594 2594 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 2595 2595 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2596 2596 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2597 2597 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 08 GP08 2598 2598 ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 03 GP03 2599 2599 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 259a ; -------------------------------------------------------------------------------------- 259a ; Comes from: 259a ; 2591 C True from color 0x258e 259a ; -------------------------------------------------------------------------------------- 259a 259a seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 17 LOOP_COUNTER typ_alu_func 18 NOT_A_AND_B typ_b_adr 21 TR05:01 typ_frame 5 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 259b 259b seq_b_timing 0 Early Condition; Flow C 0x210 seq_br_type 9 Return False seq_branch_adr 0210 0x0210 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 31 TR09:11 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 9 259c ; -------------------------------------------------------------------------------------- 259c ; Comes from: 259c ; 258e C False from color 0x258e 259c ; -------------------------------------------------------------------------------------- 259c 259c seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 259d 0x259d seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) val_a_adr 01 GP01 val_b_adr 31 VR02:11 val_frame 2 val_m_a_src 1 Bits 16…31 val_rand c START_MULTIPLY 259d 259d seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 259e 259e seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 259f 0x259f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 val_m_a_src 1 Bits 16…31 259f 259f seq_br_type 1 Branch True; Flow J cc=True 0x25a2 seq_branch_adr 25a2 0x25a2 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 25a0 25a0 seq_br_type 1 Branch True; Flow J cc=True 0x25a2 seq_branch_adr 25a2 0x25a2 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 25a1 25a1 seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 25a2 0x25a2 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 25a2 25a2 seq_br_type a Unconditional Return; Flow R typ_a_adr 22 TR01:02 typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 25a3 ; -------------------------------------------------------------------------------------- 25a3 ; Comes from: 25a3 ; 2593 C False from color 0x258e 25a3 ; -------------------------------------------------------------------------------------- 25a3 25a3 seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 25a4 0x25a4 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 07 GP07 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR00:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 25a4 25a4 seq_br_type a Unconditional Return; Flow R typ_a_adr 07 GP07 typ_alu_func 19 X_XOR_B typ_b_adr 22 TR01:02 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 25a5 25a5 seq_br_type 4 Call False; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 1d TOP - 3 val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 25a6 25a6 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 1c TOP - 4 typ_frame 1c val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 1d TOP - 3 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 25a7 25a7 ioc_fiubs 0 fiu ; Flow C cc=True 0x32dd seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 0f GP0f val_c_adr 3c GP03 val_c_source 0 FIU_BUS 25a8 25a8 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32dd fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 1d TOP - 3 val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR05:16 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 25a9 25a9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value 25aa 25aa fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32dd fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32dd 0x32dd seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 25ab 25ab ioc_tvbs 1 typ+fiu val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 25ac 25ac seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR07:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 01 GP01 val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 25ad 25ad fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_b_adr 03 GP03 25ae 25ae fiu_len_fill_lit 48 zero-fill 0x8 fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 25af 25af seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU 25b0 25b0 seq_en_micro 0 val_a_adr 0f GP0f val_b_adr 2d VR04:0d val_frame 4 val_rand c START_MULTIPLY 25b1 25b1 ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT 25b2 25b2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 25b3 25b3 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 51 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_b_adr 01 GP01 25b4 25b4 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 25b5 25b5 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_adrbs 2 typ ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 03 GP03 val_b_adr 0e GP0e val_c_adr 3f GP00 25b6 25b6 ioc_fiubs 0 fiu ; Flow C 0x26e8 ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 26e8 0x26e8 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 1c TOP - 4 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_b_adr 1c TOP - 4 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 25b7 25b7 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 25b8 25b8 seq_br_type 7 Unconditional Call; Flow C 0x270d seq_branch_adr 270d 0x270d seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 25b9 25b9 seq_br_type 1 Branch True; Flow J cc=True 0x25be seq_branch_adr 25be 0x25be seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 25ba 25ba val_a_adr 01 GP01 val_b_adr 31 VR02:11 val_frame 2 val_m_a_src 1 Bits 16…31 val_rand c START_MULTIPLY 25bb 25bb seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 25bc 25bc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x25be seq_br_type 1 Branch True seq_branch_adr 25be 0x25be seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 25bd 25bd typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 25be 25be ioc_fiubs 1 val ; Flow J cc=True 0x25c0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 25c0 0x25c0 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25bf 25bf typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 25c0 25c0 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 25c1 25c1 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1b A_OR_B val_b_adr 22 VR08:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 25c2 25c2 val_a_adr 01 GP01 val_b_adr 31 VR02:11 val_frame 2 val_m_a_src 1 Bits 16…31 val_rand c START_MULTIPLY 25c3 25c3 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 25c4 25c4 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0f GP0f 25c5 25c5 ioc_fiubs 0 fiu ; Flow J 0x25c6 seq_br_type 3 Unconditional Branch seq_branch_adr 25c6 0x25c6 val_a_adr 1d TOP - 3 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25c6 25c6 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 22 VR07:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 25c7 25c7 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x258d seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 258d 0x258d seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR05:17 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 25c8 25c8 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 25c9 25c9 ioc_fiubs 1 val ; Flow C cc=True 0x32dd ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 25ca 25ca fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32dd fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 25cb 25cb ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32dd seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 25cc 25cc fiu_load_var 1 hold_var; Flow C 0x2ab4 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 25cd 25cd ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32dd seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 25ce 25ce ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32dd seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 25cf 25cf fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 04 GP04 25d0 25d0 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32dd seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 25d1 25d1 seq_br_type 7 Unconditional Call; Flow C 0x26e8 seq_branch_adr 26e8 0x26e8 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 25d2 25d2 val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 25d3 25d3 ioc_fiubs 2 typ ; Flow J cc=True 0x25d5 seq_br_type 1 Branch True seq_branch_adr 25d5 0x25d5 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 14 ZEROS val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25d4 25d4 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 25d5 25d5 seq_br_type 7 Unconditional Call; Flow C 0x270d seq_branch_adr 270d 0x270d val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 25d6 25d6 fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 25d7 25d7 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2585 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2585 0x2585 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 25d8 25d8 seq_br_type 0 Branch False; Flow J cc=False 0x25c6 seq_branch_adr 25c6 0x25c6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 25d9 25d9 seq_br_type 3 Unconditional Branch; Flow J 0x25c6 seq_branch_adr 25c6 0x25c6 val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 25da ; -------------------------------------------------------------------------------------- 25da ; 0x0303 Complete_Type Variant_Record,By_Component_Completion 25da ; -------------------------------------------------------------------------------------- 25da MACRO_Complete_Type_Variant_Record,By_Component_Completion: 25da 25da dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 25da fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 25db 25db typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 25dc 25dc fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 25dd 25dd fiu_mem_start 2 start-rd; Flow J cc=True 0x25de ; Flow J cc=#0x0 0x25e3 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 25e3 0x25e3 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR 25de 25de fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 25df 25df typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 25e0 25e0 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 25e1 25e1 fiu_mem_start 2 start-rd ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 6 INCREMENT_MAR 25e2 25e2 seq_br_type 3 Unconditional Branch; Flow J 0x25e7 seq_branch_adr 25e7 0x25e7 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 25e3 25e3 seq_br_type 3 Unconditional Branch; Flow J 0x265a seq_branch_adr 265a 0x265a typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 25e4 25e4 ioc_fiubs 2 typ ; Flow J 0x25e7 seq_br_type 3 Unconditional Branch seq_branch_adr 25e7 0x25e7 typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame c typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 38 GP07 val_c_source 0 FIU_BUS 25e5 25e5 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 25e6 25e6 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_rand a PASS_B_HIGH 25e7 25e7 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 25e8 25e8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 25e9 25e9 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ typ_a_adr 14 ZEROS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 25ea 25ea fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 31 GP0e val_c_source 0 FIU_BUS 25eb 25eb ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 07 GP07 25ec 25ec ioc_tvbs 3 fiu+fiu; Flow J 0x25ed seq_br_type 3 Unconditional Branch seq_branch_adr 25ed 0x25ed seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 25ed 25ed fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x261c ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 261c 0x261c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR07:00 val_frame 7 25ee 25ee seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x260e seq_br_type 5 Call True seq_branch_adr 260e 0x260e seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 25ef 25ef fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 3 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25f0 25f0 ioc_fiubs 2 typ ; Flow J cc=False 0x25f6 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 25f6 0x25f6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 7 25f1 25f1 fiu_load_tar 1 hold_tar; Flow C cc=True 0x2611 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2611 0x2611 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A 25f2 25f2 ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 25f3 25f3 seq_b_timing 1 Latch Condition; Flow C cc=False 0x25f9 seq_br_type 4 Call False seq_branch_adr 25f9 0x25f9 typ_c_adr 30 GP0f 25f4 25f4 ioc_fiubs 1 val ; Flow J cc=True 0x25ed ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 25ed 0x25ed seq_cond_sel 07 VAL.ALU_32_CO(late) val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25f5 25f5 ioc_fiubs 1 val ; Flow J 0x25ed seq_br_type 3 Unconditional Branch seq_branch_adr 25ed 0x25ed val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 25f6 25f6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_frame 9 val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 25f7 25f7 ioc_tvbs 2 fiu+val; Flow C cc=True 0x2611 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2611 0x2611 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_c_adr 31 GP0e val_c_mux_sel 2 ALU 25f8 25f8 fiu_mem_start 3 start-wr; Flow J 0x25f4 ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 25f4 0x25f4 seq_en_micro 0 typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 0e GP0e 25f9 ; -------------------------------------------------------------------------------------- 25f9 ; Comes from: 25f9 ; 25f3 C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 25f9 ; -------------------------------------------------------------------------------------- 25f9 25f9 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x25fb seq_br_type 1 Branch True seq_branch_adr 25fb 0x25fb seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 25fa 25fa seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 25fb 25fb seq_br_type 4 Call False; Flow C cc=False 0x25fe seq_branch_adr 25fe 0x25fe seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 0f GP0f typ_c_adr 3b GP04 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame a val_c_adr 30 GP0f val_c_mux_sel 2 ALU 25fc 25fc fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 8 Return True seq_branch_adr 25fd 0x25fd seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_b_adr 2d TR05:0d typ_frame 5 val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3b GP04 val_c_mux_sel 2 ALU 25fd 25fd seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 25fe ; -------------------------------------------------------------------------------------- 25fe ; Comes from: 25fe ; 25fb C False from color 0x25f9 25fe ; 2635 C False from color 0x2633 25fe ; -------------------------------------------------------------------------------------- 25fe 25fe fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 7 INC_A typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 25ff 25ff fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 36 GP09 val_c_source 0 FIU_BUS 2600 2600 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x2605 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2605 0x2605 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 36 GP09 val_c_source 0 FIU_BUS val_frame 2 2601 2601 seq_en_micro 0 val_c_adr 33 GP0c val_c_mux_sel 2 ALU 2602 2602 seq_en_micro 0 val_a_adr 09 GP09 val_b_adr 3f VR02:1f val_frame 2 val_rand c START_MULTIPLY 2603 2603 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 2604 2604 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 0c GP0c val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2605 2605 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x260c ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 260c 0x260c seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2606 2606 fiu_mem_start 4 continue typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2607 2607 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x260a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 260a 0x260a seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_rand 6 CHECK_CLASS_A_??_B 2608 2608 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2605 seq_br_type 1 Branch True seq_branch_adr 2605 0x2605 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 2609 2609 seq_br_type 3 Unconditional Branch; Flow J 0x2602 seq_branch_adr 2602 0x2602 val_c_adr 33 GP0c val_c_mux_sel 2 ALU 260a 260a seq_en_micro 0 val_a_adr 09 GP09 val_b_adr 2d VR05:0d val_frame 5 val_rand c START_MULTIPLY 260b 260b seq_br_type 3 Unconditional Branch; Flow J 0x2602 seq_branch_adr 2602 0x2602 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU 260c ; -------------------------------------------------------------------------------------- 260c ; Comes from: 260c ; 2605 C True from color 0x25fe 260c ; -------------------------------------------------------------------------------------- 260c 260c seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 260d 260d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 260e ; -------------------------------------------------------------------------------------- 260e ; Comes from: 260e ; 25ee C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 260e ; 2628 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 260e ; -------------------------------------------------------------------------------------- 260e 260e seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 260f 260f fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2610 2610 seq_br_type a Unconditional Return; Flow R 2611 ; -------------------------------------------------------------------------------------- 2611 ; Comes from: 2611 ; 25f1 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2611 ; 25f7 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2611 ; -------------------------------------------------------------------------------------- 2611 2611 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x2616 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2616 0x2616 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2612 2612 seq_b_timing 1 Latch Condition; Flow J cc=False 0x2619 seq_br_type 0 Branch False seq_branch_adr 2619 0x2619 seq_en_micro 0 2613 2613 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2614 0x2614 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 2614 2614 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2615 0x2615 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 2615 2615 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 21 TR05:01 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 2616 ; -------------------------------------------------------------------------------------- 2616 ; Comes from: 2616 ; 2638 C True from color 0x2638 2616 ; -------------------------------------------------------------------------------------- 2616 2616 seq_en_micro 0 typ_c_adr 32 GP0d 2617 2617 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 2618 0x2618 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x49) Float_Var seq_en_micro 0 typ_b_adr 0d GP0d typ_c_lit 1 typ_frame 9 2618 2618 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 2619 2619 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 261a 0x261a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 261a 261a seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 261b 0x261b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 261b 261b seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 21 TR05:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 261c 261c fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 261d 261d ioc_fiubs 1 val typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 07 GP07 261e 261e seq_b_timing 1 Latch Condition; Flow J cc=True 0x2620 seq_br_type 1 Branch True seq_branch_adr 2620 0x2620 seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 typ_rand e CHECK_CLASS_SYSTEM_B 261f 261f typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 2620 2620 typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 2621 2621 fiu_vmux_sel 1 fill value; Flow J cc=True 0x2623 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 2623 0x2623 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3b TR07:1b typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 7 val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2622 2622 seq_br_type 3 Unconditional Branch; Flow J 0x2623 seq_branch_adr 2623 0x2623 seq_en_micro 0 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2623 2623 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2648 seq_br_type 1 Branch True seq_branch_adr 2648 0x2648 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2624 2624 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2625 2625 typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2626 2626 fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x2627 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2627 0x2627 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2627 2627 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x263c ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 263c 0x263c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 20 VR07:00 val_frame 7 2628 2628 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x260e seq_br_type 5 Call True seq_branch_adr 260e 0x260e seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_rand 2 DEC_LOOP_COUNTER 2629 2629 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 3 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 262a 262a ioc_fiubs 2 typ ; Flow J cc=False 0x2630 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2630 0x2630 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 7 262b 262b fiu_load_tar 1 hold_tar; Flow C cc=True 0x2638 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2638 0x2638 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 0 PASS_A 262c 262c ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 262d 262d seq_b_timing 1 Latch Condition; Flow C cc=False 0x2633 seq_br_type 4 Call False seq_branch_adr 2633 0x2633 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 03 GP03 typ_c_adr 30 GP0f 262e 262e ioc_fiubs 1 val ; Flow J cc=True 0x2627 ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 2627 0x2627 seq_cond_sel 07 VAL.ALU_32_CO(late) val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 262f 262f ioc_fiubs 1 val ; Flow J 0x2627 seq_br_type 3 Unconditional Branch seq_branch_adr 2627 0x2627 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2630 2630 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 28 TR09:08 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_frame 9 val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 2631 2631 ioc_tvbs 2 fiu+val; Flow C cc=True 0x2638 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2638 0x2638 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 0e GP0e val_alu_func 1b A_OR_B val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2632 2632 fiu_mem_start 3 start-wr; Flow J 0x262e ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 262e 0x262e seq_en_micro 0 typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 0e GP0e 2633 ; -------------------------------------------------------------------------------------- 2633 ; Comes from: 2633 ; 262d C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2633 ; -------------------------------------------------------------------------------------- 2633 2633 fiu_vmux_sel 1 fill value; Flow J cc=True 0x2635 ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 2635 0x2635 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2634 2634 seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 2635 2635 seq_br_type 4 Call False; Flow C cc=False 0x25fe seq_branch_adr 25fe 0x25fe seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 0f GP0f typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame a val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2636 2636 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 8 Return True seq_branch_adr 2637 0x2637 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_b_adr 2d TR05:0d typ_frame 5 val_a_adr 05 GP05 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2637 2637 seq_br_type a Unconditional Return; Flow R val_alu_func 1a PASS_B val_b_adr 3b VR02:1b val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 2638 ; -------------------------------------------------------------------------------------- 2638 ; Comes from: 2638 ; 262b C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2638 ; 2631 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2638 ; -------------------------------------------------------------------------------------- 2638 2638 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x2616 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2616 0x2616 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2639 2639 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 263a 0x263a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 263a 263a seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 263b 0x263b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 263b 263b seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 21 TR05:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 263c 263c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x263e fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 263e 0x263e seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 14 ZEROS typ_b_adr 20 TR08:00 typ_frame 8 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 263d 263d val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 263e 263e fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x2644 fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type 1 Branch True seq_branch_adr 2644 0x2644 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 03 GP03 263f 263f fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 2640 2640 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2585 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2585 0x2585 seq_en_micro 0 2641 2641 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2643 seq_br_type 1 Branch True seq_branch_adr 2643 0x2643 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 06 GP06 val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 2642 2642 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2643 2643 seq_br_type 3 Unconditional Branch; Flow J 0x2623 seq_branch_adr 2623 0x2623 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3b TR07:1b typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 7 2644 2644 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 2645 2645 ioc_tvbs 2 fiu+val; Flow J cc=True 0x2643 seq_br_type 1 Branch True seq_branch_adr 2643 0x2643 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 2646 2646 seq_br_type 3 Unconditional Branch; Flow J 0x2642 seq_branch_adr 2642 0x2642 2647 ; -------------------------------------------------------------------------------------- 2647 ; Comes from: 2647 ; 2649 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2647 ; 264a C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2647 ; -------------------------------------------------------------------------------------- 2647 2647 seq_br_type a Unconditional Return; Flow R val_rand 1 INC_LOOP_COUNTER 2648 2648 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 07 GP07 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2649 2649 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2647 seq_br_type 5 Call True seq_branch_adr 2647 0x2647 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 23 TR05:03 typ_frame 5 264a 264a seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2647 seq_br_type 5 Call True seq_branch_adr 2647 0x2647 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 21 TR05:01 typ_frame 5 264b 264b seq_b_timing 0 Early Condition; Flow J cc=False 0x264b seq_br_type 0 Branch False seq_branch_adr 264b 0x264b seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR01:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 val_rand 2 DEC_LOOP_COUNTER 264c 264c seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2655 seq_br_type 1 Branch True seq_branch_adr 2655 0x2655 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 23 TR05:03 typ_frame 5 typ_rand d SET_PASS_PRIVACY_BIT 264d 264d typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU 264e 264e seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU 264f 264f seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2655 seq_br_type 0 Branch False seq_branch_adr 2655 0x2655 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 2f TR11:0f typ_frame 11 2650 2650 seq_br_type 1 Branch True; Flow J cc=True 0x2654 seq_branch_adr 2654 0x2654 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2f TR11:0f typ_frame 11 2651 2651 seq_b_timing 0 Early Condition; Flow J cc=False 0x2654 seq_br_type 0 Branch False seq_branch_adr 2654 0x2654 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 2652 2652 seq_b_timing 0 Early Condition; Flow J cc=False 0x2654 seq_br_type 0 Branch False seq_branch_adr 2654 0x2654 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 2653 2653 seq_b_timing 0 Early Condition; Flow J cc=True 0x2655 seq_br_type 1 Branch True seq_branch_adr 2655 0x2655 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) 2654 2654 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 2655 2655 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2656 2656 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 33 VR11:13 val_frame 11 2657 2657 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_random 02 ? typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 07 GP07 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 2658 2658 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 2659 2659 ioc_load_wdr 0 ; Flow J cc=True 0x265b seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 265b 0x265b typ_b_adr 03 GP03 val_b_adr 03 GP03 265a 265a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 265b 265b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 265c ; -------------------------------------------------------------------------------------- 265c ; 0x0306 Complete_Type Variant_Record,By_Renaming 265c ; -------------------------------------------------------------------------------------- 265c MACRO_Complete_Type_Variant_Record,By_Renaming: 265c 265c dispatch_brk_class 4 ; Flow C 0x332e dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 265c fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame c typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 265d 265d fiu_mem_start 2 start-rd; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 265e 265e fiu_mem_start 4 continue ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 265f 265f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32d9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR06:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 2660 2660 fiu_load_var 1 hold_var; Flow C cc=False 0x32d9 fiu_mem_start 5 start_rd_if_true fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2661 2661 fiu_len_fill_lit 5a zero-fill 0x1a fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2662 2662 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32a9 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2663 2663 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32db fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32db 0x32db seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 01 GP01 typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2664 2664 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32d9 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 27 VR08:07 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 8 2665 2665 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 58 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 val_rand 1 INC_LOOP_COUNTER 2666 2666 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J 0x2667 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 32d9 0x32d9 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER 2667 2667 fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True ; Flow J cc=False 0x2669 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2669 0x2669 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2668 2668 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2669 2669 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 266a 266a fiu_mem_start 3 start-wr; Flow J cc=True 0x2668 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2668 0x2668 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 6 A_MINUS_B typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A 266b 266b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 266c ; -------------------------------------------------------------------------------------- 266c ; Comes from: 266c ; 2688 C from color MACRO_Declare_Type_Variant_Record,Defined 266c ; 26c4 C from color MACRO_Declare_Type_Variant_Record,Defined 266c ; -------------------------------------------------------------------------------------- 266c 266c seq_b_timing 1 Latch Condition; Flow C cc=False 0x32a9 seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 266d 266d ioc_fiubs 1 val ; Flow C cc=True 0x32d9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1e TOP - 2 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1b A_OR_B val_b_adr 10 TOP val_c_adr 39 GP06 val_c_mux_sel 2 ALU 266e 266e fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=True 0x2672 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 20 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2672 0x2672 typ_a_adr 1f TOP - 1 typ_b_adr 1d TOP - 3 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 1d TOP - 3 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 266f 266f fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x2678 fiu_load_mdr 1 hold_mdr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2678 0x2678 typ_a_adr 1c TOP - 4 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 1c TOP - 4 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 2670 2670 fiu_len_fill_lit 7d zero-fill 0x3d; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1b TOP - 5 typ_frame 1c val_a_adr 07 GP07 val_b_adr 1b TOP - 5 2671 2671 fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x267b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 267b 0x267b typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 1c TOP - 4 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2672 2672 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_b_adr 1c TOP - 4 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 1c TOP - 4 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 2673 2673 val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 1f TOP - 1 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2674 2674 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR05:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1c TOP - 4 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 2675 2675 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x2678 fiu_load_mdr 1 hold_mdr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2678 0x2678 typ_a_adr 1b TOP - 5 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 1b TOP - 5 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 2676 2676 fiu_len_fill_lit 7d zero-fill 0x3d; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1a TOP - 6 typ_frame 1c val_a_adr 07 GP07 val_b_adr 1a TOP - 6 2677 2677 fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x267b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 267b 0x267b typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 1b TOP - 5 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2678 ; -------------------------------------------------------------------------------------- 2678 ; Comes from: 2678 ; 266f C from color 0x266c 2678 ; 2675 C from color 0x266c 2678 ; -------------------------------------------------------------------------------------- 2678 2678 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 23 TR05:03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2679 2679 ioc_tvbs 3 fiu+fiu typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 267a 267a fiu_len_fill_lit 78 zero-fill 0x38; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_frame 2 val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 28 VR05:08 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 5 267b 267b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 1d TOP - 3 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 267c 267c fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32dd fiu_offs_lit 50 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR05:16 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 5 267d 267d fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 267e 267e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_en_micro 0 typ_b_adr 32 TR02:12 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR05:00 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 26 VR05:06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 267f 267f ioc_tvbs 1 typ+fiu; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2680 2680 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2681 0x2681 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 2 DEC_LOOP_COUNTER 2681 2681 typ_a_adr 14 ZEROS typ_alu_func 1c DEC_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2682 2682 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x332e fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2683 2683 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2684 2684 ioc_load_wdr 0 ; Flow C 0x2ab4 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_b_adr 05 GP05 2685 2685 ioc_tvbs 1 typ+fiu; Flow J 0x2680 seq_br_type 3 Unconditional Branch seq_branch_adr 2680 0x2680 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2686 ; -------------------------------------------------------------------------------------- 2686 ; 0x031e Declare_Type Variant_Record,Defined,Visible 2686 ; -------------------------------------------------------------------------------------- 2686 MACRO_Declare_Type_Variant_Record,Defined,Visible: 2686 2686 dispatch_brk_class 4 ; Flow J 0x2687 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2686 seq_br_type 2 Push (branch address) seq_branch_adr 2689 0x2689 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 2687 2687 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x266c fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 266c 0x266c seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2688 ; -------------------------------------------------------------------------------------- 2688 ; 0x031d Declare_Type Variant_Record,Defined 2688 ; -------------------------------------------------------------------------------------- 2688 MACRO_Declare_Type_Variant_Record,Defined: 2688 2688 dispatch_brk_class 4 ; Flow C 0x266c dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2688 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 266c 0x266c seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2689 2689 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x26c6 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 26c6 0x26c6 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 6 A_MINUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 268a 268a ioc_fiubs 0 fiu ; Flow C 0x26e8 seq_br_type 7 Unconditional Call seq_branch_adr 26e8 0x26e8 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 1d TOP - 3 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 268b 268b typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 268c 268c typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 268d 268d typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1b A_OR_B val_b_adr 22 VR08:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 268e 268e seq_b_timing 0 Early Condition; Flow C cc=False 0x26b5 seq_br_type 4 Call False seq_branch_adr 26b5 0x26b5 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 1c TOP - 4 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU 268f 268f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 22 VR07:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 2690 2690 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x269a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 269a 0x269a seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2691 2691 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2692 2692 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32dd seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2693 2693 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32dd fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2694 2694 ioc_tvbs 1 typ+fiu; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2695 2695 seq_br_type 7 Unconditional Call; Flow C 0x26e8 seq_branch_adr 26e8 0x26e8 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2696 2696 fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 2697 2697 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x26a8 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 26a8 0x26a8 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 2698 2698 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x268f seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 268f 0x268f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2699 2699 ioc_fiubs 0 fiu ; Flow J 0x268f seq_br_type 3 Unconditional Branch seq_branch_adr 268f 0x268f val_c_adr 37 GP08 val_c_source 0 FIU_BUS 269a 269a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR07:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 03 GP03 val_b_adr 1c TOP - 4 269b 269b ioc_tvbs 5 seq+seq; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 269c 269c fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x26b0 fiu_load_tar 1 hold_tar fiu_offs_lit 38 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 26b0 0x26b0 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 04 GP04 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 1e TOP - 2 269d 269d ioc_fiubs 0 fiu ; Flow C cc=True 0x32dd ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 06 GP06 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 269e 269e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_b_adr 10 TOP 269f 269f ioc_fiubs 0 fiu typ_a_adr 17 LOOP_COUNTER typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR05:00 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 26a0 26a0 seq_b_timing 0 Early Condition; Flow C cc=False 0x26b6 seq_br_type 4 Call False seq_branch_adr 26b6 0x26b6 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 26a1 26a1 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 08 GP08 26a2 26a2 fiu_mem_start 4 continue ioc_fiubs 1 val typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 26a3 26a3 ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 03 GP03 26a4 26a4 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 18 Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 26a5 26a5 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 23 VR08:03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 26a6 26a6 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR08:1d typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 26a7 26a7 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 26a8 ; -------------------------------------------------------------------------------------- 26a8 ; Comes from: 26a8 ; 2697 C #0x0 from color 0x2695 26a8 ; 26e4 C #0x0 from color 0x26da 26a8 ; -------------------------------------------------------------------------------------- 26a8 26a8 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 30 VR02:10 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26a9 26a9 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 26aa 26aa fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 26ab 26ab fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x26a9 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26a9 0x26a9 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 26ac 26ac fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 26ad 26ad fiu_mem_start 3 start-wr; Flow J 0x26a9 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26a9 0x26a9 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 26ae 26ae fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 26af 26af fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x26a9 fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26a9 0x26a9 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26b0 ; -------------------------------------------------------------------------------------- 26b0 ; Comes from: 26b0 ; 269c C False from color 0x269c 26b0 ; -------------------------------------------------------------------------------------- 26b0 26b0 seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 26b1 0x26b1 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 26b1 26b1 ioc_tvbs 2 fiu+val; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 26b2 0x26b2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 22 TR01:02 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 0f GP0f val_alu_func 5 DEC_A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 26b2 26b2 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x26b4 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 26b4 0x26b4 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 26b3 26b3 seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 26b4 0x26b4 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 1c TOP - 4 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 26b4 26b4 fiu_load_tar 1 hold_tar; Flow R fiu_tivi_src 8 type_var seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 0f GP0f 26b5 ; -------------------------------------------------------------------------------------- 26b5 ; Comes from: 26b5 ; 268e C False from color MACRO_Declare_Type_Variant_Record,Defined 26b5 ; 26cd C True from color MACRO_Declare_Type_Variant_Record,Defined 26b5 ; -------------------------------------------------------------------------------------- 26b5 26b5 seq_br_type a Unconditional Return; Flow R typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 26b6 ; -------------------------------------------------------------------------------------- 26b6 ; Comes from: 26b6 ; 26a0 C False from color 0x269c 26b6 ; -------------------------------------------------------------------------------------- 26b6 26b6 seq_b_timing 0 Early Condition; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 26b7 0x26b7 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 1 26b7 26b7 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 21 TR00:01 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 26b8 26b8 fiu_tivi_src c mar_0xc; Flow R cc=False ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 26b9 0x26b9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 26b9 26b9 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 22 TR02:02 typ_frame 2 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 3b VR02:1b val_frame 2 26ba 26ba fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1e A_AND_B typ_b_adr 21 TR05:01 typ_frame 5 26bb 26bb ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 25 TR09:05 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 08 GP08 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 26bc 26bc fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 20 TR08:00 typ_frame 8 val_a_adr 1e TOP - 2 val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 26bd 26bd fiu_len_fill_lit 7d zero-fill 0x3d; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 26be 0x26be seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 21 VR05:01 val_frame 5 26be 26be ioc_fiubs 0 fiu val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 26bf 26bf fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_rand 2 DEC_LOOP_COUNTER 26c0 26c0 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 26c1 26c1 fiu_mem_start 8 start_wr_if_false; Flow R cc=True ; Flow J cc=False 0x26c0 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 26c0 0x26c0 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand 2 DEC_LOOP_COUNTER 26c2 ; -------------------------------------------------------------------------------------- 26c2 ; 0x0316 Declare_Type Variant_Record,Defined_Incomplete,Visible 26c2 ; -------------------------------------------------------------------------------------- 26c2 MACRO_Declare_Type_Variant_Record,Defined_Incomplete,Visible: 26c2 26c2 dispatch_brk_class 4 ; Flow J 0x26c3 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 26c2 seq_br_type 2 Push (branch address) seq_branch_adr 26c5 0x26c5 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 26c3 26c3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x266c fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 266c 0x266c seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 22 VR06:02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 26c4 ; -------------------------------------------------------------------------------------- 26c4 ; 0x0315 Declare_Type Variant_Record,Defined_Incomplete 26c4 ; -------------------------------------------------------------------------------------- 26c4 MACRO_Declare_Type_Variant_Record,Defined_Incomplete: 26c4 26c4 dispatch_brk_class 4 ; Flow C 0x266c dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 26c4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 266c 0x266c seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_c_adr 3d GP02 val_c_mux_sel 2 ALU 26c5 26c5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x268a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 268a 0x268a seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 6 A_MINUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 26c6 26c6 ioc_fiubs 0 fiu ; Flow C 0x26e8 seq_br_type 7 Unconditional Call seq_branch_adr 26e8 0x26e8 typ_a_adr 27 TR02:07 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 1d TOP - 3 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 26c7 26c7 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 26c8 26c8 seq_br_type 7 Unconditional Call; Flow C 0x270d seq_branch_adr 270d 0x270d typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 1c TOP - 4 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 26c9 26c9 seq_br_type 1 Branch True; Flow J cc=True 0x26cd seq_branch_adr 26cd 0x26cd seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1d A_AND_NOT_B typ_b_adr 20 TR05:00 typ_frame 5 val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 26ca 26ca val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 1e TOP - 2 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 26cb 26cb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x26cd seq_br_type 1 Branch True seq_branch_adr 26cd 0x26cd seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 26cc 26cc typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 26cd 26cd ioc_fiubs 1 val ; Flow C cc=True 0x26b5 seq_br_type 5 Call True seq_branch_adr 26b5 0x26b5 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26ce 26ce seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 26cf 26cf typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1b A_OR_B val_b_adr 22 VR08:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 26d0 26d0 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1c TOP - 4 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 26d1 26d1 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0f GP0f 26d2 26d2 ioc_fiubs 0 fiu ; Flow J 0x26d3 seq_br_type 3 Unconditional Branch seq_branch_adr 26d3 0x26d3 val_a_adr 1b TOP - 5 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26d3 26d3 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 22 VR07:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 26d4 26d4 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x26e7 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 26e7 0x26e7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 1e TOP - 2 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 26d5 26d5 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 26d6 26d6 ioc_fiubs 1 val ; Flow C cc=True 0x32dd ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 26d7 26d7 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32dd fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 26d8 26d8 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32dd seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 26d9 26d9 fiu_load_var 1 hold_var; Flow C 0x2ab4 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_a_adr 38 VR02:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 26da 26da ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32dd seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 26db 26db ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32dd seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 26dc 26dc fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 04 GP04 26dd 26dd ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32dd seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 0a VAL.ALU_LT_ZERO(late) val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 26de 26de seq_br_type 7 Unconditional Call; Flow C 0x26e8 seq_branch_adr 26e8 0x26e8 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 26df 26df val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 26e0 26e0 ioc_fiubs 2 typ ; Flow J cc=True 0x26e2 seq_br_type 1 Branch True seq_branch_adr 26e2 0x26e2 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 14 ZEROS val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 26e1 26e1 val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 26e2 26e2 seq_br_type 7 Unconditional Call; Flow C 0x270d seq_branch_adr 270d 0x270d val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 26e3 26e3 fiu_len_fill_lit 42 zero-fill 0x2 fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 23 TR08:03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 26e4 26e4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x26a8 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 26a8 0x26a8 seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 8 26e5 26e5 seq_br_type 0 Branch False; Flow J cc=False 0x26d3 seq_branch_adr 26d3 0x26d3 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 08 GP08 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 26e6 26e6 seq_br_type 3 Unconditional Branch; Flow J 0x26d3 seq_branch_adr 26d3 0x26d3 val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 26e7 26e7 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x269b fiu_load_var 1 hold_var fiu_offs_lit 58 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 269b 0x269b typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 38 TR05:18 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 03 GP03 val_b_adr 1b TOP - 5 26e8 ; -------------------------------------------------------------------------------------- 26e8 ; Comes from: 26e8 ; 1eb7 C from color 0x1eb4 26e8 ; 1edc C from color 0x1ed6 26e8 ; 2574 C from color 0x2569 26e8 ; 2580 C from color 0x2580 26e8 ; 25b6 C from color 0x25a7 26e8 ; 25d1 C from color 0x25cd 26e8 ; 268a C from color MACRO_Declare_Type_Variant_Record,Defined 26e8 ; 2695 C from color 0x2695 26e8 ; 26c6 C from color MACRO_Declare_Type_Variant_Record,Defined 26e8 ; 26de C from color 0x26da 26e8 ; -------------------------------------------------------------------------------------- 26e8 26e8 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 26e9 0x26e9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 20 VR07:00 val_frame 7 26e9 26e9 seq_br_type 3 Unconditional Branch; Flow J 0x26eb seq_branch_adr 26eb 0x26eb typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 3c VR07:1c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 2 DEC_LOOP_COUNTER 26ea 26ea ioc_tvbs 1 typ+fiu; Flow C cc=False 0x2708 seq_br_type 4 Call False seq_branch_adr 2708 0x2708 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 2b TR02:0b typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 26eb 26eb fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x32d7 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 16 CSA/VAL_BUS 26ec 26ec fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=#0x0 0x26ef fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 26ef 0x26ef seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 0 PASS_A val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 6 26ed 26ed fiu_len_fill_lit 64 zero-fill 0x24; Flow C cc=True 0x2705 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2705 0x2705 seq_en_micro 0 26ee 26ee seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 26ef ; -------------------------------------------------------------------------------------- 26ef ; Comes from: 26ef ; 26ec C #0x0 from color 0x26ec 26ef ; -------------------------------------------------------------------------------------- 26ef 26ef fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True ; Flow J cc=False 0x2705 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2705 0x2705 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26f0 26f0 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x2705 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2705 0x2705 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26f1 26f1 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x2705 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2705 0x2705 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26f2 26f2 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x2705 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2705 0x2705 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26f3 26f3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26f4 26f4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26f5 26f5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26f6 26f6 fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x2705 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2705 0x2705 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 7 26f7 26f7 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True ; Flow J cc=False 0x2705 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2705 0x2705 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 26f8 26f8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x26ff fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 26ff 0x26ff typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 26f9 26f9 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26fa 26fa seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26fb 26fb seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 26fc 26fc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2703 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2703 0x2703 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 26fd 26fd fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2703 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2703 0x2703 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 26fe 26fe fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2703 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2703 0x2703 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_c_adr 30 GP0f val_c_source 0 FIU_BUS 26ff 26ff fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x2705 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2705 0x2705 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl 1 RESTORE_RDR val_a_adr 20 VR00:00 val_alu_func 1e A_AND_B val_b_adr 0f GP0f 2700 2700 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2702 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2702 0x2702 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE 2701 2701 fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32d9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 07 GP07 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2702 2702 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True ; Flow J cc=False 0x2705 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2705 0x2705 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 2703 2703 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x2705 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2705 0x2705 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_a_adr 20 VR00:00 val_alu_func 1e A_AND_B val_b_adr 0f GP0f 2704 2704 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32d9 seq_br_type 9 Return False seq_branch_adr 32d9 0x32d9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 20 VR00:00 val_alu_func 1e A_AND_B val_b_adr 0f GP0f 2705 2705 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2709 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2709 0x2709 seq_en_micro 0 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 07 GP07 val_alu_func 1b A_OR_B val_c_adr 38 GP07 val_c_mux_sel 2 ALU 2706 2706 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x26ea fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 26ea 0x26ea seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 06 Pop_stack+? typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 3c VR07:1c val_frame 7 2707 2707 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2708 0x2708 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2708 2708 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return typ_a_adr 35 TR07:15 typ_frame 7 val_alu_func 1d A_AND_NOT_B val_b_adr 3d VR07:1d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2709 ; -------------------------------------------------------------------------------------- 2709 ; Comes from: 2709 ; 2705 C #0x0 from color 0x0000 2709 ; 2727 C #0x0 from color 0x2715 2709 ; -------------------------------------------------------------------------------------- 2709 2709 ioc_load_wdr 0 ; Flow C 0x2ab4 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 20 VR08:00 val_alu_func 18 NOT_A_AND_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 270a 270a ioc_load_wdr 0 ; Flow C 0x2ab4 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 20 TR05:00 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR08:00 val_alu_func 18 NOT_A_AND_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 270b 270b ioc_load_wdr 0 ; Flow C 0x2ab4 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 20 VR08:00 val_alu_func 18 NOT_A_AND_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 270c 270c fiu_load_oreg 1 hold_oreg; Flow C 0x2ab4 fiu_offs_lit 40 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 21 TR05:01 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR08:00 val_alu_func 18 NOT_A_AND_B val_b_adr 07 GP07 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 270d ; -------------------------------------------------------------------------------------- 270d ; Comes from: 270d ; 25b8 C from color 0x25a7 270d ; 25d5 C from color 0x25cd 270d ; 26c8 C from color MACRO_Declare_Type_Variant_Record,Defined 270d ; 26e2 C from color 0x26da 270d ; -------------------------------------------------------------------------------------- 270d 270d fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 270e 0x270e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR07:16 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 270e 270e seq_br_type 3 Unconditional Branch; Flow J 0x2710 seq_branch_adr 2710 0x2710 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 2b VR08:0b val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 val_rand 2 DEC_LOOP_COUNTER 270f 270f seq_br_type 4 Call False; Flow C cc=False 0x2708 seq_branch_adr 2708 0x2708 seq_cond_sel 07 VAL.ALU_32_CO(late) val_alu_func 1 A_PLUS_B val_b_adr 2c VR07:0c val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand 2 DEC_LOOP_COUNTER 2710 2710 fiu_len_fill_lit 42 zero-fill 0x2; Flow C 0x32d7 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3a fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE val_b_adr 16 CSA/VAL_BUS 2711 2711 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=#0x0 0x2714 fiu_load_tar 1 hold_tar fiu_mem_start 9 start_continue_if_true fiu_offs_lit 20 fiu_op_sel 3 insert ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2714 0x2714 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 2712 2712 fiu_len_fill_lit 64 zero-fill 0x24; Flow C cc=True 0x2727 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2727 0x2727 seq_en_micro 0 2713 2713 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 2714 ; -------------------------------------------------------------------------------------- 2714 ; Comes from: 2714 ; 2711 C #0x0 from color 0x2711 2714 ; -------------------------------------------------------------------------------------- 2714 2714 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2715 2715 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x271c fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 271c 0x271c seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 07 GP07 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_frame 2 2716 2716 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2717 2717 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2718 2718 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2719 2719 fiu_mem_start 2 start-rd; Flow J 0x271e ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 271e 0x271e typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 271a 271a fiu_mem_start 2 start-rd; Flow J 0x271f ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 271f 0x271f typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 271b 271b seq_br_type 3 Unconditional Branch; Flow J 0x2720 seq_branch_adr 2720 0x2720 271c 271c seq_b_timing 0 Early Condition; Flow C cc=True 0x32d9 seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 271d 271d fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True ; Flow J cc=False 0x2727 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2727 0x2727 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 271e 271e seq_br_type 3 Unconditional Branch; Flow J 0x2723 seq_branch_adr 2723 0x2723 typ_alu_func 1a PASS_B typ_b_adr 31 TR11:11 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 271f 271f seq_br_type 3 Unconditional Branch; Flow J 0x2723 seq_branch_adr 2723 0x2723 typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 34 VR07:14 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 7 2720 2720 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 5 2721 2721 fiu_len_fill_lit 7a zero-fill 0x3a fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 3f VR02:1f val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 2722 2722 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 08 GP08 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 2723 2723 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 2724 2724 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x2726 fiu_load_tar 1 hold_tar fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 2726 0x2726 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 07 GP07 typ_c_adr 30 GP0f val_a_adr 31 VR02:11 val_c_adr 30 GP0f val_frame 2 2725 2725 ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 07 GP07 val_a_adr 0f GP0f val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2726 2726 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2727 0x2727 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl 1 RESTORE_RDR val_b_adr 0f GP0f 2727 ; -------------------------------------------------------------------------------------- 2727 ; Comes from: 2727 ; 2712 C True from color 0x2712 2727 ; -------------------------------------------------------------------------------------- 2727 2727 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=#0x0 0x2709 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2709 0x2709 seq_en_micro 0 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 3d VR06:1d val_alu_func 1b A_OR_B val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 6 2728 2728 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x270f ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 270f 0x270f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 06 Pop_stack+? typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 2729 2729 fiu_load_var 1 hold_var; Flow C cc=False 0x272b fiu_tivi_src 1 tar_val seq_br_type 4 Call False seq_branch_adr 272b 0x272b seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1b A_OR_B typ_b_adr 2f TR11:0f typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 08 GP08 val_alu_func 0 PASS_A 272a 272a fiu_len_fill_lit 40 zero-fill 0x0; Flow R cc=True ; Flow J cc=False 0x2708 fiu_offs_lit 50 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 8 Return True seq_branch_adr 2708 0x2708 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 272b ; -------------------------------------------------------------------------------------- 272b ; Comes from: 272b ; 2729 C False from color 0x26e8 272b ; -------------------------------------------------------------------------------------- 272b 272b seq_br_type a Unconditional Return; Flow R val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 272c ; -------------------------------------------------------------------------------------- 272c ; Comes from: 272c ; 1493 C True from color 0x09ac 272c ; 177b C from color 0x09ae 272c ; 1822 C from color 0x09ad 272c ; 1864 C True from color 0x09ab 272c ; 1ba6 C from color 0x1ba5 272c ; 1def C from color 0x0000 272c ; -------------------------------------------------------------------------------------- 272c 272c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 272d 272d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x2738 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2738 0x2738 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 01 GP01 272e 272e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2733 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2733 0x2733 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR 272f 272f fiu_fill_mode_src 0 ; Flow J 0x2730 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2730 0x2730 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2730 2730 fiu_fill_mode_src 0 ; Flow J cc=False 0x2735 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2735 0x2735 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2731 2731 fiu_fill_mode_src 0 ; Flow C 0x2ab4 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 2732 2732 fiu_vmux_sel 1 fill value; Flow R ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2733 2733 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2734 2734 fiu_fill_mode_src 0 ; Flow J 0x2730 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2730 0x2730 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2735 2735 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2736 2736 fiu_fill_mode_src 0 ; Flow C 0x2ab4 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 2737 2737 fiu_vmux_sel 1 fill value; Flow R ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2738 2738 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x273f fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 273f 0x273f seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 14 ZEROS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2739 2739 fiu_load_tar 1 hold_tar; Flow J cc=True 0x274c fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 274c 0x274c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B 273a 273a fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 273b 273b fiu_fill_mode_src 0 ; Flow J 0x2742 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2742 0x2742 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 273c 273c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 273d 273d fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x272e fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 272e 0x272e seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 01 GP01 273e 273e fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x2739 fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2739 0x2739 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 14 ZEROS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 273f 273f fiu_load_tar 1 hold_tar; Flow J cc=True 0x274c fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 274c 0x274c 2740 2740 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 2741 2741 fiu_fill_mode_src 0 ; Flow J 0x2742 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2742 0x2742 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2742 2742 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2746 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2746 0x2746 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 39 TR02:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2743 2743 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA 2744 2744 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2749 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2749 0x2749 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 2745 2745 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x2732 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 2732 0x2732 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B 2746 2746 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 2747 2747 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2749 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2749 0x2749 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 2748 2748 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x2732 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 2732 0x2732 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B 2749 ; -------------------------------------------------------------------------------------- 2749 ; Comes from: 2749 ; 2744 C True from color 0x272c 2749 ; 2747 C True from color 0x272c 2749 ; 2760 C True from color 0x272c 2749 ; 2764 C True from color 0x272c 2749 ; 276b C True from color 0x272c 2749 ; 2771 C True from color 0x272c 2749 ; 2776 C True from color 0x272c 2749 ; -------------------------------------------------------------------------------------- 2749 2749 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 274a 274a fiu_mem_start 2 start-rd 274b 274b seq_br_type a Unconditional Return; Flow R 274c 274c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2753 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2753 0x2753 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 4 274d 274d fiu_fill_mode_src 0 ; Flow J cc=True 0x275b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 275b 0x275b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 274e 274e fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1e typ_mar_cntl b LOAD_MAR_DATA val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 274f 274f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2757 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2757 0x2757 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2750 2750 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 2751 2751 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2752 2752 ioc_tvbs 1 typ+fiu; Flow R cc=False ; Flow J cc=True 0x275b seq_br_type 9 Return False seq_branch_adr 275b 0x275b seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2753 2753 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 2 2754 2754 fiu_fill_mode_src 0 ; Flow J cc=True 0x275b fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 275b 0x275b seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2755 2755 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1e typ_mar_cntl b LOAD_MAR_DATA val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2756 2756 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2750 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2750 0x2750 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2757 2757 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 2758 2758 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2759 2759 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 275a 0x275a seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 275a 275a ioc_tvbs 1 typ+fiu; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 275b 0x275b seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 275b 275b fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x273c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 273c 0x273c seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 275c 275c fiu_mem_start 4 continue; Flow J cc=False 0x2766 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2766 0x2766 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 275d 275d fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 275e 275e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32cc seq_br_type 5 Call True seq_branch_adr 32cc 0x32cc seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 27 TR02:07 typ_frame 2 275f 275f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2764 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2764 0x2764 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2760 2760 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2749 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2749 0x2749 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2761 2761 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2762 0x2762 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 2762 2762 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2763 2763 fiu_load_oreg 1 hold_oreg; Flow J 0x275f fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 275f 0x275f typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2764 2764 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2749 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2749 0x2749 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2765 2765 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x273c seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 273c 0x273c seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 2766 2766 fiu_load_var 1 hold_var; Flow J cc=False 0x2774 fiu_tivi_src 1 tar_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2774 0x2774 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2767 2767 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2768 2768 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 01 GP01 val_alu_func 0 PASS_A 2769 2769 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32cc seq_br_type 5 Call True seq_branch_adr 32cc 0x32cc seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 27 TR02:07 typ_frame 2 276a 276a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x276f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 276f 0x276f typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 276b 276b fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2749 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2749 0x2749 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 276c 276c ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 276d 0x276d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 276d 276d fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 276e 276e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x276a fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 276a 0x276a typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 276f 276f fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2770 2770 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2771 0x2771 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 2771 2771 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x2749 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2749 0x2749 seq_cond_sel 67 REFRESH_MACRO_EVENT 2772 2772 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2773 0x2773 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2773 2773 ioc_tvbs 2 fiu+val; Flow R cc=True ; Flow J cc=False 0x273c seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 273c 0x273c seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 2774 2774 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 2775 2775 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 2776 2776 ioc_fiubs 0 fiu ; Flow C cc=True 0x2749 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2749 0x2749 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2777 2777 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True ; Flow J cc=False 0x273c seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 273c 0x273c seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 2778 ; -------------------------------------------------------------------------------------- 2778 ; 0x02cb Declare_Variable Entry 2778 ; -------------------------------------------------------------------------------------- 2778 MACRO_Declare_Variable_Entry: 2778 2778 dispatch_brk_class 4 ; Flow C cc=False 0x32dc dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2778 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 25 TR05:05 typ_frame 5 val_a_adr 3b VR06:1b val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_frame 6 2779 2779 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 277a 277a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 32 TR02:12 typ_frame 2 typ_rand 9 PASS_A_HIGH val_a_adr 21 VR02:01 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 val_rand a PASS_B_HIGH 277b 277b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x277f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 277f 0x277f seq_int_reads 6 CONTROL TOP val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 277c 277c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 14 ZEROS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 2 DEC_LOOP_COUNTER 277d 277d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a9 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 277e 277e fiu_len_fill_lit 58 zero-fill 0x18; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 1c ? typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 277f ; -------------------------------------------------------------------------------------- 277f ; Comes from: 277f ; 277b C True from color MACRO_Declare_Variable_Entry 277f ; 2785 C True from color 0x0000 277f ; -------------------------------------------------------------------------------------- 277f 277f seq_br_type a Unconditional Return; Flow R val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2780 ; -------------------------------------------------------------------------------------- 2780 ; 0x02c9 Declare_Variable Family 2780 ; -------------------------------------------------------------------------------------- 2780 MACRO_Declare_Variable_Family: 2780 2780 dispatch_brk_class 4 ; Flow C cc=False 0x32dc dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2780 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 25 TR05:05 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 3b VR06:1b val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_frame 6 2781 2781 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_b_adr 20 TR02:00 typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 2782 2782 fiu_tivi_src 1 tar_val; Flow C cc=False 0x32dc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 val_rand 2 DEC_LOOP_COUNTER 2783 2783 fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=False 0x2792 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2792 0x2792 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 30 VR05:10 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 2784 2784 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a9 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 32a9 0x32a9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2785 2785 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x277f seq_br_type 5 Call True seq_branch_adr 277f 0x277f seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_frame 4 val_rand a PASS_B_HIGH 2786 2786 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x278d seq_br_type 5 Call True seq_branch_adr 278d 0x278d seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3f TR06:1f typ_frame 6 2787 2787 fiu_load_oreg 1 hold_oreg fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 2788 2788 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2788 fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2788 0x2788 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2789 2789 fiu_len_fill_lit 58 zero-fill 0x18; Flow J cc=True 0x2790 fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 2790 0x2790 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 20 TOP - 0x1 typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 278a 278a seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 278b 278b fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 278c 278c fiu_mem_start 3 start-wr; Flow J 0x2788 seq_br_type 3 Unconditional Branch seq_branch_adr 2788 0x2788 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A val_a_adr 30 VR05:10 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 278d ; -------------------------------------------------------------------------------------- 278d ; Comes from: 278d ; 2786 C True from color 0x0000 278d ; -------------------------------------------------------------------------------------- 278d 278d fiu_len_fill_lit 79 zero-fill 0x39 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 01 GP01 278e 278e ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 278f 278f fiu_len_fill_lit 50 zero-fill 0x10; Flow J 0xf96 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 0f96 0x0f96 2790 2790 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 02 GP02 2791 2791 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_b_adr 3b TR06:1b typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2792 2792 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR01:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_mar_cntl b LOAD_MAR_DATA 2793 2793 fiu_tivi_src c mar_0xc; Flow C cc=False 0x32dc ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_c_adr 3f GP00 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2794 2794 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2790 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2790 0x2790 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 6 CONTROL TOP typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2795 2795 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 2796 ; -------------------------------------------------------------------------------------- 2796 ; 0x02cf Declare_Variable Select 2796 ; -------------------------------------------------------------------------------------- 2796 MACRO_Declare_Variable_Select: 2796 2796 dispatch_brk_class 4 ; Flow J 0x2799 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2796 ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2799 0x2799 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 34 TR05:14 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2797 ; -------------------------------------------------------------------------------------- 2797 ; Comes from: 2797 ; 279a C True from color 0x0000 2797 ; -------------------------------------------------------------------------------------- 2797 2797 seq_br_type a Unconditional Return; Flow R typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 21 TR00:01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 2798 ; -------------------------------------------------------------------------------------- 2798 ; 0x02ce Declare_Variable Select,Choice_Open 2798 ; -------------------------------------------------------------------------------------- 2798 MACRO_Declare_Variable_Select,Choice_Open: 2798 2798 dispatch_brk_class 4 ; Flow J 0x2799 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2798 ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2799 0x2799 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 20 TR06:00 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2799 2799 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x27b3 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 27b3 0x27b3 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 1d TOP - 3 typ_b_adr 1e TOP - 2 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_alu_func 1a PASS_B val_b_adr 1d TOP - 3 279a 279a seq_b_timing 1 Latch Condition; Flow C cc=True 0x2797 seq_br_type 5 Call True seq_branch_adr 2797 0x2797 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 279b 279b fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x32e2 fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 32e2 0x32e2 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_b_adr 32 TR02:12 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 279c 279c fiu_load_var 1 hold_var; Flow C cc=True 0x32dc fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dc 0x32dc seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 279d 279d fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 30 VR06:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 val_rand a PASS_B_HIGH 279e 279e fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 3e TR05:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1 A_PLUS_B val_b_adr 2f VR05:0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 279f 279f fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x27a6 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 27a6 0x27a6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR02:1f typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 27a0 27a0 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_mar_cntl 6 INCREMENT_MAR val_a_adr 26 VR07:06 val_frame 7 27a1 27a1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 27a2 27a2 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_mdr 1 hold_mdr fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 27a3 27a3 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 6d fiu_op_sel 3 insert ioc_adrbs 1 val typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_frame 2 27a4 27a4 ioc_load_wdr 0 ; Flow C 0x2ab4 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 val_rand 2 DEC_LOOP_COUNTER 27a5 27a5 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x27a0 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 27a0 0x27a0 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 27a6 27a6 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x27ae ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 27ae 0x27ae seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 27a7 27a7 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_alu_func 1b A_OR_B typ_b_adr 27 TR02:07 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 26 VR07:06 val_frame 7 27a8 27a8 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 27a9 27a9 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_mdr 1 hold_mdr fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 27aa 27aa fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 6d fiu_op_sel 3 insert ioc_adrbs 1 val typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 33 TR11:13 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 27ab 27ab fiu_mem_start 4 continue ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 36 TR02:16 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME 27ac 27ac fiu_tivi_src 2 tar_fiu; Flow C 0x2ab4 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_random 02 ? typ_a_adr 14 ZEROS typ_b_adr 02 GP02 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 27ad 27ad fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x27a7 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 27a7 0x27a7 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU 27ae 27ae fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x27b0 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27b0 0x27b0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 37 TR05:17 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 03 GP03 27af 27af fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 14 ZEROS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 27b0 27b0 ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_csa_cntl 1 START_POP_DOWN val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 27b1 27b1 ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 7 FINISH_POP_DOWN typ_rand c WRITE_OUTER_FRAME val_a_adr 05 GP05 val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 27b2 27b2 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 27b3 27b3 seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x32e2 seq_br_type 9 Return False seq_branch_adr 32e2 0x32e2 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 2a TR07:0a typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 7 27b4 ; -------------------------------------------------------------------------------------- 27b4 ; 0x0271 Execute Discrete,Times 27b4 ; -------------------------------------------------------------------------------------- 27b4 MACRO_Execute_Discrete,Times: 27b4 27b4 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 27b4 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 27b5 27b5 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 27b6 0x27b6 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 27b6 27b6 ioc_fiubs 0 fiu ; Flow J cc=True 0x27c7 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 27c7 0x27c7 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 seq_random 02 ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27b7 27b7 seq_b_timing 1 Latch Condition; Flow J cc=False 0x27ba seq_br_type 0 Branch False seq_branch_adr 27ba 0x27ba seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27b8 27b8 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 27b9 0x27b9 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27b9 27b9 seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 seq_en_micro 0 seq_random 02 ? 27ba 27ba seq_b_timing 1 Latch Condition; Flow J cc=True 0x27c0 seq_br_type 1 Branch True seq_branch_adr 27c0 0x27c0 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_rand e PRODUCT_LEFT_32 27bb 27bb seq_b_timing 1 Latch Condition; Flow J cc=True 0x27bd seq_br_type 1 Branch True seq_branch_adr 27bd 0x27bd seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 2e TR06:0e typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27bc 27bc fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27bf fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27bf 0x27bf seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 27bd 27bd seq_b_timing 1 Latch Condition; Flow C cc=True 0x32a8 seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27be 27be fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32a8 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_alu_func 0 PASS_A 27bf 27bf fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x27b9 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 27b9 0x27b9 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 27c0 27c0 seq_b_timing 1 Latch Condition; Flow C cc=True 0x32a8 seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_m_b_src 1 Bits 16…31 27c1 27c1 seq_b_timing 1 Latch Condition; Flow J cc=False 0x27c3 seq_br_type 0 Branch False seq_branch_adr 27c3 0x27c3 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 35 TR06:15 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27c2 27c2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27c6 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27c6 0x27c6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 27c3 27c3 fiu_load_var 1 hold_var; Flow C cc=True 0x32a8 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27c4 27c4 fiu_load_var 1 hold_var; Flow C cc=False 0x32a8 fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 27c5 27c5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x27b9 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 27b9 0x27b9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 27c6 27c6 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x27b9 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 27b9 0x27b9 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 27c7 27c7 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 11 TOP + 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 27c8 27c8 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x27cd seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 27cd 0x27cd seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 27c9 27c9 ioc_fiubs 1 val ; Flow J cc=True 0x27ce ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 27ce 0x27ce seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 27ca 27ca fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 27cb 27cb fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 27cc 0x27cc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 27cc 27cc ioc_fiubs 0 fiu ; Flow J 0x27b7 seq_br_type 3 Unconditional Branch seq_branch_adr 27b7 0x27b7 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27cd 27cd fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 1b A_OR_B val_b_adr 11 TOP + 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 27ce 27ce ioc_fiubs 1 val ; Flow J cc=True 0x27df seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 27df 0x27df seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 27cf 27cf ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27d0 27d0 seq_b_timing 1 Latch Condition; Flow J cc=False 0x27d2 seq_br_type 0 Branch False seq_branch_adr 27d2 0x27d2 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27d1 27d1 seq_br_type 3 Unconditional Branch; Flow J 0x27df seq_branch_adr 27df 0x27df seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27d2 27d2 seq_b_timing 1 Latch Condition; Flow J cc=True 0x27d8 seq_br_type 1 Branch True seq_branch_adr 27d8 0x27d8 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_rand e PRODUCT_LEFT_32 27d3 27d3 seq_b_timing 1 Latch Condition; Flow J cc=True 0x27d5 seq_br_type 1 Branch True seq_branch_adr 27d5 0x27d5 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 2e TR06:0e typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27d4 27d4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27d7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27d7 0x27d7 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 27d5 27d5 seq_b_timing 1 Latch Condition; Flow C cc=True 0x32a8 seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27d6 27d6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32a8 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_alu_func 0 PASS_A 27d7 27d7 ioc_tvbs 1 typ+fiu; Flow J 0x27df seq_br_type 3 Unconditional Branch seq_branch_adr 27df 0x27df seq_en_micro 0 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 27d8 27d8 seq_b_timing 1 Latch Condition; Flow C cc=True 0x32a8 seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_m_b_src 1 Bits 16…31 27d9 27d9 seq_b_timing 1 Latch Condition; Flow J cc=False 0x27db seq_br_type 0 Branch False seq_branch_adr 27db 0x27db seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 35 TR06:15 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27da 27da fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27de fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27de 0x27de seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 27db 27db fiu_load_var 1 hold_var; Flow C cc=True 0x32a8 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27dc 27dc fiu_load_var 1 hold_var; Flow C cc=False 0x32a8 fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 27dd 27dd fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x27df fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 27df 0x27df seq_en_micro 0 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 27de 27de ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 27df 27df fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x27b9 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 27b9 0x27b9 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 27e0 ; -------------------------------------------------------------------------------------- 27e0 ; 0x026d Execute Discrete,Exponentiate 27e0 ; -------------------------------------------------------------------------------------- 27e0 MACRO_Execute_Discrete,Exponentiate: 27e0 27e0 dispatch_brk_class 8 ; Flow J cc=False 0x2801 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 27e0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type 0 Branch False seq_branch_adr 2801 0x2801 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 3a VR02:1a val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_frame 2 27e1 27e1 ioc_fiubs 1 val ; Flow C cc=True 0x280b seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 280b 0x280b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3a VR02:1a val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 27e2 27e2 fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 3f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu 27e3 27e3 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=True 0x27e4 ; Flow J cc=#0x0 0x27e4 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 27e4 0x27e4 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 27e4 27e4 ioc_fiubs 1 val ; Flow J 0x27e6 seq_br_type 3 Unconditional Branch seq_branch_adr 27e6 0x27e6 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand c START_MULTIPLY 27e5 27e5 fiu_load_var 1 hold_var; Flow J 0x27ed fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 27ed 0x27ed seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 1b A_OR_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand c START_MULTIPLY 27e6 27e6 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x27ea fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 27ea 0x27ea seq_en_micro 0 typ_b_adr 03 GP03 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 27e7 27e7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a8 seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 04 GP04 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27e8 27e8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27e9 27e9 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_b_adr 03 GP03 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27ea 27ea fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=True 0x27eb ; Flow J cc=#0x0 0x27e4 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 27e4 0x27e4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 27eb 27eb seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 27ec 27ec ioc_fiubs 0 fiu ; Flow J 0x27ea seq_br_type 3 Unconditional Branch seq_branch_adr 27ea 0x27ea 27ed 27ed ioc_fiubs 1 val ; Flow J cc=True 0x27fd seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 27fd 0x27fd seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 16 PRODUCT val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_m_b_src 2 Bits 32…47 27ee 27ee ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27ef 27ef seq_b_timing 1 Latch Condition; Flow J cc=False 0x27f1 seq_br_type 0 Branch False seq_branch_adr 27f1 0x27f1 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 27f0 27f0 seq_br_type 3 Unconditional Branch; Flow J 0x27fd seq_branch_adr 27fd 0x27fd seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 27f1 27f1 seq_b_timing 1 Latch Condition; Flow J cc=True 0x27f7 seq_br_type 1 Branch True seq_branch_adr 27f7 0x27f7 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_rand e PRODUCT_LEFT_32 27f2 27f2 seq_b_timing 1 Latch Condition; Flow J cc=True 0x27f4 seq_br_type 1 Branch True seq_branch_adr 27f4 0x27f4 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 2e TR06:0e typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 1 ALU >> 16 val_m_a_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27f3 27f3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27f6 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27f6 0x27f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_a_adr 04 GP04 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 27f4 27f4 seq_b_timing 1 Latch Condition; Flow C cc=True 0x32a8 seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27f5 27f5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32a8 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 0 PASS_A 27f6 27f6 ioc_tvbs 1 typ+fiu; Flow J 0x27fd seq_br_type 3 Unconditional Branch seq_branch_adr 27fd 0x27fd seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 27f7 27f7 seq_b_timing 1 Latch Condition; Flow C cc=True 0x32a8 seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 33 TR06:13 typ_frame 6 val_m_b_src 1 Bits 16…31 27f8 27f8 seq_b_timing 1 Latch Condition; Flow J cc=False 0x27fa seq_br_type 0 Branch False seq_branch_adr 27fa 0x27fa seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 35 TR06:15 typ_frame 6 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 27f9 27f9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x27f6 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27f6 0x27f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 val_a_adr 04 GP04 val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 27fa 27fa fiu_load_var 1 hold_var; Flow C cc=True 0x32a8 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 27fb 27fb fiu_load_var 1 hold_var; Flow C cc=False 0x32a8 fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 27fc 27fc fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x27fd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 27fd 0x27fd seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 27fd 27fd ioc_fiubs 2 typ ; Flow J cc=True 0x27e4 seq_br_type 1 Branch True seq_branch_adr 27e4 0x27e4 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 27fe 27fe seq_b_timing 0 Early Condition; Flow J cc=False 0x2800 seq_br_type 0 Branch False seq_branch_adr 2800 0x2800 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 27ff 27ff fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x27b9 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 27b9 0x27b9 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2800 2800 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x27b9 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 27b9 0x27b9 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2801 2801 ioc_tvbs 2 fiu+val; Flow J cc=True 0x280a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 280a 0x280a seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 20 TR05:00 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 val_a_adr 1f TOP - 1 val_alu_func 3 LEFT_I_A 2802 2802 ioc_tvbs 2 fiu+val; Flow J cc=True 0x2805 seq_br_type 1 Branch True seq_branch_adr 2805 0x2805 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2f TR11:0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 14 ZEROS val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand b DIVIDE 2803 2803 ioc_tvbs 2 fiu+val; Flow J cc=True 0x27ff seq_br_type 1 Branch True seq_branch_adr 27ff 0x27ff seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2804 2804 seq_br_type 7 Unconditional Call; Flow C 0x32a0 seq_branch_adr 32a0 0x32a0 2805 2805 ioc_fiubs 1 val seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 05 GP05 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand c START_MULTIPLY 2806 2806 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2807 0x2807 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 2807 2807 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a8 seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 04 GP04 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2808 2808 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2809 2809 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x27b9 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 27b9 0x27b9 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 280a 280a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 280b 280b fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x280e fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 280e 0x280e seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 280c 280c seq_b_timing 3 Late Condition, Hint False; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 280d 0x280d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3a VR02:1a val_frame 2 280d 280d fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x2812 fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2812 0x2812 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 05 GP05 280e 280e fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x280f ; Flow J cc=#0x0 0x280f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 280f 0x280f seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 280f 280f fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x27b9 ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 27b9 0x27b9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 32 VR06:12 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 6 2810 2810 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2811 2811 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x27b9 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 27b9 0x27b9 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 30 VR05:10 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 5 2812 2812 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x2813 ; Flow J cc=#0x0 0x2813 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 2813 0x2813 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 2813 2813 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2814 2814 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2815 2815 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a8 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 30 VR05:10 val_frame 5 2816 2816 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2817 2817 <halt> ; Flow R 2818 ; -------------------------------------------------------------------------------------- 2818 ; 0x0141 Execute Discrete,Multiply_And_Scale 2818 ; -------------------------------------------------------------------------------------- 2818 MACRO_Execute_Discrete,Multiply_And_Scale: 2818 2818 dispatch_brk_class 8 ; Flow C cc=False 0x2832 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2818 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 2832 0x2832 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 2819 2819 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x2834 fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 2834 0x2834 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 281a 281a fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 281b 281b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 15 ZERO_COUNTER val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 281c 281c fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 1f TOP - 1 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand c START_MULTIPLY 281d 281d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 1 Bits 16…31 val_rand e PRODUCT_LEFT_32 281e 281e seq_br_type 0 Branch False; Flow J cc=False 0x2835 seq_branch_adr 2835 0x2835 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 2b TR02:0b typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 281f 281f ioc_tvbs 2 fiu+val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 35 TR07:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 2820 2820 seq_b_timing 0 Early Condition; Flow J cc=True 0x282f seq_br_type 1 Branch True seq_branch_adr 282f 0x282f seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 2821 2821 ioc_tvbs 2 fiu+val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 24 TR11:04 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 2 Bits 32…47 2822 2822 seq_b_timing 0 Early Condition; Flow J cc=True 0x282a seq_br_type 1 Branch True seq_branch_adr 282a 0x282a seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 2823 2823 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand e PRODUCT_LEFT_32 2824 2824 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 1 ALU >> 16 val_m_b_src 2 Bits 32…47 2825 2825 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 2826 2826 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 2827 2827 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 0 Bits 0…15 2828 2828 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2829 2829 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 282a 282a seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 282b 282b seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 282c 282c seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 1 ALU >> 16 282d 282d seq_br_type 3 Unconditional Branch; Flow J 0x282f seq_branch_adr 282f 0x282f seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 282e 282e seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a8 seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 282f 282f fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x282e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 282e 0x282e seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_alu_func 0 PASS_A val_a_adr 02 GP02 2830 2830 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x27df fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 27df 0x27df typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 2f TOP val_c_source 0 FIU_BUS 2831 2831 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32a8 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a8 0x32a8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 2832 2832 seq_br_type 0 Branch False; Flow J cc=False 0x2835 seq_branch_adr 2835 0x2835 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 2833 2833 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 seq_latch 1 typ_csa_cntl 2 PUSH_CSA 2834 2834 seq_br_type 1 Branch True; Flow J cc=True 0x2833 seq_branch_adr 2833 0x2833 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 2835 2835 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2836 ; -------------------------------------------------------------------------------------- 2836 ; 0x0247 Execute Float,Equal 2836 ; -------------------------------------------------------------------------------------- 2836 MACRO_Execute_Float,Equal: 2836 2836 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2836 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2837 2837 <halt> ; Flow R 2838 ; -------------------------------------------------------------------------------------- 2838 ; 0x014e Execute Float,Equal_Zero 2838 ; -------------------------------------------------------------------------------------- 2838 MACRO_Execute_Float,Equal_Zero: 2838 2838 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2838 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 2839 2839 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 11 TOP + 1 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 283a ; -------------------------------------------------------------------------------------- 283a ; 0x0245 Execute Float,Greater 283a ; -------------------------------------------------------------------------------------- 283a MACRO_Execute_Float,Greater: 283a 283a dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 283a ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 283b 283b fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2839 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2839 0x2839 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 283c ; -------------------------------------------------------------------------------------- 283c ; 0x014c Execute Float,Greater_Zero 283c ; -------------------------------------------------------------------------------------- 283c MACRO_Execute_Float,Greater_Zero: 283c 283c dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 283c fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 283d 283d <halt> ; Flow R 283e ; -------------------------------------------------------------------------------------- 283e ; 0x0246 Execute Float,Not_Equal 283e ; -------------------------------------------------------------------------------------- 283e MACRO_Execute_Float,Not_Equal: 283e 283e dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 283e fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 283f 283f <halt> ; Flow R 2840 ; -------------------------------------------------------------------------------------- 2840 ; 0x014d Execute Float,Not_Equal_Zero 2840 ; -------------------------------------------------------------------------------------- 2840 MACRO_Execute_Float,Not_Equal_Zero: 2840 2840 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2840 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 2841 2841 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 6 A_MINUS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2842 ; -------------------------------------------------------------------------------------- 2842 ; 0x0244 Execute Float,Less 2842 ; -------------------------------------------------------------------------------------- 2842 MACRO_Execute_Float,Less: 2842 2842 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2842 ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2843 2843 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2841 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2841 0x2841 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2844 ; -------------------------------------------------------------------------------------- 2844 ; 0x014b Execute Float,Less_Zero 2844 ; -------------------------------------------------------------------------------------- 2844 MACRO_Execute_Float,Less_Zero: 2844 2844 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2844 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 2845 2845 <halt> ; Flow R 2846 ; -------------------------------------------------------------------------------------- 2846 ; 0x0243 Execute Float,Greater_Equal 2846 ; -------------------------------------------------------------------------------------- 2846 MACRO_Execute_Float,Greater_Equal: 2846 2846 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2846 ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2847 2847 fiu_mem_start 2 start-rd; Flow R cc=False fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2848 0x2848 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2848 2848 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 11 TOP + 1 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2849 2849 <halt> ; Flow R 284a ; -------------------------------------------------------------------------------------- 284a ; 0x014a Execute Float,Greater_Equal_Zero 284a ; -------------------------------------------------------------------------------------- 284a MACRO_Execute_Float,Greater_Equal_Zero: 284a 284a dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 284a fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 284b 284b fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 5 DEC_A_MINUS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 284c ; -------------------------------------------------------------------------------------- 284c ; 0x0242 Execute Float,Less_Equal 284c ; -------------------------------------------------------------------------------------- 284c MACRO_Execute_Float,Less_Equal: 284c 284c dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 284c ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 284d 284d fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x284b fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 284b 0x284b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 284e ; -------------------------------------------------------------------------------------- 284e ; 0x0149 Execute Float,Less_Equal_Zero 284e ; -------------------------------------------------------------------------------------- 284e MACRO_Execute_Float,Less_Equal_Zero: 284e 284e dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 284e fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 284f 284f <halt> ; Flow R 2850 ; -------------------------------------------------------------------------------------- 2850 ; 0x0241 Execute Float,First 2850 ; -------------------------------------------------------------------------------------- 2850 MACRO_Execute_Float,First: 2850 2850 dispatch_brk_class 8 ; Flow J 0x2851 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2850 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg seq_br_type 3 Unconditional Branch seq_branch_adr 2851 0x2851 typ_b_adr 10 TOP typ_frame 8 typ_rand a PASS_B_HIGH 2851 2851 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2852 ; -------------------------------------------------------------------------------------- 2852 ; 0x0240 Execute Float,Last 2852 ; -------------------------------------------------------------------------------------- 2852 MACRO_Execute_Float,Last: 2852 2852 dispatch_brk_class 8 ; Flow J 0x2851 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2852 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 seq_br_type 3 Unconditional Branch seq_branch_adr 2851 0x2851 typ_b_adr 10 TOP typ_frame 8 typ_rand a PASS_B_HIGH 2853 2853 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 2854 ; -------------------------------------------------------------------------------------- 2854 ; 0x023f Execute Float,Unary_Minus 2854 ; -------------------------------------------------------------------------------------- 2854 MACRO_Execute_Float,Unary_Minus: 2854 2854 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2854 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2855 2855 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2853 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2853 0x2853 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2856 ; -------------------------------------------------------------------------------------- 2856 ; 0x023e Execute Float,Absolute_Value 2856 ; -------------------------------------------------------------------------------------- 2856 MACRO_Execute_Float,Absolute_Value: 2856 2856 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2856 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2857 2857 seq_br_type 7 Unconditional Call; Flow C 0x329e seq_branch_adr 329e 0x329e seq_en_micro 0 seq_random 02 ? 2858 ; -------------------------------------------------------------------------------------- 2858 ; 0x023d Execute Float,Plus 2858 ; -------------------------------------------------------------------------------------- 2858 MACRO_Execute_Float,Plus: 2858 2858 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2858 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 3 LEFT_I_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2859 2859 fiu_len_fill_lit 4a zero-fill 0xa fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 08 VAL.ALU_CARRY(late) seq_latch 1 typ_a_adr 3c TR08:1c typ_alu_func 1b A_OR_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 285a 285a fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=False 0x286b fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 286b 0x286b typ_a_adr 3c TR08:1c typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 10 TOP 285b 285b fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2866 fiu_load_mdr 1 hold_mdr fiu_offs_lit 0b fiu_rdata_src 0 rotator ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2866 0x2866 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 8 val_a_adr 3c VR08:1c val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 285c 285c fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2874 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2874 0x2874 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 285d 285d fiu_len_fill_lit 73 zero-fill 0x33; Flow J 0x285e fiu_load_var 1 hold_var fiu_offs_lit 4a fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 285e 0x285e seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 285e 285e fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2864 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2864 0x2864 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 285f 285f ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2873 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2873 0x2873 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 2a TR02:0a typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 04 GP04 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 2860 2860 fiu_len_fill_lit 74 zero-fill 0x34 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 05 GP05 2861 2861 fiu_fill_mode_src 0 ; Flow J cc=False 0x2876 fiu_len_fill_lit 73 zero-fill 0x33 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 2876 0x2876 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 2862 2862 fiu_len_fill_lit 4b zero-fill 0xb; Flow C cc=True 0x32a8 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR09:02 typ_frame 9 2863 2863 fiu_len_fill_lit 73 zero-fill 0x33; Flow R cc=False ; Flow J cc=True 0x2865 fiu_mem_start 2 start-rd fiu_offs_lit 4c fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2865 0x2865 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2864 2864 seq_b_timing 0 Early Condition; Flow J cc=False 0x2870 seq_br_type 0 Branch False seq_branch_adr 2870 0x2870 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2865 2865 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 1b A_OR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2866 2866 fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2874 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2874 0x2874 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 2867 2867 fiu_len_fill_lit 74 zero-fill 0x34; Flow J 0x285e fiu_load_var 1 hold_var fiu_offs_lit 49 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 285e 0x285e seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2868 ; -------------------------------------------------------------------------------------- 2868 ; 0x023c Execute Float,Minus 2868 ; -------------------------------------------------------------------------------------- 2868 MACRO_Execute_Float,Minus: 2868 2868 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2868 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 3 LEFT_I_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2869 2869 fiu_len_fill_lit 4a zero-fill 0xa fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 08 VAL.ALU_CARRY(late) seq_latch 1 typ_a_adr 3c TR08:1c typ_alu_func 1b A_OR_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 286a 286a fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x285b fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 285b 0x285b seq_random 02 ? typ_a_adr 3c TR08:1c typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 286b 286b fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2871 fiu_load_mdr 1 hold_mdr fiu_offs_lit 0b fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2871 0x2871 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_frame 8 val_a_adr 3c VR08:1c val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 8 286c 286c fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2875 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2875 0x2875 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 02 GP02 val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 286d 286d fiu_len_fill_lit 73 zero-fill 0x33; Flow J 0x286e fiu_load_var 1 hold_var fiu_offs_lit 4a fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 286e 0x286e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 286e 286e fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x285f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 285f 0x285f seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 286f 286f seq_b_timing 0 Early Condition; Flow J cc=True 0x2865 seq_br_type 1 Branch True seq_branch_adr 2865 0x2865 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 10 TOP val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2870 2870 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 18 NOT_A_AND_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2871 2871 fiu_len_fill_lit 76 zero-fill 0x36; Flow J cc=True 0x2875 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2875 0x2875 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 02 GP02 val_a_adr 02 GP02 val_alu_func 2 INC_A_PLUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 2872 2872 fiu_len_fill_lit 74 zero-fill 0x34; Flow J 0x286e fiu_load_var 1 hold_var fiu_offs_lit 49 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 286e 0x286e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2873 2873 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2874 2874 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2875 2875 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2876 2876 fiu_len_fill_lit 74 zero-fill 0x34; Flow J cc=False 0x2873 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 0 Branch False seq_branch_adr 2873 0x2873 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR11:17 typ_frame 11 2877 2877 fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x2865 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2865 0x2865 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2878 ; -------------------------------------------------------------------------------------- 2878 ; 0x023b Execute Float,Times 2878 ; -------------------------------------------------------------------------------------- 2878 MACRO_Execute_Float,Times: 2878 2878 dispatch_brk_class 8 ; Flow J cc=True 0x289f dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2878 fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 289f 0x289f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 2879 2879 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 3c TR08:1c typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR06:12 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 287a 287a fiu_len_fill_lit 74 zero-fill 0x34; Flow J cc=True 0x289f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 289f 0x289f seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 2d VR1b:0d val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1b 287b 287b ioc_tvbs 1 typ+fiu; Flow J cc=True 0x288c seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 288c 0x288c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3d TR08:1d typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 287c 287c seq_b_timing 0 Early Condition; Flow J cc=True 0x2899 seq_br_type 1 Branch True seq_branch_adr 2899 0x2899 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 287d 287d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 287e 287e seq_b_timing 1 Latch Condition; Flow J cc=True 0x28a0 seq_br_type 1 Branch True seq_branch_adr 28a0 0x28a0 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 287f 287f seq_b_timing 1 Latch Condition; Flow J cc=True 0x28a4 seq_br_type 1 Branch True seq_branch_adr 28a4 0x28a4 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 1 Bits 16…31 2880 2880 seq_br_type 0 Branch False; Flow J cc=False 0x28a8 seq_branch_adr 28a8 0x28a8 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR08:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 2881 2881 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28a8 seq_br_type 1 Branch True seq_branch_adr 28a8 0x28a8 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR09:00 typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 2882 2882 seq_br_type 7 Unconditional Call; Flow C 0x28be seq_branch_adr 28be 0x28be seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 2883 2883 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 1 Bits 16…31 2884 2884 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2885 2885 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2886 2886 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 2887 2887 fiu_load_var 1 hold_var; Flow J cc=True 0x288a fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 288a 0x288a seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 06 GP06 typ_csa_cntl 3 POP_CSA val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2888 2888 fiu_len_fill_lit 73 zero-fill 0x33 fiu_load_var 1 hold_var fiu_offs_lit 42 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 2f TOP val_c_source 0 FIU_BUS 2889 2889 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 288a 0x288a seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 288a 288a fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 31 TR02:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 2f TOP val_c_source 0 FIU_BUS 288b 288b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 288c 288c seq_b_timing 0 Early Condition; Flow J cc=True 0x2893 seq_br_type 1 Branch True seq_branch_adr 2893 0x2893 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 288d 288d seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 288e 288e seq_b_timing 1 Latch Condition; Flow J cc=True 0x28a0 seq_br_type 1 Branch True seq_branch_adr 28a0 0x28a0 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 288f 288f seq_b_timing 1 Latch Condition; Flow J cc=True 0x28a4 seq_br_type 1 Branch True seq_branch_adr 28a4 0x28a4 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 0 Bits 0…15 2890 2890 seq_br_type 0 Branch False; Flow J cc=False 0x28a8 seq_branch_adr 28a8 0x28a8 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR08:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 2891 2891 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28a8 seq_br_type 1 Branch True seq_branch_adr 28a8 0x28a8 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR09:00 typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 2892 2892 seq_br_type 3 Unconditional Branch; Flow J 0x2883 seq_branch_adr 2883 0x2883 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 2893 2893 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 2894 2894 seq_b_timing 1 Latch Condition; Flow J cc=True 0x28a0 seq_br_type 1 Branch True seq_branch_adr 28a0 0x28a0 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2895 2895 seq_b_timing 1 Latch Condition; Flow J cc=True 0x28a4 seq_br_type 1 Branch True seq_branch_adr 28a4 0x28a4 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 2896 2896 seq_br_type 0 Branch False; Flow J cc=False 0x28a8 seq_branch_adr 28a8 0x28a8 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR08:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 1 Bits 16…31 2897 2897 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28a8 seq_br_type 1 Branch True seq_branch_adr 28a8 0x28a8 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR09:00 typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2898 2898 seq_br_type 3 Unconditional Branch; Flow J 0x2886 seq_branch_adr 2886 0x2886 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 2899 2899 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 289a 289a seq_b_timing 1 Latch Condition; Flow J cc=True 0x28a0 seq_br_type 1 Branch True seq_branch_adr 28a0 0x28a0 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 3e TR08:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 289b 289b seq_b_timing 1 Latch Condition; Flow J cc=True 0x28a4 seq_br_type 1 Branch True seq_branch_adr 28a4 0x28a4 seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 val_rand d PRODUCT_LEFT_16 289c 289c seq_br_type 0 Branch False; Flow J cc=False 0x28a8 seq_branch_adr 28a8 0x28a8 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR08:1f typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 289d 289d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28a8 seq_br_type 1 Branch True seq_branch_adr 28a8 0x28a8 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR09:00 typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 289e 289e seq_br_type 3 Unconditional Branch; Flow J 0x2883 seq_branch_adr 2883 0x2883 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 289f 289f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 28a0 28a0 fiu_len_fill_lit 4b zero-fill 0xb; Flow J cc=True 0x289f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 289f 0x289f seq_en_micro 0 typ_a_adr 01 GP01 val_a_adr 01 GP01 val_alu_func 3 LEFT_I_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 28a1 28a1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 0 PASS_A 28a2 28a2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 28a3 28a3 ioc_tvbs 3 fiu+fiu; Flow J 0x28ab seq_br_type 3 Unconditional Branch seq_branch_adr 28ab 0x28ab seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 28a4 28a4 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 3 LEFT_I_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 28a5 28a5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 0 PASS_A 28a6 28a6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 28a7 28a7 ioc_tvbs 3 fiu+fiu; Flow J 0x28ab seq_br_type 3 Unconditional Branch seq_branch_adr 28ab 0x28ab seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 28a8 28a8 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 01 GP01 val_a_adr 01 GP01 val_b_adr 02 GP02 val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 28a9 28a9 fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x28aa fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 28ad 0x28ad seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 28aa 28aa fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x28b7 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 28b7 0x28b7 seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 28ab 28ab seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 28ac 28ac seq_br_type 7 Unconditional Call; Flow C 0x28b7 seq_branch_adr 28b7 0x28b7 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 28ad 28ad seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR09:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 28ae 28ae seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 2b TR08:0b typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 28af 28af fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x28b1 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 28b1 0x28b1 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 28b0 28b0 fiu_len_fill_lit 74 zero-fill 0x34; Flow J cc=False 0x28b2 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 41 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 28b2 0x28b2 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A 28b1 28b1 fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 28b2 28b2 fiu_len_fill_lit 4a zero-fill 0xa; Flow C cc=True 0x32a8 fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR09:02 typ_frame 9 28b3 28b3 fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=False 0x28b5 fiu_load_tar 1 hold_tar fiu_offs_lit 0c fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 28b5 0x28b5 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 23 TR09:03 typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 28b4 28b4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28b5 28b5 fiu_len_fill_lit 7e zero-fill 0x3e; Flow J cc=False 0x289f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 289f 0x289f seq_en_micro 0 val_b_adr 39 VR02:19 val_frame 2 28b6 28b6 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28b7 ; -------------------------------------------------------------------------------------- 28b7 ; Comes from: 28b7 ; 28db C from color MACRO_Execute_Float,Exponentiate 28b7 ; -------------------------------------------------------------------------------------- 28b7 28b7 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 28b8 28b8 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 1 Bits 16…31 28b9 28b9 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 28ba 28ba seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_b_src 0 Bits 0…15 28bb 28bb seq_br_type 7 Unconditional Call; Flow C 0x28be seq_branch_adr 28be 0x28be seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 28bc 28bc seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 1 Bits 16…31 28bd 28bd seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 28be ; -------------------------------------------------------------------------------------- 28be ; Comes from: 28be ; 2882 C from color MACRO_Execute_Float,Times 28be ; 28bb C from color MACRO_Execute_Float,Times 28be ; -------------------------------------------------------------------------------------- 28be 28be seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 1 Bits 16…31 28bf 28bf seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 2 Bits 32…47 28c0 28c0 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 1 ALU >> 16 val_m_a_src 2 Bits 32…47 val_m_b_src 0 Bits 0…15 28c1 28c1 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 1 Bits 16…31 val_m_b_src 1 Bits 16…31 28c2 ; -------------------------------------------------------------------------------------- 28c2 ; 0x0239 Execute Float,Exponentiate 28c2 ; -------------------------------------------------------------------------------------- 28c2 MACRO_Execute_Float,Exponentiate: 28c2 28c2 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 28c2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 0b fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_b_adr 39 VR02:19 val_frame 2 28c3 28c3 fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x28c7 fiu_offs_lit 01 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_br_type 1 Branch True seq_branch_adr 28c7 0x28c7 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 8 val_a_adr 32 VR06:12 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 28c4 28c4 fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value val_a_adr 01 GP01 val_alu_func 3 LEFT_I_A val_rand 5 COUNT_ZEROS 28c5 28c5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 29 VR05:09 val_frame 5 28c6 28c6 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3e GP01 val_c_source 0 FIU_BUS 28c7 28c7 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x28c9 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 28c9 0x28c9 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 3b TR11:1b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 32 VR06:12 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 6 28c8 28c8 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP 28c9 28c9 fiu_load_var 1 hold_var; Flow J 0x28cc fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 28cc 0x28cc typ_a_adr 14 ZEROS typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_a_adr 31 VR02:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 28ca 28ca fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x28da fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 28da 0x28da typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 28cb 28cb seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3e GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 28cc 28cc fiu_len_fill_lit 7e zero-fill 0x3e; Flow C cc=False 0x28da fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 28da 0x28da seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 val_m_b_src 2 Bits 32…47 val_rand c START_MULTIPLY 28cd 28cd fiu_len_fill_lit 74 zero-fill 0x34; Flow J cc=True 0x28ca fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 28ca 0x28ca seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3b GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 28ce 28ce fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x28d0 fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 28d0 0x28d0 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 3b TR11:1b typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 14 ZEROS 28cf 28cf fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=False 0x28d8 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 28d8 0x28d8 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 37 TR11:17 typ_c_adr 3b GP04 typ_frame 11 val_a_adr 02 GP02 val_b_adr 39 VR02:19 val_frame 2 28d0 28d0 fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=True 0x28d8 fiu_load_tar 1 hold_tar fiu_offs_lit 0c fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28d8 0x28d8 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 3f TR08:1f typ_b_adr 03 GP03 typ_frame 8 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 28d1 28d1 fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=False 0x28d4 fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 28d4 0x28d4 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR09:02 typ_frame 9 28d2 28d2 seq_br_type 0 Branch False; Flow J cc=False 0x28d9 seq_branch_adr 28d9 0x28d9 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 38 TR05:18 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_alu_func 1a PASS_B val_b_adr 10 TOP 28d3 28d3 fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x28d7 fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28d7 0x28d7 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR09:02 typ_frame 9 val_a_adr 39 VR12:19 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 12 28d4 28d4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 28d5 0x28d5 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28d5 28d5 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 28d6 28d6 seq_br_type 3 Unconditional Branch; Flow J 0x28e0 seq_branch_adr 28e0 MACRO_Execute_Float,Divide val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 28d7 28d7 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x28d9 ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type c Dispatch True seq_branch_adr 28d9 0x28d9 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28d8 28d8 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 28d9 0x28d9 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28d9 28d9 seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 seq_en_micro 0 seq_random 02 ? 28da 28da fiu_len_fill_lit 40 zero-fill 0x0 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 28db 28db ioc_tvbs 2 fiu+val; Flow C 0x28b7 seq_br_type 7 Unconditional Call seq_branch_adr 28b7 0x28b7 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 28dc 28dc seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28d7 seq_br_type 1 Branch True seq_branch_adr 28d7 0x28d7 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3a TR05:1a typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 0 Bits 0…15 val_rand d PRODUCT_LEFT_16 28dd 28dd seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28d8 seq_br_type 1 Branch True seq_branch_adr 28d8 0x28d8 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 3a TR05:1a typ_frame 5 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_m_a_src 0 Bits 0…15 val_m_b_src 2 Bits 32…47 val_rand e PRODUCT_LEFT_32 28de 28de ioc_load_wdr 0 ; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 28df 0x28df seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 28df 28df ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 02 GP02 val_alu_func 3 LEFT_I_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 28e0 ; -------------------------------------------------------------------------------------- 28e0 ; 0x023a Execute Float,Divide 28e0 ; -------------------------------------------------------------------------------------- 28e0 MACRO_Execute_Float,Divide: 28e0 28e0 dispatch_brk_class 8 ; Flow C cc=True 0x32a7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 28e0 fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 3 LEFT_I_A val_b_adr 1f TOP - 1 val_rand 5 COUNT_ZEROS 28e1 28e1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x28ef fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 28ef 0x28ef seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 32 VR06:12 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 28e2 28e2 fiu_len_fill_lit 74 zero-fill 0x34 fiu_load_var 1 hold_var fiu_offs_lit 41 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 23 VR09:03 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 9 28e3 28e3 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x28f7 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28f7 0x28f7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 3e TR08:1e typ_alu_func 1e A_AND_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 28e4 28e4 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x28f2 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28f2 0x28f2 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 28e5 28e5 fiu_len_fill_lit 61 zero-fill 0x21 fiu_load_var 1 hold_var fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 7 INC_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28e6 28e6 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_offs_lit 60 fiu_tivi_src 8 type_var seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_b_adr 35 TR02:15 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28e7 28e7 fiu_fill_mode_src 0 fiu_load_var 1 hold_var fiu_offs_lit 79 fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28e8 28e8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28e9 28e9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x28e9 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 28e9 0x28e9 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28ea 28ea fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x28ec fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 28ec 0x28ec seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_b_adr 3f TR08:1f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl b LOAD_MAR_DATA typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 28eb 28eb fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_offs_lit 0b fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 4 CHECK_CLASS_A_LIT 28ec 28ec ioc_tvbs 2 fiu+val; Flow C cc=True 0x32a8 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 28ed 28ed fiu_len_fill_lit 4b zero-fill 0xb; Flow C cc=True 0x32a8 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 3e TR08:1e typ_frame 8 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 28ee 28ee fiu_len_fill_lit 0b sign-fill 0xb; Flow R cc=True ; Flow J cc=False 0x28f4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 28f4 0x28f4 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 28ef ; -------------------------------------------------------------------------------------- 28ef ; Comes from: 28ef ; 28e1 C True from color 0x28d6 28ef ; -------------------------------------------------------------------------------------- 28ef 28ef fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 26 VR05:06 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 28f0 28f0 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_mar_cntl b LOAD_MAR_DATA val_a_adr 3a VR02:1a val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 2 28f1 28f1 fiu_len_fill_lit 4b zero-fill 0xb; Flow R fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 28f2 28f2 seq_br_type 4 Call False; Flow C cc=False 0x32a8 seq_branch_adr 32a8 0x32a8 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_frame 2 28f3 28f3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 28f4 28f4 fiu_len_fill_lit 7e zero-fill 0x3e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_b_adr 05 GP05 typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 28f5 28f5 fiu_fill_mode_src 0 ; Flow J cc=False 0x28f3 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 28f3 0x28f3 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 14 ZEROS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 23 VR09:03 val_frame 9 28f6 28f6 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 28f7 28f7 fiu_load_var 1 hold_var; Flow J cc=True 0x28fb fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 28fb 0x28fb seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR val_alu_func 3 LEFT_I_A val_b_adr 39 VR02:19 val_frame 2 val_rand 5 COUNT_ZEROS 28f8 28f8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x28f3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 28f3 0x28f3 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_alu_func 3 LEFT_I_A val_a_adr 15 ZERO_COUNTER val_alu_func 7 INC_A val_c_adr 3c GP03 val_c_source 0 FIU_BUS 28f9 28f9 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 28fa 28fa fiu_len_fill_lit 4b zero-fill 0xb; Flow J cc=True 0x28e4 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 28e4 0x28e4 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 28fb 28fb seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x28f2 seq_br_type 1 Branch True seq_branch_adr 28f2 0x28f2 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 28fc 28fc fiu_len_fill_lit 74 zero-fill 0x34; Flow C cc=True 0x32a8 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a8 0x32a8 seq_cond_sel 21 TYP.ALU_OVERFLOW(late) typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR08:1f typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 28fd 28fd ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 28fe 28fe fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x28ed fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 28ed 0x28ed typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 28ff 28ff <halt> ; Flow R 2900 ; -------------------------------------------------------------------------------------- 2900 ; 0x0238 Execute Float,Convert 2900 ; -------------------------------------------------------------------------------------- 2900 MACRO_Execute_Float,Convert: 2900 2900 dispatch_brk_class 4 ; Flow J cc=True 0x2902 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2900 dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2902 0x2902 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 2901 2901 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x2857 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2857 0x2857 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2902 2902 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2857 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2857 0x2857 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 2903 2903 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2857 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 2857 0x2857 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2904 ; -------------------------------------------------------------------------------------- 2904 ; 0x0237 Execute Float,Convert_From_Discrete 2904 ; -------------------------------------------------------------------------------------- 2904 MACRO_Execute_Float,Convert_From_Discrete: 2904 2904 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2904 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 2905 2905 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2909 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2909 0x2909 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 28 VR05:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 2906 2906 fiu_fill_mode_src 0 ; Flow R cc=True fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2907 0x2907 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR11:19 val_alu_func 6 A_MINUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 11 2907 2907 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 01 GP01 2908 2908 fiu_len_fill_lit 4b zero-fill 0xb; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2909 2909 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_rand 5 COUNT_ZEROS 290a 290a fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 28 VR05:08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 290b 290b fiu_fill_mode_src 0 ; Flow J 0x2907 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2907 0x2907 seq_en_micro 0 val_a_adr 38 VR11:18 val_alu_func 6 A_MINUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 11 290c ; -------------------------------------------------------------------------------------- 290c ; 0x0236 Execute Float,Truncate_To_Discrete 290c ; -------------------------------------------------------------------------------------- 290c MACRO_Execute_Float,Truncate_To_Discrete: 290c 290c dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 290c fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 2 290d 290d fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x2910 fiu_offs_lit 41 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2910 0x2910 seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 1 RESTORE_RDR val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 290e 290e fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=True 0x2912 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2912 0x2912 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR09:01 typ_frame 9 val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR11:17 val_frame 11 290f 290f fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x2913 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 2913 0x2913 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 37 VR11:17 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 11 2910 2910 fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=True 0x2912 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2912 0x2912 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR09:01 typ_frame 9 val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR11:17 val_frame 11 2911 2911 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x291b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 291b 0x291b seq_en_micro 0 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2912 2912 fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 2913 0x2913 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 3a VR05:1a val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 5 2913 2913 seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 2914 ; -------------------------------------------------------------------------------------- 2914 ; 0x0235 Execute Float,Round_To_Discrete 2914 ; -------------------------------------------------------------------------------------- 2914 MACRO_Execute_Float,Round_To_Discrete: 2914 2914 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2914 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 39 VR02:19 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 2 2915 2915 fiu_len_fill_lit 4a zero-fill 0xa fiu_offs_lit 41 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 1 RESTORE_RDR val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2916 2916 fiu_len_fill_lit 73 zero-fill 0x33; Flow J cc=True 0x2912 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2912 0x2912 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 3b TR11:1b typ_frame 11 val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR11:17 val_frame 11 2917 2917 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x291a fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 291a 0x291a seq_en_micro 0 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR09:01 typ_frame 9 2918 2918 fiu_len_fill_lit 40 zero-fill 0x0 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2919 2919 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2913 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2913 0x2913 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 291a 291a fiu_len_fill_lit 00 sign-fill 0x0 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 291b 291b fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2913 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 2913 0x2913 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 291c ; -------------------------------------------------------------------------------------- 291c ; 0x0230 Execute Float,In_Range 291c ; -------------------------------------------------------------------------------------- 291c MACRO_Execute_Float,In_Range: 291c 291c dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 291c fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 10 TOP 291d 291d fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x2922 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2922 0x2922 typ_a_adr 1f TOP - 1 typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_b_adr 31 VR02:11 val_frame 2 291e 291e fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2929 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2929 0x2929 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 291f 291f <halt> ; Flow R 2920 ; -------------------------------------------------------------------------------------- 2920 ; 0x014f Execute Float,Not_In_Range 2920 ; -------------------------------------------------------------------------------------- 2920 MACRO_Execute_Float,Not_In_Range: 2920 2920 dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2920 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 10 TOP 2921 2921 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x291e fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 291e 0x291e typ_a_adr 1f TOP - 1 typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_b_adr 39 VR02:19 val_frame 2 2922 2922 ioc_tvbs 2 fiu+val; Flow J cc=True 0x2929 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2929 0x2929 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA 2923 2923 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2929 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 2929 0x2929 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP 2924 ; -------------------------------------------------------------------------------------- 2924 ; 0x0234 Execute Float,In_Type 2924 ; -------------------------------------------------------------------------------------- 2924 MACRO_Execute_Float,In_Type: 2924 2924 dispatch_brk_class 8 ; Flow J cc=True 0x2927 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2924 dispatch_uses_tos 1 fiu_load_oreg 1 hold_oreg ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2927 0x2927 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_frame 2 2925 2925 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2929 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2929 0x2929 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 2926 ; -------------------------------------------------------------------------------------- 2926 ; 0x0233 Execute Float,Not_In_Type 2926 ; -------------------------------------------------------------------------------------- 2926 MACRO_Execute_Float,Not_In_Type: 2926 2926 dispatch_brk_class 8 ; Flow J cc=False 0x2925 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2926 dispatch_uses_tos 1 fiu_load_oreg 1 hold_oreg fiu_offs_lit 01 ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2925 0x2925 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 2927 2927 fiu_load_var 1 hold_var; Flow J cc=True 0x2929 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2929 0x2929 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA 2928 2928 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 2929 0x2929 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP 2929 2929 fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 7f fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 292a ; -------------------------------------------------------------------------------------- 292a ; 0x0232 Execute Float,Check_In_Type 292a ; -------------------------------------------------------------------------------------- 292a MACRO_Execute_Float,Check_In_Type: 292a 292a dispatch_brk_class 8 ; Flow J cc=True 0x292c dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 292a dispatch_uses_tos 1 ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 292c 0x292c seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 292b 292b fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2857 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2857 0x2857 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 292c 292c ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2857 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2857 0x2857 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 292d 292d fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2857 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 2857 0x2857 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 292e ; -------------------------------------------------------------------------------------- 292e ; 0x0231 Execute Float,Write_Unchecked 292e ; -------------------------------------------------------------------------------------- 292e MACRO_Execute_Float,Write_Unchecked: 292e 292e dispatch_brk_class 2 ; Flow C 0x32d7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 292e fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_frame c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 292f 292f typ_a_adr 1f TOP - 1 typ_frame 8 typ_rand b CARRY IN = Q BIT FROM VAL 2930 2930 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x32a9 fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 2931 2931 fiu_fill_mode_src 0 ; Flow J cc=False 0x2933 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2933 0x2933 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 2932 2932 fiu_fill_mode_src 0 ; Flow J 0x2936 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2936 0x2936 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 2933 2933 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2934 2934 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2935 2935 fiu_load_var 1 hold_var; Flow J 0x2936 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2936 0x2936 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 2936 2936 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA 2937 2937 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2938 ; -------------------------------------------------------------------------------------- 2938 ; 0x4800-0x4fff Short_Literal slit 2938 ; -------------------------------------------------------------------------------------- 2938 MACRO_Short_Literal_slit: 2938 2938 dispatch_brk_class 8 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_uadr 2938 fiu_len_fill_lit 0a sign-fill 0xa fiu_mem_start 2 start-rd fiu_offs_lit 75 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 2939 2939 fiu_mem_start 2 start-rd; Flow J 0x2941 ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 2941 0x2941 seq_en_micro 0 seq_random 38 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE 293a ; -------------------------------------------------------------------------------------- 293a ; 0x6000-0x67ff Indirect_Literal Discrete,pcrel,literal 293a ; -------------------------------------------------------------------------------------- 293a MACRO_Indirect_Literal_Discrete,pcrel,literal: 293a 293a dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 293a fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 3 seq seq_random 38 ? typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 293b 293b fiu_fill_mode_src 0 ; Flow R cc=True ; Flow J cc=False 0x2939 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type c Dispatch True seq_branch_adr 2939 0x2939 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 293c ; -------------------------------------------------------------------------------------- 293c ; 0x5800-0x5fff Indirect_Literal Float,pcrel,dbl 293c ; -------------------------------------------------------------------------------------- 293c MACRO_Indirect_Literal_Float,pcrel,dbl: 293c 293c dispatch_brk_class 8 ; Flow J 0x293b dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 293c fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 293b 0x293b seq_random 38 ? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 293d 293d fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x293f fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 293f 0x293f seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 293e ; -------------------------------------------------------------------------------------- 293e ; 0x00a2 Action Push_Discrete_Extended 293e ; -------------------------------------------------------------------------------------- 293e MACRO_Action_Push_Discrete_Extended: 293e 293e dispatch_brk_class 8 ; Flow J 0x293d dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 293e fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 293d 0x293d seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 293f 293f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2941 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2941 0x2941 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 0 PASS_A 2940 ; -------------------------------------------------------------------------------------- 2940 ; 0x00a1 Action Push_Float_Extended 2940 ; -------------------------------------------------------------------------------------- 2940 MACRO_Action_Push_Float_Extended: 2940 2940 dispatch_brk_class 8 ; Flow J 0x293d dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2940 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 293d 0x293d seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_a_adr 31 TR02:11 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2941 2941 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x293b seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 293b 0x293b seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR 2942 2942 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 2943 2943 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 2944 ; -------------------------------------------------------------------------------------- 2944 ; 0x0093 PushFullAddress InMicrocode,caddr 2944 ; -------------------------------------------------------------------------------------- 2944 MACRO_PushFullAddress_InMicrocode,caddr: 2944 2944 dispatch_brk_class 4 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2944 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2945 2945 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2946 2946 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2947 2947 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2948 ; -------------------------------------------------------------------------------------- 2948 ; 0x5000-0x57ff Indirect_Literal Any,pcrel,literal 2948 ; -------------------------------------------------------------------------------------- 2948 MACRO_Indirect_Literal_Any,pcrel,literal: 2948 2948 dispatch_brk_class 8 ; Flow C 0x2953 dispatch_csa_valid 1 dispatch_uadr 2948 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2953 0x2953 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4b) Subvector_Var Subarray_Var seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 2949 2949 fiu_tivi_src c mar_0xc; Flow C 0x2993 ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 2993 0x2993 seq_random 02 ? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 294a 294a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 294b 294b <halt> ; Flow R 294c ; -------------------------------------------------------------------------------------- 294c ; 0x00a0 Action Push_Structure_Extended,abs,mark 294c ; -------------------------------------------------------------------------------------- 294c MACRO_Action_Push_Structure_Extended,abs,mark: 294c 294c dispatch_brk_class 8 ; Flow C 0x2953 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 294c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2953 0x2953 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4b) Subvector_Var Subarray_Var seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 294d 294d fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 294e 294e fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x294f fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 294a 0x294a seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 294f 294f ioc_fiubs 1 val ; Flow J 0x2993 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2993 0x2993 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 04 GP04 2950 ; -------------------------------------------------------------------------------------- 2950 ; 0x0115 Execute Any,Structure_Clear 2950 ; -------------------------------------------------------------------------------------- 2950 MACRO_Execute_Any,Structure_Clear: 2950 2950 dispatch_brk_class 4 ; Flow C 0x2953 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2950 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2953 0x2953 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x4b) Subvector_Var Subarray_Var seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 10 TOP 2951 2951 seq_br_type 7 Unconditional Call; Flow C 0x2a5e seq_branch_adr 2a5e 0x2a5e seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2952 2952 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 2953 ; -------------------------------------------------------------------------------------- 2953 ; Comes from: 2953 ; 2948 C from color MACRO_Indirect_Literal_Any,pcrel,literal 2953 ; 294c C from color MACRO_Action_Push_Structure_Extended,abs,mark 2953 ; 2950 C from color MACRO_Execute_Any,Structure_Clear 2953 ; -------------------------------------------------------------------------------------- 2953 2953 seq_b_timing 1 Latch Condition; Flow J cc=True 0x295b seq_br_type 1 Branch True seq_branch_adr 295b 0x295b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP 2954 2954 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x295c fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 295c 0x295c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_latch 1 typ_b_adr 10 TOP typ_frame 8 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2955 2955 fiu_len_fill_lit 45 zero-fill 0x5; Flow J cc=True 0x295a fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 295a 0x295a val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2956 2956 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 41 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2957 2957 val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2958 2958 fiu_len_fill_lit 77 zero-fill 0x37 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 3f TR02:1f typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_b_adr 03 GP03 2959 2959 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 295a 295a fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x32db fiu_oreg_src 0 rotator output ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32db 0x32db seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 38 ? typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 9 LOAD_MAR_CODE 295b 295b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x295a fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 295a 0x295a typ_a_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 295c 295c fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 295d 295d ioc_tvbs 2 fiu+val; Flow C cc=True 0x32db seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS 295e 295e fiu_len_fill_lit 4a zero-fill 0xa; Flow C 0x210 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame c 295f 295f fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 2960 2960 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2963 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2963 0x2963 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 2961 2961 fiu_fill_mode_src 0 ; Flow C cc=False 0x2969 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2969 0x2969 typ_alu_func 3 LEFT_I_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 2962 2962 seq_br_type 3 Unconditional Branch; Flow J 0x2966 seq_branch_adr 2966 0x2966 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 2963 2963 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2964 2964 fiu_fill_mode_src 0 ; Flow C cc=False 0x2969 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2969 0x2969 typ_alu_func 3 LEFT_I_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 2965 2965 seq_br_type 3 Unconditional Branch; Flow J 0x2966 seq_branch_adr 2966 0x2966 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_rand c START_MULTIPLY 2966 2966 fiu_load_oreg 1 hold_oreg; Flow R cc=True fiu_oreg_src 0 rotator output ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2967 0x2967 seq_en_micro 0 seq_random 38 ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 2967 2967 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 2968 2968 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 2969 ; -------------------------------------------------------------------------------------- 2969 ; Comes from: 2969 ; 2961 C False from color 0x295f 2969 ; 2964 C False from color 0x295f 2969 ; -------------------------------------------------------------------------------------- 2969 2969 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x296b seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 296b 0x296b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 296a 296a fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3f GP00 val_c_source 0 FIU_BUS 296b 296b fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 296c 296c fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3f GP00 val_c_source 0 FIU_BUS 296d 296d <halt> ; Flow R 296e ; -------------------------------------------------------------------------------------- 296e ; 0x0092 Action Push_String_Extended,pse 296e ; -------------------------------------------------------------------------------------- 296e MACRO_Action_Push_String_Extended,pse: 296e 296e dispatch_brk_class 4 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 296e fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_a_adr 29 TR0b:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 296f 296f fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2973 fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2973 0x2973 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 5d ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2970 ; -------------------------------------------------------------------------------------- 2970 ; 0x0091 Action Push_String_Extended_Indexed,pse 2970 ; -------------------------------------------------------------------------------------- 2970 MACRO_Action_Push_String_Extended_Indexed,pse: 2970 2970 dispatch_brk_class 4 ; Flow C 0x329e dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2970 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 02 ? typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 3d VR02:1d val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 2971 2971 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 29 TR0b:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 2972 2972 fiu_tivi_src 1 tar_val; Flow J 0x2973 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2973 0x2973 seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 5d ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2973 2973 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame c typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 0 PASS_A 2974 2974 fiu_mem_start a start_continue_if_false ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 65 CROSS_WORD_FIELD~ seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR02:01 val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2975 2975 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR02:1d val_frame 2 2976 2976 fiu_len_fill_lit 4f zero-fill 0xf fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 2977 2977 fiu_len_fill_lit 7c zero-fill 0x3c fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 3d VR06:1d val_frame 6 2978 2978 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x297e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 297e 0x297e typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 2f TR11:0f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2979 2979 fiu_vmux_sel 1 fill value; Flow J cc=True 0x297c ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 297c 0x297c seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 297a 297a seq_br_type 7 Unconditional Call; Flow C 0x2993 seq_branch_adr 2993 0x2993 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 297b 297b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 297c 297c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x297e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 297e 0x297e typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_frame 5 297d 297d ioc_load_wdr 0 ; Flow J 0x297b ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 297b 0x297b typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 297e ; -------------------------------------------------------------------------------------- 297e ; Comes from: 297e ; 2978 C from color MACRO_Action_Push_String_Extended,pse 297e ; 297c C from color MACRO_Action_Push_String_Extended,pse 297e ; -------------------------------------------------------------------------------------- 297e 297e fiu_fill_mode_src 0 ; Flow J cc=False 0x2980 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2980 0x2980 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 05 GP05 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 297f 297f fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2980 2980 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2981 2981 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offset_src 0 offset_register fiu_op_sel 1 insert last ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 2982 ; -------------------------------------------------------------------------------------- 2982 ; 0x0090 Action Store_String_Extended,pse 2982 ; -------------------------------------------------------------------------------------- 2982 MACRO_Action_Store_String_Extended,pse: 2982 2982 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2982 dispatch_uses_tos 1 ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 1d ? typ_b_adr 10 TOP typ_c_lit 0 typ_frame c typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2983 2983 fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_frame 2 2984 2984 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 6c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 5d ? typ_a_adr 29 TR0b:09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2985 2985 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 02 GP02 2986 2986 fiu_mem_start a start_continue_if_false seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2987 2987 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 3d VR02:1d val_frame 2 2988 2988 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=True 0x298a fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 298a 0x298a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 2989 2989 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 298a 298a fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x298e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offs_lit 5d fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 298e 0x298e typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 5 298b 298b fiu_load_oreg 1 hold_oreg; Flow C cc=True 0x2992 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2992 0x2992 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 2f TR11:0f typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 298c 298c fiu_len_fill_lit 7c zero-fill 0x3c; Flow C cc=True 0x2993 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 5 Call True seq_branch_adr 2993 0x2993 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 298d 298d fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x32a3 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 32a3 0x32a3 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 298e ; -------------------------------------------------------------------------------------- 298e ; Comes from: 298e ; 298a C True from color 0x0000 298e ; -------------------------------------------------------------------------------------- 298e 298e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2990 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2990 0x2990 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 298f 298f fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 2990 2990 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2991 2991 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 2992 ; -------------------------------------------------------------------------------------- 2992 ; Comes from: 2992 ; 298b C True from color 0x0000 2992 ; -------------------------------------------------------------------------------------- 2992 2992 fiu_load_oreg 1 hold_oreg; Flow R fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type a Unconditional Return typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 2993 ; -------------------------------------------------------------------------------------- 2993 ; Comes from: 2993 ; 2949 C from color MACRO_Indirect_Literal_Any,pcrel,literal 2993 ; 297a C from color MACRO_Action_Push_String_Extended,pse 2993 ; 298c C True from color 0x0000 2993 ; -------------------------------------------------------------------------------------- 2993 2993 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2994 2994 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x299f fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 299f 0x299f seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 20 VR00:00 val_alu_func 1a PASS_B val_b_adr 01 GP01 2995 2995 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x299a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 299a 0x299a seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR 2996 2996 fiu_fill_mode_src 0 ; Flow J 0x2997 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2997 0x2997 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2997 2997 fiu_fill_mode_src 0 ; Flow J cc=False 0x299c fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 299c 0x299c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2998 2998 fiu_fill_mode_src 0 ; Flow J 0x2999 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2999 0x2999 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2999 2999 ioc_load_wdr 0 ; Flow C 0x2ab4 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 299a 299a fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 299b 299b fiu_fill_mode_src 0 ; Flow J 0x2997 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2997 0x2997 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 299c 299c fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 299d 299d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 299e 299e fiu_load_var 1 hold_var; Flow J 0x2999 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2999 0x2999 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 299f 299f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x29a8 fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 29a8 0x29a8 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29a0 29a0 fiu_load_tar 1 hold_tar; Flow J cc=True 0x29bb fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29bb 0x29bb typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B 29a1 29a1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_latch 1 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 29a2 29a2 fiu_fill_mode_src 0 ; Flow J cc=True 0x29ac fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 29ac 0x29ac seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29a3 29a3 fiu_mem_start 2 start-rd; Flow J 0x29a4 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 29a4 0x29a4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 29a4 29a4 seq_br_type 3 Unconditional Branch; Flow J 0x2993 seq_branch_adr 2993 0x2993 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 29a5 29a5 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29a6 29a6 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x2995 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2995 0x2995 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 35 TR02:15 typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 01 GP01 29a7 29a7 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=True 0x29a0 fiu_mem_start a start_continue_if_false fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 29a0 0x29a0 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 29a8 29a8 fiu_load_tar 1 hold_tar; Flow J cc=True 0x29be fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29be 0x29be seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_latch 1 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 29a9 29a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x29ab fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29ab 0x29ab seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 seq_latch 1 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 29aa 29aa seq_br_type 0 Branch False; Flow J cc=False 0x29a4 seq_branch_adr 29a4 0x29a4 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 29ab 29ab fiu_fill_mode_src 0 ; Flow J 0x29ac fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29ac 0x29ac typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29ac 29ac fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x29b0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 9 start_continue_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29b0 0x29b0 typ_mar_cntl 6 INCREMENT_MAR 29ad 29ad fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 29ae 29ae fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 29af 29af fiu_fill_mode_src 0 ; Flow J 0x2999 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2999 0x2999 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 29b0 29b0 fiu_load_tar 1 hold_tar; Flow J cc=False 0x29b6 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 29b6 0x29b6 seq_cond_sel 64 OFFSET_REGISTER_???? 29b1 29b1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29a4 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 29a4 0x29a4 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 29b2 29b2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 29b3 29b3 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_op_sel 2 insert first ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29b4 29b4 fiu_fill_mode_src 0 ; Flow J 0x29b5 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29b5 0x29b5 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 29b5 29b5 fiu_mem_start 4 continue; Flow J 0x2999 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2999 0x2999 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP 29b6 29b6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29a4 fiu_length_src 0 length_register fiu_op_sel 2 insert first ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 29a4 0x29a4 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 29b7 29b7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 1 insert last fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 seq_latch 1 typ_alu_func 0 PASS_A 29b8 29b8 fiu_fill_mode_src 0 ; Flow J cc=True 0x29ba fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29ba 0x29ba seq_en_micro 0 typ_c_adr 3f GP00 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29b9 29b9 fiu_fill_mode_src 0 ; Flow J 0x29b5 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29b5 0x29b5 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 29ba 29ba fiu_fill_mode_src 0 ; Flow J 0x29b5 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29b5 0x29b5 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 29bb 29bb fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 29bc 29bc fiu_fill_mode_src 0 ; Flow J cc=True 0x29c4 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29c4 0x29c4 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29bd 29bd fiu_load_oreg 1 hold_oreg; Flow J 0x29c1 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 29c1 0x29c1 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA 29be 29be fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1e) Control_Allocation Accept_Subprogram_Ref Record_Var Accept_Subprogram Scheduling_Allocation Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var Activation_State seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 29bf 29bf seq_b_timing 1 Latch Condition; Flow J cc=True 0x29c6 seq_br_type 1 Branch True seq_branch_adr 29c6 0x29c6 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 29c0 29c0 fiu_fill_mode_src 0 ; Flow J 0x29c1 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29c1 0x29c1 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29c1 29c1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 29c2 29c2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x29c3 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 2 insert first fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29c3 0x29c3 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29c3 29c3 ioc_load_wdr 0 ; Flow J 0x29cb ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29cb 0x29cb seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 29c4 29c4 fiu_fill_mode_src 0 ; Flow J cc=True 0x29cb fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29cb 0x29cb seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 29c5 29c5 fiu_fill_mode_src 0 ; Flow J 0x29c8 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29c8 0x29c8 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA 29c6 29c6 fiu_fill_mode_src 0 ; Flow J cc=True 0x29cb fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 29cb 0x29cb seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 29c7 29c7 fiu_fill_mode_src 0 ; Flow J 0x29c8 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29c8 0x29c8 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA 29c8 29c8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 29c9 29c9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A 29ca 29ca fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x29c3 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 29c3 0x29c3 typ_a_adr 17 LOOP_COUNTER typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29cb 29cb fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x29a5 fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29a5 0x29a5 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 0 PASS_A 29cc 29cc fiu_mem_start 4 continue; Flow J cc=False 0x29d8 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 29d8 0x29d8 seq_cond_sel 64 OFFSET_REGISTER_???? typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 29cd 29cd fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29ce 29ce fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29d7 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29d7 0x29d7 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29cf 29cf fiu_load_oreg 1 hold_oreg; Flow J 0x29d0 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29d0 0x29d0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 29d0 29d0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 0 PASS_A 29d1 29d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29d4 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 29d4 0x29d4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29d2 29d2 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 29d3 29d3 fiu_mem_start 2 start-rd; Flow C 0x332e seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e 29d4 29d4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29d6 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29d6 0x29d6 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29d5 29d5 fiu_load_oreg 1 hold_oreg; Flow J 0x29d0 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29d0 0x29d0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29d6 29d6 ioc_load_wdr 0 ; Flow J 0x29a5 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29a5 0x29a5 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29d7 29d7 ioc_load_wdr 0 ; Flow J 0x29a5 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29a5 0x29a5 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 29d8 29d8 fiu_load_var 1 hold_var; Flow J cc=False 0x29e2 fiu_tivi_src 1 tar_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29e2 0x29e2 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 29d9 29d9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29da 29da fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 01 GP01 val_alu_func 0 PASS_A 29db 29db fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29df fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 29df 0x29df typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29dc 29dc fiu_load_oreg 1 hold_oreg; Flow C 0x2ab4 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29dd 29dd fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 0 PASS_A 29de 29de fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x29db fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29db 0x29db typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29df 29df fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29e0 29e0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 29e1 29e1 ioc_load_wdr 0 ; Flow J 0x29a5 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29a5 0x29a5 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 29e2 29e2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29e3 29e3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 29e4 29e4 ioc_load_wdr 0 ; Flow J 0x29a5 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29a5 0x29a5 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 29e5 ; -------------------------------------------------------------------------------------- 29e5 ; Comes from: 29e5 ; 1101 C from color 0x10f1 29e5 ; 1302 C from color 0x12f9 29e5 ; 1720 C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 29e5 ; 17f7 C from color MACRO_Execute_Any,Set_Constraint 29e5 ; 17ff C True from color MACRO_Execute_Any,Set_Constraint 29e5 ; -------------------------------------------------------------------------------------- 29e5 29e5 fiu_load_tar 1 hold_tar; Flow J cc=True 0x29ea fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 29ea 0x29ea seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 09 GP09 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_b_adr 09 GP09 29e6 29e6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x2a5e fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2a5e 0x2a5e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 09 GP09 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 29e7 29e7 seq_br_type 5 Call True; Flow C cc=True 0x2a5e seq_branch_adr 2a5e 0x2a5e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29e8 29e8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_b_adr 09 GP09 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_b_adr 09 GP09 29e9 29e9 ioc_fiubs 0 fiu ; Flow J 0x2a5e seq_br_type 3 Unconditional Branch seq_branch_adr 2a5e 0x2a5e val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29ea 29ea fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 08 GP08 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 29eb 29eb fiu_len_fill_lit 48 zero-fill 0x8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal seq_en_micro 0 typ_a_adr 3b TR07:1b typ_alu_func 1e A_AND_B typ_b_adr 09 GP09 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 0f GP0f val_alu_func 1b A_OR_B val_b_adr 2e VR04:0e val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 29ec 29ec fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x29f2 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 29f2 0x29f2 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 29ed 29ed fiu_fill_mode_src 0 ; Flow J cc=False 0x29ef fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 29ef 0x29ef seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29ee 29ee fiu_fill_mode_src 0 ; Flow J 0x29f4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29f4 0x29f4 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 29ef 29ef fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 29f0 29f0 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 29f1 29f1 fiu_load_var 1 hold_var; Flow J 0x29f4 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29f4 0x29f4 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 29f2 29f2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_b_adr 0f GP0f val_c_adr 3f GP00 val_c_source 0 FIU_BUS 29f3 29f3 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x29f4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29f4 0x29f4 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A 29f4 29f4 ioc_load_wdr 0 ; Flow J cc=True 0x2a01 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a01 0x2a01 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 29f5 29f5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x29f8 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 29f8 0x29f8 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 29f6 29f6 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 29f7 29f7 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 0 PASS_A 29f8 29f8 <default> 29f9 29f9 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 29fa 29fa fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator 29fb 29fb fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 29fc 29fc fiu_fill_mode_src 0 ; Flow J cc=False 0x29fe fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 29fe 0x29fe seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 29fd 29fd fiu_fill_mode_src 0 ; Flow J 0x29f4 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 29f4 0x29f4 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 29fe 29fe fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 29ff 29ff fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a00 2a00 fiu_load_var 1 hold_var; Flow J 0x29f4 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 29f4 0x29f4 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 2a01 2a01 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 09 GP09 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_b_adr 09 GP09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2a02 2a02 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2a05 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a05 0x2a05 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 09 GP09 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 2a03 2a03 seq_b_timing 1 Latch Condition; Flow J cc=False 0x2a5e seq_br_type 0 Branch False seq_branch_adr 2a5e 0x2a5e seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a04 2a04 seq_br_type 3 Unconditional Branch; Flow J 0x2a06 seq_branch_adr 2a06 0x2a06 2a05 2a05 ioc_tvbs 3 fiu+fiu; Flow J cc=False 0x2a5e seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a5e 0x2a5e seq_en_micro 0 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a06 2a06 seq_br_type 5 Call True; Flow C cc=True 0x2a5e seq_branch_adr 2a5e 0x2a5e seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 0 PASS_A 2a07 2a07 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val typ_b_adr 09 GP09 val_b_adr 09 GP09 2a08 2a08 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a09 2a09 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 2a0a 2a0a fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x2a10 fiu_offs_lit 28 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a10 0x2a10 typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2a0b 2a0b fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 17 LOOP_COUNTER 2a0c 2a0c fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 2a0d 2a0d typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2a0e 2a0e fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2a0f 2a0f fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x2a11 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a11 0x2a11 typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 17 LOOP_COUNTER 2a10 2a10 fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2a11 0x2a11 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 17 LOOP_COUNTER typ_b_adr 32 TR02:12 typ_frame 2 2a11 2a11 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS 2a12 2a12 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 2a13 2a13 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 17 LOOP_COUNTER typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2a14 2a14 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2a21 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a21 0x2a21 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2a) Vector_Var Matrix_Var Array_Var seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame a val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2a15 2a15 fiu_mem_start 2 start-rd; Flow J cc=False 0x2a18 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a18 0x2a18 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 2a16 2a16 ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2a17 2a17 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2a23 seq_br_type 3 Unconditional Branch seq_branch_adr 2a23 0x2a23 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2a18 2a18 ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2a19 2a19 fiu_tivi_src c mar_0xc; Flow J cc=False 0x2a23 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a23 0x2a23 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2a1a 2a1a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2a1b 2a1b ioc_load_wdr 0 ioc_tvbs 1 typ+fiu val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 2a1c 2a1c fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_c_adr 30 GP0f 2a1d 2a1d fiu_len_fill_lit 7d zero-fill 0x3d fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_source 0 FIU_BUS 2a1e 2a1e ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2a20 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a20 0x2a20 seq_en_micro 0 val_a_adr 21 VR05:01 val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand c START_MULTIPLY 2a1f 2a1f seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 31 GP0e val_c_mux_sel 2 ALU 2a20 2a20 seq_br_type 3 Unconditional Branch; Flow J 0x2a23 seq_branch_adr 2a23 0x2a23 seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a21 2a21 ioc_tvbs 2 fiu+val; Flow J 0x2a23 seq_br_type 3 Unconditional Branch seq_branch_adr 2a23 0x2a23 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2a22 2a22 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a34 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a34 0x2a34 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2a23 2a23 fiu_load_tar 1 hold_tar; Flow J cc=True 0x2a28 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a28 0x2a28 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 09 GP09 2a24 2a24 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2a22 seq_br_type 0 Branch False seq_branch_adr 2a22 0x2a22 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2a25 2a25 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 2a26 2a26 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2a27 2a27 seq_br_type 3 Unconditional Branch; Flow J 0x2a22 seq_branch_adr 2a22 0x2a22 2a28 2a28 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a29 2a29 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 28 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2a2a 0x2a2a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 36 VR05:16 val_frame 5 2a2a 2a2a fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val val_a_adr 14 ZEROS 2a2b 2a2b fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 2a2c 2a2c <default> 2a2d 2a2d fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS 2a2e 2a2e ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x2a34 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2a34 0x2a34 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 36 VR07:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2a2f 2a2f fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 2a30 0x2a30 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2a30 2a30 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2a2e seq_br_type 0 Branch False seq_branch_adr 2a2e 0x2a2e seq_cond_sel 67 REFRESH_MACRO_EVENT 2a31 2a31 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 2a32 2a32 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2a33 2a33 seq_br_type 3 Unconditional Branch; Flow J 0x2a2e seq_branch_adr 2a2e 0x2a2e 2a34 ; -------------------------------------------------------------------------------------- 2a34 ; Comes from: 2a34 ; 2a22 C True from color 0x0000 2a34 ; 2a2e C True from color 0x0000 2a34 ; -------------------------------------------------------------------------------------- 2a34 2a34 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2a35 2a35 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2a4b fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a4b 0x2a4b typ_a_adr 20 TR08:00 typ_frame 8 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2a36 2a36 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1a PASS_B val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2a37 2a37 ioc_fiubs 0 fiu val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2a38 2a38 fiu_len_fill_lit 45 zero-fill 0x5 fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2a39 2a39 seq_br_type 3 Unconditional Branch; Flow J 0x2a3d seq_branch_adr 2a3d 0x2a3d val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2a3a 2a3a fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2a44 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2a44 0x2a44 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 2a3b 2a3b fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 2a3c 2a3c val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2a3d 2a3d fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 2a3e 2a3e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2a44 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 2a44 0x2a44 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 04 GP04 val_alu_func 0 PASS_A val_rand 2 DEC_LOOP_COUNTER 2a3f 2a3f fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2a4e ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a4e 0x2a4e seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 2a40 2a40 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2a3a seq_br_type 0 Branch False seq_branch_adr 2a3a 0x2a3a seq_cond_sel 67 REFRESH_MACRO_EVENT 2a41 2a41 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 2a42 2a42 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2a43 2a43 seq_br_type 3 Unconditional Branch; Flow J 0x2a3a seq_branch_adr 2a3a 0x2a3a 2a44 ; -------------------------------------------------------------------------------------- 2a44 ; Comes from: 2a44 ; 2a3a C from color 0x2a34 2a44 ; 2a3e C from color 0x2a34 2a44 ; 2a55 C from color 0x2a34 2a44 ; -------------------------------------------------------------------------------------- 2a44 2a44 fiu_fill_mode_src 0 ; Flow J cc=False 0x2a47 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a47 0x2a47 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2a45 2a45 fiu_fill_mode_src 0 ; Flow J cc=True 0x2a4a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a4a 0x2a4a typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 2a46 ; -------------------------------------------------------------------------------------- 2a46 ; Comes from: 2a46 ; 2a4d C from color 0x2a34 2a46 ; -------------------------------------------------------------------------------------- 2a46 2a46 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 02 GP02 2a47 2a47 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2a48 2a48 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a49 2a49 fiu_load_var 1 hold_var; Flow J cc=False 0x2a46 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a46 0x2a46 seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 2a4a 2a4a ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 26 TYP.TRUE (early) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 2a4b 2a4b fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1a PASS_B 2a4c 2a4c ioc_fiubs 0 fiu val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2a4d 2a4d fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x2a46 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2a46 0x2a46 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 2a4e 2a4e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a58 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a58 0x2a58 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2a4f 2a4f fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2a50 2a50 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2a51 2a51 fiu_len_fill_lit 45 zero-fill 0x5 fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2a52 2a52 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 val_rand 2 DEC_LOOP_COUNTER 2a53 2a53 fiu_fill_mode_src 0 ; Flow C 0x2ab4 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 2a54 2a54 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 22 VR06:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 6 2a55 2a55 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x2a44 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2a44 0x2a44 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 04 GP04 val_alu_func 0 PASS_A 2a56 2a56 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a52 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a52 0x2a52 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 2d VR05:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 2a57 2a57 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2a58 2a58 fiu_fill_mode_src 0 ; Flow J cc=False 0x2a5b fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a5b 0x2a5b seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 03 GP03 2a59 2a59 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2a5a 2a5a ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2a5b 2a5b fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2a5c 2a5c fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a5d 2a5d fiu_load_var 1 hold_var; Flow J 0x2a5a fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2a5a 0x2a5a seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 2a5e ; -------------------------------------------------------------------------------------- 2a5e ; Comes from: 2a5e ; 10fa C from color 0x10da 2a5e ; 1119 C from color 0x1106 2a5e ; 112c C from color 0x1107 2a5e ; 1257 C from color 0x1106 2a5e ; 1267 C from color 0x1231 2a5e ; 12eb C from color 0x128f 2a5e ; 1317 C True from color 0x1307 2a5e ; 1322 C from color 0x1307 2a5e ; 13cd C from color 0x13cc 2a5e ; 13ed C from color 0x13ec 2a5e ; 143f C from color 0x143c 2a5e ; 1771 C from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 2a5e ; 1f0b C from color 0x098b 2a5e ; 1f0e C True from color 0x098b 2a5e ; 2951 C from color MACRO_Execute_Any,Structure_Clear 2a5e ; -------------------------------------------------------------------------------------- 2a5e 2a5e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_alu_func 0 PASS_A val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 2a5f 2a5f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a65 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a65 0x2a65 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_alu_func 0 PASS_A typ_b_adr 35 TR02:15 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR04:0d val_frame 4 2a60 2a60 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2a62 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a62 0x2a62 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2a61 2a61 fiu_fill_mode_src 0 ; Flow J 0x2a8d fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a8d 0x2a8d typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2a62 2a62 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2a63 2a63 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a64 2a64 fiu_load_var 1 hold_var; Flow J 0x2a8d fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2a8d 0x2a8d seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 2a65 2a65 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x2a74 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a74 0x2a74 typ_a_adr 14 ZEROS val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a66 2a66 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a72 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a72 0x2a72 seq_cond_sel 64 OFFSET_REGISTER_???? typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_frame 5 2a67 2a67 fiu_fill_mode_src 0 ; Flow J cc=True 0x2a8d fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a8d 0x2a8d seq_cond_sel 65 CROSS_WORD_FIELD~ typ_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a68 2a68 fiu_load_oreg 1 hold_oreg; Flow J 0x2a69 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a69 0x2a69 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a69 2a69 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x2a70 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a70 0x2a70 seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 30 VR05:10 val_frame 5 2a6a 2a6a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a71 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2a71 0x2a71 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a6b 2a6b fiu_mem_start 4 continue; Flow J cc=True 0x2a8d fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 2a8d 0x2a8d seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR04:11 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 4 2a6c 2a6c fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2a6d 2a6d seq_en_micro 0 2a6e 2a6e fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x2a8d ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 2a8d 0x2a8d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 7 INC_A typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP 2a6f 2a6f fiu_mem_start 3 start-wr; Flow J 0x2a5e ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2a5e 0x2a5e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 2a70 2a70 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2a6b fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2a6b 0x2a6b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_mar_cntl b LOAD_MAR_DATA val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a71 2a71 fiu_mem_start 2 start-rd; Flow J 0x2a5e ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a5e 0x2a5e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 0 PASS_A 2a72 2a72 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a73 2a73 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2a69 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_op_sel 2 insert first fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a69 0x2a69 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a74 2a74 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a76 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a76 0x2a76 seq_cond_sel 64 OFFSET_REGISTER_???? typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a75 2a75 fiu_load_oreg 1 hold_oreg; Flow J 0x2a77 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2a77 0x2a77 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a76 2a76 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2a77 fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_op_sel 2 insert first fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a77 0x2a77 seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a77 2a77 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x2a79 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2a79 0x2a79 seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 30 VR05:10 val_frame 5 2a78 2a78 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2a7a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a7a 0x2a7a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a79 2a79 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2a7a fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 5 fiu_val ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a7a 0x2a7a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2a7a 2a7a fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x2a71 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a71 0x2a71 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 2a7b 2a7b fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x2a6b fiu_mem_start 7 start_wr_if_true fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a6b 0x2a6b seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 3f VR06:1f val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_frame 6 2a7c 2a7c fiu_mem_start 3 start-wr; Flow J cc=True 0x2a81 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a81 0x2a81 seq_cond_sel 13 VAL.Q_BIT(early) seq_en_micro 0 2a7d 2a7d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_en_micro 0 val_alu_func 1c DEC_A val_b_adr 0e GP0e val_c_adr 30 GP0f val_c_mux_sel 2 ALU 2a7e 2a7e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2a6f fiu_mem_start 7 start_wr_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 2a6f 0x2a6f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2a7f 2a7f ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a80 2a80 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_load_wdr 0 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 2a81 2a81 fiu_mem_start 4 continue seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a82 2a82 fiu_mem_start 4 continue; Flow J cc=False 0x2a8d fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a8d 0x2a8d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a83 2a83 fiu_mem_start 4 continue; Flow J cc=False 0x2a8d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a8d 0x2a8d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a84 2a84 fiu_mem_start 4 continue; Flow J cc=False 0x2a8d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a8d 0x2a8d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a85 2a85 fiu_mem_start 4 continue; Flow J cc=False 0x2a8d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a8d 0x2a8d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a86 2a86 fiu_mem_start 4 continue; Flow J cc=False 0x2a8d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a8d 0x2a8d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a87 2a87 fiu_mem_start 4 continue; Flow J cc=False 0x2a8d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a8d 0x2a8d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a88 2a88 fiu_mem_start 4 continue; Flow J cc=False 0x2a8d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a8d 0x2a8d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a89 2a89 fiu_mem_start 4 continue; Flow J cc=False 0x2a8d seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2a8d 0x2a8d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a8a 2a8a seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 2a8b 2a8b seq_br_type 4 Call False; Flow C cc=False 0x32cc seq_branch_adr 32cc 0x32cc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 5 DEC_A_MINUS_B val_b_adr 34 VR02:14 val_frame 2 2a8c 2a8c fiu_mem_start 3 start-wr; Flow J cc=True 0x2a82 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2a82 0x2a82 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2a8d 2a8d ioc_load_wdr 0 ; Flow C 0x2ab4 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 2a8e 2a8e fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x2a92 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a92 0x2a92 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 1 seq_random 13 ? typ_a_adr 26 TR05:06 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 2a8f 2a8f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2a93 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2a93 0x2a93 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2a90 2a90 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2a92 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2a92 0x2a92 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 3e ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2a91 2a91 seq_br_type 3 Unconditional Branch; Flow J 0x2a90 seq_branch_adr 2a90 0x2a90 val_rand 1 INC_LOOP_COUNTER 2a92 2a92 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2a94 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 2a94 0x2a94 seq_cond_sel 4a SEQ.ME_resolve_ref seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2a93 2a93 ioc_tvbs 2 fiu+val; Flow C cc=True 0x32de seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 2a94 2a94 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 2a95 2a95 fiu_mem_start d start_physical_rd; Flow J 0x2a96 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2a96 0x2a96 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a96 2a96 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 1c TR1d:03 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 1c VR1d:03 val_c_mux_sel 2 ALU val_frame 1d 2a97 2a97 fiu_mem_start d start_physical_rd ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a98 2a98 seq_en_micro 0 typ_a_adr 2b TR04:0b typ_alu_func 7 INC_A typ_c_adr 14 TR04:0b typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 2b VR04:0b val_alu_func 1 A_PLUS_B val_b_adr 2a VR04:0a val_c_adr 14 VR04:0b val_c_mux_sel 2 ALU val_frame 4 2a99 2a99 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start d start_physical_rd fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR1d:02 typ_c_source 0 FIU_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a9a 2a9a fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 20 VR1d:00 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR1d:02 val_c_mux_sel 2 ALU val_frame 1d 2a9b 2a9b fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 3f fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a9c 2a9c fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 32 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 6 A_MINUS_B val_b_adr 3d VR02:1d val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 val_rand 3 CONDITION_TO_FIU 2a9d 2a9d fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2a9e 2a9e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 30 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 val_a_adr 17 LOOP_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 2b VR04:0b val_c_adr 14 VR04:0b val_c_mux_sel 2 ALU val_frame 4 2a9f 2a9f fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2aa0 2aa0 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 0d fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 1d val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2aa1 2aa1 fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 36 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2aa2 2aa2 fiu_len_fill_lit 45 zero-fill 0x5; Flow C cc=True 0x20d fiu_load_tar 1 hold_tar fiu_offs_lit 33 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2aa3 2aa3 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 32 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2aa4 2aa4 fiu_len_fill_lit 43 zero-fill 0x3; Flow C cc=True 0x20d fiu_load_tar 1 hold_tar fiu_offs_lit 18 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2aa5 2aa5 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2aa6 2aa6 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x20d fiu_load_tar 1 hold_tar fiu_offs_lit 0c fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2aa7 2aa7 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start d start_physical_rd fiu_offs_lit 0f fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2aa8 2aa8 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x20d fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2aa9 2aa9 fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start d start_physical_rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2aaa 2aaa fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=True 0x20d fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_random 8 read and clear rtc ioc_tvbs 4 ioc+ioc seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2aab 2aab fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start d start_physical_rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2aac 2aac ioc_tvbs 1 typ+fiu; Flow J 0x2aae seq_br_type 3 Unconditional Branch seq_branch_adr 2aae 0x2aae seq_en_micro 0 val_a_adr 35 VR04:15 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0a VR04:15 val_c_mux_sel 2 ALU val_frame 4 2aad 2aad fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x20d fiu_load_var 1 hold_var fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020d 0x020d seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 13 LOOP_REG typ_alu_func 19 X_XOR_B typ_b_adr 13 LOOP_REG val_a_adr 13 LOOP_REG val_alu_func 19 X_XOR_B val_b_adr 13 LOOP_REG 2aae 2aae fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x2aad fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start d start_physical_rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2aad 0x2aad seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED typ_rand e CHECK_CLASS_SYSTEM_B val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d val_rand 1 INC_LOOP_COUNTER 2aaf 2aaf seq_b_timing 1 Latch Condition; Flow J cc=True 0x2ab5 seq_br_type 1 Branch True seq_branch_adr 2ab5 0x2ab5 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 34 TR0d:14 typ_alu_func 0 PASS_A typ_frame d val_a_adr 35 VR0d:15 val_alu_func 0 PASS_A val_c_adr 0b VR0d:14 val_c_mux_sel 2 ALU val_frame d 2ab0 2ab0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2ab2 fiu_load_tar 1 hold_tar fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2ab2 0x2ab2 seq_en_micro 0 typ_a_adr 22 TR1d:02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2ab1 2ab1 fiu_mem_start 18 acknowledge_refresh; Flow J 0x2ab3 fiu_tivi_src c mar_0xc seq_br_type 3 Unconditional Branch seq_branch_adr 2ab3 0x2ab3 seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 1d 2ab2 2ab2 seq_br_type 3 Unconditional Branch; Flow J 0x2ab3 seq_branch_adr 2ab3 0x2ab3 seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 1d 2ab3 2ab3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 13 ONES typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 1d 2ab4 ; -------------------------------------------------------------------------------------- 2ab4 ; Comes from: 2ab4 ; 0146 C from color 0x0146 2ab4 ; 0147 C from color 0x0147 2ab4 ; 0245 C from color 0x0245 2ab4 ; 0274 C from color 0x0274 2ab4 ; 02cc C from color 0x02c7 2ab4 ; 02ce C from color 0x02c2 2ab4 ; 02dd C from color 0x02d6 2ab4 ; 02df C from color 0x02d6 2ab4 ; 0302 C from color 0x0000 2ab4 ; 031f C from color MACRO_Action_Name_Partner 2ab4 ; 038b C from color 0x0000 2ab4 ; 03b6 C from color 0x0000 2ab4 ; 03df C from color 0x0000 2ab4 ; 0460 C from color 0x0460 2ab4 ; 049f C from color 0x049f 2ab4 ; 0568 C from color 0x0567 2ab4 ; 056c C from color 0x0000 2ab4 ; 058f C from color 0x058d 2ab4 ; 0596 C from color 0x0573 2ab4 ; 05af C from color 0x05af 2ab4 ; 05b6 C from color 0x05b5 2ab4 ; 05c8 C from color 0x05a7 2ab4 ; 0632 C from color 0x0000 2ab4 ; 0637 C from color 0x0000 2ab4 ; 06b6 C from color 0x06b6 2ab4 ; 06d7 C from color 0x06d2 2ab4 ; 06de C from color 0x06dc 2ab4 ; 070d C from color 0x0000 2ab4 ; 0718 C from color 0x0717 2ab4 ; 0736 C from color 0x0000 2ab4 ; 07a0 C from color 0x079f 2ab4 ; 07a1 C from color 0x079f 2ab4 ; 07ac C from color 0x07ab 2ab4 ; 07b5 C from color 0x07b5 2ab4 ; 07e8 C from color 0x07e8 2ab4 ; 080e C from color 0x0808 2ab4 ; 0839 C from color ME_PACKET 2ab4 ; 083e C from color ME_PACKET 2ab4 ; 0851 C from color 0x0820 2ab4 ; 085f C from color 0x0820 2ab4 ; 0869 C from color 0x0820 2ab4 ; 086f C from color 0x0820 2ab4 ; 0898 C from color 0x0000 2ab4 ; 08ff C from color 0x0127 2ab4 ; 090d C from color 0x090d 2ab4 ; 093e C from color 0x0921 2ab4 ; 0adb C from color 0x0ac4 2ab4 ; 0b55 C from color 0x0b53 2ab4 ; 0b61 C from color 0x0000 2ab4 ; 0b8e C from color 0x0b85 2ab4 ; 0b96 C from color 0x0b95 2ab4 ; 0ba9 C from color 0x0b95 2ab4 ; 0cbf C from color 0x0000 2ab4 ; 0ce9 C from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 2ab4 ; 0d03 C from color 0x0d03 2ab4 ; 0d9e C from color 0x0d65 2ab4 ; 0dc8 C from color 0x0dc3 2ab4 ; 0ebe C from color 0x0000 2ab4 ; 0ef5 C from color 0x0000 2ab4 ; 0f1e C from color UE_MEM_EXP 2ab4 ; 0f2f C from color 0x0f29 2ab4 ; 0fc1 C from color 0x0f29 2ab4 ; 0ff9 C from color 0x0f29 2ab4 ; 1003 C from color 0x1001 2ab4 ; 100a C from color 0x1004 2ab4 ; 101a C from color 0x1004 2ab4 ; 1029 C from color 0x1004 2ab4 ; 10ac C from color 0x109e 2ab4 ; 10af C from color 0x10ad 2ab4 ; 10b9 C from color 0x10ad 2ab4 ; 134b C from color 0x1346 2ab4 ; 1358 C from color 0x1346 2ab4 ; 1393 C from color 0x0000 2ab4 ; 1427 C from color MACRO_Declare_Variable_Array,With_Constraint 2ab4 ; 1448 C from color 0x1441 2ab4 ; 16f7 C from color 0x16f7 2ab4 ; 1746 C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 2ab4 ; 1748 C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 2ab4 ; 1751 C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 2ab4 ; 17c6 C from color 0x17c6 2ab4 ; 1896 C from color MACRO_Execute_Vector,Greater_Equal 2ab4 ; 1960 C from color 0x195c 2ab4 ; 1966 C from color 0x195c 2ab4 ; 197c C from color MACRO_Execute_Vector,Complement 2ab4 ; 1c85 C from color 0x1c85 2ab4 ; 1c8d C from color 0x0000 2ab4 ; 1c93 C from color 0x0000 2ab4 ; 1cb9 C from color MACRO_Execute_Array,Subarray 2ab4 ; 1d54 C from color 0x1cc6 2ab4 ; 1ecd C from color MACRO_Declare_Type_Record,Incomplete 2ab4 ; 1eec C from color MACRO_Complete_Type_Record,By_Renaming 2ab4 ; 1efa C from color MACRO_Complete_Type_Record,By_Renaming 2ab4 ; 1f24 C from color 0x098b 2ab4 ; 1f66 C from color 0x098b 2ab4 ; 1f6c C from color 0x098b 2ab4 ; 1f73 C from color 0x098b 2ab4 ; 1f76 C from color 0x098b 2ab4 ; 1f79 C from color 0x098b 2ab4 ; 201f C from color MACRO_Complete_Type_Array,By_Constraining 2ab4 ; 207c C from color 0x2042 2ab4 ; 2122 C from color 0x2042 2ab4 ; 21bd C from color MACRO_Declare_Type_Array,Constrained 2ab4 ; 2247 C from color 0x2035 2ab4 ; 225b C from color 0x2258 2ab4 ; 2273 C from color 0x2258 2ab4 ; 2288 C from color 0x1bae 2ab4 ; 228e C from color 0x1bae 2ab4 ; 22d4 C from color 0x22d2 2ab4 ; 22d7 C from color 0x22d2 2ab4 ; 22d8 C from color 0x22d8 2ab4 ; 22e8 C from color 0x09aa 2ab4 ; 22f4 C from color 0x22f3 2ab4 ; 22f6 C from color 0x22f3 2ab4 ; 22fc C from color 0x22fb 2ab4 ; 2307 C from color 0x0000 2ab4 ; 2308 C from color 0x0000 2ab4 ; 2313 C from color 0x0000 2ab4 ; 232b C from color MACRO_Declare_Type_Array,Incomplete 2ab4 ; 232d C from color MACRO_Declare_Type_Array,Incomplete 2ab4 ; 234c C from color 0x233d 2ab4 ; 23b0 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2ab4 ; 23b4 C from color 0x23b4 2ab4 ; 23be C from color 0x23be 2ab4 ; 23c3 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 2ab4 ; 23dd C from color 0x23dd 2ab4 ; 241f C from color 0x241f 2ab4 ; 246c C from color 0x246c 2ab4 ; 2482 C from color 0x2482 2ab4 ; 2491 C from color 0x0000 2ab4 ; 24a7 C from color 0x0000 2ab4 ; 24b0 C from color 0x24b0 2ab4 ; 2510 C from color 0x250a 2ab4 ; 2522 C from color 0x24ba 2ab4 ; 2540 C from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 2ab4 ; 254a C from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 2ab4 ; 2550 C from color 0x2550 2ab4 ; 2559 C from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 2ab4 ; 257f C from color 0x2569 2ab4 ; 25cc C from color 0x2569 2ab4 ; 260c C from color 0x260c 2ab4 ; 260e C from color 0x260e 2ab4 ; 2668 C from color MACRO_Complete_Type_Variant_Record,By_Renaming 2ab4 ; 267f C from color 0x2671 2ab4 ; 2684 C from color 0x2680 2ab4 ; 2694 C from color MACRO_Declare_Type_Variant_Record,Defined 2ab4 ; 26c0 C from color 0x26c0 2ab4 ; 26d9 C from color MACRO_Declare_Type_Variant_Record,Defined 2ab4 ; 2709 C from color 0x2709 2ab4 ; 270a C from color 0x270a 2ab4 ; 270b C from color 0x270b 2ab4 ; 270c C from color 0x270c 2ab4 ; 2731 C from color 0x272c 2ab4 ; 2736 C from color 0x272c 2ab4 ; 2749 C from color 0x2749 2ab4 ; 278a C from color 0x0000 2ab4 ; 27a4 C from color 0x0000 2ab4 ; 27ac C from color 0x0000 2ab4 ; 27eb C from color 0x0000 2ab4 ; 28cb C from color MACRO_Execute_Float,Exponentiate 2ab4 ; 28d5 C from color MACRO_Execute_Float,Exponentiate 2ab4 ; 2999 C from color MACRO_Action_Push_Structure_Extended,abs,mark 2ab4 ; 29d2 C from color MACRO_Action_Push_Structure_Extended,abs,mark 2ab4 ; 29dc C from color MACRO_Action_Push_Structure_Extended,abs,mark 2ab4 ; 29f6 C from color 0x0000 2ab4 ; 2a25 C from color 0x0000 2ab4 ; 2a31 C from color 0x0000 2ab4 ; 2a41 C from color 0x2a34 2ab4 ; 2a53 C from color 0x2a34 2ab4 ; 2a8a C from color 0x0000 2ab4 ; 2a8d C from color 0x0000 2ab4 ; 2ae6 C from color 0x0127 2ab4 ; 2d18 C from color 0x0000 2ab4 ; 2d1b C from color 0x0000 2ab4 ; 2d4c C from color 0x0000 2ab4 ; 2d5a C from color 0x2d51 2ab4 ; 2dc1 C from color 0x0000 2ab4 ; 2dff C from color 0x2dff 2ab4 ; 2e21 C from color 0x2e21 2ab4 ; 2e27 C from color 0x0000 2ab4 ; 2f1f C from color 0x2f17 2ab4 ; 2f8f C from color 0x0000 2ab4 ; 2fa6 C from color 0x2fa5 2ab4 ; 32c7 C from color 0x0000 2ab4 ; 3388 C from color MACRO_Action_Accept_Activation 2ab4 ; 33a4 C from color 0x0000 2ab4 ; 33af C from color 0x33af 2ab4 ; 33c1 C from color 0x0000 2ab4 ; 33d8 C from color 0x0000 2ab4 ; 340c C from color 0x0f36 2ab4 ; 3428 C from color 0x3411 2ab4 ; 3455 C from color 0x0b53 2ab4 ; 3456 C from color 0x0e8e 2ab4 ; 3461 C from color 0x3457 2ab4 ; 3469 C from color 0x3457 2ab4 ; 346e C from color 0x3457 2ab4 ; 34ca C from color 0x34a6 2ab4 ; 34cc C from color 0x34a6 2ab4 ; 34e1 C from color 0x0000 2ab4 ; 3504 C from color 0x3504 2ab4 ; 3510 C from color 0x3510 2ab4 ; 351d C from color 0x3511 2ab4 ; 355d C from color 0x0000 2ab4 ; 35c5 C from color 0x0000 2ab4 ; 3644 C from color 0x108b 2ab4 ; 3652 C from color 0x364d 2ab4 ; 36c1 C from color 0x36c1 2ab4 ; 376b C from color 0x376a 2ab4 ; 3815 C from color 0x3810 2ab4 ; 3827 C from color 0x3810 2ab4 ; 3887 C from color 0x0000 2ab4 ; 38c0 C from color 0x0000 2ab4 ; 38d1 C from color 0x2aef 2ab4 ; 393d C from color 0x393d 2ab4 ; 3a50 C from color 0x0000 2ab4 ; 3bad C from color 0x3bad 2ab4 ; 3bc2 C from color 0x3bbf 2ab4 ; 3bd7 C from color 0x3bcb 2ab4 ; -------------------------------------------------------------------------------------- 2ab4 2ab4 fiu_mem_start d start_physical_rd; Flow J 0x139 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 0139 0x0139 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 20 VR1d:00 val_alu_func 0 PASS_A val_c_adr 1e VR1d:01 val_c_source 0 FIU_BUS val_frame 1d 2ab5 2ab5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2ab7 fiu_load_tar 1 hold_tar fiu_mem_start d start_physical_rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2ab7 0x2ab7 seq_en_micro 0 typ_a_adr 22 TR1d:02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 20 VR1d:00 val_alu_func 2 INC_A_PLUS_B val_b_adr 24 VR1d:04 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 1d 2ab6 2ab6 fiu_mem_start 18 acknowledge_refresh; Flow J 0x2ab8 fiu_tivi_src c mar_0xc seq_br_type 3 Unconditional Branch seq_branch_adr 2ab8 0x2ab8 seq_en_micro 0 2ab7 2ab7 seq_br_type 3 Unconditional Branch; Flow J 0x2ab8 seq_branch_adr 2ab8 0x2ab8 seq_en_micro 0 2ab8 2ab8 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 20 TR1d:00 typ_alu_func 7 INC_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 1d 2ab9 2ab9 seq_en_micro 0 typ_a_adr 23 TR1d:03 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 23 VR1d:03 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 1d 2aba 2aba fiu_len_fill_reg_ctl 2 ; Flow R fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_alu_func 13 ONES typ_b_adr 21 TR1d:01 typ_c_adr 1e TR1d:01 typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl 4 RESTORE_MAR val_a_adr 22 VR1d:02 val_alu_func 1a PASS_B val_b_adr 21 VR1d:01 val_frame 1d 2abb 2abb fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src b type_frame ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 25 TR1d:05 typ_frame 1d typ_mar_cntl 4 RESTORE_MAR val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 25 VR1d:05 val_frame 1d val_rand 9 PASS_A_HIGH 2abc 2abc fiu_len_fill_lit 72 zero-fill 0x32; Flow J cc=True 0x18c fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 018c 0x018c seq_cond_sel 7a IOC.CHECKBIT_ERROR~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2abd 2abd fiu_len_fill_lit 4d zero-fill 0xd; Flow J cc=True 0x2aea fiu_offs_lit 42 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2aea 0x2aea seq_cond_sel 6d MAR_MODIFIED seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 10 NOT_A typ_c_adr 14 TR1d:0b typ_c_mux_sel 0 ALU typ_frame 1d val_c_adr 12 VR1d:0d val_c_source 0 FIU_BUS val_frame 1d 2abe 2abe fiu_fill_mode_src 0 ; Flow J 0x2abf fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2abf 0x2abf seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 18 TR1d:07 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2a VR1d:0a val_alu_func 1e A_AND_B val_b_adr 2c VR1d:0c val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 2abf 2abf fiu_fill_mode_src 0 ; Flow J 0x2ac0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2ac0 0x2ac0 seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 10 NOT_A typ_c_adr 15 TR1d:0a typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2a VR1d:0a val_alu_func 0 PASS_A val_c_adr 17 VR1d:08 val_c_source 0 FIU_BUS val_frame 1d 2ac0 2ac0 fiu_mem_start d start_physical_rd seq_en_micro 0 2ac1 2ac1 ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x2ac4 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2ac4 0x2ac4 seq_cond_sel 62 FIU.WRITE_LAST seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 17 TR1d:08 typ_c_mux_sel 0 ALU typ_frame 1d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 18 VR1d:07 val_c_mux_sel 2 ALU val_frame 1d 2ac2 2ac2 fiu_mem_start e start_physical_wr; Flow J cc=False 0x2acc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2acc 0x2acc seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 28 TR1d:08 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d val_a_adr 28 VR1d:08 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2ac3 2ac3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 2ac4 2ac4 fiu_vmux_sel 1 fill value; Flow J cc=True 0x2acc ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 2acc 0x2acc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR1d:0d val_alu_func 19 X_XOR_B val_b_adr 2f VR1d:0f val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2ac5 2ac5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 2ac6 2ac6 fiu_len_fill_lit 00 sign-fill 0x0; Flow C 0x210 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 62 FIU.WRITE_LAST seq_en_micro 0 typ_a_adr 2c TR08:0c typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 8 val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2ac7 2ac7 fiu_fill_mode_src 0 ; Flow J cc=False 0x2aca fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2aca 0x2aca seq_cond_sel 7a IOC.CHECKBIT_ERROR~ seq_en_micro 0 seq_random 06 Pop_stack+? typ_c_adr 14 TR1d:0b typ_c_source 0 FIU_BUS typ_frame 1d 2ac8 2ac8 fiu_len_fill_lit 00 sign-fill 0x0; Flow J cc=True 0x18d fiu_len_fill_reg_ctl 1 len=literal, fill=literal seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 018d 0x018d seq_cond_sel 78 IOC.MULTIBIT_ERROR seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 10 NOT_A typ_c_adr 14 TR1d:0b typ_c_mux_sel 0 ALU typ_frame 1d 2ac9 2ac9 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_frame 1d 2aca 2aca fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 2acb 2acb fiu_mem_start e start_physical_wr; Flow C 0x210 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 28 TR1d:08 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 1d val_a_adr 28 VR1d:08 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 1d 2acc 2acc fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 2a VR1d:0a val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 2acd 2acd fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 10 NOT_A typ_c_adr 15 TR1d:0a typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2a VR1d:0a val_frame 1d 2ace 2ace fiu_len_fill_lit 7b zero-fill 0x3b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 35 VR04:15 val_frame 4 2acf 2acf ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS 2ad0 2ad0 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 01 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_frame 1d 2ad1 2ad1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 5d fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 25 TR1d:05 typ_frame 1d val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 14 VR1d:0b val_c_mux_sel 2 ALU val_frame 1d 2ad2 2ad2 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 14 TR1d:0b typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2d VR1d:0d val_c_adr 15 VR1d:0a val_frame 1d 2ad3 2ad3 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_frame 1d val_a_adr 2a VR1d:0a val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 2ad4 2ad4 fiu_len_fill_lit 48 zero-fill 0x8 fiu_load_tar 1 hold_tar fiu_offs_lit 03 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 25 VR08:05 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 8 2ad5 2ad5 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val seq_en_micro 0 val_b_adr 2d VR12:0d val_frame 12 2ad6 2ad6 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2ad9 seq_br_type 1 Branch True seq_branch_adr 2ad9 0x2ad9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2c VR0d:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame d 2ad7 2ad7 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR1d:0a val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_frame 1d 2ad8 2ad8 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x2adb fiu_load_var 1 hold_var fiu_offs_lit 1b fiu_rdata_src 0 rotator ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2adb 0x2adb seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU 2ad9 2ad9 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR1d:0a val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_frame 1d 2ada 2ada ioc_tvbs 2 fiu+val; Flow J 0x2adb seq_br_type 3 Unconditional Branch seq_branch_adr 2adb 0x2adb seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU 2adb 2adb fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x2adf fiu_load_var 1 hold_var fiu_offs_lit 79 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2adf 0x2adf seq_en_micro 0 typ_a_adr 13 LOOP_REG val_a_adr 2d VR06:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 6 2adc 2adc fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER val_b_adr 30 VR02:10 val_frame 2 2add 2add fiu_len_fill_lit 40 zero-fill 0x0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 13 LOOP_REG val_b_adr 13 LOOP_REG 2ade 2ade ioc_tvbs 3 fiu+fiu; Flow J 0x2ae2 seq_br_type 3 Unconditional Branch seq_branch_adr 2ae2 0x2ae2 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU 2adf 2adf fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 20 TR08:00 typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2ae0 2ae0 fiu_len_fill_lit 40 zero-fill 0x0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 27 TR01:07 typ_frame 1 val_b_adr 27 VR01:07 val_frame 1 2ae1 2ae1 ioc_tvbs 3 fiu+fiu; Flow J 0x2ae2 seq_br_type 3 Unconditional Branch seq_branch_adr 2ae2 0x2ae2 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 18 TR01:07 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 18 VR01:07 val_c_mux_sel 2 ALU val_frame 1 2ae2 2ae2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2ae4 fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2ae4 0x2ae4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 2c TR1d:0c typ_b_adr 27 TR1d:07 typ_frame 1d 2ae3 2ae3 fiu_mem_start 18 acknowledge_refresh fiu_tivi_src c mar_0xc seq_en_micro 0 typ_a_adr 25 TR1d:05 typ_alu_func 0 PASS_A typ_b_adr 21 TR1d:01 typ_c_adr 1a TR1d:05 typ_c_mux_sel 0 ALU typ_frame 1d typ_rand 5 CHECK_CLASS_B_LIT 2ae4 2ae4 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 25 TR1d:05 typ_alu_func 0 PASS_A typ_b_adr 26 TR1d:06 typ_frame 1d val_a_adr 27 VR1d:07 val_b_adr 26 VR1d:06 val_frame 1d 2ae5 2ae5 fiu_len_fill_reg_ctl 2 ; Flow J cc=False 0x18e fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 018e 0x018e seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 0 PASS_A typ_b_adr 25 TR1d:05 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl 4 RESTORE_MAR val_a_adr 2b VR1d:0b val_alu_func 1a PASS_B val_b_adr 25 VR1d:05 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 1d 2ae6 2ae6 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 typ_a_adr 28 TR1d:08 typ_alu_func 0 PASS_A typ_c_adr 16 TR1d:09 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 28 VR1d:08 val_alu_func 0 PASS_A val_c_adr 16 VR1d:09 val_c_mux_sel 2 ALU val_frame 1d 2ae7 2ae7 seq_en_micro 0 typ_a_adr 29 TR1d:09 typ_alu_func 0 PASS_A typ_c_adr 17 TR1d:08 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 29 VR1d:09 val_alu_func 0 PASS_A val_c_adr 17 VR1d:08 val_c_mux_sel 2 ALU val_frame 1d 2ae8 2ae8 fiu_len_fill_lit 4d zero-fill 0xd; Flow J 0x18e fiu_offs_lit 42 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 018e 0x018e seq_en_micro 0 val_c_adr 12 VR1d:0d val_c_source 0 FIU_BUS val_frame 1d 2ae9 ; -------------------------------------------------------------------------------------- 2ae9 ; Comes from: 2ae9 ; 0189 C True from color 0x0127 2ae9 ; -------------------------------------------------------------------------------------- 2ae9 2ae9 fiu_mem_start 18 acknowledge_refresh; Flow R fiu_tivi_src c mar_0xc ioc_fiubs 2 typ seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 21 TR1d:01 typ_frame 1d val_c_adr 15 VR1d:0a val_c_source 0 FIU_BUS val_frame 1d 2aea 2aea fiu_fill_mode_src 0 ; Flow J cc=False 0x2abf fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2abf 0x2abf seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_a_adr 2b TR1d:0b typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 18 TR1d:07 typ_c_mux_sel 0 ALU typ_frame 1d val_a_adr 2a VR1d:0a val_alu_func 1e A_AND_B val_b_adr 2c VR1d:0c val_c_adr 15 VR1d:0a val_c_mux_sel 2 ALU val_frame 1d 2aeb 2aeb fiu_fill_mode_src 0 ; Flow J cc=True 0x2ac0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_random 11 disable ecc event ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2ac0 0x2ac0 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ seq_en_micro 0 typ_a_adr 2a TR1d:0a typ_alu_func 10 NOT_A typ_c_adr 15 TR1d:0a typ_c_mux_sel 0 ALU typ_frame 1d typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 2a VR1d:0a val_alu_func 1c DEC_A val_c_adr 17 VR1d:08 val_c_source 0 FIU_BUS val_frame 1d 2aec 2aec seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 2aed 2aed seq_br_type 2 Push (branch address); Flow J 0x2aee seq_branch_adr 01d1 0x01d1 seq_en_micro 0 2aee 2aee fiu_len_fill_lit 4d zero-fill 0xd; Flow J 0x8aa fiu_offs_lit 42 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 08aa 0x08aa seq_en_micro 0 val_c_adr 10 VR1d:0f val_c_source 0 FIU_BUS val_frame 1d 2aef ; -------------------------------------------------------------------------------------- 2aef ; Comes from: 2aef ; 061b C from color 0x0000 2aef ; 067e C from color 0x066a 2aef ; -------------------------------------------------------------------------------------- 2aef 2aef fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 34 TR11:14 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 11 val_a_adr 02 GP02 2af0 2af0 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 3e VR02:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 2af1 2af1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2af5 fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2af5 0x2af5 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_alu_func 1b A_OR_B typ_b_adr 21 TR01:01 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 6 A_MINUS_B val_b_adr 3d VR06:1d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2af2 2af2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2b0d fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2b0d 0x2b0d typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 3d VR06:1d val_alu_func 0 PASS_A val_b_adr 04 GP04 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2af3 2af3 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x2b00 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2b00 0x2b00 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 04 GP04 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 24 VR05:04 val_frame 5 2af4 2af4 ioc_load_wdr 0 ; Flow R ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 val_b_adr 04 GP04 2af5 2af5 fiu_mem_start 11 start_tag_query; Flow C cc=False 0x20a seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2af6 2af6 seq_br_type 7 Unconditional Call; Flow C 0x3524 seq_branch_adr 3524 0x3524 seq_en_micro 0 2af7 2af7 ioc_tvbs 8 typ+mem; Flow J cc=True 0x2afa seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2afa 0x2afa seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2af8 2af8 fiu_mem_start 2 start-rd; Flow C 0x34bf fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34bf 0x34bf typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 2af9 2af9 seq_br_type a Unconditional Return; Flow R seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 2afa 2afa fiu_mem_start 3 start-wr fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 2afb 2afb ioc_load_wdr 0 typ_b_adr 20 TR05:00 typ_frame 5 val_b_adr 39 VR02:19 val_frame 2 2afc 2afc fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 2afd 2afd fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 14 ZEROS 2afe 2afe fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 2aff 2aff ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 01 GP01 2b00 2b00 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2b01 2b01 <default> 2b02 2b02 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 2b03 2b03 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 05 GP05 val_alu_func 6 A_MINUS_B val_b_adr 3e VR06:1e val_frame 6 2b04 2b04 fiu_mem_start 3 start-wr; Flow J cc=False 0x2b08 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2b08 0x2b08 val_a_adr 3e VR06:1e val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 2b05 2b05 ioc_load_wdr 0 ; Flow C cc=False 0x20a ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 12 val_b_adr 05 GP05 2b06 2b06 fiu_mem_start 3 start-wr ioc_adrbs 2 typ seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 01 GP01 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 05 GP05 val_alu_func 1a PASS_B val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2b07 2b07 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 04 GP04 val_b_adr 04 GP04 2b08 2b08 ioc_load_wdr 0 ; Flow C cc=False 0x20a ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 12 2b09 2b09 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B 2b0a 2b0a <default> 2b0b 2b0b fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2b0c 2b0c ioc_fiubs 0 fiu ; Flow J 0x2b06 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2b06 0x2b06 val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2b0d ; -------------------------------------------------------------------------------------- 2b0d ; Comes from: 2b0d ; 2af2 C False from color 0x2aef 2b0d ; -------------------------------------------------------------------------------------- 2b0d 2b0d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 6 CHECK_CLASS_A_??_B 2b0e 2b0e fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x2b12 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2b12 0x2b12 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_frame 2 2b0f 2b0f fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2b10 2b10 ioc_load_wdr 0 ; Flow C cc=True 0x20a ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020a 0x020a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 12 val_b_adr 05 GP05 2b11 2b11 fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True ; Flow J cc=False 0x2b13 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 2b13 0x2b13 seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2b12 2b12 fiu_len_fill_lit 78 zero-fill 0x38; Flow J 0x2b13 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2b13 0x2b13 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2b13 2b13 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2b14 2b14 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 01 GP01 2b15 2b15 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2b16 2b16 ioc_load_wdr 0 ; Flow C cc=True 0x20a ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020a 0x020a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 12 val_b_adr 05 GP05 2b17 2b17 seq_br_type a Unconditional Return; Flow R 2b18 ; -------------------------------------------------------------------------------------- 2b18 ; 0x03d5 Declare_Type Access,Defined 2b18 ; -------------------------------------------------------------------------------------- 2b18 MACRO_Declare_Type_Access,Defined: 2b18 2b18 dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b18 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR00:01 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b19 2b19 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32d9 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2b1a 2b1a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2b28 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2b28 0x2b28 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2b1b 2b1b <halt> ; Flow R 2b1c ; -------------------------------------------------------------------------------------- 2b1c ; 0x03d6 Declare_Type Access,Defined,Visible 2b1c ; -------------------------------------------------------------------------------------- 2b1c MACRO_Declare_Type_Access,Defined,Visible: 2b1c 2b1c dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b1c seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b1d 2b1d fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 21 VR00:01 2b1e 2b1e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32d9 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2b1f 2b1f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2b28 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2b28 0x2b28 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2b20 ; -------------------------------------------------------------------------------------- 2b20 ; 0x03d3 Declare_Type Access,Defined,Accesses_Protected 2b20 ; -------------------------------------------------------------------------------------- 2b20 MACRO_Declare_Type_Access,Defined,Accesses_Protected: 2b20 2b20 dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b20 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b21 2b21 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32d9 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2b22 2b22 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2b28 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2b28 0x2b28 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2b23 2b23 <halt> ; Flow R 2b24 ; -------------------------------------------------------------------------------------- 2b24 ; 0x03d4 Declare_Type Access,Defined,Visible,Accesses_Protected 2b24 ; -------------------------------------------------------------------------------------- 2b24 MACRO_Declare_Type_Access,Defined,Visible,Accesses_Protected: 2b24 2b24 dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b24 seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b25 2b25 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1e TOP - 2 typ_alu_func 1c DEC_A typ_b_adr 1e TOP - 2 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 2b26 2b26 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32d9 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2b27 2b27 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2b28 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2b28 0x2b28 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2b28 2b28 fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR05:0d val_frame 5 2b29 2b29 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2b47 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2b47 0x2b47 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2b2a 2b2a fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x2b35 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2b35 0x2b35 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 09 GP09 typ_b_adr 03 GP03 val_b_adr 3a VR02:1a val_frame 2 2b2b 2b2b fiu_mem_start 4 continue; Flow J cc=True 0x2b2d ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2b2d 0x2b2d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2b2c 2b2c fiu_load_var 1 hold_var; Flow J 0x2b2e fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2b2e 0x2b2e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 09 GP09 val_a_adr 30 VR02:10 val_b_adr 09 GP09 val_frame 2 2b2d 2b2d fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_b_adr 09 GP09 val_frame 2 2b2e 2b2e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32d7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 10 TOP 2b2f 2b2f fiu_fill_mode_src 0 ; Flow C 0x352d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 7 Unconditional Call seq_branch_adr 352d 0x352d typ_a_adr 1e TOP - 2 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 2b30 2b30 ioc_load_wdr 0 ; Flow C cc=True 0x2b32 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2b32 0x2b32 typ_b_adr 1e TOP - 2 typ_csa_cntl 3 POP_CSA 2b31 2b31 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2b32 ; -------------------------------------------------------------------------------------- 2b32 ; Comes from: 2b32 ; 2b30 C True from color 0x2b2f 2b32 ; -------------------------------------------------------------------------------------- 2b32 2b32 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2b33 2b33 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3b fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_frame 2 2b34 2b34 ioc_load_wdr 0 ; Flow R ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return val_b_adr 09 GP09 2b35 ; -------------------------------------------------------------------------------------- 2b35 ; Comes from: 2b35 ; 2b2a C #0x0 from color 0x2b19 2b35 ; -------------------------------------------------------------------------------------- 2b35 2b35 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b36 2b36 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b37 2b37 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b38 2b38 fiu_mem_start 3 start-wr; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 0210 0x0210 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b39 2b39 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b3a 2b3a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b3b 2b3b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b3c 2b3c fiu_mem_start 3 start-wr; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 0210 0x0210 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b3d 2b3d fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b3e 2b3e seq_br_type 3 Unconditional Branch; Flow J 0x2b45 seq_branch_adr 2b45 0x2b45 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2b3f 2b3f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b40 2b40 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b41 2b41 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b42 2b42 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b46 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b46 0x2b46 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b43 2b43 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b46 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b46 0x2b46 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b44 2b44 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b46 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b46 0x2b46 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b45 2b45 fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b46 2b46 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 1e TOP - 2 2b47 2b47 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x2b4a fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2b4a 0x2b4a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 09 GP09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_b_adr 3a VR02:1a val_frame 2 2b48 2b48 fiu_mem_start 4 continue ioc_fiubs 1 val ioc_load_wdr 0 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2b49 2b49 fiu_load_var 1 hold_var; Flow J 0x2b2e fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2b2e 0x2b2e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 09 GP09 val_a_adr 30 VR02:10 val_b_adr 09 GP09 val_frame 2 2b4a ; -------------------------------------------------------------------------------------- 2b4a ; Comes from: 2b4a ; 2b47 C #0x0 from color 0x2b19 2b4a ; -------------------------------------------------------------------------------------- 2b4a 2b4a seq_br_type 3 Unconditional Branch; Flow J 0x2b5a seq_branch_adr 2b5a 0x2b5a val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2b4b 2b4b fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b4c 2b4c fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b4d 2b4d fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b5c fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b5c 0x2b5c typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b4e 2b4e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b4f 2b4f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b50 2b50 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b51 2b51 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b5c fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b5c 0x2b5c typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b52 2b52 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b5e fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b5e 0x2b5e typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b53 2b53 seq_br_type 3 Unconditional Branch; Flow J 0x2b5d seq_branch_adr 2b5d 0x2b5d typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2b54 2b54 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b55 2b55 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b56 2b56 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2b57 2b57 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b5f fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b5f 0x2b5f typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b58 2b58 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b5f fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b5f 0x2b5f typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b59 2b59 fiu_mem_start 7 start_wr_if_true; Flow R cc=True ; Flow J cc=False 0x2b5f fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b5f 0x2b5f typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b5a 2b5a typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 32 TR11:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 2b5b 2b5b fiu_mem_start 3 start-wr; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 21 TR00:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 2b5c 2b5c fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 0 PASS_A 2b5d 2b5d fiu_mem_start 7 start_wr_if_true; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2b5e 0x2b5e typ_a_adr 1e TOP - 2 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 2b5e 2b5e seq_br_type 3 Unconditional Branch; Flow J 0x2b60 seq_branch_adr 2b60 0x2b60 typ_a_adr 1e TOP - 2 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 2b5f 2b5f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2b5c seq_br_type 1 Branch True seq_branch_adr 2b5c 0x2b5c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1e TOP - 2 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 1 2b60 2b60 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 22 TR02:02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 val_alu_func 0 PASS_A 2b61 2b61 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 1f TOP - 1 2b62 2b62 fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 1e TOP - 2 typ_b_adr 09 GP09 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2b63 2b63 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 04 GP04 val_b_adr 39 VR02:19 val_frame 2 2b64 2b64 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2b65 2b65 <halt> ; Flow R 2b66 ; -------------------------------------------------------------------------------------- 2b66 ; 0x03ce Declare_Type Access,Incomplete 2b66 ; -------------------------------------------------------------------------------------- 2b66 MACRO_Declare_Type_Access,Incomplete: 2b66 2b66 dispatch_brk_class 4 ; Flow J 0x2b6e dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b66 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b6e 0x2b6e typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 22 TR00:02 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b67 2b67 <halt> ; Flow R 2b68 ; -------------------------------------------------------------------------------------- 2b68 ; 0x03cf Declare_Type Access,Incomplete,Visible 2b68 ; -------------------------------------------------------------------------------------- 2b68 MACRO_Declare_Type_Access,Incomplete,Visible: 2b68 2b68 dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b68 seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2b69 2b69 fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x2b6e fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b6e 0x2b6e typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 22 TR00:02 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b6a ; -------------------------------------------------------------------------------------- 2b6a ; 0x03cc Declare_Type Access,Incomplete,Accesses_Protected 2b6a ; -------------------------------------------------------------------------------------- 2b6a MACRO_Declare_Type_Access,Incomplete,Accesses_Protected: 2b6a 2b6a dispatch_brk_class 4 ; Flow J 0x2b6e dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b6a fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b6e 0x2b6e typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 23 TR00:03 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b6b 2b6b <halt> ; Flow R 2b6c ; -------------------------------------------------------------------------------------- 2b6c ; 0x03cd Declare_Type Access,Incomplete,Visible,Accesses_Protected 2b6c ; -------------------------------------------------------------------------------------- 2b6c MACRO_Declare_Type_Access,Incomplete,Visible,Accesses_Protected: 2b6c 2b6c dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2b6c seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2b6d 2b6d fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x2b6e fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b6e 0x2b6e typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 23 TR00:03 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b6e 2b6e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32d9 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 2b6f 2b6f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32d9 fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR05:0d val_frame 5 2b70 2b70 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert ioc_load_wdr 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_b_adr 39 VR02:19 val_frame 2 2b71 2b71 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 09 GP09 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_alu_func 1b A_OR_B val_b_adr 3d VR02:1d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2b72 2b72 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2b73 2b73 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 2b74 2b74 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 2b75 2b75 <halt> ; Flow R 2b76 ; -------------------------------------------------------------------------------------- 2b76 ; 0x038e Declare_Type Package,Defined 2b76 ; -------------------------------------------------------------------------------------- 2b76 MACRO_Declare_Type_Package,Defined: 2b76 2b76 dispatch_brk_class 4 ; Flow J 0x2b85 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b76 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b85 0x2b85 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 36 TR05:16 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 22 VR06:02 val_frame 6 2b77 ; -------------------------------------------------------------------------------------- 2b77 ; Comes from: 2b77 ; 2b91 C from color MACRO_Declare_Type_Task,Incomplete 2b77 ; 2b98 C from color 0x2b81 2b77 ; -------------------------------------------------------------------------------------- 2b77 2b77 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 2b78 ; -------------------------------------------------------------------------------------- 2b78 ; 0x038c Declare_Type Package,Defined,Not_Elaborated 2b78 ; -------------------------------------------------------------------------------------- 2b78 MACRO_Declare_Type_Package,Defined,Not_Elaborated: 2b78 2b78 dispatch_brk_class 4 ; Flow J 0x2b85 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b78 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b85 0x2b85 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 36 TR05:16 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 39 VR02:19 val_frame 2 2b79 2b79 fiu_len_fill_lit 53 zero-fill 0x13; Flow R cc=False ; Flow J cc=True 0x2b88 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2b88 0x2b88 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR02:1c val_frame 2 2b7a ; -------------------------------------------------------------------------------------- 2b7a ; 0x038f Declare_Type Package,Defined,Visible 2b7a ; -------------------------------------------------------------------------------------- 2b7a MACRO_Declare_Type_Package,Defined,Visible: 2b7a 2b7a dispatch_brk_class 4 ; Flow J 0x2b85 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b7a fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b85 0x2b85 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 25 TR06:05 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 22 VR06:02 val_frame 6 2b7b 2b7b fiu_mem_start 4 continue; Flow J 0x2b7d ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2b7d 0x2b7d typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 2b7c ; -------------------------------------------------------------------------------------- 2b7c ; 0x038d Declare_Type Package,Defined,Visible,Not_Elaborated 2b7c ; -------------------------------------------------------------------------------------- 2b7c MACRO_Declare_Type_Package,Defined,Visible,Not_Elaborated: 2b7c 2b7c dispatch_brk_class 4 ; Flow J 0x2b85 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b7c fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b85 0x2b85 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 25 TR06:05 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 39 VR02:19 val_frame 2 2b7d 2b7d ioc_load_wdr 0 ; Flow J 0x2b7f ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2b7f 0x2b7f seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_b_adr 03 GP03 2b7e ; -------------------------------------------------------------------------------------- 2b7e ; 0x037d Declare_Type Task,Defined 2b7e ; -------------------------------------------------------------------------------------- 2b7e MACRO_Declare_Type_Task,Defined: 2b7e 2b7e dispatch_brk_class 4 ; Flow J 0x2b85 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b7e fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b85 0x2b85 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 35 TR05:15 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 27 VR06:07 val_frame 6 2b7f 2b7f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 2b80 ; -------------------------------------------------------------------------------------- 2b80 ; 0x037e Declare_Type Task,Defined,Visible 2b80 ; -------------------------------------------------------------------------------------- 2b80 MACRO_Declare_Type_Task,Defined,Visible: 2b80 2b80 dispatch_brk_class 4 ; Flow J 0x2b85 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b80 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b85 0x2b85 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 24 TR06:04 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 27 VR06:07 val_frame 6 2b81 2b81 ioc_load_wdr 0 ; Flow J 0x2b83 seq_br_type 3 Unconditional Branch seq_branch_adr 2b83 0x2b83 typ_b_adr 01 GP01 val_b_adr 01 GP01 2b82 ; -------------------------------------------------------------------------------------- 2b82 ; 0x037a Declare_Type Task,Defined,Not_Elaborated 2b82 ; -------------------------------------------------------------------------------------- 2b82 MACRO_Declare_Type_Task,Defined,Not_Elaborated: 2b82 2b82 dispatch_brk_class 4 ; Flow J 0x2b85 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b82 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b85 0x2b85 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 35 TR05:15 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR06:00 val_frame 6 2b83 2b83 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2b84 ; -------------------------------------------------------------------------------------- 2b84 ; 0x037b Declare_Type Task,Defined,Visible,Not_Elaborated 2b84 ; -------------------------------------------------------------------------------------- 2b84 MACRO_Declare_Type_Task,Defined,Visible,Not_Elaborated: 2b84 2b84 dispatch_brk_class 4 ; Flow J 0x2b85 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2b84 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b85 0x2b85 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 24 TR06:04 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 20 VR06:00 val_frame 6 2b85 2b85 seq_br_type 2 Push (branch address); Flow J 0x2b86 seq_branch_adr 32a9 0x32a9 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 11 2b86 2b86 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2b79 fiu_load_mdr 1 hold_mdr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2b79 0x2b79 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 03 GP03 val_alu_func 1b A_OR_B val_b_adr 31 VR02:11 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2b87 2b87 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x2b88 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b88 0x2b88 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR02:1c val_frame 2 2b88 2b88 fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x32d7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_b_adr 10 TOP 2b89 2b89 fiu_mem_start 4 continue; Flow J 0x2b7b ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2b7b 0x2b7b typ_a_adr 3e TR06:1e typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 29 VR06:09 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2b8a ; -------------------------------------------------------------------------------------- 2b8a ; 0x0377 Declare_Type Task,Incomplete 2b8a ; -------------------------------------------------------------------------------------- 2b8a MACRO_Declare_Type_Task,Incomplete: 2b8a 2b8a dispatch_brk_class 4 ; Flow J 0x2b8d dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b8a fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b8d 0x2b8d seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 35 TR05:15 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR06:00 val_frame 6 2b8b 2b8b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 2b8c ; -------------------------------------------------------------------------------------- 2b8c ; 0x0378 Declare_Type Task,Incomplete,Visible 2b8c ; -------------------------------------------------------------------------------------- 2b8c MACRO_Declare_Type_Task,Incomplete,Visible: 2b8c 2b8c dispatch_brk_class 4 ; Flow J 0x2b8d dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2b8c fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2b8d 0x2b8d seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 24 TR06:04 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 20 VR06:00 val_frame 6 2b8d 2b8d ioc_fiubs 1 val ; Flow J 0x2b8e seq_br_type 2 Push (branch address) seq_branch_adr 32a9 0x32a9 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR02:1c val_frame 2 2b8e 2b8e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2b90 fiu_load_mdr 1 hold_mdr fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2b90 0x2b90 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 22 TR02:02 typ_frame 2 2b8f 2b8f fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x2b91 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2b91 0x2b91 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR06:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2b90 2b90 fiu_len_fill_lit 53 zero-fill 0x13; Flow R cc=False fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2b91 0x2b91 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR06:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2b91 2b91 fiu_mem_start 3 start-wr; Flow C 0x2b77 fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 2b77 0x2b77 typ_a_adr 32 TR02:12 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 29 VR06:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2b92 2b92 fiu_mem_start 4 continue ioc_load_wdr 0 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 2b93 2b93 ioc_load_wdr 0 ; Flow J 0x2b8b ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2b8b 0x2b8b seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2b94 ; -------------------------------------------------------------------------------------- 2b94 ; 0x0374 Complete_Type Task,By_Renaming 2b94 ; -------------------------------------------------------------------------------------- 2b94 MACRO_Complete_Type_Task,By_Renaming: 2b94 2b94 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2b94 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 2b95 2b95 fiu_mem_start 4 continue ioc_fiubs 2 typ typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_frame 18 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2b96 2b96 fiu_mem_start 4 continue; Flow C 0x210 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 16 CSA/VAL_BUS typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR 2b97 2b97 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2b98 2b98 fiu_mem_start 3 start-wr; Flow C 0x2b77 fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2b77 0x2b77 seq_random 02 ? typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 4 2b99 2b99 fiu_mem_start 4 continue; Flow J 0x2b81 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2b81 0x2b81 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 2b9a ; -------------------------------------------------------------------------------------- 2b9a ; 0x009c Action Load_Dynamic 2b9a ; -------------------------------------------------------------------------------------- 2b9a MACRO_Action_Load_Dynamic: 2b9a 2b9a dispatch_brk_class 8 ; Flow C 0x2ca0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2b9a seq_br_type 7 Unconditional Call seq_branch_adr 2ca0 0x2ca0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 2b9b 2b9b fiu_mem_start 2 start-rd 2b9c ; -------------------------------------------------------------------------------------- 2b9c ; 0xe000-0xffff Load llvl,ldelta 2b9c ; -------------------------------------------------------------------------------------- 2b9c MACRO_Load_llvl,ldelta: 2b9c 2b9c dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 2b9c 2b9d 2b9d fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b9e 0x2b9e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2b9e 2b9e fiu_load_var 1 hold_var; Flow J cc=True 0x2b9f ; Flow J cc=#0x0 0x2ba0 fiu_mem_start 5 start_rd_if_true fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 2ba0 0x2ba0 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 6 2b9f 2b9f fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2ba8 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2ba8 0x2ba8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x03) Discrete_Var Float_Var Access_Var Task_Var Heap_Access_Var Package_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2ba0 2ba0 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2ba1 2ba1 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 2ba2 2ba2 seq_br_type 3 Unconditional Branch; Flow J 0x2ba9 seq_branch_adr 2ba9 0x2ba9 2ba3 2ba3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2ba4 2ba4 fiu_mem_start 6 start_rd_if_false; Flow J 0x2baa ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2baa 0x2baa seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref seq_en_micro 0 seq_latch 1 typ_a_adr 11 TOP + 1 typ_alu_func 1c DEC_A typ_b_adr 11 TOP + 1 typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2ba5 2ba5 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2ba8 ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2ba8 0x2ba8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x17) Module_Key Deletion_Key seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2ba6 2ba6 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2ba8 ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2ba8 0x2ba8 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x18) Select_Var Default_Var Exception_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2ba7 2ba7 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 2ba8 2ba8 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de seq_en_micro 0 typ_csa_cntl 3 POP_CSA 2ba9 2ba9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2baa 2baa ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x2bb2 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2bb2 0x2bb2 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2bab 2bab fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 2bac 2bac fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2bae fiu_load_tar 1 hold_tar fiu_mem_start a start_continue_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2bae 0x2bae seq_cond_sel 65 CROSS_WORD_FIELD~ seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR05:01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR 2bad 2bad fiu_fill_mode_src 0 ; Flow R cc=False ; Flow J cc=True 0x2bb0 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2bb0 0x2bb0 seq_random 04 Load_save_offset+? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2bae 2bae fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2baf 2baf fiu_fill_mode_src 0 ; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2bb0 0x2bb0 seq_random 04 Load_save_offset+? typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2bb0 2bb0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2bb1 0x2bb1 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_random 04 Load_save_offset+? typ_a_adr 35 TR07:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 02 GP02 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2bb1 2bb1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2bb2 2bb2 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2bb3 0x2bb3 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2bb3 2bb3 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_en_micro 0 typ_csa_cntl 3 POP_CSA 2bb4 ; -------------------------------------------------------------------------------------- 2bb4 ; 0x00d8 Load_Top At_Offset_0 2bb4 ; -------------------------------------------------------------------------------------- 2bb4 MACRO_Load_Top_At_Offset_0: 2bb4 2bb4 dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b9e dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2bb4 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b9e 0x2b9e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2bb5 2bb5 <halt> ; Flow R 2bb6 ; -------------------------------------------------------------------------------------- 2bb6 ; 0x00d9 Load_Top At_Offset_1 2bb6 ; -------------------------------------------------------------------------------------- 2bb6 MACRO_Load_Top_At_Offset_1: 2bb6 2bb6 dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b9e dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2bb6 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b9e 0x2b9e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1f TOP - 1 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2bb7 2bb7 <halt> ; Flow R 2bb8 ; -------------------------------------------------------------------------------------- 2bb8 ; 0x00da Load_Top At_Offset_2 2bb8 ; -------------------------------------------------------------------------------------- 2bb8 MACRO_Load_Top_At_Offset_2: 2bb8 2bb8 dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b9e dispatch_csa_free 1 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2bb8 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b9e 0x2b9e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1e TOP - 2 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2bb9 2bb9 <halt> ; Flow R 2bba ; -------------------------------------------------------------------------------------- 2bba ; 0x00db Load_Top At_Offset_3 2bba ; -------------------------------------------------------------------------------------- 2bba MACRO_Load_Top_At_Offset_3: 2bba 2bba dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b9e dispatch_csa_free 1 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2bba fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b9e 0x2b9e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1d TOP - 3 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1d TOP - 3 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2bbb 2bbb <halt> ; Flow R 2bbc ; -------------------------------------------------------------------------------------- 2bbc ; 0x00dc Load_Top At_Offset_4 2bbc ; -------------------------------------------------------------------------------------- 2bbc MACRO_Load_Top_At_Offset_4: 2bbc 2bbc dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b9e dispatch_csa_free 1 dispatch_csa_valid 5 dispatch_ignore 1 dispatch_uadr 2bbc fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b9e 0x2b9e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1c TOP - 4 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1c TOP - 4 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2bbd 2bbd <halt> ; Flow R 2bbe ; -------------------------------------------------------------------------------------- 2bbe ; 0x00dd Load_Top At_Offset_5 2bbe ; -------------------------------------------------------------------------------------- 2bbe MACRO_Load_Top_At_Offset_5: 2bbe 2bbe dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b9e dispatch_csa_free 1 dispatch_csa_valid 6 dispatch_ignore 1 dispatch_uadr 2bbe fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b9e 0x2b9e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1b TOP - 5 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1b TOP - 5 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2bbf 2bbf <halt> ; Flow R 2bc0 ; -------------------------------------------------------------------------------------- 2bc0 ; 0x00de Load_Top At_Offset_6 2bc0 ; -------------------------------------------------------------------------------------- 2bc0 MACRO_Load_Top_At_Offset_6: 2bc0 2bc0 dispatch_brk_class 8 ; Flow R cc=False ; Flow J cc=True 0x2b9e dispatch_csa_free 1 dispatch_csa_valid 7 dispatch_ignore 1 dispatch_uadr 2bc0 fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2b9e 0x2b9e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR16:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 1a TOP - 6 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 1a TOP - 6 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2bc1 2bc1 <halt> ; Flow R 2bc2 ; -------------------------------------------------------------------------------------- 2bc2 ; 0x00e0 Load_Encached eon 2bc2 ; -------------------------------------------------------------------------------------- 2bc2 MACRO_Load_Encached_eon: 2bc2 2bc2 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 20 TR0b:00 typ_alu_func 15 NOT_B typ_b_adr 20 TR0b:00 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 20 VR0b:00 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc3 2bc3 <halt> ; Flow R 2bc4 ; -------------------------------------------------------------------------------------- 2bc4 ; 0x00e1 Load_Encached eon 2bc4 ; -------------------------------------------------------------------------------------- 2bc4 MACRO_Load_Encached_eon: 2bc4 2bc4 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR0b:01 typ_alu_func 15 NOT_B typ_b_adr 21 TR0b:01 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 21 VR0b:01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc5 2bc5 <halt> ; Flow R 2bc6 ; -------------------------------------------------------------------------------------- 2bc6 ; 0x00e2 Load_Encached eon 2bc6 ; -------------------------------------------------------------------------------------- 2bc6 MACRO_Load_Encached_eon: 2bc6 2bc6 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 22 TR0b:02 typ_alu_func 15 NOT_B typ_b_adr 22 TR0b:02 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 22 VR0b:02 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc7 2bc7 <halt> ; Flow R 2bc8 ; -------------------------------------------------------------------------------------- 2bc8 ; 0x00e3 Load_Encached eon 2bc8 ; -------------------------------------------------------------------------------------- 2bc8 MACRO_Load_Encached_eon: 2bc8 2bc8 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bc8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 23 TR0b:03 typ_alu_func 15 NOT_B typ_b_adr 23 TR0b:03 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 23 VR0b:03 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bc9 2bc9 <halt> ; Flow R 2bca ; -------------------------------------------------------------------------------------- 2bca ; 0x00e4 Load_Encached eon 2bca ; -------------------------------------------------------------------------------------- 2bca MACRO_Load_Encached_eon: 2bca 2bca dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bca fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 24 TR0b:04 typ_alu_func 15 NOT_B typ_b_adr 24 TR0b:04 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 24 VR0b:04 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bcb 2bcb <halt> ; Flow R 2bcc ; -------------------------------------------------------------------------------------- 2bcc ; 0x00e5 Load_Encached eon 2bcc ; -------------------------------------------------------------------------------------- 2bcc MACRO_Load_Encached_eon: 2bcc 2bcc dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bcc fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 25 TR0b:05 typ_alu_func 15 NOT_B typ_b_adr 25 TR0b:05 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 25 VR0b:05 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bcd 2bcd <halt> ; Flow R 2bce ; -------------------------------------------------------------------------------------- 2bce ; 0x00e6 Load_Encached eon 2bce ; -------------------------------------------------------------------------------------- 2bce MACRO_Load_Encached_eon: 2bce 2bce dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bce fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 26 TR0b:06 typ_alu_func 15 NOT_B typ_b_adr 26 TR0b:06 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 26 VR0b:06 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bcf 2bcf <halt> ; Flow R 2bd0 ; -------------------------------------------------------------------------------------- 2bd0 ; 0x00e7 Load_Encached eon 2bd0 ; -------------------------------------------------------------------------------------- 2bd0 MACRO_Load_Encached_eon: 2bd0 2bd0 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bd0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 27 TR0b:07 typ_alu_func 15 NOT_B typ_b_adr 27 TR0b:07 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 27 VR0b:07 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bd1 2bd1 <halt> ; Flow R 2bd2 ; -------------------------------------------------------------------------------------- 2bd2 ; 0x00e8 Load_Encached eon 2bd2 ; -------------------------------------------------------------------------------------- 2bd2 MACRO_Load_Encached_eon: 2bd2 2bd2 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bd2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 28 TR0b:08 typ_alu_func 15 NOT_B typ_b_adr 28 TR0b:08 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 28 VR0b:08 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bd3 2bd3 <halt> ; Flow R 2bd4 ; -------------------------------------------------------------------------------------- 2bd4 ; 0x00e9 Load_Encached eon 2bd4 ; -------------------------------------------------------------------------------------- 2bd4 MACRO_Load_Encached_eon: 2bd4 2bd4 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bd4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 29 TR0b:09 typ_alu_func 15 NOT_B typ_b_adr 29 TR0b:09 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 29 VR0b:09 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bd5 2bd5 <halt> ; Flow R 2bd6 ; -------------------------------------------------------------------------------------- 2bd6 ; 0x00ea Load_Encached eon 2bd6 ; -------------------------------------------------------------------------------------- 2bd6 MACRO_Load_Encached_eon: 2bd6 2bd6 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bd6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2a TR0b:0a typ_alu_func 15 NOT_B typ_b_adr 2a TR0b:0a typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2a VR0b:0a val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bd7 2bd7 <halt> ; Flow R 2bd8 ; -------------------------------------------------------------------------------------- 2bd8 ; 0x00eb Load_Encached eon 2bd8 ; -------------------------------------------------------------------------------------- 2bd8 MACRO_Load_Encached_eon: 2bd8 2bd8 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bd8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2b TR0b:0b typ_alu_func 15 NOT_B typ_b_adr 2b TR0b:0b typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2b VR0b:0b val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bd9 2bd9 <halt> ; Flow R 2bda ; -------------------------------------------------------------------------------------- 2bda ; 0x00ec Load_Encached eon 2bda ; -------------------------------------------------------------------------------------- 2bda MACRO_Load_Encached_eon: 2bda 2bda dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bda fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2c TR0b:0c typ_alu_func 15 NOT_B typ_b_adr 2c TR0b:0c typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2c VR0b:0c val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bdb 2bdb <halt> ; Flow R 2bdc ; -------------------------------------------------------------------------------------- 2bdc ; 0x00ed Load_Encached eon 2bdc ; -------------------------------------------------------------------------------------- 2bdc MACRO_Load_Encached_eon: 2bdc 2bdc dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bdc fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2d TR0b:0d typ_alu_func 15 NOT_B typ_b_adr 2d TR0b:0d typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2d VR0b:0d val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bdd 2bdd <halt> ; Flow R 2bde ; -------------------------------------------------------------------------------------- 2bde ; 0x00ee Load_Encached eon 2bde ; -------------------------------------------------------------------------------------- 2bde MACRO_Load_Encached_eon: 2bde 2bde dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bde fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2e TR0b:0e typ_alu_func 15 NOT_B typ_b_adr 2e TR0b:0e typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR0b:0e val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bdf 2bdf <halt> ; Flow R 2be0 ; -------------------------------------------------------------------------------------- 2be0 ; 0x00ef Load_Encached eon 2be0 ; -------------------------------------------------------------------------------------- 2be0 MACRO_Load_Encached_eon: 2be0 2be0 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2be0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 2f TR0b:0f typ_alu_func 15 NOT_B typ_b_adr 2f TR0b:0f typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2f VR0b:0f val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2be1 2be1 <halt> ; Flow R 2be2 ; -------------------------------------------------------------------------------------- 2be2 ; 0x00f0 Load_Encached eon 2be2 ; -------------------------------------------------------------------------------------- 2be2 MACRO_Load_Encached_eon: 2be2 2be2 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2be2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 30 TR0b:10 typ_alu_func 15 NOT_B typ_b_adr 30 TR0b:10 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 30 VR0b:10 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2be3 2be3 <halt> ; Flow R 2be4 ; -------------------------------------------------------------------------------------- 2be4 ; 0x00f1 Load_Encached eon 2be4 ; -------------------------------------------------------------------------------------- 2be4 MACRO_Load_Encached_eon: 2be4 2be4 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2be4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 31 TR0b:11 typ_alu_func 15 NOT_B typ_b_adr 31 TR0b:11 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 31 VR0b:11 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2be5 2be5 <halt> ; Flow R 2be6 ; -------------------------------------------------------------------------------------- 2be6 ; 0x00f2 Load_Encached eon 2be6 ; -------------------------------------------------------------------------------------- 2be6 MACRO_Load_Encached_eon: 2be6 2be6 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2be6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 32 TR0b:12 typ_alu_func 15 NOT_B typ_b_adr 32 TR0b:12 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 32 VR0b:12 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2be7 2be7 <halt> ; Flow R 2be8 ; -------------------------------------------------------------------------------------- 2be8 ; 0x00f3 Load_Encached eon 2be8 ; -------------------------------------------------------------------------------------- 2be8 MACRO_Load_Encached_eon: 2be8 2be8 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2be8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 33 TR0b:13 typ_alu_func 15 NOT_B typ_b_adr 33 TR0b:13 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 33 VR0b:13 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2be9 2be9 <halt> ; Flow R 2bea ; -------------------------------------------------------------------------------------- 2bea ; 0x00f4 Load_Encached eon 2bea ; -------------------------------------------------------------------------------------- 2bea MACRO_Load_Encached_eon: 2bea 2bea dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bea fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 34 TR0b:14 typ_alu_func 15 NOT_B typ_b_adr 34 TR0b:14 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 34 VR0b:14 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2beb 2beb <halt> ; Flow R 2bec ; -------------------------------------------------------------------------------------- 2bec ; 0x00f5 Load_Encached eon 2bec ; -------------------------------------------------------------------------------------- 2bec MACRO_Load_Encached_eon: 2bec 2bec dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bec fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 35 TR0b:15 typ_alu_func 15 NOT_B typ_b_adr 35 TR0b:15 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 35 VR0b:15 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bed 2bed <halt> ; Flow R 2bee ; -------------------------------------------------------------------------------------- 2bee ; 0x00f6 Load_Encached eon 2bee ; -------------------------------------------------------------------------------------- 2bee MACRO_Load_Encached_eon: 2bee 2bee dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bee fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 36 TR0b:16 typ_alu_func 15 NOT_B typ_b_adr 36 TR0b:16 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 36 VR0b:16 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bef 2bef <halt> ; Flow R 2bf0 ; -------------------------------------------------------------------------------------- 2bf0 ; 0x00f7 Load_Encached eon 2bf0 ; -------------------------------------------------------------------------------------- 2bf0 MACRO_Load_Encached_eon: 2bf0 2bf0 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bf0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 37 TR0b:17 typ_alu_func 15 NOT_B typ_b_adr 37 TR0b:17 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 37 VR0b:17 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bf1 2bf1 <halt> ; Flow R 2bf2 ; -------------------------------------------------------------------------------------- 2bf2 ; 0x00f8 Load_Encached eon 2bf2 ; -------------------------------------------------------------------------------------- 2bf2 MACRO_Load_Encached_eon: 2bf2 2bf2 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bf2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 38 TR0b:18 typ_alu_func 15 NOT_B typ_b_adr 38 TR0b:18 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 38 VR0b:18 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bf3 2bf3 <halt> ; Flow R 2bf4 ; -------------------------------------------------------------------------------------- 2bf4 ; 0x00f9 Load_Encached eon 2bf4 ; -------------------------------------------------------------------------------------- 2bf4 MACRO_Load_Encached_eon: 2bf4 2bf4 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bf4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 39 TR0b:19 typ_alu_func 15 NOT_B typ_b_adr 39 TR0b:19 typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR0b:19 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bf5 2bf5 <halt> ; Flow R 2bf6 ; -------------------------------------------------------------------------------------- 2bf6 ; 0x00fa Load_Encached eon 2bf6 ; -------------------------------------------------------------------------------------- 2bf6 MACRO_Load_Encached_eon: 2bf6 2bf6 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bf6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3a TR0b:1a typ_alu_func 15 NOT_B typ_b_adr 3a TR0b:1a typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3a VR0b:1a val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bf7 2bf7 <halt> ; Flow R 2bf8 ; -------------------------------------------------------------------------------------- 2bf8 ; 0x00fb Load_Encached eon 2bf8 ; -------------------------------------------------------------------------------------- 2bf8 MACRO_Load_Encached_eon: 2bf8 2bf8 dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bf8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3b TR0b:1b typ_alu_func 15 NOT_B typ_b_adr 3b TR0b:1b typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3b VR0b:1b val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bf9 2bf9 <halt> ; Flow R 2bfa ; -------------------------------------------------------------------------------------- 2bfa ; 0x00fc Load_Encached eon 2bfa ; -------------------------------------------------------------------------------------- 2bfa MACRO_Load_Encached_eon: 2bfa 2bfa dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bfa fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3c TR0b:1c typ_alu_func 15 NOT_B typ_b_adr 3c TR0b:1c typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3c VR0b:1c val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bfb 2bfb <halt> ; Flow R 2bfc ; -------------------------------------------------------------------------------------- 2bfc ; 0x00fd Load_Encached eon 2bfc ; -------------------------------------------------------------------------------------- 2bfc MACRO_Load_Encached_eon: 2bfc 2bfc dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bfc fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3d TR0b:1d typ_alu_func 15 NOT_B typ_b_adr 3d TR0b:1d typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3d VR0b:1d val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bfd 2bfd <halt> ; Flow R 2bfe ; -------------------------------------------------------------------------------------- 2bfe ; 0x00fe Load_Encached eon 2bfe ; -------------------------------------------------------------------------------------- 2bfe MACRO_Load_Encached_eon: 2bfe 2bfe dispatch_brk_class 4 ; Flow R cc=True ; Flow J cc=False 0x2c01 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2bfe fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3e TR0b:1e typ_alu_func 15 NOT_B typ_b_adr 3e TR0b:1e typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3e VR0b:1e val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2bff 2bff <halt> ; Flow R 2c00 ; -------------------------------------------------------------------------------------- 2c00 ; 0x00ff Load_Encached eon 2c00 ; -------------------------------------------------------------------------------------- 2c00 MACRO_Load_Encached_eon: 2c00 2c00 dispatch_brk_class 4 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2c00 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type c Dispatch True seq_branch_adr 2c01 0x2c01 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3f TR0b:1f typ_alu_func 15 NOT_B typ_b_adr 3f TR0b:1f typ_c_adr 2e TOP + 1 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3f VR0b:1f val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame b 2c01 2c01 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de seq_en_micro 0 typ_csa_cntl 3 POP_CSA 2c02 ; -------------------------------------------------------------------------------------- 2c02 ; 0x1b00-0x1bff Execute Package,Field_Read,fieldnum 2c02 ; -------------------------------------------------------------------------------------- 2c02 MACRO_Execute_Package,Field_Read,fieldnum: 2c02 2c02 dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_mem_strt 6 CONTROL READ, AT VALUE_ITEM.NAME PLUS FIELD NUMBER dispatch_uadr 2c02 dispatch_uses_tos 1 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 22 VR06:02 val_b_adr 10 TOP val_frame 6 2c03 2c03 fiu_load_tar 1 hold_tar; Flow R cc=True fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_random 17 force type bus receivers ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 2c04 0x2c04 seq_cond_sel 79 IOC.PFR seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c04 2c04 ioc_tvbs 2 fiu+val; Flow J cc=False 0x2c0f seq_br_type 0 Branch False seq_branch_adr 2c0f 0x2c0f seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2c05 2c05 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x2baa ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2baa 0x2baa seq_cond_sel 28 TYP.OF_KIND_MATCH(0x06) Heap_Access_Ref seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_frame 6 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2c06 2c06 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2bb2 ioc_adrbs 1 val seq_br_type 0 Branch False seq_branch_adr 2bb2 0x2bb2 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_en_micro 0 typ_b_adr 11 TOP + 1 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 0 PASS_A 2c07 2c07 seq_br_type 1 Branch True; Flow J cc=True 0x2b9f seq_branch_adr 2b9f 0x2b9f seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 11 TOP + 1 typ_frame a 2c08 2c08 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 2e TOP + 1 typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 2c09 2c09 <halt> ; Flow R 2c0a ; -------------------------------------------------------------------------------------- 2c0a ; 0x0098 Execute Package,Field_Read_Dynamic 2c0a ; -------------------------------------------------------------------------------------- 2c0a MACRO_Execute_Package,Field_Read_Dynamic: 2c0a 2c0a dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2c0a fiu_len_fill_lit 58 zero-fill 0x18 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_a_adr 10 TOP val_b_adr 1f TOP - 1 2c0b 2c0b fiu_mem_start 2 start-rd; Flow C cc=True 0x32de ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3e VR05:1e val_frame 5 2c0c 2c0c ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 22 VR06:02 val_b_adr 10 TOP val_frame 6 2c0d 2c0d fiu_load_tar 1 hold_tar; Flow R cc=False fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c0e 0x2c0e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x16) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c0e 2c0e ioc_tvbs 2 fiu+val; Flow J 0x2c05 seq_br_type 3 Unconditional Branch seq_branch_adr 2c05 0x2c05 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2c0f 2c0f fiu_tivi_src 2 tar_fiu; Flow C cc=True 0x32da ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32da 0x32da seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 24 TR05:04 typ_frame 5 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR05:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2c10 2c10 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 2c11 2c11 seq_br_type 4 Call False; Flow C 0x329e seq_branch_adr 329e 0x329e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR1b:0d val_frame 1b 2c12 2c12 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2c16 seq_br_type 1 Branch True seq_branch_adr 2c16 0x2c16 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 1f TOP - 1 typ_frame 1 val_a_adr 26 VR12:06 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 12 2c13 2c13 ioc_fiubs 1 val ; Flow C cc=False 0x32da seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 1f TOP - 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 17 LOOP_COUNTER 2c14 2c14 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2c18 seq_br_type 1 Branch True seq_branch_adr 2c18 0x2c18 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 13 LOOP_REG typ_alu_func 10 NOT_A val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 10 TOP 2c15 2c15 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 2c LOOP_REG typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU 2c16 2c16 ioc_fiubs 1 val ; Flow J cc=False 0x2c14 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2c14 0x2c14 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_b_adr 1f TOP - 1 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 1b val_a_adr 17 LOOP_COUNTER 2c17 2c17 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 2c18 2c18 seq_b_timing 3 Late Condition, Hint False; Flow C 0x329e seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 39 VR02:19 val_frame 2 2c19 2c19 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 2c1a ; -------------------------------------------------------------------------------------- 2c1a ; 0x009a Action Call_Dynamic 2c1a ; -------------------------------------------------------------------------------------- 2c1a MACRO_Action_Call_Dynamic: 2c1a 2c1a dispatch_brk_class 6 ; Flow C 0x2ca0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2c1a seq_br_type 7 Unconditional Call seq_branch_adr 2ca0 0x2ca0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 2c1b 2c1b fiu_mem_start 2 start-rd; Flow J cc=True 0x2c24 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2c24 MACRO_Call_llvl,ldelta 2c1c ; -------------------------------------------------------------------------------------- 2c1c ; 0x8200-0x9fff Call llvl,ldelta 2c1c ; -------------------------------------------------------------------------------------- 2c1c MACRO_Call_llvl,ldelta: 2c1c 2c1c dispatch_brk_class 6 dispatch_csa_free 2 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 2c1c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 22 TR02:02 typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 2c1d 2c1d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2c1f fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c1f 0x2c1f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 50 Load_current_lex+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2c1e 2c1e fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2c37 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c37 0x2c37 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c1f 2c1f fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2c6a ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c6a 0x2c6a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_int_reads 5 RESOLVE RAM seq_random 6b ? typ_a_adr 22 TR10:02 typ_alu_func 10 NOT_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 04 GP04 val_alu_func 0 PASS_A 2c20 2c20 seq_br_type 2 Push (branch address); Flow J 0x2c21 seq_branch_adr 2c37 0x2c37 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 2a ? 2c21 2c21 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2c6f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2c6f 0x2c6f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2c22 2c22 fiu_len_fill_lit 4b zero-fill 0xb; Flow R cc=False ; Flow J cc=True 0x2c67 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2c67 0x2c67 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c23 2c23 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2c24 ; -------------------------------------------------------------------------------------- 2c24 ; 0x8000-0x81ff Call llvl,ldelta 2c24 ; -------------------------------------------------------------------------------------- 2c24 MACRO_Call_llvl,ldelta: 2c24 2c24 dispatch_brk_class 6 dispatch_csa_free 2 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 2c24 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 14 ZEROS typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 2c25 2c25 fiu_mem_start 6 start_rd_if_false; Flow C 0x32d7 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2c26 2c26 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 37 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 2c27 2c27 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2c67 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c67 0x2c67 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2c28 2c28 fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2c37 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c37 0x2c37 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c29 2c29 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2c23 seq_br_type 3 Unconditional Branch seq_branch_adr 2c23 0x2c23 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2c2a ; -------------------------------------------------------------------------------------- 2c2a ; 0x1800-0x18ff Execute Package,Field_Execute,fieldnum 2c2a ; -------------------------------------------------------------------------------------- 2c2a MACRO_Execute_Package,Field_Execute,fieldnum: 2c2a 2c2a dispatch_brk_class 6 ; Flow J cc=True 0x3bc8 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_mem_strt 6 CONTROL READ, AT VALUE_ITEM.NAME PLUS FIELD NUMBER dispatch_uadr 2c2a dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3bc8 0x3bc8 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 0a ? typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 18 NOT_A_AND_B val_b_adr 22 VR11:02 val_frame 11 2c2b 2c2b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2c2d fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2c2d 0x2c2d seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 4a Load_current_lex+? typ_a_adr 20 TR16:00 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 16 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2c2c 2c2c fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2c37 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c37 0x2c37 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c2d 2c2d seq_br_type 0 Branch False; Flow J cc=False 0x2c32 seq_branch_adr 2c32 0x2c32 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 10 TOP typ_c_adr 3e GP01 val_c_adr 3e GP01 2c2e 2c2e fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2c6b ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c6b 0x2c6b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_int_reads 5 RESOLVE RAM seq_random 6b ? typ_a_adr 22 TR10:02 typ_alu_func 10 NOT_A typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 0 PASS_A 2c2f 2c2f seq_br_type 2 Push (branch address); Flow J 0x2c30 seq_branch_adr 2c37 0x2c37 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 2a ? 2c30 2c30 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2c6f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2c6f 0x2c6f seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2c31 2c31 fiu_len_fill_lit 4b zero-fill 0xb; Flow R cc=False ; Flow J cc=True 0x2c67 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2c67 0x2c67 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c32 2c32 seq_br_type 1 Branch True; Flow J cc=True 0x2c6b seq_branch_adr 2c6b 0x2c6b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 01 GP01 typ_frame 10 2c33 2c33 ioc_load_wdr 0 ; Flow J 0x2c6b seq_br_type 3 Unconditional Branch seq_branch_adr 2c6b 0x2c6b typ_b_adr 29 TR05:09 typ_frame 5 val_b_adr 01 GP01 2c34 ; -------------------------------------------------------------------------------------- 2c34 ; 0x0096 Execute Package,Field_Execute_Dynamic 2c34 ; -------------------------------------------------------------------------------------- 2c34 MACRO_Execute_Package,Field_Execute_Dynamic: 2c34 2c34 dispatch_brk_class 6 ; Flow C cc=False 0x32de dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2c34 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32de 0x32de seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3e VR05:1e val_frame 5 2c35 2c35 fiu_mem_start 2 start-rd; Flow C 0x32d7 ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var seq_random 02 ? typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 1d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2c36 2c36 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2c2b fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c2b 0x2c2b seq_int_reads 5 RESOLVE RAM seq_random 0a ? 2c37 2c37 ioc_fiubs 0 fiu ; Flow J cc=False 0x2c39 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2c39 0x2c39 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 2d Load_ibuff+? typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c38 2c38 fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=False ; Flow J cc=True 0x2c23 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c23 0x2c23 seq_cond_sel 4f SEQ.uE_field_number_error seq_random 54 Load_save_offset+Load_control_pred+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c39 2c39 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2c59 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2c59 0x2c59 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 41 Load_control_pred+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c3a ; -------------------------------------------------------------------------------------- 2c3a ; 0x1c00-0x1cff Execute_Immediate Run_Utility,uimmediate 2c3a ; -------------------------------------------------------------------------------------- 2c3a MACRO_Execute_Immediate_Run_Utility,uimmediate: 2c3a 2c3a dispatch_brk_class 6 ; Flow C 0x32d7 dispatch_csa_free 3 dispatch_csa_valid 1 dispatch_uadr 2c3a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 36 VR05:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 2c3b 2c3b fiu_tivi_src 4 fiu_var; Flow C 0x32d7 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 0 Branch False seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c3c 2c3c fiu_load_tar 1 hold_tar; Flow J cc=True 0x2c55 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2c55 0x2c55 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated seq_int_reads 5 RESOLVE RAM seq_random 14 Load_save_offset+? typ_a_adr 2d TR1b:0d typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_frame 1b typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3f GP00 2c3d 2c3d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 59 fiu_rdata_src 0 rotator ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4c Load_current_lex+? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3e GP01 2c3e 2c3e fiu_load_tar 1 hold_tar; Flow J cc=False 0x2c4d fiu_mem_start 5 start_rd_if_true fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2c4d 0x2c4d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 2c3f 2c3f fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR00:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c40 2c40 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2c4a fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2c4a 0x2c4a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 1b A_OR_B typ_b_adr 23 TR01:03 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2c41 2c41 ioc_fiubs 0 fiu seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 4 SAVE OFFSET seq_latch 1 seq_lex_adr 1 seq_random 5a Load_control_pred+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c42 2c42 fiu_load_var 1 hold_var; Flow R cc=False fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2c43 0x2c43 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c43 2c43 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2c44 2c44 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_b_adr 16 CSA/VAL_BUS 2c45 2c45 fiu_len_fill_lit 4c zero-fill 0xc; Flow R cc=False ; Flow J cc=True 0x332e fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 332e 0x332e seq_random 04 Load_save_offset+? typ_b_adr 01 GP01 typ_c_lit 0 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_c_adr 21 TOP - 0x2 val_c_source 0 FIU_BUS 2c46 ; -------------------------------------------------------------------------------------- 2c46 ; 0x0127 Execute Any,Run_Initialization_Utility 2c46 ; -------------------------------------------------------------------------------------- 2c46 MACRO_Execute_Any,Run_Initialization_Utility: 2c46 2c46 dispatch_brk_class 6 ; Flow C 0x32d7 dispatch_csa_free 3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2c46 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 10 TOP typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2c47 2c47 seq_br_type 0 Branch False; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x08) Subvector_Var Subarray_Var typ_b_adr 10 TOP typ_frame 8 2c48 2c48 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 2c49 0x2c49 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 21 TR05:01 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 2c49 2c49 fiu_mem_start 2 start-rd; Flow J 0x2c3b ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2c3b 0x2c3b typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 11 TOP + 1 typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 2c4a 2c4a ioc_fiubs 0 fiu seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 4 SAVE OFFSET seq_latch 1 seq_lex_adr 1 seq_random 5a Load_control_pred+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c4b 2c4b fiu_load_var 1 hold_var; Flow C cc=True 0x2c43 fiu_tivi_src 1 tar_val seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2c43 0x2c43 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c4c 2c4c fiu_mem_start 2 start-rd; Flow J 0x2c59 ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c59 0x2c59 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2c4d 2c4d fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR00:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c4e 2c4e ioc_fiubs 0 fiu typ_alu_func 1b A_OR_B typ_b_adr 23 TR01:03 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2c4f 2c4f seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 4 SAVE OFFSET seq_latch 1 seq_lex_adr 1 seq_random 5a Load_control_pred+? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 2c50 2c50 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 10 TOP typ_c_adr 3d GP02 val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c51 2c51 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 1d TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2c52 2c52 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 16 CSA/VAL_BUS 2c53 2c53 ioc_tvbs 2 fiu+val; Flow C cc=True 0x2c43 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 2c43 0x2c43 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2c54 2c54 fiu_mem_start 2 start-rd; Flow J 0x2c59 ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 2c59 0x2c59 seq_random 15 ? typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE 2c55 2c55 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type c Dispatch True seq_branch_adr 2c56 0x2c56 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 16 typ_mar_cntl e LOAD_MAR_CONTROL 2c56 2c56 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 2c57 2c57 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 2c58 2c58 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2c59 2c59 seq_br_type 3 Unconditional Branch; Flow J 0x2c29 seq_branch_adr 2c29 0x2c29 2c5a ; -------------------------------------------------------------------------------------- 2c5a ; 0x00c5 Action Set_Block_Start 2c5a ; -------------------------------------------------------------------------------------- 2c5a MACRO_Action_Set_Block_Start: 2c5a 2c5a dispatch_brk_class 8 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2c5a ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2c5b 2c5b fiu_len_fill_lit 4e zero-fill 0xe fiu_load_mdr 1 hold_mdr fiu_offs_lit 54 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val 2c5c 2c5c fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x2c5d fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2c29 0x2c29 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 22 VR02:02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2c5d 2c5d fiu_mem_start 3 start-wr; Flow C 0x332e ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_random 16 ? typ_alu_func 7 INC_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_c_adr 1d VR02:02 val_c_source 0 FIU_BUS val_frame 2 2c5e 2c5e fiu_mem_start 2 start-rd; Flow J 0x332e ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 332e 0x332e seq_random 02 ? typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1 A_PLUS_B val_b_adr 3d VR02:1d val_frame 2 2c5f ; -------------------------------------------------------------------------------------- 2c5f ; Comes from: 2c5f ; 2c67 C from color 0x0000 2c5f ; 2c6b C from color 0x0000 2c5f ; 2c70 C from color 0x2c6d 2c5f ; -------------------------------------------------------------------------------------- 2c5f 2c5f fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 2c60 2c60 ioc_fiubs 1 val seq_random 41 Load_control_pred+? val_a_adr 3e VR02:1e val_frame 2 2c61 2c61 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_int_reads 0 TYP VAL BUS seq_random 12 Load_current_lex+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_b_adr 31 VR02:11 val_frame 2 2c62 2c62 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 3e ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2c63 2c63 ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_random 6c Load_control_pred+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2c64 2c64 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 48 Load_current_lex+? typ_b_adr 02 GP02 typ_csa_cntl 3 POP_CSA val_b_adr 02 GP02 2c65 2c65 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 03 GP03 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2c66 2c66 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? 2c67 2c67 fiu_load_var 1 hold_var; Flow C 0x2c5f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2c5f 0x2c5f seq_en_micro 0 seq_random 0a ? typ_c_adr 3f GP00 val_a_adr 3e VR02:1e val_c_adr 3f GP00 val_frame 2 2c68 2c68 seq_b_timing 3 Late Condition, Hint False; Flow C 0x32d7 seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_frame 1b 2c69 2c69 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 2c6a 2c6a seq_br_type 3 Unconditional Branch; Flow J 0x2c67 seq_branch_adr 2c67 0x2c67 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c6b 2c6b fiu_load_var 1 hold_var; Flow C 0x2c5f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2c5f 0x2c5f seq_en_micro 0 seq_random 0a ? typ_c_adr 3f GP00 val_a_adr 3e VR02:1e val_c_adr 3f GP00 val_frame 2 2c6c 2c6c seq_b_timing 3 Late Condition, Hint False; Flow C 0x32d7 seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_frame 1b 2c6d 2c6d seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a9 seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated typ_frame 2 2c6e 2c6e seq_br_type 7 Unconditional Call; Flow C 0x32da seq_branch_adr 32da 0x32da 2c6f ; -------------------------------------------------------------------------------------- 2c6f ; Comes from: 2c6f ; 2c21 C False from color 0x0000 2c6f ; 2c30 C False from color 0x0000 2c6f ; -------------------------------------------------------------------------------------- 2c6f 2c6f ioc_fiubs 0 fiu seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 6b ? val_c_adr 3a GP05 val_c_source 0 FIU_BUS 2c70 2c70 fiu_load_var 1 hold_var; Flow C 0x2c5f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2c5f 0x2c5f seq_en_micro 0 seq_random 0a ? val_a_adr 3e VR02:1e val_frame 2 2c71 2c71 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A 2c72 2c72 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_b_adr 16 CSA/VAL_BUS 2c73 2c73 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 2a ? val_a_adr 05 GP05 2c74 2c74 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2c75 2c75 <halt> ; Flow R 2c76 ; -------------------------------------------------------------------------------------- 2c76 ; 0x1d00-0x1dff Execute_Immediate Reference_Lex_1,uimmediate 2c76 ; -------------------------------------------------------------------------------------- 2c76 MACRO_Execute_Immediate_Reference_Lex_1,uimmediate: 2c76 2c76 dispatch_brk_class 4 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_uadr 2c76 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_alu_func 1a PASS_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME 2c77 2c77 fiu_mem_start 2 start-rd; Flow J 0x2c7a ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2c7a 0x2c7a typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 2c78 ; -------------------------------------------------------------------------------------- 2c78 ; 0x0099 Action Reference_Dynamic 2c78 ; -------------------------------------------------------------------------------------- 2c78 MACRO_Action_Reference_Dynamic: 2c78 2c78 dispatch_brk_class 4 ; Flow C 0x2ca0 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2c78 seq_br_type 7 Unconditional Call seq_branch_adr 2ca0 0x2ca0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 2c79 2c79 fiu_mem_start 2 start-rd; Flow J cc=True 0x2c88 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2c88 MACRO_Reference_zdelta 2c7a 2c7a fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_lex_adr 3 typ_a_adr 32 TR05:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2c7b 2c7b fiu_load_tar 1 hold_tar; Flow R cc=False fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c7c 0x2c7c seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_random 1c ? typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2c7c 2c7c fiu_len_fill_lit 42 zero-fill 0x2; Flow R cc=False fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c7d 0x2c7d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x65) Entry_Var Family_Var seq_random 04 Load_save_offset+? typ_a_adr 24 TR05:04 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2c7d 2c7d seq_b_timing 3 Late Condition, Hint False; Flow C cc=#0x0 0x2c7f seq_br_type f Unconditional Case Call seq_branch_adr 2c7f 0x2c7f seq_en_micro 0 2c7e 2c7e seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 2c7f ; -------------------------------------------------------------------------------------- 2c7f ; Comes from: 2c7f ; 2c7d C #0x0 from color MACRO_Execute_Immediate_Reference_Lex_1,uimmediate 2c7f ; -------------------------------------------------------------------------------------- 2c7f 2c7f seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2c80 2c80 seq_br_type a Unconditional Return; Flow R 2c81 2c81 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c82 2c82 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2c83 2c83 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c84 2c84 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2c7e ioc_adrbs 3 seq ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c7e 0x2c7e seq_cond_sel 28 TYP.OF_KIND_MATCH(0x15) Interface_Key seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_frame 15 typ_mar_cntl e LOAD_MAR_CONTROL 2c85 2c85 seq_br_type a Unconditional Return; Flow R 2c86 2c86 seq_br_type a Unconditional Return; Flow R 2c87 2c87 <halt> ; Flow R 2c88 ; -------------------------------------------------------------------------------------- 2c88 ; 0xa000-0xa1ff Reference zdelta 2c88 ; -------------------------------------------------------------------------------------- 2c88 MACRO_Reference_zdelta: 2c88 2c88 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_mem_strt 1 CONTROL READ, AT LEX LEVEL DELTA dispatch_uadr 2c88 2c89 2c89 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2c8a 0x2c8a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x64) Subprogram_Ref_For_Call Variable_Ref Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_random 1c ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2c8a 2c8a seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram typ_b_adr 10 TOP typ_frame 11 2c8b 2c8b seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 2c8c ; -------------------------------------------------------------------------------------- 2c8c ; 0x1900-0x19ff Execute Package,Field_Reference,fieldnum 2c8c ; -------------------------------------------------------------------------------------- 2c8c MACRO_Execute_Package,Field_Reference,fieldnum: 2c8c 2c8c dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_mem_strt 6 CONTROL READ, AT VALUE_ITEM.NAME PLUS FIELD NUMBER dispatch_uadr 2c8c dispatch_uses_tos 1 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 18 typ_rand a PASS_B_HIGH val_b_adr 10 TOP val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2c8d 2c8d fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_tar 1 hold_tar fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2c8e 2c8e fiu_len_fill_lit 01 sign-fill 0x1; Flow J cc=True 0x2c8f ; Flow J cc=#0x0 0x2c90 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 2c90 0x2c90 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x00) Discrete_Var Subprogram_Ref_For_Call Discrete_Ref Subprogram_For_Call Float_Var Variable_Ref Float_Ref Entry_Var Access_Var Subprogram_Ref_For_Call_Elaborated Access_Ref Subprogram_For_Call_Elaborated Task_Var Task_Ref Select_Var Subprogram_Ref_For_Call_Visible Subvector_Var Subprogram_For_Call_Visible Subarray_Var Family_Var Subprogram_Ref_For_Call_Visible_Elaborated Subprogram_For_Call_Visible_Elaborated Heap_Access_Var Heap_Access_Ref Default_Var Accept_Subprogram_Ref Record_Var Accept_Subprogram Variant_Record_Var Delay_Alternative Interface_Subprogram_Ref Interface_Subprogram Package_Var Utility_Subprogram Vector_Var Familiy_Alternative Matrix_Var Null_Subprogram Array_Var Exception_Var seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c8f 2c8f seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 2c90 2c90 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c98 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c98 0x2c98 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 24 TR05:04 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c91 2c91 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c98 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c98 0x2c98 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c92 2c92 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c98 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c98 0x2c98 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c93 2c93 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c98 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 2c98 0x2c98 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 32 TR05:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 2c94 2c94 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c98 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c98 0x2c98 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 24 TR05:04 typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c95 2c95 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c98 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c98 0x2c98 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c96 2c96 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2c98 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2c98 0x2c98 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2c97 2c97 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 2c98 2c98 fiu_len_fill_lit 45 zero-fill 0x5 fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2c99 2c99 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 0 Early Condition seq_br_type c Dispatch True seq_branch_adr 2c9a 0x2c9a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2c9a 2c9a seq_br_type 7 Unconditional Call; Flow C 0x32da seq_branch_adr 32da 0x32da seq_en_micro 0 typ_c_adr 2f TOP val_c_adr 2f TOP 2c9b 2c9b <halt> ; Flow R 2c9c ; -------------------------------------------------------------------------------------- 2c9c ; 0x0095 Execute Package,Field_Reference_Dynamic 2c9c ; -------------------------------------------------------------------------------------- 2c9c MACRO_Execute_Package,Field_Reference_Dynamic: 2c9c 2c9c dispatch_brk_class 8 ; Flow C 0x32d7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2c9c fiu_len_fill_lit 58 zero-fill 0x18 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1d) Task_Var Package_Var typ_b_adr 10 TOP typ_frame 1d val_a_adr 10 TOP val_b_adr 1f TOP - 1 2c9d 2c9d fiu_mem_start 2 start-rd; Flow C cc=True 0x32de ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 3e VR05:1e val_frame 5 2c9e 2c9e fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 1f TOP - 1 val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2c9f 2c9f fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x2c8e fiu_load_tar 1 hold_tar fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2c8e 0x2c8e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2ca0 ; -------------------------------------------------------------------------------------- 2ca0 ; Comes from: 2ca0 ; 1cca C from color 0x1cc9 2ca0 ; 2b9a C from color MACRO_Action_Load_Dynamic 2ca0 ; 2c1a C from color 0x0000 2ca0 ; 2c78 C from color MACRO_Execute_Immediate_Reference_Lex_1,uimmediate 2ca0 ; -------------------------------------------------------------------------------------- 2ca0 2ca0 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x2ca6 fiu_mem_start 2 start-rd fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2ca6 0x2ca6 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_lex_adr 3 typ_a_adr 38 TR05:18 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2ca1 2ca1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32de fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32de 0x32de seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 14 ZEROS val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2ca2 2ca2 fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=True 0x2ca5 fiu_load_tar 1 hold_tar fiu_mem_start 6 start_rd_if_false fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2ca5 0x2ca5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 5 RESOLVE RAM seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 2ca3 2ca3 val_rand 2 DEC_LOOP_COUNTER 2ca4 2ca4 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x2ca3 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2ca3 0x2ca3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2ca5 2ca5 ioc_adrbs 2 typ ; Flow R ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2ca6 2ca6 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x32de fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 1b A_OR_B val_b_adr 1f TOP - 1 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2ca7 2ca7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2ca5 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2ca5 0x2ca5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ca8 2ca8 ioc_adrbs 1 val ; Flow R seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_csa_cntl 3 POP_CSA typ_mar_cntl a LOAD_MAR_IMPORT val_alu_func 0 PASS_A 2ca9 2ca9 <halt> ; Flow R 2caa ; -------------------------------------------------------------------------------------- 2caa ; 0x1100-0x11ff Execute Select,Member_Write,fieldnum 2caa ; -------------------------------------------------------------------------------------- 2caa MACRO_Execute_Select,Member_Write,fieldnum: 2caa 2caa dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_uadr 2caa fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A 2cab 2cab fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x2cbe fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2cbe 0x2cbe seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 2cac 2cac fiu_mem_start 2 start-rd; Flow C cc=False 0x32de ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32de 0x32de seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2cad 2cad seq_br_type 4 Call False; Flow C cc=False 0x32a6 seq_branch_adr 32a6 0x32a6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR06:16 val_frame 6 2cae 2cae fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=False 0x2cb6 fiu_load_tar 1 hold_tar fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2cb6 0x2cb6 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame e typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2caf 2caf fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 2cb0 2cb0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a6 fiu_offs_lit 07 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a6 0x32a6 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2cb1 2cb1 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame e typ_mar_cntl b LOAD_MAR_DATA val_b_adr 16 CSA/VAL_BUS 2cb2 2cb2 typ_a_adr 05 GP05 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2cb3 2cb3 fiu_mem_start 3 start-wr; Flow C cc=False 0x32a6 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32a6 0x32a6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2cb4 2cb4 ioc_load_wdr 0 seq_random 02 ? typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 2cb5 2cb5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2cb6 ; -------------------------------------------------------------------------------------- 2cb6 ; Comes from: 2cb6 ; 2cae C False from color MACRO_Execute_Select,Member_Write,fieldnum 2cb6 ; -------------------------------------------------------------------------------------- 2cb6 2cb6 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL 2cb7 2cb7 typ_a_adr 2d TR05:0d typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 2cb8 2cb8 fiu_len_fill_lit 1f sign-fill 0x1f; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame e val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2cb9 2cb9 fiu_len_fill_lit 58 zero-fill 0x18; Flow C cc=True 0x32a6 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a6 0x32a6 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR06:02 val_alu_func 1e A_AND_B val_b_adr 04 GP04 val_c_adr 3a GP05 val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2cba 2cba fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 19 fiu_rdata_src 0 rotator ioc_tvbs 3 fiu+fiu typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2cbb 2cbb fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_random 02 ? typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 2cbc 2cbc fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 2cbd 0x2cbd seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 2cbd 2cbd seq_br_type 7 Unconditional Call; Flow C 0x32a6 seq_branch_adr 32a6 0x32a6 2cbe 2cbe fiu_mem_start 2 start-rd; Flow C cc=False 0x32de ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32de 0x32de seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2cbf 2cbf seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2cae seq_br_type 0 Branch False seq_branch_adr 2cae 0x2cae seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR06:17 val_frame 6 2cc0 2cc0 seq_br_type 7 Unconditional Call; Flow C 0x32a6 seq_branch_adr 32a6 0x32a6 2cc1 2cc1 <halt> ; Flow R 2cc2 ; -------------------------------------------------------------------------------------- 2cc2 ; 0x1000-0x10ff Execute Select,Guard_Write,fieldnum 2cc2 ; -------------------------------------------------------------------------------------- 2cc2 MACRO_Execute_Select,Guard_Write,fieldnum: 2cc2 2cc2 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_uadr 2cc2 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 2cc3 2cc3 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 2cc4 2cc4 fiu_mem_start 2 start-rd; Flow C cc=False 0x32de ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32de 0x32de seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2cc5 2cc5 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2cc9 seq_br_type 1 Branch True seq_branch_adr 2cc9 0x2cc9 typ_a_adr 10 TOP typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL 2cc6 2cc6 fiu_mem_start 7 start_wr_if_true ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 3a TR06:1a typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2cc7 2cc7 ioc_load_wdr 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 2cc8 2cc8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2cc9 2cc9 fiu_mem_start 3 start-wr; Flow J 0x2cc7 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2cc7 0x2cc7 typ_a_adr 3a TR06:1a typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2cca ; -------------------------------------------------------------------------------------- 2cca ; 0x013d Execute Select,Timed_Duration_Write 2cca ; -------------------------------------------------------------------------------------- 2cca MACRO_Execute_Select,Timed_Duration_Write: 2cca 2cca dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2cca fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 2ccb 2ccb ioc_fiubs 2 typ ; Flow C cc=False 0x32e2 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32e2 0x32e2 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 10 TOP typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ccc 2ccc fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_random 02 ? typ_b_adr 3a TR07:1a typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B 2ccd 2ccd ioc_load_wdr 0 ; Flow J cc=True 0x2ccf ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ccf 0x2ccf seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_a_adr 3b TR07:1b typ_alu_func 18 NOT_A_AND_B typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA typ_frame 7 val_a_adr 25 VR07:05 val_alu_func 18 NOT_A_AND_B val_b_adr 10 TOP val_frame 7 2cce 2cce fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2ccf 2ccf seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32de seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3b TR07:1b typ_alu_func 18 NOT_A_AND_B typ_b_adr 01 GP01 typ_csa_cntl 2 PUSH_CSA typ_frame 7 2cd0 2cd0 seq_b_timing 3 Late Condition, Hint False; Flow C 0x329e seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_alu_func 1a PASS_B val_b_adr 10 TOP 2cd1 2cd1 fiu_mem_start 3 start-wr; Flow J 0x2ccd ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2ccd 0x2ccd typ_a_adr 14 ZEROS typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS 2cd2 ; -------------------------------------------------------------------------------------- 2cd2 ; 0x013e Execute Select,Timed_Guard_Write 2cd2 ; -------------------------------------------------------------------------------------- 2cd2 MACRO_Execute_Select,Timed_Guard_Write: 2cd2 2cd2 dispatch_brk_class 8 ; Flow C cc=False 0x32e2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2cd2 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 21 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32e2 0x32e2 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2cd3 2cd3 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2cd4 2cd4 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL 2cd5 2cd5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2cd6 ; -------------------------------------------------------------------------------------- 2cd6 ; 0x013c Execute Select,Terminate_Guard_Write 2cd6 ; -------------------------------------------------------------------------------------- 2cd6 MACRO_Execute_Select,Terminate_Guard_Write: 2cd6 2cd6 dispatch_brk_class 8 ; Flow C cc=False 0x32e2 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2cd6 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_br_type 4 Call False seq_branch_adr 32e2 0x32e2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 02 ? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2cd7 2cd7 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2cd8 2cd8 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL 2cd9 2cd9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2cda ; -------------------------------------------------------------------------------------- 2cda ; 0x029f Declare_Subprogram For_Call,subp 2cda ; -------------------------------------------------------------------------------------- 2cda MACRO_Declare_Subprogram_For_Call,subp: 2cda 2cda dispatch_brk_class 4 ; Flow J 0x2cdb dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cda fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 7c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2ce6 0x2ce6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2cdb 2cdb fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2ce9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2ce9 0x2ce9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_alu_func 1b A_OR_B typ_b_adr 29 TR05:09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cdc ; -------------------------------------------------------------------------------------- 2cdc ; 0x029e Declare_Subprogram For_Call,Unelaborated,subp 2cdc ; -------------------------------------------------------------------------------------- 2cdc MACRO_Declare_Subprogram_For_Call,Unelaborated,subp: 2cdc 2cdc dispatch_brk_class 4 ; Flow J 0x2cdd dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cdc fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 7c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2ce6 0x2ce6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2cdd 2cdd fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2ce9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2ce9 0x2ce9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_alu_func 1b A_OR_B typ_b_adr 23 TR05:03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cde ; -------------------------------------------------------------------------------------- 2cde ; 0x029d Declare_Subprogram For_Outer_Call,subp 2cde ; -------------------------------------------------------------------------------------- 2cde MACRO_Declare_Subprogram_For_Outer_Call,subp: 2cde 2cde dispatch_brk_class 4 ; Flow J 0x2cdf dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2cde fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2ce6 0x2ce6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2cdf 2cdf fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2ce9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2ce9 0x2ce9 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 30 VR07:10 val_frame 7 2ce0 ; -------------------------------------------------------------------------------------- 2ce0 ; 0x029c Declare_Subprogram For_Outer_Call,Visible,subp 2ce0 ; -------------------------------------------------------------------------------------- 2ce0 MACRO_Declare_Subprogram_For_Outer_Call,Visible,subp: 2ce0 2ce0 dispatch_brk_class 4 ; Flow J 0x2ce1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ce0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2ce6 0x2ce6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2ce1 2ce1 fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2ce9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2ce9 0x2ce9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2b VR07:0b val_frame 7 2ce2 ; -------------------------------------------------------------------------------------- 2ce2 ; 0x029b Declare_Subprogram For_Outer_Call,Unelaborated,subp 2ce2 ; -------------------------------------------------------------------------------------- 2ce2 MACRO_Declare_Subprogram_For_Outer_Call,Unelaborated,subp: 2ce2 2ce2 dispatch_brk_class 4 ; Flow J 0x2ce3 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ce2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2ce6 0x2ce6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2ce3 2ce3 fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2ce9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2ce9 0x2ce9 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 23 VR05:03 val_frame 5 2ce4 ; -------------------------------------------------------------------------------------- 2ce4 ; 0x029a Declare_Subprogram For_Outer_Call,Visible,Unelaborated,subp 2ce4 ; -------------------------------------------------------------------------------------- 2ce4 MACRO_Declare_Subprogram_For_Outer_Call,Visible,Unelaborated,subp: 2ce4 2ce4 dispatch_brk_class 4 ; Flow J 0x2ce5 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2ce4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2ce6 0x2ce6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 15 ? typ_a_adr 20 TR05:00 typ_frame 5 val_a_adr 26 VR09:06 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 2ce5 2ce5 fiu_len_fill_lit 4e zero-fill 0xe; Flow R cc=False ; Flow J cc=True 0x2ce9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2ce9 0x2ce9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_latch 1 seq_random 16 ? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2a VR07:0a val_frame 7 2ce6 2ce6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2ce7 0x2ce7 seq_en_micro 0 seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ce7 2ce7 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32dc seq_br_type 5 Call True seq_branch_adr 32dc 0x32dc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2ce8 2ce8 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 2ce9 2ce9 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 seq_random 1d ? typ_mar_cntl 9 LOAD_MAR_CODE 2cea 2cea ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2ceb 2ceb <halt> ; Flow R 2cec ; -------------------------------------------------------------------------------------- 2cec ; 0x0299 Declare_Subprogram For_Accept,subp 2cec ; -------------------------------------------------------------------------------------- 2cec MACRO_Declare_Subprogram_For_Accept,subp: 2cec 2cec dispatch_brk_class 4 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cec fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 7c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 1d ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3d VR02:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 2ced 2ced fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=True 0x32dc fiu_offs_lit 6d fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dc 0x32dc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 16 ? typ_alu_func 1b A_OR_B typ_b_adr 2e TR05:0e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 6 2cee 2cee fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 2cef 2cef fiu_len_fill_lit 57 zero-fill 0x17; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 2 INC_A_PLUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2cf0 ; -------------------------------------------------------------------------------------- 2cf0 ; 0x02ab Declare_Subprogram For_Call,With_Address 2cf0 ; -------------------------------------------------------------------------------------- 2cf0 MACRO_Declare_Subprogram_For_Call,With_Address: 2cf0 2cf0 dispatch_brk_class 4 ; Flow J cc=True 0x32dc dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cf0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2cf1 2cf1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2cfd fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2cfd 0x2cfd seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 29 TR05:09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cf2 ; -------------------------------------------------------------------------------------- 2cf2 ; 0x02aa Declare_Subprogram For_Call,Visible,With_Address 2cf2 ; -------------------------------------------------------------------------------------- 2cf2 MACRO_Declare_Subprogram_For_Call,Visible,With_Address: 2cf2 2cf2 dispatch_brk_class 4 ; Flow J cc=True 0x32dc dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cf2 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2cf3 2cf3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2cfc fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2cfc 0x2cfc seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 2b TR05:0b typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cf4 ; -------------------------------------------------------------------------------------- 2cf4 ; 0x02a9 Declare_Subprogram For_Call,Unelaborated,With_Address 2cf4 ; -------------------------------------------------------------------------------------- 2cf4 MACRO_Declare_Subprogram_For_Call,Unelaborated,With_Address: 2cf4 2cf4 dispatch_brk_class 4 ; Flow J cc=True 0x32dc dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cf4 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2cf5 2cf5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2cfd fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2cfd 0x2cfd seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 23 TR05:03 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cf6 ; -------------------------------------------------------------------------------------- 2cf6 ; 0x02a8 Declare_Subprogram For_Call,Visible,Unelaborated,With_Address 2cf6 ; -------------------------------------------------------------------------------------- 2cf6 MACRO_Declare_Subprogram_For_Call,Visible,Unelaborated,With_Address: 2cf6 2cf6 dispatch_brk_class 4 ; Flow J cc=True 0x32dc dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cf6 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2cf7 2cf7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2cfc fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2cfc 0x2cfc seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 2a TR05:0a typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2cf8 ; -------------------------------------------------------------------------------------- 2cf8 ; 0x02a5 Declare_Subprogram For_Outer_Call,With_Address 2cf8 ; -------------------------------------------------------------------------------------- 2cf8 MACRO_Declare_Subprogram_For_Outer_Call,With_Address: 2cf8 2cf8 dispatch_brk_class 4 ; Flow J cc=True 0x32dc dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cf8 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_frame 11 2cf9 2cf9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2cfd fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2cfd 0x2cfd seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 29 TR05:09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2cfa ; -------------------------------------------------------------------------------------- 2cfa ; 0x02a4 Declare_Subprogram For_Outer_Call,Visible,With_Address 2cfa ; -------------------------------------------------------------------------------------- 2cfa MACRO_Declare_Subprogram_For_Outer_Call,Visible,With_Address: 2cfa 2cfa dispatch_brk_class 4 ; Flow J cc=True 0x32dc dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2cfa fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_frame 11 2cfb 2cfb fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2cfc fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 2cfc 0x2cfc seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_alu_func 1b A_OR_B typ_b_adr 2b TR05:0b typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2cfc 2cfc seq_br_type 4 Call False; Flow C cc=False 0x32da seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2cfd 2cfd fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2cfe 0x2cfe seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 01 GP01 val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2cfe 2cfe seq_br_type 3 Unconditional Branch; Flow J 0x32dc seq_branch_adr 32dc 0x32dc typ_csa_cntl 3 POP_CSA 2cff 2cff <halt> ; Flow R 2d00 ; -------------------------------------------------------------------------------------- 2d00 ; 0x02a2 Declare_Subprogram For_Accept,With_Address 2d00 ; -------------------------------------------------------------------------------------- 2d00 MACRO_Declare_Subprogram_For_Accept,With_Address: 2d00 2d00 dispatch_brk_class 4 ; Flow J cc=True 0x32dc dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2d00 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7c fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32dc 0x32dc seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 5 RESOLVE RAM typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 23 VR11:03 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 11 2d01 2d01 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32dc fiu_load_mdr 1 hold_mdr fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dc 0x32dc seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1b A_OR_B typ_b_adr 2e TR05:0e typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 21 VR06:01 val_frame 6 2d02 2d02 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 38 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d03 2d03 fiu_len_fill_lit 57 zero-fill 0x17; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 2 INC_A_PLUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2d04 ; -------------------------------------------------------------------------------------- 2d04 ; 0x02a0 Declare_Subprogram Null_Subprogram 2d04 ; -------------------------------------------------------------------------------------- 2d04 MACRO_Declare_Subprogram_Null_Subprogram: 2d04 2d04 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2d04 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 38 TR06:18 typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2d05 2d05 <halt> ; Flow R 2d06 ; -------------------------------------------------------------------------------------- 2d06 ; 0x00c7 Action Elaborate_Subprogram 2d06 ; -------------------------------------------------------------------------------------- 2d06 MACRO_Action_Elaborate_Subprogram: 2d06 2d06 dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2d06 fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3d VR02:1d val_alu_func 1a PASS_B val_b_adr 10 TOP val_frame 2 2d07 2d07 fiu_mem_start 8 start_wr_if_false; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d08 2d08 ioc_load_wdr 0 seq_random 02 ? 2d09 2d09 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2d0a ; -------------------------------------------------------------------------------------- 2d0a ; 0x00c6 Action Check_Subprogram_Elaborated 2d0a ; -------------------------------------------------------------------------------------- 2d0a MACRO_Action_Check_Subprogram_Elaborated: 2d0a 2d0a dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2d0a fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 10 TOP typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A 2d0b 2d0b seq_br_type 2 Push (branch address); Flow J 0x2d0c seq_branch_adr 32a9 0x32a9 2d0c 2d0c fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2d0d 0x2d0d seq_cond_sel 28 TYP.OF_KIND_MATCH(0x02) Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible_Elaborated seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS 2d0d 2d0d seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 9 Return False seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1b) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated typ_frame 1b 2d0e 2d0e fiu_mem_start 2 start-rd; Flow C 0x2d24 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 5 val_rand a PASS_B_HIGH 2d0f 2d0f fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d10 2d10 ioc_load_wdr 0 ; Flow J 0x2d48 seq_br_type 3 Unconditional Branch seq_branch_adr 2d48 0x2d48 typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 2d11 ; -------------------------------------------------------------------------------------- 2d11 ; Comes from: 2d11 ; 2d27 C from color 0x2d26 2d11 ; -------------------------------------------------------------------------------------- 2d11 2d11 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f val_c_source 0 FIU_BUS 2d12 2d12 ioc_tvbs 5 seq+seq; Flow J cc=False 0x2d24 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2d24 0x2d24 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_b_adr 16 CSA/VAL_BUS 2d13 2d13 fiu_mem_start 2 start-rd; Flow C 0x2d24 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 0f GP0f val_frame 4 val_rand a PASS_B_HIGH 2d14 2d14 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2d17 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d17 0x2d17 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f 2d15 2d15 fiu_mem_start 2 start-rd; Flow C 0x2d1f ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d1f 0x2d1f seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A 2d16 2d16 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 2d17 2d17 fiu_mem_start 2 start-rd; Flow C 0x2d16 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d16 0x2d16 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 0f GP0f val_frame 4 val_rand a PASS_B_HIGH 2d18 2d18 fiu_tivi_src c mar_0xc; Flow C 0x2ab4 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 38 VR02:18 val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 2d19 2d19 fiu_mem_start 2 start-rd; Flow C 0x2d1f ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d1f 0x2d1f seq_en_micro 0 typ_a_adr 25 TR12:05 typ_alu_func 0 PASS_A typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f 2d1a 2d1a fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x2d15 fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d15 0x2d15 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 2d1b 2d1b seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 2d1c 2d1c seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2d15 seq_br_type 0 Branch False seq_branch_adr 2d15 0x2d15 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 0c GP0c typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU 2d1d 2d1d ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 2 INC_A_PLUS_B typ_b_adr 34 TR12:14 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 12 typ_rand c WRITE_OUTER_FRAME val_a_adr 0f GP0f 2d1e 2d1e fiu_mem_start 2 start-rd; Flow J 0x2d16 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 2d16 0x2d16 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 2d1f 2d1f seq_en_micro 0 2d20 2d20 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2d21 0x2d21 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 2d21 2d21 seq_en_micro 0 seq_random 06 Pop_stack+? 2d22 2d22 seq_br_type 7 Unconditional Call; Flow C 0x2d24 seq_branch_adr 2d24 0x2d24 seq_en_micro 0 2d23 2d23 seq_br_type 3 Unconditional Branch; Flow J 0x2d13 seq_branch_adr 2d13 0x2d13 val_c_adr 30 GP0f 2d24 ; -------------------------------------------------------------------------------------- 2d24 ; Comes from: 2d24 ; 2d0e C from color ML_break_class 2d24 ; 2d2b C from color 0x2d2b 2d24 ; 2d2d C from color 0x2d2d 2d24 ; 2d30 C from color 0x2d30 2d24 ; 2d31 C from color 0x2d30 2d24 ; 2d33 C from color 0x2d26 2d24 ; 2d40 C from color ML_break_class 2d24 ; 2d44 C from color 0x2d44 2d24 ; 2d6f C from color ML_break_class 2d24 ; 2d73 C from color ML_break_class 2d24 ; 2d76 C from color 0x2d75 2d24 ; -------------------------------------------------------------------------------------- 2d24 2d24 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 2d25 0x2d25 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_frame 2 2d25 ; -------------------------------------------------------------------------------------- 2d25 ; Comes from: 2d25 ; 2d36 C True from color ML_break_class 2d25 ; 2d39 C True from color ML_break_class 2d25 ; -------------------------------------------------------------------------------------- 2d25 2d25 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32e5 seq_branch_adr 32e5 0x32e5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 2d26 2d26 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_b_adr 1f TOP - 1 2d27 2d27 fiu_mem_start 2 start-rd; Flow C 0x2d11 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 2d11 0x2d11 typ_b_adr 10 TOP typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2d28 2d28 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2d63 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d63 0x2d63 seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2d29 2d29 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 25 TR00:05 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2d2a 2d2a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 24 TR00:04 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 2d2b 2d2b fiu_mem_start 2 start-rd; Flow C 0x2d24 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 typ_a_adr 10 TOP typ_b_adr 25 TR00:05 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 2d2c 2d2c fiu_len_fill_lit 44 zero-fill 0x4; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_c_adr 2f TOP val_c_source 0 FIU_BUS 2d2d 2d2d fiu_mem_start 2 start-rd; Flow C 0x2d24 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 typ_b_adr 10 TOP typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 2d2e 2d2e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d2f 2d2f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 2d30 2d30 fiu_mem_start 2 start-rd; Flow C 0x2d24 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 typ_a_adr 10 TOP typ_b_adr 25 TR00:05 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 22 VR09:02 val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 9 val_rand a PASS_B_HIGH 2d31 2d31 fiu_mem_start 2 start-rd; Flow C 0x2d24 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d32 2d32 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR06:01 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 2d33 2d33 fiu_mem_start 2 start-rd; Flow C 0x2d24 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 typ_a_adr 10 TOP typ_b_adr 25 TR00:05 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 4 val_rand a PASS_B_HIGH 2d34 2d34 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2d63 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d63 0x2d63 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d35 2d35 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 25 TR00:05 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_frame 4 val_rand a PASS_B_HIGH 2d36 2d36 fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=True 0x2d25 fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2d25 0x2d25 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_frame 2 2d37 2d37 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2d47 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d47 0x2d47 seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_csa_cntl 3 POP_CSA typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d38 2d38 fiu_mem_start 2 start-rd fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 15 NOT_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d39 2d39 fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=True 0x2d25 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2d25 0x2d25 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_frame 2 2d3a 2d3a fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_a_adr 1f TOP - 1 typ_b_adr 16 CSA/VAL_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_b_adr 16 CSA/VAL_BUS 2d3b 2d3b fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 25 VR09:05 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 val_rand 3 CONDITION_TO_FIU 2d3c 2d3c fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2d3d 2d3d fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x2d3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2d3f 0x2d3f typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 01 GP01 2d3e 2d3e ioc_tvbs 3 fiu+fiu; Flow J 0x2d48 seq_br_type 3 Unconditional Branch seq_branch_adr 2d48 0x2d48 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 2d3f 2d3f fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x2d47 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 23 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d47 0x2d47 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d40 2d40 fiu_mem_start 2 start-rd; Flow C 0x2d24 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 32 VR05:12 val_alu_func 0 PASS_A val_b_adr 10 TOP val_frame 5 val_rand a PASS_B_HIGH 2d41 2d41 fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d42 2d42 ioc_load_wdr 0 ; Flow J 0x2d48 seq_br_type 3 Unconditional Branch seq_branch_adr 2d48 0x2d48 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 2d43 2d43 fiu_mem_start 6 start_rd_if_false; Flow C 0x32d7 fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref typ_b_adr 1f TOP - 1 typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 37 VR05:17 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_frame 5 2d44 2d44 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2d24 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_b_adr 24 VR11:04 val_frame 11 2d45 2d45 fiu_len_fill_lit 46 zero-fill 0x6; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x11) Subprogram_For_Call Subprogram_For_Call_Elaborated Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Accept_Subprogram Interface_Subprogram Utility_Subprogram Null_Subprogram seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 11 val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 2d46 2d46 fiu_mem_start 3 start-wr; Flow C cc=True 0x32dd ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dd 0x32dd seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 28 TR06:08 typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 2d47 2d47 ioc_load_wdr 0 ; Flow J 0x2d48 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2d48 0x2d48 2d48 2d48 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 2d49 2d49 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2d4a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 2d4f 0x2d4f seq_int_reads 5 RESOLVE RAM typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 2d4a 2d4a ioc_tvbs 2 fiu+val; Flow J cc=False 0x2d4d seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2d4d 0x2d4d seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 2d4b 2d4b seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x2d25 seq_br_type 9 Return False seq_branch_adr 2d25 0x2d25 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 20 VR02:00 val_frame 2 2d4c 2d4c seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 2d4d 2d4d fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2d4c ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d4c 0x2d4c seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2d4e 2d4e seq_br_type 7 Unconditional Call; Flow C 0x2d11 seq_branch_adr 2d11 0x2d11 seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 2d4f 2d4f fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2d4d fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2d4d 0x2d4d seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 39 VR0d:19 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame d 2d50 2d50 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 01 GP01 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2d51 2d51 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d52 2d52 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x2d5b fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 2d5b 0x2d5b seq_cond_sel 08 VAL.ALU_CARRY(late) typ_c_adr 0f TR00:10 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA val_a_adr 3d VR02:1d val_alu_func 6 A_MINUS_B val_frame 2 2d53 2d53 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2d5b ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2d5b 0x2d5b seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 23 VR07:03 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 7 2d54 2d54 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1c DEC_A val_c_adr 2c LOOP_REG val_c_source 0 FIU_BUS 2d55 2d55 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 2d56 2d56 ioc_fiubs 0 fiu ; Flow J cc=False 0x2d5c ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2d5c 0x2d5c seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2c LOOP_REG typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_alu_func 6 A_MINUS_B val_b_adr 3a VR02:1a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 2d57 2d57 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2d5c ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2d5c 0x2d5c typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2c LOOP_REG val_c_mux_sel 2 ALU val_rand 1 INC_LOOP_COUNTER 2d58 2d58 fiu_vmux_sel 1 fill value; Flow J 0x2d55 ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2d55 0x2d55 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand e CHECK_CLASS_SYSTEM_B val_alu_func 1c DEC_A val_c_adr 2c LOOP_REG val_c_source 0 FIU_BUS 2d59 2d59 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2d5a 2d5a ioc_tvbs c mem+mem+csa+dummy; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2d5b 2d5b fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x2d59 fiu_mem_start 5 start_rd_if_true fiu_offs_lit 10 fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2d59 0x2d59 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0f TR00:10 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 2d5c 2d5c fiu_len_fill_lit 45 zero-fill 0x5; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 30 TR00:10 typ_alu_func 0 PASS_A typ_c_adr 0f TR00:10 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME 2d5d 2d5d <halt> ; Flow R 2d5e ; -------------------------------------------------------------------------------------- 2d5e ; 0x006b Action Query_Break_Address 2d5e ; -------------------------------------------------------------------------------------- 2d5e MACRO_Action_Query_Break_Address: 2d5e 2d5e dispatch_brk_class 0 ; Flow C 0x2d65 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2d5e fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d65 0x2d65 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 2d5f 2d5f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 15 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 32 VR1d:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 1d 2d60 ; -------------------------------------------------------------------------------------- 2d60 ; 0x006d Action Query_Break_Cause 2d60 ; -------------------------------------------------------------------------------------- 2d60 MACRO_Action_Query_Break_Cause: 2d60 2d60 dispatch_brk_class 0 ; Flow J 0x2d61 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2d60 fiu_len_fill_lit 42 zero-fill 0x2 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 7d ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2d61 0x2d61 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 2d61 2d61 ioc_tvbs 5 seq+seq; Flow C cc=True 0x32db seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS 2d62 2d62 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 15 typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2d63 2d63 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2d64 ; -------------------------------------------------------------------------------------- 2d64 ; 0x006c Action Query_Break_Mask 2d64 ; -------------------------------------------------------------------------------------- 2d64 MACRO_Action_Query_Break_Mask: 2d64 2d64 dispatch_brk_class 0 ; Flow J 0x2d61 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2d64 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 20 ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2d61 0x2d61 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 2d65 ; -------------------------------------------------------------------------------------- 2d65 ; Comes from: 2d65 ; 2d5e C from color MACRO_Action_Query_Break_Address 2d65 ; 2d66 C from color ML_break_class 2d65 ; -------------------------------------------------------------------------------------- 2d65 2d65 ioc_tvbs 5 seq+seq; Flow R cc=False ; Flow J cc=True 0x32db seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32db 0x32db seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS 2d66 ; -------------------------------------------------------------------------------------- 2d66 ; 0x006a Action Alter_Break_Mask 2d66 ; -------------------------------------------------------------------------------------- 2d66 MACRO_Action_Alter_Break_Mask: 2d66 2d66 dispatch_brk_class 0 ; Flow C 0x2d65 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2d66 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d65 0x2d65 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 2d67 2d67 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_mdr 1 hold_mdr fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 2d68 2d68 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2d47 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2d47 0x2d47 seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_frame 15 typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2d69 2d69 <halt> ; Flow R 2d6a ; -------------------------------------------------------------------------------------- 2d6a ; 0x006f Action Break_Unconditional 2d6a ; -------------------------------------------------------------------------------------- 2d6a MACRO_Action_Break_Unconditional: 2d6a 2d6a dispatch_brk_class 0 dispatch_csa_free 3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 2d6a fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val val_a_adr 3e VR03:1e val_frame 3 2d6b 2d6b fiu_load_tar 1 hold_tar; Flow J 0x14a fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 32 VR1d:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 1d 2d6c 2d6c fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_load_wdr 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 2d6d 2d6d ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 16 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2d6e 2d6e ioc_tvbs 2 fiu+val; Flow J cc=True 0x2d7a seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2d7a 0x2d7a typ_a_adr 2e TR06:0e typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 6 2d6f 2d6f fiu_mem_start 2 start-rd; Flow C 0x2d24 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 typ_a_adr 28 TR06:08 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2d70 2d70 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x2d79 fiu_load_var 1 hold_var fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d79 0x2d79 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2d71 2d71 seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_en_micro 0 2d72 2d72 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x2d6b seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2d6b 0x2d6b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2d73 2d73 fiu_mem_start 2 start-rd; Flow C 0x2d24 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2d74 2d74 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_b_adr 16 CSA/VAL_BUS 2d75 2d75 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2d76 2d76 fiu_mem_start 2 start-rd; Flow C 0x2d24 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2d77 2d77 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2d78 2d78 ioc_load_wdr 0 ; Flow J 0x2d6b seq_br_type 3 Unconditional Branch seq_branch_adr 2d6b 0x2d6b seq_en_micro 0 typ_b_adr 02 GP02 val_b_adr 02 GP02 2d79 2d79 seq_br_type 0 Branch False; Flow J cc=False 0x2dec seq_branch_adr 2dec 0x2dec seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_b_adr 03 GP03 typ_c_lit 1 typ_frame 16 val_b_adr 39 VR02:19 val_frame 2 2d7a 2d7a fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 0a ? typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 30 VR02:10 val_frame 2 2d7b 2d7b fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 34 VR02:14 val_frame 2 2d7c 2d7c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 02 ? 2d7d 2d7d seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 2d7e 2d7e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 03 GP03 2d7f 2d7f fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2d80 2d80 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 3 seq_random 25 Load_ibuff+? typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2d81 2d81 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2d83 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2d83 0x2d83 seq_en_micro 0 seq_random 41 Load_control_pred+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2d82 2d82 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d83 seq_br_type 3 Unconditional Branch seq_branch_adr 2d83 0x2d83 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2d83 2d83 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2d84 2d84 seq_br_type 3 Unconditional Branch; Flow J 0x2dec seq_branch_adr 2dec 0x2dec seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 39 VR02:19 val_frame 2 2d85 ; -------------------------------------------------------------------------------------- 2d85 ; Comes from: 2d85 ; 0148 C True from color ML_break_class 2d85 ; -------------------------------------------------------------------------------------- 2d85 2d85 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION 2d86 2d86 ioc_tvbs 5 seq+seq; Flow J cc=True 0x2d87 ; Flow J cc=#0x0 0x2d87 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 2d87 0x2d87 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? val_a_adr 32 VR1d:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 1d 2d87 2d87 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 2d88 2d88 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d89 2d89 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d8a 2d8a ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d8b 2d8b ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d8c 2d8c ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d8d 2d8d ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d8e 2d8e ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d8f 2d8f ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 30 TR00:10 2d90 2d90 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 22 VR05:02 val_frame 5 2d91 2d91 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 22 VR05:02 val_frame 5 2d92 2d92 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 21 VR05:01 val_frame 5 2d93 2d93 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 21 VR05:01 val_frame 5 2d94 2d94 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 2d95 2d95 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 2d96 2d96 fiu_load_var 1 hold_var; Flow J 0x14a fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 014a 0x014a seq_en_micro 0 val_a_adr 3a VR02:1a val_frame 2 2d97 2d97 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 38 TR00:18 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 38 VR00:18 2d98 2d98 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 37 TR00:17 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 37 VR00:17 2d99 2d99 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 36 TR00:16 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 36 VR00:16 2d9a 2d9a fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 35 TR00:15 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 35 VR00:15 2d9b 2d9b fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 34 TR00:14 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 34 VR00:14 2d9c 2d9c fiu_tivi_src 4 fiu_var; Flow J cc=True 0x14a ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 014a 0x014a seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 33 TR00:13 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 33 VR00:13 2d9d 2d9d fiu_tivi_src 4 fiu_var; Flow J cc=True 0x2da0 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2da0 0x2da0 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 32 TR00:12 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 32 VR00:12 2d9e 2d9e fiu_tivi_src 4 fiu_var; Flow J cc=False 0x2dec ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2dec 0x2dec seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 31 TR00:11 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 19 X_XOR_B val_b_adr 31 VR00:11 val_c_adr 3b GP04 2d9f 2d9f seq_br_type 3 Unconditional Branch; Flow J 0x14a seq_branch_adr 014a 0x014a seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 04 GP04 2da0 2da0 seq_br_type 3 Unconditional Branch; Flow J 0x2d9f seq_branch_adr 2d9f 0x2d9f seq_en_micro 0 val_c_adr 3b GP04 2da1 2da1 <halt> ; Flow R 2da2 ; -------------------------------------------------------------------------------------- 2da2 ; 0x006e Action Exit_Break 2da2 ; -------------------------------------------------------------------------------------- 2da2 MACRO_Action_Exit_Break: 2da2 2da2 dispatch_brk_class 0 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 2da2 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2da3 2da3 fiu_mem_start 2 start-rd; Flow C 0x2d24 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 typ_a_adr 20 TR00:00 typ_alu_func 1 A_PLUS_B typ_mar_cntl e LOAD_MAR_CONTROL 2da4 2da4 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 15 typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 2da5 2da5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 15 NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2da6 2da6 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2da7 2da7 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2da8 2da8 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_lex_adr 2 seq_random 0b ? typ_a_adr 14 ZEROS val_a_adr 25 VR09:05 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 9 val_rand 3 CONDITION_TO_FIU 2da9 2da9 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 3 seq ioc_fiubs 1 val seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 2daa 2daa ioc_tvbs 3 fiu+fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 2dab 2dab seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 31 ? typ_b_adr 01 GP01 2dac 2dac fiu_mem_start 2 start-rd; Flow J 0x2e0c seq_br_type 3 Unconditional Branch seq_branch_adr 2e0c MACRO_Exit_Subprogram_topoffset,>R seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 2 seq_random 14 Load_save_offset+? 2dad ; -------------------------------------------------------------------------------------- 2dad ; Comes from: 2dad ; 2dce C from color MACRO_Action_Query_Frame 2dad ; 2dde C from color ML_break_class 2dad ; -------------------------------------------------------------------------------------- 2dad 2dad ioc_fiubs 1 val typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 3a VR02:1a val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2dae 2dae fiu_load_tar 1 hold_tar; Flow J cc=True 0x2db2 fiu_tivi_src 8 type_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2db2 0x2db2 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 5 RESOLVE RAM typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 1f TOP - 1 2daf 2daf fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2d11 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 2d11 0x2d11 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 2db0 2db0 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x2dbf seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2dbf 0x2dbf seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_rand a PASS_B_HIGH val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2db1 2db1 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 05 ? val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2db2 2db2 fiu_mem_start 2 start-rd; Flow C 0x2d24 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d24 0x2d24 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand 9 PASS_A_HIGH 2db3 2db3 seq_br_type 1 Branch True; Flow J cc=True 0x2db6 seq_branch_adr 2db6 0x2db6 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 2db4 2db4 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2db5 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 2dbf 0x2dbf typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2db5 2db5 fiu_mem_start 2 start-rd; Flow J 0x2d11 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2d11 0x2d11 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 2db6 2db6 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2db7 2db7 fiu_len_fill_lit 5a zero-fill 0x1a fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2db8 2db8 fiu_mem_start 2 start-rd; Flow C 0x2d11 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d11 0x2d11 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A 2db9 2db9 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 21 VR06:01 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 2dba 2dba fiu_mem_start 2 start-rd; Flow C 0x2d11 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d11 0x2d11 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2dbb 2dbb ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2dbc 2dbc fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2dbd 2dbd fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 2dbe 2dbe seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 02 GP02 val_alu_func 1b A_OR_B val_b_adr 0f GP0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2dbf 2dbf fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2dc4 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 2dc4 0x2dc4 seq_cond_sel 56 SEQ.LATCHED_COND typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2dc0 2dc0 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2db1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2db1 0x2db1 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 3e VR02:1e val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2dc1 2dc1 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 1a PASS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 val_rand 9 PASS_A_HIGH 2dc2 2dc2 fiu_mem_start 2 start-rd; Flow C 0x2d11 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 2d11 0x2d11 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2dc3 2dc3 seq_br_type 3 Unconditional Branch; Flow J 0x2dbf seq_branch_adr 2dbf 0x2dbf seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 06 GP06 typ_alu_func 1c DEC_A typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 2dc4 2dc4 fiu_len_fill_lit 13 sign-fill 0x13 fiu_mem_start 2 start-rd fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 val_rand a PASS_B_HIGH 2dc5 2dc5 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2db1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2db1 0x2db1 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 20 TR08:00 typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2dc6 2dc6 seq_br_type 7 Unconditional Call; Flow C 0x2d11 seq_branch_adr 2d11 0x2d11 seq_en_micro 0 2dc7 2dc7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x2d11 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 2d11 0x2d11 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 2dc8 2dc8 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x2dcb seq_br_type 0 Branch False seq_branch_adr 2dcb 0x2dcb seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2dc9 2dc9 fiu_mem_start 2 start-rd; Flow C 0x2d11 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 2d11 0x2d11 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_frame 4 2dca 2dca ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 2dcb 0x2dcb seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 2dcb 2dcb seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 05 ? val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 2dcc ; -------------------------------------------------------------------------------------- 2dcc ; Comes from: 2dcc ; 2dd0 C from color MACRO_Action_Query_Frame 2dcc ; 2df1 C from color 0x2def 2dcc ; 2df5 C from color 0x2def 2dcc ; -------------------------------------------------------------------------------------- 2dcc 2dcc seq_br_type a Unconditional Return; Flow R seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 2dcd 2dcd <halt> ; Flow R 2dce ; -------------------------------------------------------------------------------------- 2dce ; 0x0069 Action Query_Frame 2dce ; -------------------------------------------------------------------------------------- 2dce MACRO_Action_Query_Frame: 2dce 2dce dispatch_brk_class 0 ; Flow C 0x2dad dispatch_csa_free 2 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 2dce seq_br_type 7 Unconditional Call seq_branch_adr 2dad 0x2dad 2dcf 2dcf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2dd7 seq_br_type 1 Branch True seq_branch_adr 2dd7 0x2dd7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 2dd0 2dd0 ioc_fiubs 1 val ; Flow C 0x2dcc seq_br_type 7 Unconditional Call seq_branch_adr 2dcc 0x2dcc typ_a_adr 1e TOP - 2 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 2dd1 2dd1 seq_b_timing 1 Latch Condition; Flow J cc=False 0x2dd8 seq_br_type 0 Branch False seq_branch_adr 2dd8 0x2dd8 seq_random 02 ? typ_csa_cntl 2 PUSH_CSA 2dd2 2dd2 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2dd3 2dd3 ioc_tvbs 1 typ+fiu typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR11:03 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 11 2dd4 2dd4 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR07:00 val_alu_func 1e A_AND_B val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 7 2dd5 2dd5 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 32 TR02:12 typ_c_adr 22 TOP - 0x3 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 28 VR07:08 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU val_frame 7 2dd6 2dd6 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 32 TR02:12 typ_c_adr 23 TOP - 0x4 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU val_frame 6 2dd7 2dd7 seq_random 02 ? typ_csa_cntl 2 PUSH_CSA 2dd8 2dd8 seq_random 02 ? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2dd9 2dd9 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2dda 2dda typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 2ddb 2ddb typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 22 TOP - 0x3 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 22 TOP - 0x3 val_c_mux_sel 2 ALU 2ddc 2ddc fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 23 TOP - 0x4 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 23 TOP - 0x4 val_c_mux_sel 2 ALU 2ddd 2ddd <halt> ; Flow R 2dde ; -------------------------------------------------------------------------------------- 2dde ; 0x0068 Action Establish_Frame 2dde ; -------------------------------------------------------------------------------------- 2dde MACRO_Action_Establish_Frame: 2dde 2dde dispatch_brk_class 0 ; Flow C 0x2dad dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 2dde seq_br_type 7 Unconditional Call seq_branch_adr 2dad 0x2dad 2ddf 2ddf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2ded seq_br_type 1 Branch True seq_branch_adr 2ded 0x2ded seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 3a VR02:1a val_frame 2 2de0 2de0 ioc_fiubs 1 val typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 2de1 2de1 typ_a_adr 29 TR05:09 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 1e TOP - 2 val_alu_func 1b A_OR_B val_b_adr 1d TOP - 3 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2de2 2de2 val_a_adr 06 GP06 val_alu_func 1d A_AND_NOT_B val_b_adr 21 VR06:01 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 6 2de3 2de3 val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 6 2de4 2de4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 14 Load_save_offset+? typ_a_adr 01 GP01 typ_alu_func 15 NOT_B typ_b_adr 3d TR02:1d typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 06 GP06 val_alu_func 2 INC_A_PLUS_B val_b_adr 07 GP07 val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2de5 2de5 seq_en_micro 0 seq_random 02 ? typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 2de6 2de6 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 2a ? typ_b_adr 05 GP05 typ_csa_cntl 3 POP_CSA typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2de7 2de7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 39 TR02:19 typ_alu_func 1b A_OR_B typ_b_adr 06 GP06 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 06 GP06 2de8 2de8 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_op_sel 3 insert ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 43 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 2de9 2de9 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 2d Load_ibuff+? typ_a_adr 05 GP05 typ_alu_func 1e A_AND_B typ_b_adr 21 TR02:01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2dea 2dea fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2dec fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2dec 0x2dec seq_en_micro 0 seq_random 41 Load_control_pred+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2deb 2deb ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2dec seq_br_type 3 Unconditional Branch seq_branch_adr 2dec 0x2dec seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2dec 2dec fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2ded 2ded seq_random 02 ? typ_csa_cntl 3 POP_CSA 2dee 2dee seq_br_type 3 Unconditional Branch; Flow J 0x2d48 seq_branch_adr 2d48 0x2d48 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU 2def 2def ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2df0 2df0 ioc_fiubs 1 val typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_rand a PASS_B_HIGH val_a_adr 10 TOP 2df1 2df1 ioc_fiubs 2 typ ; Flow C 0x2dcc seq_br_type 7 Unconditional Call seq_branch_adr 2dcc 0x2dcc typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 2df2 2df2 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2dfd ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2dfd 0x2dfd seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_frame 7 val_rand a PASS_B_HIGH 2df3 2df3 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU 2df4 2df4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e02 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e02 0x2e02 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2df5 2df5 seq_br_type 7 Unconditional Call; Flow C 0x2dcc seq_branch_adr 2dcc 0x2dcc 2df6 2df6 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2dfd ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2dfd 0x2dfd seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 2df7 2df7 ioc_fiubs 1 val ; Flow J cc=True 0x2dfd seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2dfd 0x2dfd seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 val_rand 9 PASS_A_HIGH 2df8 2df8 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2dfd fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2dfd 0x2dfd seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2df9 2df9 fiu_mem_start 2 start-rd; Flow C 0x339d ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 339d 0x339d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2dfa 2dfa fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2dfe ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2dfe 0x2dfe seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 07 GP07 typ_b_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2dfb 2dfb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2dff seq_br_type 5 Call True seq_branch_adr 2dff 0x2dff seq_cond_sel 67 REFRESH_MACRO_EVENT 2dfc 2dfc fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x2df9 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 2df9 0x2df9 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f val_b_adr 16 CSA/VAL_BUS 2dfd 2dfd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2dfe 2dfe fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 20 VR07:00 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 7 2dff ; -------------------------------------------------------------------------------------- 2dff ; Comes from: 2dff ; 2dfb C True from color 0x2def 2dff ; -------------------------------------------------------------------------------------- 2dff 2dff seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2e00 2e00 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 2e01 2e01 seq_br_type a Unconditional Return; Flow R 2e02 2e02 ioc_fiubs 0 fiu typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS 2e03 2e03 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2df9 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 2df9 0x2df9 typ_b_adr 08 GP08 2e04 2e04 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2e05 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 2e05 0x2e05 typ_a_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 2 2e05 2e05 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2e08 ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2e08 0x2e08 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR 2e06 2e06 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 2e07 2e07 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x2e0a fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 2e0a 0x2e0a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 2 DEC_LOOP_COUNTER 2e08 2e08 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 2e09 2e09 fiu_fill_mode_src 0 ; Flow J 0x2e07 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2e07 0x2e07 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_frame 2 2e0a 2e0a fiu_mem_start 2 start-rd; Flow C 0x32f5 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32f5 0x32f5 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x10) Subprogram_Ref_For_Call Subprogram_Ref_For_Call_Elaborated Subprogram_Ref_For_Call_Visible Subprogram_Ref_For_Call_Visible_Elaborated Accept_Subprogram_Ref Interface_Subprogram_Ref seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL 2e0b 2e0b <halt> ; Flow R 2e0c ; -------------------------------------------------------------------------------------- 2e0c ; 0x4500-0x45ff Exit_Subprogram topoffset,>R 2e0c ; -------------------------------------------------------------------------------------- 2e0c MACRO_Exit_Subprogram_topoffset,>R: 2e0c 2e0c dispatch_brk_class 6 ; Flow J cc=False 0x2f7c dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 0 CONTROL READ, AT CONTROL PRED dispatch_uadr 2e0c fiu_mem_start 9 start_continue_if_true fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_random 12 exit function pop below tcb event enable ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f7c 0x2f7c seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 4 SAVE OFFSET seq_random 68 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2e0d 2e0d ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e0e 2e0e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e12 fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e12 0x2e12 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2e0f 2e0f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2e17 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e17 0x2e17 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_c_adr 1d TR02:02 typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 1d VR02:02 val_frame 2 2e10 2e10 ioc_fiubs 2 typ ; Flow J cc=False 0x2e15 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e15 0x2e15 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 2e11 2e11 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER 2e12 2e12 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2e13 2e13 fiu_load_tar 1 hold_tar; Flow J cc=True 0x2e19 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e19 0x2e19 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2e14 2e14 ioc_fiubs 0 fiu ; Flow J 0x2eb3 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2eb3 0x2eb3 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2e15 2e15 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2e16 2e16 fiu_tivi_src 4 fiu_var; Flow J 0x2eb6 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 2eb6 0x2eb6 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 39 VR02:19 val_b_adr 39 VR02:19 val_frame 2 2e17 2e17 fiu_load_var 1 hold_var; Flow C 0x2e1d fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2e1d 0x2e1d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2e18 2e18 seq_br_type 7 Unconditional Call; Flow C 0x32df seq_branch_adr 32df 0x32df 2e19 2e19 seq_br_type 7 Unconditional Call; Flow C 0x2e1d seq_branch_adr 2e1d 0x2e1d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 2e1a 2e1a ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2e1b 2e1b fiu_load_tar 1 hold_tar; Flow J 0x2e1c fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 32df 0x32df seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2e1c 2e1c seq_br_type 3 Unconditional Branch; Flow J 0x2eb3 seq_branch_adr 2eb3 0x2eb3 seq_cond_sel 16 VAL.TRUE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2e1d 2e1d ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 2e1e 2e1e fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2e1f 2e1f fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x2e27 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e27 0x2e27 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 2e20 2e20 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2e21 2e21 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_rand 2 DEC_LOOP_COUNTER 2e22 2e22 seq_b_timing 0 Early Condition; Flow J cc=False 0x2e22 seq_br_type 0 Branch False seq_branch_adr 2e22 0x2e22 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA val_rand 2 DEC_LOOP_COUNTER 2e23 2e23 ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP 2e24 2e24 ioc_fiubs 2 typ ; Flow C 0x332e seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 0c TR18:13 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 18 2e25 2e25 ioc_tvbs 5 seq+seq; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 2e26 0x2e26 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 2e26 2e26 seq_br_type 8 Return True; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 11 TOP + 1 typ_c_lit 0 typ_frame 1f 2e27 2e27 fiu_len_fill_lit 78 zero-fill 0x38; Flow C 0x2ab4 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 2e28 2e28 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2e29 2e29 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 2e2a 2e2a ioc_adrbs 2 typ ; Flow J cc=True 0x2e23 ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e23 0x2e23 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_csa_cntl 0 LOAD_CONTROL_TOP val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 2e2b 2e2b seq_br_type 3 Unconditional Branch; Flow J 0x2e22 seq_branch_adr 2e22 0x2e22 seq_en_micro 0 val_rand 2 DEC_LOOP_COUNTER 2e2c ; -------------------------------------------------------------------------------------- 2e2c ; 0x00cc Action Pop_Block 2e2c ; -------------------------------------------------------------------------------------- 2e2c MACRO_Action_Pop_Block: 2e2c 2e2c dispatch_brk_class 6 ; Flow J cc=False 0x2f7c dispatch_csa_valid 0 dispatch_ignore 1 dispatch_mem_strt 0 CONTROL READ, AT CONTROL PRED dispatch_uadr 2e2c fiu_mem_start 9 start_continue_if_true ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f7c 0x2f7c seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 62 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 6 CHECK_CLASS_A_??_B 2e2d 2e2d ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e2e 2e2e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e31 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e31 0x2e31 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 2e2f 2e2f fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_csa_cntl 1 START_POP_DOWN 2e30 2e30 ioc_fiubs 2 typ ; Flow J 0x2e11 seq_br_type 3 Unconditional Branch seq_branch_adr 2e11 0x2e11 seq_en_micro 0 seq_lex_adr 2 seq_random 64 Load_control_top+? typ_c_adr 1d TR02:02 typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2e31 2e31 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 2e32 2e32 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL 2e33 2e33 ioc_fiubs 2 typ ; Flow J 0x2eb3 seq_br_type 3 Unconditional Branch seq_branch_adr 2eb3 0x2eb3 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_lex_adr 2 seq_random 64 Load_control_top+? 2e34 ; -------------------------------------------------------------------------------------- 2e34 ; 0x4300-0x43ff Exit_Subprogram From_Utility,>R,topoffset 2e34 ; -------------------------------------------------------------------------------------- 2e34 MACRO_Exit_Subprogram_From_Utility,>R,topoffset: 2e34 2e34 dispatch_brk_class 6 ; Flow C cc=False 0x32df dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 0 CONTROL READ, AT CONTROL PRED dispatch_uadr 2e34 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_random 12 exit function pop below tcb event enable ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32df 0x32df seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 4 SAVE OFFSET seq_random 68 ? typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2e35 2e35 fiu_load_tar 1 hold_tar; Flow J cc=True 0x2e3a fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e3a 0x2e3a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 0 typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2e36 2e36 ioc_adrbs 3 seq ; Flow J 0x2e37 ioc_fiubs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 2e11 0x2e11 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 51 Load_current_lex+? typ_a_adr 14 ZEROS typ_csa_cntl 1 START_POP_DOWN val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e37 2e37 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e40 fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e40 0x2e40 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2e38 2e38 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2e17 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e17 0x2e17 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_c_adr 1d TR02:02 typ_frame 2 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 1d VR02:02 val_frame 2 2e39 2e39 ioc_fiubs 2 typ ; Flow R cc=True ; Flow J cc=False 0x2e15 ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 2e15 0x2e15 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? 2e3a 2e3a fiu_mem_start 2 start-rd; Flow J 0x2e3b ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2e11 0x2e11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 2e3b 2e3b typ_a_adr 28 TR02:08 typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e3c 2e3c fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 2e3d 2e3d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2eaf fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2eaf 0x2eaf seq_random 02 ? typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_b_adr 02 GP02 2e3e 2e3e ioc_adrbs 3 seq ioc_tvbs 3 fiu+fiu seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 51 Load_current_lex+? typ_csa_cntl 1 START_POP_DOWN 2e3f 2e3f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2e38 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 2e38 0x2e38 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_b_adr 02 GP02 typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_b_adr 02 GP02 2e40 2e40 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2e41 2e41 fiu_load_var 1 hold_var; Flow J cc=True 0x2e17 fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e17 0x2e17 seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B 2e42 2e42 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2e43 2e43 fiu_tivi_src 2 tar_fiu; Flow J 0x2eb3 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2eb3 0x2eb3 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 14 ZEROS typ_b_adr 32 TR02:12 typ_frame 2 2e44 ; -------------------------------------------------------------------------------------- 2e44 ; 0x4400-0x44ff Exit_Subprogram With_Result,>R,topoffset 2e44 ; -------------------------------------------------------------------------------------- 2e44 MACRO_Exit_Subprogram_With_Result,>R,topoffset: 2e44 2e44 dispatch_brk_class 6 ; Flow J cc=False 0x2f7f dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_mem_strt 2 CONTROL READ, AT (INNER - PARAMS) dispatch_uadr 2e44 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f7f 0x2f7f seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 4 SAVE OFFSET seq_random 69 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2e45 2e45 fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=False 0x2fbc fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2fbc 0x2fbc seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e46 2e46 fiu_mem_start 4 continue; Flow C cc=#0x0 0x2e4b fiu_tivi_src c mar_0xc ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2e4b 0x2e4b seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 seq_random 0a ? typ_a_adr 22 TR02:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2e47 2e47 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e65 fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e65 0x2e65 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e48 2e48 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e5f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 2e5f 0x2e5f seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_a_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2e49 2e49 ioc_fiubs 2 typ ; Flow J cc=False 0x2e6a ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e6a 0x2e6a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2e4a 2e4a fiu_mem_start 2 start-rd; Flow R fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e4b 2e4b fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=True ; Flow J cc=False 0x2e56 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2e56 0x2e56 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e4c 2e4c seq_br_type 3 Unconditional Branch; Flow J 0x2eb8 seq_branch_adr 2eb8 0x2eb8 2e4d 2e4d seq_br_type 3 Unconditional Branch; Flow J 0x2eb8 seq_branch_adr 2eb8 0x2eb8 2e4e 2e4e seq_br_type 3 Unconditional Branch; Flow J 0x2eb8 seq_branch_adr 2eb8 0x2eb8 2e4f 2e4f fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=True ; Flow J cc=False 0x2e56 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2e56 0x2e56 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e50 2e50 seq_br_type 3 Unconditional Branch; Flow J 0x2eb8 seq_branch_adr 2eb8 0x2eb8 2e51 2e51 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2e53 seq_br_type 1 Branch True seq_branch_adr 2e53 0x2e53 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1e val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2e52 2e52 seq_br_type 3 Unconditional Branch; Flow J 0x2eb8 seq_branch_adr 2eb8 0x2eb8 2e53 2e53 fiu_len_fill_lit 5a zero-fill 0x1a; Flow R cc=True ; Flow J cc=False 0x2e56 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2e56 0x2e56 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 03 GP03 typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 03 GP03 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e54 ; -------------------------------------------------------------------------------------- 2e54 ; 0x00ca Action Exit_Nullary_Function,>R 2e54 ; -------------------------------------------------------------------------------------- 2e54 MACRO_Action_Exit_Nullary_Function,>R: 2e54 2e54 dispatch_brk_class 6 ; Flow J cc=False 0x2f7f dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 2e54 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f7f 0x2f7f seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 14 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e55 2e55 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x2e46 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2e46 0x2e46 seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_c_adr 3e GP01 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR02:10 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 2e56 2e56 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e5c fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e5c 0x2e5c seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e57 2e57 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? 2e58 2e58 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 seq_lex_adr 2 seq_random 0b ? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2e59 2e59 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f 2e5a 2e5a seq_br_type 7 Unconditional Call; Flow C 0x2e1d seq_branch_adr 2e1d 0x2e1d seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 2e5b 2e5b seq_br_type 7 Unconditional Call; Flow C 0x32df seq_branch_adr 32df 0x32df 2e5c 2e5c fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? 2e5d 2e5d fiu_load_var 1 hold_var; Flow J 0x2e5e fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2e1a 0x2e1a seq_en_micro 0 seq_lex_adr 2 seq_random 0b ? typ_a_adr 01 GP01 2e5e 2e5e seq_br_type 3 Unconditional Branch; Flow J 0x2e1d seq_branch_adr 2e1d 0x2e1d seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 2e5f 2e5f ioc_fiubs 2 typ ; Flow J cc=False 0x2e61 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e61 0x2e61 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2e60 2e60 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2e64 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2e64 0x2e64 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_frame 2 2e61 2e61 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e62 2e62 fiu_mem_start 2 start-rd; Flow J cc=True 0x2e64 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2e64 0x2e64 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 15 ? typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_frame 2 2e63 2e63 seq_br_type 3 Unconditional Branch; Flow J 0x2eb6 seq_branch_adr 2eb6 0x2eb6 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2e64 2e64 seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e65 2e65 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2e66 2e66 fiu_mem_start 2 start-rd; Flow J cc=False 0x2e68 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 2e68 0x2e68 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 14 ZEROS val_b_adr 39 VR02:19 val_frame 2 2e67 2e67 ioc_fiubs 2 typ ; Flow J 0x2eb3 seq_br_type 3 Unconditional Branch seq_branch_adr 2eb3 0x2eb3 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e68 2e68 ioc_fiubs 2 typ ; Flow C 0x2eb3 seq_br_type 7 Unconditional Call seq_branch_adr 2eb3 0x2eb3 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e69 2e69 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2e64 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2e64 0x2e64 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2e6a 2e6a fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2e6b 2e6b seq_br_type 3 Unconditional Branch; Flow J 0x2eb6 seq_branch_adr 2eb6 0x2eb6 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_random 03 ? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e6c ; -------------------------------------------------------------------------------------- 2e6c ; 0x00cb Action Pop_Block_With_Result 2e6c ; -------------------------------------------------------------------------------------- 2e6c MACRO_Action_Pop_Block_With_Result: 2e6c 2e6c dispatch_brk_class 6 ; Flow J cc=False 0x2f7f dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2e6c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 5 start_rd_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2f7f 0x2f7f seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 2b ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e6d 2e6d seq_random 14 Load_save_offset+? typ_c_adr 3e GP01 val_c_adr 3c GP03 2e6e 2e6e fiu_len_fill_lit 42 zero-fill 0x2 fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e6f 2e6f fiu_mem_start 4 continue; Flow J cc=True 0x2e70 ; Flow J cc=#0x0 0x2e70 ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 2e70 0x2e70 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_random 62 ? typ_a_adr 22 TR02:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3d GP02 val_c_source 0 FIU_BUS 2e70 2e70 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2e78 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2e78 0x2e78 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e71 2e71 seq_br_type 3 Unconditional Branch; Flow J 0x2e7f seq_branch_adr 2e7f 0x2e7f 2e72 2e72 seq_br_type 3 Unconditional Branch; Flow J 0x2e7f seq_branch_adr 2e7f 0x2e7f 2e73 2e73 seq_br_type 3 Unconditional Branch; Flow J 0x2e7f seq_branch_adr 2e7f 0x2e7f 2e74 2e74 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2e78 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2e78 0x2e78 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e75 2e75 seq_br_type 3 Unconditional Branch; Flow J 0x2e7f seq_branch_adr 2e7f 0x2e7f 2e76 2e76 seq_br_type 3 Unconditional Branch; Flow J 0x2e7f seq_branch_adr 2e7f 0x2e7f 2e77 2e77 seq_br_type 3 Unconditional Branch; Flow J 0x2e7f seq_branch_adr 2e7f 0x2e7f 2e78 2e78 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e82 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e82 0x2e82 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2e79 2e79 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e7c fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 2e7c 0x2e7c seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_a_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2e7a 2e7a ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2e7b 2e7b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e7c 2e7c ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2e7d 2e7d fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2e7e 0x2e7e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 2f TOP typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_frame 2 2e7e 2e7e seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e7f 2e7f ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 2e80 2e80 seq_int_reads 0 TYP VAL BUS seq_random 59 ? val_b_adr 03 GP03 2e81 2e81 seq_br_type 3 Unconditional Branch; Flow J 0x2eb8 seq_branch_adr 2eb8 0x2eb8 seq_int_reads 0 TYP VAL BUS seq_random 4f ? typ_b_adr 05 GP05 val_b_adr 05 GP05 2e82 2e82 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 2e83 2e83 fiu_mem_start 2 start-rd; Flow J cc=False 0x2e7c ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 2e7c 0x2e7c seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2e84 2e84 ioc_fiubs 2 typ ; Flow J 0x2eb3 seq_br_type 3 Unconditional Branch seq_branch_adr 2eb3 0x2eb3 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e85 2e85 <halt> ; Flow R 2e86 ; -------------------------------------------------------------------------------------- 2e86 ; 0x4200-0x42ff Exit_Subprogram From_Utility,With_Result,>R,topoffset 2e86 ; -------------------------------------------------------------------------------------- 2e86 MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset: 2e86 2e86 dispatch_brk_class 6 ; Flow C cc=False 0x32df dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_mem_strt 2 CONTROL READ, AT (INNER - PARAMS) dispatch_uadr 2e86 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 32df 0x32df seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 4 SAVE OFFSET seq_random 69 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 2e87 2e87 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x2fbe fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2fbe 0x2fbe seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0b) Control_State Word3_Flag Module_Key Mark_Word_Flag Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Auxiliary_Mark Micro_State1 Micro_state2 Activation_Link Control_Allocation Scheduling_Allocation Accept_Link Activation_State typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame b typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2e88 2e88 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x2eaa fiu_mem_start 2 start-rd fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2eaa 0x2eaa seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2e89 2e89 fiu_mem_start 4 continue; Flow C cc=#0x0 0x2e8b fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2e8b 0x2e8b seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 seq_random 0a ? typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 2e8a 2e8a seq_br_type 3 Unconditional Branch; Flow J 0x2e56 seq_branch_adr 2e56 0x2e56 seq_en_micro 0 2e8b ; -------------------------------------------------------------------------------------- 2e8b ; Comes from: 2e8b ; 2e89 C #0x0 from color MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset 2e8b ; -------------------------------------------------------------------------------------- 2e8b 2e8b ioc_adrbs 3 seq ; Flow R cc=False ; Flow J cc=True 0x2e93 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2e93 0x2e93 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e8c 2e8c seq_br_type 3 Unconditional Branch; Flow J 0x2eb8 seq_branch_adr 2eb8 0x2eb8 2e8d 2e8d ioc_adrbs 3 seq ; Flow R cc=False ; Flow J cc=True 0x2e98 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2e98 0x2e98 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2e8e 2e8e seq_br_type 3 Unconditional Branch; Flow J 0x2eb8 seq_branch_adr 2eb8 0x2eb8 2e8f 2e8f ioc_adrbs 3 seq ; Flow R cc=False ; Flow J cc=True 0x2e93 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2e93 0x2e93 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4e Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2e90 2e90 seq_br_type 3 Unconditional Branch; Flow J 0x2eb8 seq_branch_adr 2eb8 0x2eb8 2e91 2e91 seq_br_type 3 Unconditional Branch; Flow J 0x2eb8 seq_branch_adr 2eb8 0x2eb8 2e92 2e92 seq_br_type 3 Unconditional Branch; Flow J 0x2eb8 seq_branch_adr 2eb8 0x2eb8 2e93 2e93 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e95 fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e95 0x2e95 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2e94 2e94 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2e49 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2e49 0x2e49 seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_b_adr 02 GP02 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e95 2e95 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e96 2e96 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 1 val seq_random 0f Load_control_top+? typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 01 GP01 2e97 2e97 seq_br_type 3 Unconditional Branch; Flow J 0x2eb3 seq_branch_adr 2eb3 0x2eb3 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_alu_func 0 PASS_A typ_b_adr 32 TR02:12 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 2e98 2e98 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2e9e fiu_load_mdr 1 hold_mdr fiu_mem_start 5 start_rd_if_true fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2e9e 0x2e9e seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 47 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2e99 2e99 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 7 CONTROL PRED seq_latch 1 seq_random 57 Load_control_pred+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e9a 2e9a ioc_fiubs 2 typ ; Flow J cc=False 0x2ea6 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ea6 0x2ea6 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 61 Load_ibuff+Load_control_pred+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2e9b 2e9b fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2e9c 0x2e9c seq_cond_sel 08 VAL.ALU_CARRY(late) seq_latch 1 seq_random 04 Load_save_offset+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B 2e9c 2e9c fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2e9d 0x2e9d seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2e9d 2e9d seq_br_type 7 Unconditional Call; Flow C 0x32df seq_branch_adr 32df 0x32df typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2e9e 2e9e ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 21 VR02:01 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2e9f 2e9f ioc_fiubs 2 typ seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 seq_random 0f Load_control_top+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_csa_cntl 2 PUSH_CSA val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2ea0 2ea0 fiu_load_var 1 hold_var; Flow J cc=True 0x2ea2 fiu_mem_start 2 start-rd fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2ea2 0x2ea2 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 14 ZEROS 2ea1 2ea1 seq_br_type 3 Unconditional Branch; Flow J 0x2eb3 seq_branch_adr 2eb3 0x2eb3 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_alu_func 0 PASS_A typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2ea2 2ea2 ioc_tvbs 1 typ+fiu; Flow J 0x2eb3 seq_br_type 3 Unconditional Branch seq_branch_adr 2eb3 0x2eb3 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_alu_func 0 PASS_A typ_b_adr 32 TR02:12 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 2ea3 2ea3 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 2ea4 2ea4 ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2ea5 2ea5 seq_br_type 7 Unconditional Call; Flow C 0x32df seq_branch_adr 32df 0x32df 2ea6 2ea6 seq_br_type 2 Push (branch address); Flow J 0x2ea7 seq_branch_adr 2ea3 0x2ea3 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 2ea7 2ea7 fiu_mem_start 2 start-rd; Flow J cc=True 0x2ea9 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2ea9 0x2ea9 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2ea8 2ea8 seq_br_type 3 Unconditional Branch; Flow J 0x2eb6 seq_branch_adr 2eb6 0x2eb6 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 2ea9 2ea9 fiu_tivi_src 2 tar_fiu; Flow J 0x2eb6 ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2eb6 0x2eb6 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 14 ZEROS typ_b_adr 32 TR02:12 typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 2eaa 2eaa fiu_mem_start 2 start-rd ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2eab 2eab typ_a_adr 28 TR02:08 typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 2eac 2eac fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2ead 2ead fiu_load_var 1 hold_var; Flow C cc=False 0x2eaf fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2eaf 0x2eaf seq_random 02 ? typ_b_adr 04 GP04 val_a_adr 03 GP03 val_b_adr 04 GP04 2eae 2eae fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x2e89 fiu_mem_start 2 start-rd fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2e89 0x2e89 seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2eaf ; -------------------------------------------------------------------------------------- 2eaf ; Comes from: 2eaf ; 2e3d C False from color 0x0000 2eaf ; 2ead C False from color MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset 2eaf ; 2f3a C False from color 0x2f36 2eaf ; -------------------------------------------------------------------------------------- 2eaf 2eaf fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2eb0 2eb0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2eb1 2eb1 fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert ioc_adrbs 3 seq seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2eb2 2eb2 ioc_load_wdr 0 ; Flow R ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_b_adr 03 GP03 2eb3 2eb3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2eb4 2eb4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_random 41 Load_control_pred+? typ_c_adr 1d TR02:02 typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 2eb5 2eb5 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 2eb6 2eb6 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 2eb7 0x2eb7 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2eb7 2eb7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2eb8 2eb8 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 2eb9 2eb9 ioc_adrbs 2 typ ; Flow J 0x2eba seq_br_type 2 Push (branch address) seq_branch_adr 32d8 0x32d8 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP 2eba 2eba ioc_fiubs 2 typ ; Flow J 0x2fc8 seq_br_type 3 Unconditional Branch seq_branch_adr 2fc8 0x2fc8 seq_en_micro 0 seq_random 0f Load_control_top+? typ_csa_cntl 7 FINISH_POP_DOWN 2ebb 2ebb <halt> ; Flow R 2ebc ; -------------------------------------------------------------------------------------- 2ebc ; 0x0100 Execute Exception,Raise,>R 2ebc ; -------------------------------------------------------------------------------------- 2ebc MACRO_Execute_Exception,Raise,>R: 2ebc 2ebc dispatch_brk_class 8 ; Flow J cc=False 0x2ef0 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_mem_strt 2 CONTROL READ, AT (INNER - PARAMS) dispatch_uadr 2ebc fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 2ef0 0x2ef0 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 7 CONTROL PRED seq_random 15 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2ebd 2ebd fiu_mem_start 2 start-rd; Flow J cc=True 0x2edc ioc_adrbs 3 seq ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2edc 0x2edc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2ebe 2ebe fiu_len_fill_lit 4e zero-fill 0xe fiu_mem_start 4 continue fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 3b Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ebf 2ebf ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 0 typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2ec0 2ec0 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=False 0x2ed4 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ed4 0x2ed4 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2ec1 2ec1 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_int_reads 7 CONTROL PRED seq_random 4b ? typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2ec2 2ec2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2ec3 2ec3 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x2ed9 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ed9 0x2ed9 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ec4 2ec4 fiu_len_fill_lit 56 zero-fill 0x16; Flow J cc=False 0x2ed2 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ed2 0x2ed2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 2ec5 2ec5 typ_a_adr 01 GP01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 2ec6 2ec6 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x2ed2 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2ed2 0x2ed2 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ec7 2ec7 fiu_len_fill_lit 7b zero-fill 0x3b; Flow J cc=True 0x2ed2 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2ed2 0x2ed2 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 05 GP05 2ec8 2ec8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 65 Load_control_pred+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2ec9 2ec9 fiu_mem_start 2 start-rd; Flow J cc=True 0x2ecb ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2ecb 0x2ecb seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2eca 2eca seq_br_type 3 Unconditional Branch; Flow J 0x2ecc seq_branch_adr 2ecc 0x2ecc val_a_adr 26 VR05:06 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 2ecb 2ecb seq_br_type 3 Unconditional Branch; Flow J 0x2ecc seq_branch_adr 2ecc 0x2ecc val_a_adr 27 VR05:07 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 5 2ecc 2ecc fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2ecd 2ecd fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 03 GP03 2ece 2ece fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 2ecf 2ecf ioc_tvbs 3 fiu+fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 10 Load_break_mask+? typ_a_adr 21 TR10:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 2ed0 2ed0 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2ed1 0x2ed1 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2ed1 2ed1 seq_br_type 3 Unconditional Branch; Flow J 0x2eb5 seq_branch_adr 2eb5 0x2eb5 seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 59 ? val_b_adr 04 GP04 2ed2 2ed2 seq_br_type 2 Push (branch address); Flow J 0x2ed3 seq_branch_adr 2eca 0x2eca seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2ed3 2ed3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x2ecb fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2ecb 0x2ecb seq_int_reads 0 TYP VAL BUS seq_random 65 Load_control_pred+? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2ed4 2ed4 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4b ? typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2ed5 2ed5 ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2ed6 2ed6 fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2ed7 2ed7 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2ed8 2ed8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ec3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 2ec3 0x2ec3 typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 2ed9 2ed9 seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2eda 2eda fiu_mem_start 2 start-rd; Flow J cc=True 0x2ec2 seq_br_type 1 Branch True seq_branch_adr 2ec2 0x2ec2 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_rand 0 NO_OP 2edb 2edb seq_br_type 3 Unconditional Branch; Flow J 0x2ed2 seq_branch_adr 2ed2 0x2ed2 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2edc 2edc fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_a_adr 20 TR02:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 33 VR09:13 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 9 val_rand a PASS_B_HIGH 2edd 2edd fiu_len_fill_lit 41 zero-fill 0x1 fiu_mem_start 2 start-rd fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 38 TR05:18 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 01 GP01 2ede 2ede fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=#0x0 0x2edf fiu_load_tar 1 hold_tar fiu_offs_lit 1a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2edf 0x2edf seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 seq_random 03 ? typ_a_adr 2f TR11:0f typ_frame 11 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2edf ; -------------------------------------------------------------------------------------- 2edf ; Comes from: 2edf ; 2ede C #0x0 from color 0x0000 2edf ; -------------------------------------------------------------------------------------- 2edf 2edf fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ee3 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2ee3 0x2ee3 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 30 VR02:10 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 2ee0 2ee0 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2ee8 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2ee8 0x2ee8 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 30 VR02:10 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 2ee1 2ee1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2eed seq_br_type 3 Unconditional Branch seq_branch_adr 2eed 0x2eed seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 2ee2 2ee2 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2ee3 2ee3 fiu_load_var 1 hold_var; Flow C cc=True 0x2ee7 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ee7 0x2ee7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 28 TR12:08 typ_frame 12 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_frame 4 2ee4 2ee4 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x2ee6 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2ee6 0x2ee6 typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2ee5 2ee5 ioc_fiubs 0 fiu ; Flow C 0x3949 seq_br_type 7 Unconditional Call seq_branch_adr 3949 0x3949 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_b_adr 26 VR05:06 val_frame 5 2ee6 2ee6 ioc_fiubs 0 fiu ; Flow C 0x3949 seq_br_type 7 Unconditional Call seq_branch_adr 3949 0x3949 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_b_adr 27 VR05:07 val_frame 5 2ee7 2ee7 seq_br_type a Unconditional Return; Flow R val_a_adr 31 VR09:11 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 9 2ee8 2ee8 fiu_mem_start 4 continue typ_a_adr 31 TR08:11 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR 2ee9 2ee9 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2eea 2eea ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2eec seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2eec 0x2eec typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 2eeb 2eeb seq_br_type 7 Unconditional Call; Flow C 0x398d seq_branch_adr 398d 0x398d seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_b_adr 26 VR05:06 val_frame 5 2eec 2eec seq_br_type 7 Unconditional Call; Flow C 0x398d seq_branch_adr 398d 0x398d seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_b_adr 27 VR05:07 val_frame 5 2eed 2eed seq_b_timing 1 Latch Condition; Flow J cc=True 0x2eef seq_br_type 1 Branch True seq_branch_adr 2eef 0x2eef 2eee 2eee seq_br_type 3 Unconditional Branch; Flow J 0x2eb7 seq_branch_adr 2eb7 0x2eb7 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 26 VR05:06 val_frame 5 2eef 2eef seq_br_type 3 Unconditional Branch; Flow J 0x2eb7 seq_branch_adr 2eb7 0x2eb7 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? val_b_adr 27 VR05:07 val_frame 5 2ef0 2ef0 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2f17 seq_br_type 5 Call True seq_branch_adr 2f17 0x2f17 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2ef1 2ef1 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x2edc seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2edc 0x2edc seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 3d GP02 typ_c_lit 0 typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2ef2 2ef2 fiu_load_var 1 hold_var; Flow J cc=True 0x2f33 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f33 0x2f33 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2ef3 2ef3 ioc_load_wdr 0 ; Flow J cc=False 0x2f7c ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2f7c 0x2f7c seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2ef4 2ef4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2f92 seq_br_type 1 Branch True seq_branch_adr 2f92 0x2f92 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 38 GP07 typ_frame 2 2ef5 2ef5 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 4 2ef6 2ef6 seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 31 VR09:11 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 03 GP03 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 9 2ef7 2ef7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 14 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 2ef8 2ef8 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 06 GP06 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 2ef9 2ef9 fiu_len_fill_lit 4e zero-fill 0xe fiu_mem_start 4 continue fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 3b Load_save_offset+? typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 06 GP06 typ_c_adr 38 GP07 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1f typ_mar_cntl 6 INCREMENT_MAR typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2efa 2efa fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_csa_cntl 1 START_POP_DOWN typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS val_c_adr 38 GP07 val_c_source 0 FIU_BUS 2efb 2efb fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=False 0x2f0d fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f0d 0x2f0d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2efc 2efc fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_int_reads 7 CONTROL PRED seq_random 4b ? typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2efd 2efd fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 07 GP07 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2efe 2efe fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=False 0x2f12 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 2f12 0x2f12 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2eff 2eff fiu_len_fill_lit 56 zero-fill 0x16; Flow J cc=False 0x2f0a fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f0a 0x2f0a seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 05 GP05 typ_c_adr 3e GP01 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 2f00 2f00 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2f0a seq_br_type 1 Branch True seq_branch_adr 2f0a 0x2f0a typ_a_adr 01 GP01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 2f01 2f01 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x2f0b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f0b 0x2f0b seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 1d TR02:02 typ_frame 2 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f02 2f02 fiu_len_fill_lit 7b zero-fill 0x3b; Flow J cc=True 0x2f0b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f0b 0x2f0b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 05 GP05 2f03 2f03 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 65 Load_control_pred+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_b_adr 30 TR09:10 typ_csa_cntl 1 START_POP_DOWN typ_frame 9 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2f04 2f04 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 05 GP05 typ_c_adr 37 GP08 typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 07 GP07 val_c_adr 37 GP08 val_c_mux_sel 2 ALU 2f05 2f05 fiu_mem_start 2 start-rd; Flow J cc=True 0x2f07 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2f07 0x2f07 typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2f06 2f06 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x2f08 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 2f08 0x2f08 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 0 PASS_A val_b_adr 26 VR05:06 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 2f07 2f07 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x2f08 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_br_type 3 Unconditional Branch seq_branch_adr 2f08 0x2f08 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 0 PASS_A val_b_adr 27 VR05:07 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 2f08 2f08 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 07 GP07 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 2f09 2f09 ioc_adrbs 1 val ; Flow J 0x2f3c ioc_fiubs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2f3c 0x2f3c seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 36 GP09 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 2f0a 2f0a seq_br_type 3 Unconditional Branch; Flow J 0x2f0b seq_branch_adr 2f0b 0x2f0b typ_c_adr 1d TR02:02 typ_frame 2 2f0b 2f0b fiu_load_var 1 hold_var; Flow J 0x2f0c fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2f06 0x2f06 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 30 TR09:10 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 9 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2f0c 2f0c fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x2f07 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 2f07 0x2f07 seq_int_reads 0 TYP VAL BUS seq_random 65 Load_control_pred+? typ_a_adr 05 GP05 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 32 VR02:12 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 2f0d 2f0d fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4b ? typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 2f0e 2f0e ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 07 GP07 typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 2f0f 2f0f fiu_len_fill_lit 52 zero-fill 0x12 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 2f10 2f10 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 2f11 2f11 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2efe fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 2efe 0x2efe val_b_adr 22 VR02:02 val_frame 2 2f12 2f12 seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 2f13 2f13 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x2f15 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type 0 Branch False seq_branch_adr 2f15 0x2f15 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_b_adr 22 VR02:02 val_frame 2 2f14 2f14 fiu_mem_start 2 start-rd; Flow J 0x2efd seq_br_type 3 Unconditional Branch seq_branch_adr 2efd 0x2efd seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 2f15 2f15 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 38 TR07:18 typ_frame 7 2f16 2f16 ioc_tvbs 1 typ+fiu; Flow J 0x2f0b seq_br_type 3 Unconditional Branch seq_branch_adr 2f0b 0x2f0b seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_c_adr 1d TR02:02 typ_frame 2 2f17 ; -------------------------------------------------------------------------------------- 2f17 ; Comes from: 2f17 ; 2ef0 C True from color 0x0000 2f17 ; -------------------------------------------------------------------------------------- 2f17 2f17 fiu_mem_start 2 start-rd; Flow C 0x339b ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 339b 0x339b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2f18 2f18 fiu_mem_start 2 start-rd; Flow C 0x3377 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 3377 0x3377 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2f19 2f19 fiu_load_var 1 hold_var; Flow J cc=True 0x2f1a ; Flow J cc=#0x0 0x2f1b fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 2f1b 0x2f1b seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 2f1a 2f1a fiu_len_fill_lit 43 zero-fill 0x3; Flow R fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_br_type a Unconditional Return seq_int_reads 7 CONTROL PRED seq_random 15 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2f1b 2f1b seq_br_type 3 Unconditional Branch; Flow J 0x2f23 seq_branch_adr 2f23 0x2f23 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2f1c 2f1c seq_br_type 3 Unconditional Branch; Flow J 0x2f23 seq_branch_adr 2f23 0x2f23 typ_a_adr 14 ZEROS typ_alu_func 10 NOT_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU 2f1d 2f1d seq_br_type 3 Unconditional Branch; Flow J 0x2f1f seq_branch_adr 2f1f 0x2f1f seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 2f1e 2f1e seq_br_type 3 Unconditional Branch; Flow J 0x2f1f seq_branch_adr 2f1f 0x2f1f seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 2f1f 2f1f seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 2f20 2f20 seq_b_timing 1 Latch Condition; Flow J cc=True 0x2f1a seq_br_type 1 Branch True seq_branch_adr 2f1a 0x2f1a 2f21 2f21 seq_br_type 2 Push (branch address); Flow J 0x2f22 seq_branch_adr 2f19 0x2f19 2f22 2f22 fiu_load_oreg 1 hold_oreg; Flow J 0x338c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 338c 0x338c seq_int_reads 6 CONTROL TOP typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 2f23 2f23 fiu_mem_start 2 start-rd; Flow C 0x34f0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f0 0x34f0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 2f24 2f24 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x2f32 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2f32 0x2f32 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 2f25 2f25 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 33 VR09:13 val_frame 9 2f26 2f26 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x2f32 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f32 0x2f32 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 2c TR02:0c typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 2f27 2f27 fiu_len_fill_lit 46 zero-fill 0x6; Flow J cc=True 0x2f32 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f32 0x2f32 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR05:01 val_frame 5 2f28 2f28 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2f32 seq_br_type 1 Branch True seq_branch_adr 2f32 0x2f32 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 25 TR08:05 typ_frame 8 2f29 2f29 fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x2f2f ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2f2f 0x2f2f typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 02 GP02 2f2a 2f2a ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 2f2b 2f2b seq_br_type 2 Push (branch address); Flow J 0x2f2c seq_branch_adr 0282 0x0282 2f2c 2f2c fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 5 seq+seq typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 38 VR05:18 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 5 val_rand a PASS_B_HIGH 2f2d 2f2d ioc_load_wdr 0 ; Flow C 0x6bd ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 06bd 0x06bd typ_b_adr 2e TR02:0e typ_frame 2 2f2e 2f2e seq_br_type 3 Unconditional Branch; Flow J 0x2f1f seq_branch_adr 2f1f 0x2f1f seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 seq_random 06 Pop_stack+? typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 2f2f 2f2f fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 1a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 2f TR11:0f typ_frame 11 2f30 2f30 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 24 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 02 GP02 2f31 2f31 ioc_load_wdr 0 ; Flow C 0x6bd ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 06bd 0x06bd typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 2f32 2f32 seq_br_type 3 Unconditional Branch; Flow J 0x2f1f seq_branch_adr 2f1f 0x2f1f seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 2f33 2f33 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x2f36 seq_br_type 5 Call True seq_branch_adr 2f36 0x2f36 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 2f34 2f34 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_load_wdr 0 seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL 2f35 2f35 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x2ebf fiu_mem_start 4 continue fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 2ebf 0x2ebf seq_int_reads 5 RESOLVE RAM seq_random 3b Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f36 ; -------------------------------------------------------------------------------------- 2f36 ; Comes from: 2f36 ; 2f33 C True from color 0x0000 2f36 ; -------------------------------------------------------------------------------------- 2f36 2f36 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_a_adr 28 TR02:08 typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f37 2f37 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 2f38 2f38 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2f39 2f39 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 2f3a 2f3a fiu_load_var 1 hold_var; Flow C cc=False 0x2eaf fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 2eaf 0x2eaf seq_random 02 ? typ_b_adr 04 GP04 val_a_adr 03 GP03 val_b_adr 04 GP04 2f3b 2f3b seq_br_type a Unconditional Return; Flow R 2f3c 2f3c ioc_fiubs 1 val ; Flow J cc=True 0x2f3e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f3e 0x2f3e seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2f3d 2f3d fiu_mem_start 2 start-rd; Flow C 0x34f0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f0 0x34f0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 0 PASS_A 2f3e 2f3e fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f3f 2f3f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 36 TR02:16 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 2f40 2f40 fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=False 0x2f70 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f70 0x2f70 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 2e VR02:0e val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f41 2f41 fiu_len_fill_lit 5a zero-fill 0x1a fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_c_adr 3e GP01 2f42 2f42 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x2f43 fiu_load_tar 1 hold_tar fiu_offs_lit 2a fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 2 Push (branch address) seq_branch_adr 2eb5 0x2eb5 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 2f43 2f43 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2f67 fiu_mem_start 6 start_rd_if_false fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f67 0x2f67 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 2f44 2f44 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2f45 2f45 fiu_len_fill_lit 52 zero-fill 0x12; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 54 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1f typ_rand c WRITE_OUTER_FRAME val_a_adr 03 GP03 2f46 2f46 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_alu_func 6 A_MINUS_B typ_b_adr 21 TR10:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 2f47 2f47 ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 02 GP02 2f48 2f48 fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x2f79 fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f79 0x2f79 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f49 2f49 fiu_len_fill_lit 56 zero-fill 0x16; Flow J cc=False 0x2f5b fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2f5b 0x2f5b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 2f4a 2f4a fiu_len_fill_lit 4f zero-fill 0xf fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 05 GP05 typ_alu_func 1d A_AND_NOT_B typ_b_adr 39 TR02:19 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f4b 2f4b ioc_adrbs 1 val ; Flow J cc=False 0x2f5b seq_br_type 0 Branch False seq_branch_adr 2f5b 0x2f5b seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 04 GP04 typ_alu_func 6 A_MINUS_B typ_b_adr 05 GP05 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 2f4c 2f4c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2f5b fiu_load_mdr 1 hold_mdr fiu_offs_lit 44 fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f5b 0x2f5b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 2f4d 2f4d fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x332e fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 6d fiu_op_sel 3 insert fiu_tivi_src 9 type_val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 01 GP01 2f4e 2f4e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_a_adr 03 GP03 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 2d VR09:0d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 9 2f4f 2f4f fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x2f60 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 25 fiu_op_sel 3 insert ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 2f60 0x2f60 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f50 2f50 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 20 VR02:00 val_frame 2 2f51 2f51 fiu_len_fill_lit 43 zero-fill 0x3 fiu_mem_start 3 start-wr fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2f52 2f52 seq_br_type 1 Branch True; Flow J cc=True 0x2f75 seq_branch_adr 2f75 0x2f75 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 20 VR02:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 val_frame 2 2f53 2f53 <default> 2f54 2f54 seq_br_type 7 Unconditional Call; Flow C 0x33a3 seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 2f55 2f55 fiu_mem_start 2 start-rd; Flow C 0x34dc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34dc 0x34dc typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 2f56 2f56 ioc_adrbs 2 typ ; Flow C 0x6b7 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2f57 2f57 fiu_mem_start 2 start-rd; Flow C 0x33c4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 33c4 0x33c4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f58 2f58 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 2f59 0x2f59 seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f59 2f59 seq_br_type 7 Unconditional Call; Flow C 0x33ec seq_branch_adr 33ec 0x33ec 2f5a 2f5a fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 0210 0x0210 seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f5b 2f5b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 2f5c 2f5c fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_op_sel 3 insert fiu_tivi_src 9 type_val typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_b_adr 01 GP01 2f5d 2f5d ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 2d VR09:0d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 9 2f5e 2f5e fiu_mem_start 7 start_wr_if_true; Flow J cc=True 0x2f50 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 2f50 0x2f50 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2f5f 2f5f seq_br_type 3 Unconditional Branch; Flow J 0x2f60 seq_branch_adr 2f60 0x2f60 2f60 2f60 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 20 TR08:00 typ_c_adr 39 GP06 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 39 GP06 val_frame 4 val_rand 9 PASS_A_HIGH 2f61 2f61 ioc_load_wdr 0 ; Flow J cc=True 0x2f64 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f64 0x2f64 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 2f62 2f62 fiu_load_mdr 1 hold_mdr; Flow J cc=True 0x2f66 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f66 0x2f66 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 37 TR06:17 typ_frame 6 val_a_adr 2e VR06:0e val_alu_func 1d A_AND_NOT_B val_b_adr 06 GP06 val_frame 6 2f63 2f63 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2f66 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 70 fiu_op_sel 3 insert ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2f66 0x2f66 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 2f64 2f64 fiu_load_mdr 1 hold_mdr; Flow J cc=True 0x2f66 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f66 0x2f66 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 25 TR05:05 typ_frame 5 val_a_adr 23 VR06:03 val_alu_func 1d A_AND_NOT_B val_b_adr 06 GP06 val_frame 6 2f65 2f65 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2f66 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 70 fiu_op_sel 3 insert ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 2f66 0x2f66 typ_a_adr 06 GP06 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 2f66 2f66 ioc_fiubs 1 val ; Flow J 0x2f51 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2f51 0x2f51 typ_b_adr 06 GP06 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 20 VR02:00 val_frame 2 2f67 2f67 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_tar 1 hold_tar fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_b_adr 01 GP01 typ_c_adr 30 GP0f 2f68 2f68 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x2f6c ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f6c 0x2f6c seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 2f69 2f69 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2f6a 2f6a fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x2f75 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2f75 0x2f75 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER 2f6b 2f6b ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2f6c 2f6c fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 3a VR13:1a val_frame 13 val_rand 9 PASS_A_HIGH 2f6d 2f6d fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_c_adr 3c GP03 val_c_source 0 FIU_BUS 2f6e 2f6e fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER 2f6f 2f6f ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 2f70 2f70 fiu_load_var 1 hold_var fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2f71 2f71 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2f72 0x2f72 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 2f72 2f72 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 2f73 2f73 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 2f74 2f74 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x2f41 fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2f41 0x2f41 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 2e VR02:0e val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f75 ; -------------------------------------------------------------------------------------- 2f75 ; Comes from: 2f75 ; 2f6a C True from color 0x2ef9 2f75 ; -------------------------------------------------------------------------------------- 2f75 2f75 fiu_mem_start 2 start-rd; Flow C 0x34de ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34de 0x34de typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR11:10 val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 11 val_rand a PASS_B_HIGH 2f76 2f76 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 02 GP02 val_frame 4 val_rand a PASS_B_HIGH 2f77 2f77 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 2f78 2f78 ioc_load_wdr 0 ; Flow J 0x6b7 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 06b7 0x06b7 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 2f79 2f79 seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2f7a 2f7a fiu_mem_start 2 start-rd; Flow J cc=True 0x2f47 seq_br_type 1 Branch True seq_branch_adr 2f47 0x2f47 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2f7b 2f7b ioc_fiubs 2 typ ; Flow J 0x2f5b seq_br_type 3 Unconditional Branch seq_branch_adr 2f5b 0x2f5b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 38 TR07:18 typ_frame 7 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f7c 2f7c fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x2f7d fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2f96 0x2f96 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? typ_a_adr 22 TR02:02 typ_frame 2 2f7d 2f7d fiu_mem_start 2 start-rd; Flow J cc=True 0x339b ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 339b 0x339b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2f7e 2f7e seq_br_type 7 Unconditional Call; Flow C 0x32df seq_branch_adr 32df 0x32df 2f7f 2f7f fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x2f80 fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 2f96 0x2f96 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? typ_a_adr 22 TR02:02 typ_frame 2 2f80 2f80 fiu_mem_start 2 start-rd; Flow J cc=True 0x339b ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 339b 0x339b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 2f81 2f81 seq_br_type 4 Call False; Flow C cc=False 0x32df seq_branch_adr 32df 0x32df seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2f82 2f82 fiu_mem_start 2 start-rd; Flow C 0x339b ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 339b 0x339b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 2f83 2f83 seq_b_timing 3 Late Condition, Hint False; Flow C 0x32d7 seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 5 CHECK_CLASS_B_LIT 2f84 2f84 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x2f96 seq_br_type 0 Branch False seq_branch_adr 2f96 0x2f96 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_b_adr 10 TOP 2f85 2f85 seq_br_type 3 Unconditional Branch; Flow J 0x2f96 seq_branch_adr 2f96 0x2f96 2f86 2f86 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f87 2f87 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2f8f seq_br_type 1 Branch True seq_branch_adr 2f8f 0x2f8f seq_cond_sel 67 REFRESH_MACRO_EVENT 2f88 2f88 fiu_mem_start 2 start-rd; Flow J cc=True 0x2f8d ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f8d 0x2f8d seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 22 VR09:02 val_frame 9 val_rand 9 PASS_A_HIGH 2f89 2f89 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 2f8a 2f8a fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand 9 PASS_A_HIGH 2f8b 2f8b ioc_fiubs 0 fiu ; Flow C cc=True 0x32d9 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 2f8c 2f8c seq_b_timing 1 Latch Condition; Flow J cc=False 0x2f86 seq_br_type 0 Branch False seq_branch_adr 2f86 0x2f86 2f8d 2f8d fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 06 GP06 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2f8e 2f8e seq_br_type 3 Unconditional Branch; Flow J 0x2f96 seq_branch_adr 2f96 0x2f96 2f8f 2f8f seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 2f90 2f90 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 2f91 2f91 seq_br_type 3 Unconditional Branch; Flow J 0x2f88 seq_branch_adr 2f88 0x2f88 2f92 2f92 seq_br_type 2 Push (branch address); Flow J 0x2f93 seq_branch_adr 2f96 0x2f96 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? 2f93 2f93 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x339b ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 339b 0x339b seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f94 2f94 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2f95 2f95 fiu_mem_start 2 start-rd; Flow C 0x339b ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 339b 0x339b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2f96 2f96 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x2f9b seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f9b 0x2f9b seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 2b TR02:0b typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 2f97 2f97 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 23 VR05:03 val_frame 5 2f98 2f98 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x2f99 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 2f95 0x2f95 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 2f99 2f99 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x2f9a fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f9a 2f9a ioc_tvbs 1 typ+fiu; Flow J 0x33a3 seq_br_type 3 Unconditional Branch seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 2f9b 2f9b fiu_mem_start 2 start-rd; Flow C 0x3377 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3377 0x3377 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 2f9c 2f9c fiu_load_var 1 hold_var; Flow C cc=#0x0 0x2fa2 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2fa2 0x2fa2 seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2f9d 2f9d ioc_fiubs 2 typ ; Flow J 0x2f9e seq_br_type 3 Unconditional Branch seq_branch_adr 2f9e 0x2f9e val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2f9e 2f9e fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2fab fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2fab 0x2fab seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 2f9f 2f9f fiu_load_oreg 1 hold_oreg; Flow C 0x338c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 338c 0x338c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 23 VR02:03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 2fa0 2fa0 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x2fa2 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 2fa2 0x2fa2 seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2fa1 2fa1 ioc_fiubs 2 typ ; Flow J 0x2f9e seq_br_type 3 Unconditional Branch seq_branch_adr 2f9e 0x2f9e val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2fa2 2fa2 seq_br_type 3 Unconditional Branch; Flow J 0x2fa8 seq_branch_adr 2fa8 0x2fa8 2fa3 2fa3 seq_br_type 3 Unconditional Branch; Flow J 0x2fa8 seq_branch_adr 2fa8 0x2fa8 2fa4 2fa4 fiu_mem_start 2 start-rd; Flow J 0x3487 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3487 0x3487 typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 2fa5 2fa5 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x2fae fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 2fae 0x2fae seq_cond_sel 67 REFRESH_MACRO_EVENT seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 2fa6 2fa6 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 2fa7 2fa7 seq_br_type 3 Unconditional Branch; Flow J 0x2fae seq_branch_adr 2fae 0x2fae 2fa8 2fa8 seq_br_type 2 Push (branch address); Flow J 0x2fa9 seq_branch_adr 2f9e 0x2f9e 2fa9 2fa9 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 5 seq+seq 2faa 2faa ioc_fiubs 0 fiu ; Flow J 0x3a10 seq_br_type 3 Unconditional Branch seq_branch_adr 3a10 0x3a10 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2fab 2fab fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 22 TR02:02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3c TR02:1c typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 2fac 2fac fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL 2fad 2fad ioc_load_wdr 0 ; Flow J 0x2eb7 seq_br_type 3 Unconditional Branch seq_branch_adr 2eb7 0x2eb7 typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 2fae 2fae fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2faf 2faf ioc_fiubs 2 typ val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2fb0 2fb0 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2fb1 2fb1 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 2fb2 2fb2 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x2fbb seq_br_type 1 Branch True seq_branch_adr 2fbb 0x2fbb seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 24 VR02:04 val_frame 2 2fb3 2fb3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_frame 2 2fb4 2fb4 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x2fb6 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 2fb6 0x2fb6 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 2fb5 2fb5 fiu_fill_mode_src 0 ; Flow J 0x2fb8 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2fb8 0x2fb8 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2fb6 2fb6 fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 2fb7 2fb7 fiu_fill_mode_src 0 ; Flow J 0x2fb8 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 2fb8 0x2fb8 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2fb8 2fb8 ioc_fiubs 2 typ ; Flow J 0x2fb9 seq_br_type 2 Push (branch address) seq_branch_adr 2fb2 0x2fb2 val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 2fb9 2fb9 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq val_a_adr 23 VR02:03 val_frame 2 2fba 2fba ioc_fiubs 0 fiu ; Flow J 0x3a10 seq_br_type 3 Unconditional Branch seq_branch_adr 3a10 0x3a10 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 2fbb 2fbb seq_br_type 3 Unconditional Branch; Flow J 0x2f9e seq_branch_adr 2f9e 0x2f9e typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 2fbc 2fbc fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2fbd 2fbd fiu_mem_start 5 start_rd_if_true; Flow R cc=True ; Flow J cc=False 0x32df ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 32df 0x32df seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 2fbe ; -------------------------------------------------------------------------------------- 2fbe ; Comes from: 2fbe ; 2e87 C False from color MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset 2fbe ; -------------------------------------------------------------------------------------- 2fbe 2fbe fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 2fbf 2fbf seq_b_timing 0 Early Condition; Flow R cc=True ; Flow J cc=False 0x32df seq_br_type 8 Return True seq_branch_adr 32df 0x32df seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) 2fc0 ; -------------------------------------------------------------------------------------- 2fc0 ; 0x4100-0x41ff End_Rendezvous >R,parmcnt 2fc0 ; -------------------------------------------------------------------------------------- 2fc0 MACRO_End_Rendezvous_>R,parmcnt: 2fc0 2fc0 dispatch_brk_class 5 ; Flow C 0x33af dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_uadr 2fc0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af seq_int_reads 5 RESOLVE RAM typ_a_adr 2f TR05:0f typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 2e VR05:0e val_frame 5 2fc1 2fc1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_alu_func 1 A_PLUS_B typ_b_adr 2b TR02:0b typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 36 VR05:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 2fc2 2fc2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x2f92 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 2f92 0x2f92 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 2 2fc3 2fc3 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x2fc6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 31 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 2fc6 0x2fc6 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 2fc4 2fc4 ioc_fiubs 2 typ ; Flow C cc=False 0x32df ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 32df 0x32df seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_source 0 FIU_BUS 2fc5 2fc5 ioc_adrbs 1 val ; Flow J 0x3762 seq_br_type 3 Unconditional Branch seq_branch_adr 3762 0x3762 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 2fc6 2fc6 seq_b_timing 3 Late Condition, Hint False; Flow C cc=False 0x32df seq_br_type 4 Call False seq_branch_adr 32df 0x32df seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 2fc7 2fc7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 2fc8 2fc8 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? 2fc9 2fc9 seq_random 6a ? 2fca 2fca seq_lex_adr 3 seq_random 6a ? 2fcb 2fcb seq_br_type a Unconditional Return; Flow R seq_lex_adr 2 seq_random 0b ? 2fcc ; -------------------------------------------------------------------------------------- 2fcc ; 0x027f Execute Discrete,Equal 2fcc ; -------------------------------------------------------------------------------------- 2fcc MACRO_Execute_Discrete,Equal: 2fcc 2fcc dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fcc fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fcd 2fcd <halt> ; Flow R 2fce ; -------------------------------------------------------------------------------------- 2fce ; 0x0f00-0x0fff Execute_Immediate Equal,uimmediate 2fce ; -------------------------------------------------------------------------------------- 2fce MACRO_Execute_Immediate_Equal,uimmediate: 2fce 2fce dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_uadr 2fce fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 6 IMMEDIATE_OP 2fcf 2fcf <halt> ; Flow R 2fd0 ; -------------------------------------------------------------------------------------- 2fd0 ; 0x027e Execute Discrete,Not_Equal 2fd0 ; -------------------------------------------------------------------------------------- 2fd0 MACRO_Execute_Discrete,Not_Equal: 2fd0 2fd0 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fd0 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fd1 2fd1 <halt> ; Flow R 2fd2 ; -------------------------------------------------------------------------------------- 2fd2 ; 0x0e00-0x0eff Execute_Immediate Not_Equal,uimmediate 2fd2 ; -------------------------------------------------------------------------------------- 2fd2 MACRO_Execute_Immediate_Not_Equal,uimmediate: 2fd2 2fd2 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_uadr 2fd2 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 6 IMMEDIATE_OP 2fd3 2fd3 <halt> ; Flow R 2fd4 ; -------------------------------------------------------------------------------------- 2fd4 ; 0x027d Execute Discrete,Greater 2fd4 ; -------------------------------------------------------------------------------------- 2fd4 MACRO_Execute_Discrete,Greater: 2fd4 2fd4 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fd4 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fd5 2fd5 <halt> ; Flow R 2fd6 ; -------------------------------------------------------------------------------------- 2fd6 ; 0x027c Execute Discrete,Less 2fd6 ; -------------------------------------------------------------------------------------- 2fd6 MACRO_Execute_Discrete,Less: 2fd6 2fd6 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fd6 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fd7 2fd7 <halt> ; Flow R 2fd8 ; -------------------------------------------------------------------------------------- 2fd8 ; 0x0d00-0x0dff Execute_Immediate Less,uimmediate 2fd8 ; -------------------------------------------------------------------------------------- 2fd8 MACRO_Execute_Immediate_Less,uimmediate: 2fd8 2fd8 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_uadr 2fd8 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_frame 2 val_rand 6 IMMEDIATE_OP 2fd9 2fd9 <halt> ; Flow R 2fda ; -------------------------------------------------------------------------------------- 2fda ; 0x027b Execute Discrete,Greater_Equal 2fda ; -------------------------------------------------------------------------------------- 2fda MACRO_Execute_Discrete,Greater_Equal: 2fda 2fda dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fda fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fdb 2fdb <halt> ; Flow R 2fdc ; -------------------------------------------------------------------------------------- 2fdc ; 0x0c00-0x0cff Execute_Immediate Greater_Equal,uimmediate 2fdc ; -------------------------------------------------------------------------------------- 2fdc MACRO_Execute_Immediate_Greater_Equal,uimmediate: 2fdc 2fdc dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_uadr 2fdc ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 2fdd 2fdd fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fde ; -------------------------------------------------------------------------------------- 2fde ; 0x027a Execute Discrete,Less_Equal 2fde ; -------------------------------------------------------------------------------------- 2fde MACRO_Execute_Discrete,Less_Equal: 2fde 2fde dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fde fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 2fdf 2fdf <halt> ; Flow R 2fe0 ; -------------------------------------------------------------------------------------- 2fe0 ; 0x0279 Execute Discrete,And 2fe0 ; -------------------------------------------------------------------------------------- 2fe0 MACRO_Execute_Discrete,And: 2fe0 2fe0 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fe0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fe1 2fe1 <halt> ; Flow R 2fe2 ; -------------------------------------------------------------------------------------- 2fe2 ; 0x0278 Execute Discrete,Or 2fe2 ; -------------------------------------------------------------------------------------- 2fe2 MACRO_Execute_Discrete,Or: 2fe2 2fe2 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fe2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fe3 2fe3 <halt> ; Flow R 2fe4 ; -------------------------------------------------------------------------------------- 2fe4 ; 0x0277 Execute Discrete,Xor 2fe4 ; -------------------------------------------------------------------------------------- 2fe4 MACRO_Execute_Discrete,Xor: 2fe4 2fe4 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fe4 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fe5 2fe5 <halt> ; Flow R 2fe6 ; -------------------------------------------------------------------------------------- 2fe6 ; 0x0276 Execute Discrete,Complement 2fe6 ; -------------------------------------------------------------------------------------- 2fe6 MACRO_Execute_Discrete,Complement: 2fe6 2fe6 dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2fe6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 10 NOT_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 2fe7 2fe7 <halt> ; Flow R 2fe8 ; -------------------------------------------------------------------------------------- 2fe8 ; 0x0275 Execute Discrete,Unary_Minus 2fe8 ; -------------------------------------------------------------------------------------- 2fe8 MACRO_Execute_Discrete,Unary_Minus: 2fe8 2fe8 dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2fe8 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fe9 0x2fe9 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_random 04 Load_save_offset+? typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 2fe9 2fe9 seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 seq_en_micro 0 seq_random 02 ? 2fea ; -------------------------------------------------------------------------------------- 2fea ; 0x0274 Execute Discrete,Absolute_Value 2fea ; -------------------------------------------------------------------------------------- 2fea MACRO_Execute_Discrete,Absolute_Value: 2fea 2fea dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2fea seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A 2feb 2feb fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x2fe9 ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fe9 0x2fe9 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU 2fec ; -------------------------------------------------------------------------------------- 2fec ; 0x0273 Execute Discrete,Plus 2fec ; -------------------------------------------------------------------------------------- 2fec MACRO_Execute_Discrete,Plus: 2fec 2fec dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2fec fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fed 0x2fed seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2fed 2fed seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 seq_en_micro 0 seq_random 02 ? 2fee ; -------------------------------------------------------------------------------------- 2fee ; 0x0a00-0x0a7f Execute_Immediate Plus,s8 2fee ; -------------------------------------------------------------------------------------- 2fee MACRO_Execute_Immediate_Plus,s8: 2fee 2fee dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 1 dispatch_uadr 2fee fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fef 0x2fef seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 2fef 2fef seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 seq_en_micro 0 seq_random 02 ? 2ff0 ; -------------------------------------------------------------------------------------- 2ff0 ; 0x0272 Execute Discrete,Minus 2ff0 ; -------------------------------------------------------------------------------------- 2ff0 MACRO_Execute_Discrete,Minus: 2ff0 2ff0 dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2ff0 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2ff1 0x2ff1 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2ff1 2ff1 seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 seq_en_micro 0 seq_random 02 ? 2ff2 ; -------------------------------------------------------------------------------------- 2ff2 ; 0x0a80-0x0aff Execute_Immediate Plus,s8 2ff2 ; -------------------------------------------------------------------------------------- 2ff2 MACRO_Execute_Immediate_Plus,s8: 2ff2 2ff2 dispatch_brk_class 8 ; Flow R cc=False dispatch_csa_valid 1 dispatch_uadr 2ff2 fiu_mem_start 2 start-rd ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2ff3 0x2ff3 seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 30 VR02:10 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 2ff3 2ff3 seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 seq_en_micro 0 seq_random 02 ? 2ff4 ; -------------------------------------------------------------------------------------- 2ff4 ; 0x026c Execute Discrete,Minimum 2ff4 ; -------------------------------------------------------------------------------------- 2ff4 MACRO_Execute_Discrete,Minimum: 2ff4 2ff4 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2ff4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 2ff5 2ff5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2ff6 ; -------------------------------------------------------------------------------------- 2ff6 ; 0x026b Execute Discrete,Maximum 2ff6 ; -------------------------------------------------------------------------------------- 2ff6 MACRO_Execute_Discrete,Maximum: 2ff6 2ff6 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 2ff6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 2ff7 2ff7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 2ff8 ; -------------------------------------------------------------------------------------- 2ff8 ; 0x026a Execute Discrete,First 2ff8 ; -------------------------------------------------------------------------------------- 2ff8 MACRO_Execute_Discrete,First: 2ff8 2ff8 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2ff8 dispatch_uses_tos 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 2ff9 2ff9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2ffa ; -------------------------------------------------------------------------------------- 2ffa ; 0x0269 Execute Discrete,Last 2ffa ; -------------------------------------------------------------------------------------- 2ffa MACRO_Execute_Discrete,Last: 2ffa 2ffa dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 2ffa dispatch_uses_tos 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 2ffb 2ffb fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 2ffc ; -------------------------------------------------------------------------------------- 2ffc ; 0x0268 Execute Discrete,Successor 2ffc ; -------------------------------------------------------------------------------------- 2ffc MACRO_Execute_Discrete,Successor: 2ffc 2ffc dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 2ffc fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 2ffd 2ffd ioc_fiubs 1 val ; Flow C 0x329e ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 2ffe 2ffe fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 2fff 0x2fff seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 2fff 2fff fiu_mem_start 2 start-rd; Flow J 0x3000 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3000 0x3000 seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3000 3000 <default> 3001 3001 fiu_mem_start 2 start-rd; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 3002 3002 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3003 0x3003 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3003 3003 seq_br_type 7 Unconditional Call; Flow C 0x329e seq_branch_adr 329e 0x329e seq_en_micro 0 seq_random 02 ? 3004 ; -------------------------------------------------------------------------------------- 3004 ; 0x0267 Execute Discrete,Predecessor 3004 ; -------------------------------------------------------------------------------------- 3004 MACRO_Execute_Discrete,Predecessor: 3004 3004 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3004 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 3005 3005 ioc_fiubs 1 val ; Flow C 0x329e ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1c DEC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3006 3006 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3007 0x3007 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 3007 3007 fiu_mem_start 2 start-rd; Flow J 0x3000 ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3000 0x3000 seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3008 ; -------------------------------------------------------------------------------------- 3008 ; 0x0b00-0x0bff Execute_Immediate Case_Compare,uimmediate 3008 ; -------------------------------------------------------------------------------------- 3008 MACRO_Execute_Immediate_Case_Compare,uimmediate: 3008 3008 dispatch_brk_class 8 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_uadr 3008 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS val_frame 2 val_rand 6 IMMEDIATE_OP 3009 3009 fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 300a ; -------------------------------------------------------------------------------------- 300a ; 0x0249 Execute Discrete,Case_In_Range 300a ; -------------------------------------------------------------------------------------- 300a MACRO_Execute_Discrete,Case_In_Range: 300a 300a dispatch_brk_class 8 ; Flow J cc=True 0x3009 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 300a seq_br_type 1 Branch True seq_branch_adr 3009 0x3009 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP 300b 300b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_c_adr 2f TOP val_c_mux_sel 2 ALU 300c ; -------------------------------------------------------------------------------------- 300c ; 0x0266 Execute Discrete,Bounds 300c ; -------------------------------------------------------------------------------------- 300c MACRO_Execute_Discrete,Bounds: 300c 300c dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 300c dispatch_uses_tos 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 300d 300d ioc_tvbs c mem+mem+csa+dummy seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 300e 300e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 300f 300f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 3010 ; -------------------------------------------------------------------------------------- 3010 ; 0x0265 Execute Discrete,Reverse_Bounds 3010 ; -------------------------------------------------------------------------------------- 3010 MACRO_Execute_Discrete,Reverse_Bounds: 3010 3010 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 3010 dispatch_uses_tos 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 3011 3011 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x300f seq_br_type 3 Unconditional Branch seq_branch_adr 300f 0x300f seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 3012 ; -------------------------------------------------------------------------------------- 3012 ; 0x0264 Execute Discrete,Below_Bound 3012 ; -------------------------------------------------------------------------------------- 3012 MACRO_Execute_Discrete,Below_Bound: 3012 3012 dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3012 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 3013 0x3013 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 3013 3013 seq_br_type 3 Unconditional Branch; Flow J 0x3015 seq_branch_adr 3015 0x3015 seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA 3014 ; -------------------------------------------------------------------------------------- 3014 ; 0x0263 Execute Discrete,Above_Bound 3014 ; -------------------------------------------------------------------------------------- 3014 MACRO_Execute_Discrete,Above_Bound: 3014 3014 dispatch_brk_class 8 ; Flow R cc=True ; Flow J cc=False 0x3013 dispatch_csa_free 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3014 fiu_mem_start 2 start-rd fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 3013 0x3013 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 3015 3015 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 3016 ; -------------------------------------------------------------------------------------- 3016 ; 0x0262 Execute Discrete,In_Range 3016 ; -------------------------------------------------------------------------------------- 3016 MACRO_Execute_Discrete,In_Range: 3016 3016 dispatch_brk_class 8 ; Flow J cc=True 0x2fda dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 3016 seq_br_type 1 Branch True seq_branch_adr 2fda MACRO_Execute_Discrete,Greater_Equal seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP 3017 3017 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3018 ; -------------------------------------------------------------------------------------- 3018 ; 0x0261 Execute Discrete,Not_In_Range 3018 ; -------------------------------------------------------------------------------------- 3018 MACRO_Execute_Discrete,Not_In_Range: 3018 3018 dispatch_brk_class 8 ; Flow J cc=True 0x2fd6 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 3018 seq_br_type 1 Branch True seq_branch_adr 2fd6 MACRO_Execute_Discrete,Less seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_b_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP 3019 3019 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 301a ; -------------------------------------------------------------------------------------- 301a ; 0x0260 Execute Discrete,In_Type 301a ; -------------------------------------------------------------------------------------- 301a MACRO_Execute_Discrete,In_Type: 301a 301a dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 301a dispatch_uses_tos 1 ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 31 VR02:11 val_frame 2 301b 301b fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x301d fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 301d 0x301d seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 301c ; -------------------------------------------------------------------------------------- 301c ; 0x025f Execute Discrete,Not_In_Type 301c ; -------------------------------------------------------------------------------------- 301c MACRO_Execute_Discrete,Not_In_Type: 301c 301c dispatch_brk_class 8 ; Flow J 0x301b dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 301c dispatch_uses_tos 1 ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 301b 0x301b typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 39 VR02:19 val_frame 2 301d 301d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 10 TOP val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 301e ; -------------------------------------------------------------------------------------- 301e ; 0x025e Execute Discrete,Convert 301e ; -------------------------------------------------------------------------------------- 301e MACRO_Execute_Discrete,Convert: 301e 301e dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 301e dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 39 VR02:19 val_frame 2 301f 301f fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3020 0x3020 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3020 3020 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 seq_random 02 ? typ_a_adr 11 TOP + 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3021 3021 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 3022 3022 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x329e seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3023 3023 seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 3024 ; -------------------------------------------------------------------------------------- 3024 ; 0x025d Execute Discrete,Bounds_Check 3024 ; -------------------------------------------------------------------------------------- 3024 MACRO_Execute_Discrete,Bounds_Check: 3024 3024 dispatch_brk_class 8 ; Flow J 0x3025 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 3024 dispatch_uses_tos 1 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3027 0x3027 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 3025 3025 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3026 0x3026 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_latch 1 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3026 3026 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3003 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 3003 0x3003 seq_random 04 Load_save_offset+? typ_b_adr 1f TOP - 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH 3027 3027 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 1f TOP - 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH 3028 ; -------------------------------------------------------------------------------------- 3028 ; 0x025c Execute Discrete,ReverseBounds_Check 3028 ; -------------------------------------------------------------------------------------- 3028 MACRO_Execute_Discrete,ReverseBounds_Check: 3028 3028 dispatch_brk_class 8 ; Flow J 0x3029 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 3028 dispatch_uses_tos 1 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3027 0x3027 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 3029 3029 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x3026 seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3026 0x3026 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_latch 1 seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 302a ; -------------------------------------------------------------------------------------- 302a ; 0x025b Execute Discrete,Check_In_Type 302a ; -------------------------------------------------------------------------------------- 302a MACRO_Execute_Discrete,Check_In_Type: 302a 302a dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 302a dispatch_uses_tos 1 ioc_fiubs 1 val typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 302b 302b fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x3020 ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3020 0x3020 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 302c ; -------------------------------------------------------------------------------------- 302c ; 0x0248 Execute Discrete,Check_In_Integer 302c ; -------------------------------------------------------------------------------------- 302c MACRO_Execute_Discrete,Check_In_Integer: 302c 302c dispatch_brk_class 8 ; Flow R cc=True dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 302c fiu_mem_start 2 start-rd fiu_tivi_src 4 fiu_var ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type c Dispatch True seq_branch_adr 302d 0x302d seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_random 04 Load_save_offset+? typ_a_adr 30 TR06:10 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 36 VR06:16 val_frame 6 302d 302d fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x32a8 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 32a8 0x32a8 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 37 VR06:17 val_frame 6 302e ; -------------------------------------------------------------------------------------- 302e ; 0x025a Execute Discrete,Write_Unchecked 302e ; -------------------------------------------------------------------------------------- 302e MACRO_Execute_Discrete,Write_Unchecked: 302e 302e dispatch_brk_class 2 ; Flow C 0x32d7 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 302e fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ seq_br_type 4 Call False seq_branch_adr 32d7 0x32d7 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 302f 302f typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL 3030 3030 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x32a9 fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 3031 3031 fiu_fill_mode_src 0 ; Flow J cc=False 0x3033 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3033 0x3033 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 3032 3032 fiu_fill_mode_src 0 ; Flow J 0x3036 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3036 0x3036 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 3033 3033 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 3034 3034 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3035 3035 fiu_load_var 1 hold_var; Flow J 0x3036 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3036 0x3036 seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 3036 3036 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA 3037 3037 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 3038 ; -------------------------------------------------------------------------------------- 3038 ; 0x0259 Execute Discrete,Test_And_Set_Previous 3038 ; -------------------------------------------------------------------------------------- 3038 MACRO_Execute_Discrete,Test_And_Set_Previous: 3038 3038 dispatch_brk_class 8 ; Flow J cc=True 0x3041 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3038 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 3041 0x3041 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 30 VR02:10 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 3039 3039 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 303a 303a fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_b_adr 16 CSA/VAL_BUS 303b 303b fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 303c 303c fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 303d 303d fiu_load_var 1 hold_var; Flow J cc=True 0x303f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 303f 0x303f typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 303e 303e fiu_mem_start 3 start-wr; Flow J cc=True 0x303f seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 303f 0x303f seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 303f 303f ioc_load_wdr 0 ; Flow J 0x3055 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3055 0x3055 seq_random 02 ? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 3040 ; -------------------------------------------------------------------------------------- 3040 ; 0x0258 Execute Discrete,Test_And_Set_Next 3040 ; -------------------------------------------------------------------------------------- 3040 MACRO_Execute_Discrete,Test_And_Set_Next: 3040 3040 dispatch_brk_class 8 ; Flow J cc=False 0x3039 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3040 fiu_mem_start 5 start_rd_if_true ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 3039 0x3039 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 31 VR02:11 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 2 3041 3041 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 3042 3042 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C cc=True 0x32a9 fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS 3043 3043 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3044 3044 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3049 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3049 0x3049 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 3045 3045 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3046 3046 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x303f seq_br_type 1 Branch True seq_branch_adr 303f 0x303f seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3047 3047 fiu_fill_mode_src 0 ; Flow J cc=True 0x303f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 303f 0x303f seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 3048 3048 fiu_fill_mode_src 0 ; Flow J 0x303f fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 303f 0x303f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 3049 3049 fiu_load_var 1 hold_var; Flow J cc=True 0x304f fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 304f 0x304f seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 304a 304a seq_br_type 7 Unconditional Call; Flow C 0x30a7 seq_branch_adr 30a7 0x30a7 304b 304b <default> 304c 304c fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A 304d 304d fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 304e 304e fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 304f 304f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3050 3050 typ_alu_func 1 A_PLUS_B typ_b_adr 03 GP03 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3051 3051 fiu_fill_mode_src 0 ; Flow J cc=True 0x303f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 303f 0x303f seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 3052 3052 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first 3053 3053 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3054 3054 fiu_load_var 1 hold_var; Flow J 0x303f fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 303f 0x303f seq_en_micro 0 seq_random 02 ? typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 3055 3055 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3056 ; -------------------------------------------------------------------------------------- 3056 ; 0x0256 Execute Discrete,Instruction_Read 3056 ; -------------------------------------------------------------------------------------- 3056 MACRO_Execute_Discrete,Instruction_Read: 3056 3056 dispatch_brk_class 8 ; Flow C 0x332e dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3056 fiu_len_fill_lit 4f zero-fill 0xf fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1d A_AND_NOT_B val_b_adr 21 VR06:01 val_frame 6 3057 3057 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 3058 ; -------------------------------------------------------------------------------------- 3058 ; 0x0255 Execute Discrete,Partial_Plus 3058 ; -------------------------------------------------------------------------------------- 3058 MACRO_Execute_Discrete,Partial_Plus: 3058 3058 dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 3058 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A 3059 3059 seq_b_timing 1 Latch Condition; Flow J cc=True 0x305b seq_br_type 1 Branch True seq_branch_adr 305b 0x305b typ_a_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL 305a 305a seq_br_type 3 Unconditional Branch; Flow J 0x305c seq_branch_adr 305c 0x305c seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 305b 305b seq_br_type 3 Unconditional Branch; Flow J 0x305c seq_branch_adr 305c 0x305c seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 1f TOP - 1 val_alu_func 2 INC_A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 305c 305c seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 4 CHECK_CLASS_A_LIT val_a_adr 14 ZEROS val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 305d 305d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 305e ; -------------------------------------------------------------------------------------- 305e ; 0x0254 Execute Discrete,Partial_Minus 305e ; -------------------------------------------------------------------------------------- 305e MACRO_Execute_Discrete,Partial_Minus: 305e 305e dispatch_brk_class 8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 305e seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 0 PASS_A 305f 305f seq_b_timing 1 Latch Condition; Flow J cc=True 0x3061 seq_br_type 1 Branch True seq_branch_adr 3061 0x3061 typ_a_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL 3060 3060 seq_br_type 3 Unconditional Branch; Flow J 0x305c seq_branch_adr 305c 0x305c seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3061 3061 seq_br_type 3 Unconditional Branch; Flow J 0x305c seq_branch_adr 305c 0x305c seq_cond_sel 09 VAL.ALU_OVERFLOW(late) typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3062 ; -------------------------------------------------------------------------------------- 3062 ; 0x0253 Execute Discrete,Binary_Scale 3062 ; -------------------------------------------------------------------------------------- 3062 MACRO_Execute_Discrete,Binary_Scale: 3062 3062 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3062 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3063 3063 fiu_tivi_src 6 fiu_fiu; Flow J cc=True 0x3068 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3068 0x3068 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3064 3064 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3065 0x3065 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 15 ZERO_COUNTER val_alu_func 5 DEC_A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 3065 3065 ioc_tvbs 2 fiu+val; Flow J cc=False 0x3067 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3067 0x3067 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 01 GP01 val_alu_func 10 NOT_A val_rand 5 COUNT_ZEROS 3066 3066 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3067 0x3067 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 15 ZERO_COUNTER val_alu_func 5 DEC_A_MINUS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS 3067 3067 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x2fe9 ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 2fe9 0x2fe9 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 3068 3068 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3069 0x3069 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR11:12 val_alu_func 5 DEC_A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 11 3069 3069 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x306b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 306b 0x306b seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 02 ? val_alu_func 6 A_MINUS_B val_b_adr 32 VR11:12 val_frame 11 306a 306a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 306b 306b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 306c ; -------------------------------------------------------------------------------------- 306c ; 0x09c0-0x09ff Execute_Immediate Binary_Scale,limitedneg 306c ; -------------------------------------------------------------------------------------- 306c MACRO_Execute_Immediate_Binary_Scale,limitedneg: 306c 306c dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_uadr 306c fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_latch 1 seq_random 02 ? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 30 VR02:10 val_frame 2 val_rand 6 IMMEDIATE_OP 306d 306d fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 306e 0x306e seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 306e 306e fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value 306f 306f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 3070 ; -------------------------------------------------------------------------------------- 3070 ; 0x0900-0x093f Execute_Immediate Binary_Scale,limitedpos 3070 ; -------------------------------------------------------------------------------------- 3070 MACRO_Execute_Immediate_Binary_Scale,limitedpos: 3070 3070 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_uadr 3070 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_latch 1 typ_a_adr 10 TOP typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 3071 3071 fiu_tivi_src 6 fiu_fiu; Flow J cc=False 0x3065 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3065 0x3065 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3072 3072 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x3065 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3065 0x3065 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 15 ZERO_COUNTER val_alu_func 5 DEC_A_MINUS_B val_c_adr 2f TOP val_c_source 0 FIU_BUS 3073 3073 <halt> ; Flow R 3074 ; -------------------------------------------------------------------------------------- 3074 ; 0x0252 Execute Discrete,Arithmetic_Shift 3074 ; -------------------------------------------------------------------------------------- 3074 MACRO_Execute_Discrete,Arithmetic_Shift: 3074 3074 dispatch_brk_class 8 ; Flow J cc=True 0x3077 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3074 fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3077 0x3077 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP 3075 3075 fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val val_b_adr 39 VR02:19 val_frame 2 3076 3076 fiu_len_fill_lit 7e zero-fill 0x3e; Flow R cc=True ; Flow J cc=False 0x3003 fiu_mem_start 2 start-rd fiu_offs_lit 41 fiu_op_sel 3 insert ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 3003 0x3003 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 3077 3077 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x3003 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 3003 0x3003 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 1 A_PLUS_B val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 3078 ; -------------------------------------------------------------------------------------- 3078 ; 0x0251 Execute Discrete,Logical_Shift 3078 ; -------------------------------------------------------------------------------------- 3078 MACRO_Execute_Discrete,Logical_Shift: 3078 3078 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3078 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP 3079 3079 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x3003 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 3003 0x3003 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 307a ; -------------------------------------------------------------------------------------- 307a ; 0x0940-0x097f Execute_Immediate Logical_Shift,limitedneg 307a ; 0x0980-0x09bf Execute_Immediate Logical_Shift,limitedpos 307a ; -------------------------------------------------------------------------------------- 307a MACRO_Execute_Immediate_Logical_Shift,limitedneg: 307a MACRO_Execute_Immediate_Logical_Shift,limitedpos: 307a 307a dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_uadr 307a fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 307b 307b fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 307c ; -------------------------------------------------------------------------------------- 307c ; 0x0250 Execute Discrete,Rotate 307c ; -------------------------------------------------------------------------------------- 307c MACRO_Execute_Discrete,Rotate: 307c 307c dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 307c fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 6 fiu_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP 307d 307d fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x3003 fiu_length_src 0 length_register fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 3003 0x3003 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 8 PLUS_ELSE_MINUS val_b_adr 10 TOP val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 307e ; -------------------------------------------------------------------------------------- 307e ; 0x024f Execute Discrete,Insert_Bits 307e ; -------------------------------------------------------------------------------------- 307e MACRO_Execute_Discrete,Insert_Bits: 307e 307e dispatch_brk_class 8 ; Flow C 0x329e dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 307e fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 307f 307f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C 0x329e fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 1 A_PLUS_B typ_b_adr 3a TR11:1a typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 11 val_a_adr 1d TOP - 3 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 3080 3080 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 3081 3081 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x3003 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 3003 0x3003 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 3082 ; -------------------------------------------------------------------------------------- 3082 ; 0x024e Execute Discrete,Extract_Bits 3082 ; -------------------------------------------------------------------------------------- 3082 MACRO_Execute_Discrete,Extract_Bits: 3082 3082 dispatch_brk_class 8 ; Flow J cc=True 0x3086 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3082 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3086 0x3086 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3083 3083 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C 0x329e fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 1 A_PLUS_B typ_b_adr 3a TR11:1a typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 11 val_a_adr 1d TOP - 3 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 3084 3084 fiu_fill_mode_src 0 ; Flow C 0x329e fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 val_alu_func 1 A_PLUS_B val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3085 3085 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3003 ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 3003 0x3003 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 2 3086 3086 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x3084 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3084 0x3084 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 5 val_a_adr 1d TOP - 3 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 3087 3087 seq_br_type 7 Unconditional Call; Flow C 0x329e seq_branch_adr 329e 0x329e seq_en_micro 0 seq_random 02 ? 3088 ; -------------------------------------------------------------------------------------- 3088 ; 0x024d Execute Discrete,Count_Nonzero_Bits 3088 ; -------------------------------------------------------------------------------------- 3088 MACRO_Execute_Discrete,Count_Nonzero_Bits: 3088 3088 dispatch_brk_class 8 ; Flow J cc=True 0x309d dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3088 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 309d 0x309d seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 15 NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 3089 3089 fiu_len_fill_lit 7d zero-fill 0x3d fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER 308a 308a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 20 TR08:00 typ_frame 8 val_a_adr 3d VR02:1d val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 308b 308b fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 308c 308c fiu_fill_mode_src 0 ; Flow J cc=True 0x308d ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_c_adr 2f TOP val_c_mux_sel 2 ALU 308d 308d fiu_fill_mode_src 0 ; Flow J cc=True 0x308e ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3e VR03:1e val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 3 val_rand 2 DEC_LOOP_COUNTER 308e 308e fiu_fill_mode_src 0 ; Flow J cc=True 0x308f ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 308f 308f fiu_fill_mode_src 0 ; Flow J cc=True 0x3090 ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 3090 3090 fiu_fill_mode_src 0 ; Flow J cc=True 0x3091 ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3091 3091 fiu_fill_mode_src 0 ; Flow J cc=True 0x3092 ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 3092 3092 fiu_fill_mode_src 0 ; Flow J cc=True 0x3093 ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3093 3093 fiu_fill_mode_src 0 ; Flow J cc=True 0x3094 ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3094 3094 fiu_fill_mode_src 0 ; Flow J cc=True 0x3095 ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3095 3095 fiu_fill_mode_src 0 ; Flow J cc=True 0x3096 ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 5 val_rand 2 DEC_LOOP_COUNTER 3096 3096 fiu_fill_mode_src 0 ; Flow J cc=True 0x3097 ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3097 3097 fiu_fill_mode_src 0 ; Flow J cc=True 0x3098 ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3098 3098 fiu_fill_mode_src 0 ; Flow J cc=True 0x3099 ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 3099 3099 fiu_fill_mode_src 0 ; Flow J cc=True 0x309a ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 309a 309a fiu_fill_mode_src 0 ; Flow J cc=True 0x309b ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 309b 309b fiu_fill_mode_src 0 ; Flow J cc=True 0x309c ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 309c 309c fiu_fill_mode_src 0 ; Flow J cc=True 0x309d ; Flow J cc=#0x0 0x308d fiu_len_fill_lit 43 zero-fill 0x3 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 308d 0x308d seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR05:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand 2 DEC_LOOP_COUNTER 309d 309d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 309e ; -------------------------------------------------------------------------------------- 309e ; 0x024c Execute Discrete,Count_Leading_Zeros 309e ; -------------------------------------------------------------------------------------- 309e MACRO_Execute_Discrete,Count_Leading_Zeros: 309e 309e dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 309e typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 309f 309f fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 15 ZERO_COUNTER val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 30a0 ; -------------------------------------------------------------------------------------- 30a0 ; 0x024b Execute Discrete,Count_Trailing_Zeros 30a0 ; -------------------------------------------------------------------------------------- 30a0 MACRO_Execute_Discrete,Count_Trailing_Zeros: 30a0 30a0 dispatch_brk_class 8 ; Flow J cc=True 0x30a3 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 30a0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 30a3 0x30a3 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30a1 30a1 val_a_adr 10 TOP val_alu_func 1e A_AND_B val_rand 5 COUNT_ZEROS 30a2 30a2 seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 7 INC_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30a3 30a3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR02:12 val_alu_func 6 A_MINUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 30a4 ; -------------------------------------------------------------------------------------- 30a4 ; 0x024a Execute Discrete,Is_Unsigned 30a4 ; -------------------------------------------------------------------------------------- 30a4 MACRO_Execute_Discrete,Is_Unsigned: 30a4 30a4 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 30a4 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value typ_a_adr 10 TOP typ_b_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL 30a5 30a5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_source 0 FIU_BUS 30a6 30a6 fiu_mem_start 2 start-rd; Flow C 0x332e fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 30a7 ; -------------------------------------------------------------------------------------- 30a7 ; Comes from: 30a7 ; 0888 C False from color 0x0000 30a7 ; 088c C False from color 0x0000 30a7 ; 0969 C False from color MACRO_0966_QQUnknown_InMicrocode 30a7 ; 0975 C False from color 0x0973 30a7 ; 09da C False from color MACRO_Execute_Any,Size 30a7 ; 09e3 C False from color 0x09e1 30a7 ; 09f0 C False from color MACRO_Execute_Any,Size 30a7 ; 0b21 C False from color 0x0000 30a7 ; 0c25 C False from color MACRO_Execute_Heap_Access,Element_Type 30a7 ; 0c63 C False from color 0x0000 30a7 ; 0c95 C False from color 0x0000 30a7 ; 0cb1 C False from color MACRO_Execute_Heap_Access,Diana_Seq_Type_Get_Head 30a7 ; 0cdc C False from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 30a7 ; 0ce3 C False from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 30a7 ; 0cfc C False from color MACRO_Execute_Heap_Access,Adaptive_Balanced_Tree_Lookup 30a7 ; 0d00 C False from color MACRO_Execute_Heap_Access,Adaptive_Balanced_Tree_Lookup 30a7 ; 0d0b C False from color MACRO_Execute_Vector,Hash 30a7 ; 0d1d C False from color MACRO_Execute_Vector,Hash 30a7 ; 0d1f C False from color MACRO_Execute_Vector,Hash 30a7 ; 0d26 C False from color MACRO_Execute_Vector,Hash 30a7 ; 0d5c C False from color 0x0000 30a7 ; 137d C False from color 0x0000 30a7 ; 1382 C False from color 0x1380 30a7 ; 1399 C False from color 0x0000 30a7 ; 1471 C False from color 0x09ac 30a7 ; 1473 C False from color 0x09ac 30a7 ; 1485 C False from color 0x09ac 30a7 ; 1487 C False from color 0x09ac 30a7 ; 149c C False from color 0x0000 30a7 ; 14a0 C False from color 0x0000 30a7 ; 14af C False from color MACRO_Execute_Matrix,Length 30a7 ; 14bc C False from color 0x14b6 30a7 ; 14c5 C False from color 0x14b6 30a7 ; 150d C False from color 0x1507 30a7 ; 1510 C False from color 0x1507 30a7 ; 1553 C False from color 0x0000 30a7 ; 1565 C False from color 0x1561 30a7 ; 1572 C False from color 0x1561 30a7 ; 15a1 C False from color 0x1599 30a7 ; 15a4 C False from color 0x1599 30a7 ; 15a6 C False from color 0x1599 30a7 ; 160f C False from color 0x0000 30a7 ; 1624 C False from color MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum 30a7 ; 1632 C False from color 0x098b 30a7 ; 1635 C False from color 0x098b 30a7 ; 163c C False from color 0x098b 30a7 ; 165c C False from color 0x165a 30a7 ; 1667 C False from color 0x165f 30a7 ; 166e C False from color 0x166c 30a7 ; 1673 C False from color 0x166c 30a7 ; 1680 C False from color 0x098b 30a7 ; 168c C False from color 0x098b 30a7 ; 1692 C False from color 0x098b 30a7 ; 1697 C False from color 0x098b 30a7 ; 16a1 C False from color 0x098b 30a7 ; 16db C False from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 30a7 ; 16fb C False from color 0x16f7 30a7 ; 170c C False from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 30a7 ; 1714 C False from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 30a7 ; 171c C False from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 30a7 ; 172f C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 30a7 ; 178c C False from color MACRO_Execute_Variant_Record,Read_Variant 30a7 ; 17fd C False from color MACRO_Execute_Any,Set_Constraint 30a7 ; 1808 C False from color MACRO_Execute_Record,Field_Read,fieldnum 30a7 ; 1851 C False from color 0x09ab 30a7 ; 185d C False from color 0x09ab 30a7 ; 1876 C False from color MACRO_Execute_Vector,Greater_Equal 30a7 ; 1880 C False from color MACRO_Execute_Vector,Greater_Equal 30a7 ; 188b C False from color MACRO_Execute_Vector,Greater_Equal 30a7 ; 1894 C False from color MACRO_Execute_Vector,Greater_Equal 30a7 ; 189b C False from color MACRO_Execute_Vector,First 30a7 ; 18a2 C False from color MACRO_Execute_Vector,First 30a7 ; 18b4 C False from color MACRO_Execute_Vector,First 30a7 ; 18c0 C False from color MACRO_Execute_Vector,Reverse_Bounds 30a7 ; 18cf C False from color MACRO_Execute_Vector,Reverse_Bounds 30a7 ; 18dc C False from color MACRO_Execute_Vector,Field_Read 30a7 ; 18ec C False from color MACRO_Execute_Vector,Field_Read 30a7 ; 1905 C False from color MACRO_Execute_Vector,Field_Write 30a7 ; 1920 C False from color MACRO_Execute_Vector,Field_Reference 30a7 ; 192e C False from color MACRO_Execute_Vector,And 30a7 ; 1937 C False from color MACRO_Execute_Vector,And 30a7 ; 1949 C False from color MACRO_Execute_Vector,And 30a7 ; 1963 C False from color 0x195c 30a7 ; 1965 C False from color 0x195c 30a7 ; 1970 C False from color MACRO_Execute_Vector,Complement 30a7 ; 1985 C False from color MACRO_Execute_Vector,Complement 30a7 ; 198f C False from color MACRO_Execute_Vector,Complement 30a7 ; 19b2 C False from color MACRO_Execute_Vector,Slice_Read 30a7 ; 19da C False from color MACRO_Execute_Vector,Slice_Write 30a7 ; 19e3 C False from color MACRO_Execute_Vector,Slice_Write 30a7 ; 19fd C False from color 0x19fa 30a7 ; 1a05 C False from color MACRO_Execute_Vector,Catenate 30a7 ; 1a10 C False from color MACRO_Execute_Vector,Catenate 30a7 ; 1a2f C False from color MACRO_Execute_Vector,Catenate 30a7 ; 1a5c C False from color MACRO_Execute_Vector,Append 30a7 ; 1a7c C False from color MACRO_Execute_Vector,Prepend 30a7 ; 1a85 C False from color 0x1a7f 30a7 ; 1a98 C False from color 0x1a95 30a7 ; 1ada C False from color 0x1ad7 30a7 ; 1b15 C False from color MACRO_Execute_Access,Element_Type 30a7 ; 1b83 C False from color 0x09aa 30a7 ; 1b8d C False from color 0x1b8a 30a7 ; 1bba C False from color 0x1bb0 30a7 ; 1bc0 C False from color 0x1bb0 30a7 ; 1c58 C False from color 0x1c57 30a7 ; 1c91 C False from color 0x0000 30a7 ; 1c95 C False from color 0x0000 30a7 ; 1c9e C False from color MACRO_Execute_Array,Field_Read 30a7 ; 1e2b C False from color 0x0000 30a7 ; 1e36 C False from color 0x0000 30a7 ; 1e4c C False from color MACRO_Execute_Matrix,Structure_Write 30a7 ; 1e50 C False from color MACRO_Execute_Matrix,Structure_Write 30a7 ; 1e56 C False from color MACRO_Execute_Matrix,Structure_Write 30a7 ; 1e5a C False from color MACRO_Execute_Matrix,Structure_Write 30a7 ; 1e6c C False from color MACRO_Execute_Matrix,Structure_Write 30a7 ; 1e6f C False from color MACRO_Execute_Matrix,Structure_Write 30a7 ; 1ea2 C False from color 0x0000 30a7 ; 1f25 C False from color 0x098b 30a7 ; 22ba C False from color 0x22b2 30a7 ; 22d5 C False from color 0x22d2 30a7 ; 22ea C False from color 0x09aa 30a7 ; 22f0 C False from color 0x09aa 30a7 ; 22f5 C False from color 0x22f3 30a7 ; 248c C False from color 0x0000 30a7 ; 249a C False from color 0x0000 30a7 ; 24a2 C False from color 0x0000 30a7 ; 24e4 C False from color 0x24ba 30a7 ; 24f1 C False from color 0x24ba 30a7 ; 250d C False from color 0x250a 30a7 ; 2520 C False from color 0x24ba 30a7 ; 252a C False from color 0x24ba 30a7 ; 2531 C False from color 0x24ba 30a7 ; 2733 C False from color 0x272c 30a7 ; 2735 C False from color 0x272c 30a7 ; 2963 C False from color 0x295f 30a7 ; 296b C False from color 0x2969 30a7 ; 2990 C False from color 0x298e 30a7 ; 2bae C False from color MACRO_Action_Load_Dynamic 30a7 ; 2e08 C False from color 0x2e04 30a7 ; 304a C from color MACRO_Execute_Discrete,Test_And_Set_Previous 30a7 ; 3621 C False from color 0x108b 30a7 ; 362c C False from color 0x108b 30a7 ; 3632 C False from color 0x3630 30a7 ; -------------------------------------------------------------------------------------- 30a7 30a7 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 30a8 0x30a8 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 30a8 30a8 fiu_mem_start 2 start-rd; Flow C 0x332e fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 30a9 30a9 fiu_load_var 1 hold_var; Flow J 0x30a6 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 30a6 0x30a6 30aa 30aa fiu_mem_start 2 start-rd; Flow C 0x332e fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 30ab ; -------------------------------------------------------------------------------------- 30ab ; Comes from: 30ab ; 0791 C False from color 0x0767 30ab ; 0ab2 C False from color 0x0aac 30ab ; 0c15 C False from color 0x0c07 30ab ; 0c9d C False from color 0x0000 30ab ; 0ca6 C False from color 0x0000 30ab ; 0d4f C False from color 0x0000 30ab ; 0d67 C False from color 0x0d65 30ab ; 1182 C False from color 0x113f 30ab ; 131c C False from color 0x1307 30ab ; 1354 C False from color 0x1346 30ab ; 13af C False from color MACRO_Declare_Variable_Array,With_Constraint 30ab ; 13f2 C False from color MACRO_Declare_Variable_Array,With_Constraint 30ab ; 1407 C False from color MACRO_Declare_Variable_Array,With_Constraint 30ab ; 1413 C False from color MACRO_Declare_Variable_Array,With_Constraint 30ab ; 1439 C False from color MACRO_Declare_Variable_Array,With_Constraint 30ab ; 1458 C False from color 0x1441 30ab ; 1463 C False from color 0x1441 30ab ; 175a C False from color 0x1757 30ab ; 1b05 C False from color 0x0000 30ab ; 1d98 C False from color 0x1cc6 30ab ; 1dad C False from color 0x1d5b 30ab ; 1dcb C False from color 0x1d5c 30ab ; 1dd3 C False from color 0x1d5c 30ab ; 1f27 C False from color 0x098b 30ab ; 2933 C False from color 0x292f 30ab ; 299c C False from color MACRO_Action_Push_Structure_Extended,abs,mark 30ab ; 29ef C False from color 0x0000 30ab ; 29fe C False from color 0x0000 30ab ; 2a47 C False from color 0x2a44 30ab ; 2a5b C False from color 0x2a34 30ab ; 2a62 C False from color 0x0000 30ab ; 3033 C False from color 0x302f 30ab ; 35d8 C False from color 0x35d3 30ab ; 395e C False from color 0x062d 30ab ; -------------------------------------------------------------------------------------- 30ab 30ab fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x30af ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 30af 0x30af seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 30 GP0f typ_mar_cntl 1 RESTORE_RDR val_c_adr 30 GP0f 30ac 30ac fiu_mem_start 7 start_wr_if_true; Flow J cc=False 0x30b0 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 30b0 0x30b0 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 30ad 30ad ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 30ae 30ae ioc_adrbs 1 val ; Flow R cc=True ; Flow J cc=False 0x30b0 seq_br_type 8 Return True seq_branch_adr 30b0 0x30b0 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_frame 4 30af 30af fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 30b0 30b0 fiu_mem_start 3 start-wr; Flow C 0x332e ioc_adrbs 1 val ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0e GP0e val_alu_func 0 PASS_A val_b_adr 0f GP0f 30b1 30b1 fiu_mem_start 2 start-rd; Flow C 0x332e fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 30b2 30b2 fiu_mem_start 3 start-wr; Flow C 0x332e ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e 30b3 30b3 fiu_mem_start 2 start-rd; Flow C 0x332e fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 30b4 30b4 fiu_fill_mode_src 0 ; Flow J 0x30aa fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 30aa 0x30aa 30b5 30b5 <halt> ; Flow R 30b6 ; -------------------------------------------------------------------------------------- 30b6 ; 0x03e6 Declare_Type Float,Defined,Visible 30b6 ; -------------------------------------------------------------------------------------- 30b6 MACRO_Declare_Type_Float,Defined,Visible: 30b6 30b6 dispatch_brk_class 4 ; Flow C 0x30b9 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 30b6 fiu_load_oreg 1 hold_oreg ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30b9 0x30b9 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 30b7 30b7 fiu_tivi_src 4 fiu_var; Flow C cc=False 0x32da ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 36 TR08:16 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 30b8 30b8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 30b9 ; -------------------------------------------------------------------------------------- 30b9 ; Comes from: 30b9 ; 30b6 C from color MACRO_Declare_Type_Float,Defined,Visible 30b9 ; 30bc C from color MACRO_Declare_Type_Float,Defined,Visible 30b9 ; -------------------------------------------------------------------------------------- 30b9 30b9 fiu_mem_start 8 start_wr_if_false; Flow C 0x32d7 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 10 TOP typ_frame 1c val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 30ba 30ba fiu_mem_start 4 continue typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_alu_func 1 A_PLUS_B val_b_adr 29 VR09:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 30bb 30bb fiu_mem_start 4 continue; Flow R fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 29 VR06:09 val_frame 6 30bc ; -------------------------------------------------------------------------------------- 30bc ; 0x03e5 Declare_Type Float,Defined 30bc ; -------------------------------------------------------------------------------------- 30bc MACRO_Declare_Type_Float,Defined: 30bc 30bc dispatch_brk_class 4 ; Flow C 0x30b9 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 30bc fiu_load_oreg 1 hold_oreg ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30b9 0x30b9 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 30bd 30bd fiu_tivi_src 4 fiu_var; Flow J 0x30b8 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 30b8 0x30b8 seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 31 TR02:11 typ_c_adr 21 TOP - 0x2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 30be ; -------------------------------------------------------------------------------------- 30be ; Comes from: 30be ; 30ca C from color 0x0000 30be ; -------------------------------------------------------------------------------------- 30be 30be fiu_load_tar 1 hold_tar; Flow J cc=False 0x30c2 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30c2 0x30c2 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_frame 8 typ_rand 8 SPARE_0x08 30bf 30bf ioc_tvbs 2 fiu+val; Flow J cc=False 0x30c3 seq_br_type 0 Branch False seq_branch_adr 30c3 0x30c3 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 30c0 30c0 fiu_mem_start 3 start-wr; Flow J cc=False 0x30c7 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30c7 0x30c7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 30c1 30c1 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0x30c4 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 30c4 0x30c4 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 30c2 30c2 ioc_tvbs 2 fiu+val; Flow J cc=False 0x30c0 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 30c0 0x30c0 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 30c3 30c3 typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU 30c4 30c4 fiu_mem_start 3 start-wr; Flow J cc=False 0x30c6 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30c6 0x30c6 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 30c5 30c5 fiu_mem_start 4 continue; Flow C 0x329e seq_br_type 8 Return True seq_branch_adr 329e 0x329e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 1e TOP - 2 30c6 30c6 fiu_mem_start 4 continue; Flow C 0x329e seq_br_type 8 Return True seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 30c7 30c7 fiu_mem_start 4 continue; Flow R cc=True ; Flow J cc=False 0x30c4 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 30c4 0x30c4 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 01 GP01 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 30c8 ; -------------------------------------------------------------------------------------- 30c8 ; Comes from: 30c8 ; 30cc C from color MACRO_Declare_Type_Float,Constrained,Visible 30c8 ; 30d0 C from color 0x30cf 30c8 ; -------------------------------------------------------------------------------------- 30c8 30c8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 30c9 30c9 fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR typ_rand b CARRY IN = Q BIT FROM VAL 30ca 30ca ioc_tvbs c mem+mem+csa+dummy; Flow C 0x30be seq_br_type 7 Unconditional Call seq_branch_adr 30be 0x30be seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30cb 30cb fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x32a9 fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 32a9 0x32a9 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 30cc ; -------------------------------------------------------------------------------------- 30cc ; 0x03e4 Declare_Type Float,Constrained,Visible 30cc ; -------------------------------------------------------------------------------------- 30cc MACRO_Declare_Type_Float,Constrained,Visible: 30cc 30cc dispatch_brk_class 4 ; Flow C 0x30c8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 30cc fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 30c8 0x30c8 typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 30cd 30cd fiu_tivi_src 4 fiu_var; Flow C cc=False 0x32da ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 30ce 30ce fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 38 TR08:18 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 30cf 30cf fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 3d TR05:1d typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 30d0 ; -------------------------------------------------------------------------------------- 30d0 ; 0x03e3 Declare_Type Float,Constrained 30d0 ; -------------------------------------------------------------------------------------- 30d0 MACRO_Declare_Type_Float,Constrained: 30d0 30d0 dispatch_brk_class 4 ; Flow C 0x30c8 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 30d0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 30c8 0x30c8 typ_a_adr 20 TR01:00 typ_alu_func 1 A_PLUS_B typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 30d1 30d1 fiu_tivi_src 4 fiu_var; Flow J 0x30cf ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 30cf 0x30cf seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 30d2 ; -------------------------------------------------------------------------------------- 30d2 ; 0x03e1 Declare_Type Float,Incomplete,Visible 30d2 ; -------------------------------------------------------------------------------------- 30d2 MACRO_Declare_Type_Float,Incomplete,Visible: 30d2 30d2 dispatch_brk_class 4 ; Flow C 0x30d5 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 30d2 fiu_load_oreg 1 hold_oreg ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30d5 0x30d5 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 30d3 30d3 fiu_tivi_src 4 fiu_var; Flow C cc=False 0x32da ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 3a TR08:1a typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 val_a_adr 14 ZEROS val_b_adr 2c VR09:0c val_frame 9 30d4 30d4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 30d5 ; -------------------------------------------------------------------------------------- 30d5 ; Comes from: 30d5 ; 30d2 C from color MACRO_Declare_Type_Float,Incomplete,Visible 30d5 ; 30d8 C from color MACRO_Declare_Type_Float,Incomplete,Visible 30d5 ; -------------------------------------------------------------------------------------- 30d5 30d5 fiu_mem_start 3 start-wr fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 30d6 30d6 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 2a VR09:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 30d7 30d7 fiu_mem_start 4 continue; Flow R fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 29 VR06:09 val_frame 6 30d8 ; -------------------------------------------------------------------------------------- 30d8 ; 0x03e0 Declare_Type Float,Incomplete 30d8 ; -------------------------------------------------------------------------------------- 30d8 MACRO_Declare_Type_Float,Incomplete: 30d8 30d8 dispatch_brk_class 4 ; Flow C 0x30d5 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 30d8 fiu_load_oreg 1 hold_oreg ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 30d5 0x30d5 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 30d9 30d9 fiu_tivi_src 4 fiu_var; Flow J 0x30d4 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 30d4 0x30d4 seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 3b TR08:1b typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 val_a_adr 14 ZEROS val_b_adr 2c VR09:0c val_frame 9 30da ; -------------------------------------------------------------------------------------- 30da ; 0x03de Complete_Type Float,By_Defining 30da ; -------------------------------------------------------------------------------------- 30da MACRO_Complete_Type_Float,By_Defining: 30da 30da dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 30da fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 30db 30db seq_br_type 2 Push (branch address); Flow J 0x30dc seq_branch_adr 32d9 0x32d9 typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_frame 8 typ_rand 8 SPARE_0x08 30dc 30dc fiu_mem_start 7 start_wr_if_true; Flow R cc=False ; Flow J cc=True 0x30ef fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 30ef 0x30ef seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 30dd 30dd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 30de ; -------------------------------------------------------------------------------------- 30de ; 0x03dd Complete_Type Float,By_Renaming 30de ; -------------------------------------------------------------------------------------- 30de MACRO_Complete_Type_Float,By_Renaming: 30de 30de dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 30de fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 30df 30df fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 30e0 30e0 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 30e1 30e1 fiu_load_var 1 hold_var; Flow C cc=True 0x32a9 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 02 GP02 typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 30e2 30e2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 30e3 30e3 fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32d9 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 21 TR06:01 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 02 GP02 30e4 30e4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 30e5 30e5 fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=True 0x32a9 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 02 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 30e6 30e6 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert typ_mar_cntl 6 INCREMENT_MAR 30e7 30e7 fiu_mem_start 4 continue; Flow J 0x30f1 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 30f1 0x30f1 typ_mar_cntl 6 INCREMENT_MAR 30e8 ; -------------------------------------------------------------------------------------- 30e8 ; 0x03dc Complete_Type Float,By_Constraining 30e8 ; -------------------------------------------------------------------------------------- 30e8 MACRO_Complete_Type_Float,By_Constraining: 30e8 30e8 dispatch_brk_class 4 ; Flow C 0x332e dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 30e8 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1d TOP - 3 val_b_adr 1e TOP - 2 30e9 30e9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 30ea 30ea fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 4 continue fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 30eb 30eb fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=False 0x32d9 fiu_load_tar 1 hold_tar fiu_mem_start 9 start_continue_if_true fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 1f TOP - 1 typ_mar_cntl 6 INCREMENT_MAR 30ec 30ec fiu_len_fill_lit 46 zero-fill 0x6; Flow C 0x30f2 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 30f2 0x30f2 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 30ed 30ed ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 30ee 30ee fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x32a9 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 30ef 30ef fiu_mem_start 4 continue seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 21 TR06:01 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 6 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 30f0 30f0 fiu_mem_start 4 continue ioc_fiubs 1 val ioc_load_wdr 0 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1e TOP - 2 30f1 30f1 ioc_load_wdr 0 ; Flow J 0x30dd seq_br_type 3 Unconditional Branch seq_branch_adr 30dd 0x30dd typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 30f2 ; -------------------------------------------------------------------------------------- 30f2 ; Comes from: 30f2 ; 30ec C from color 0x30db 30f2 ; -------------------------------------------------------------------------------------- 30f2 30f2 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x30f6 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30f6 0x30f6 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 30f3 30f3 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x30f7 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 30f7 0x30f7 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 30f4 30f4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x30fb fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30fb 0x30fb seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL 30f5 30f5 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x30f8 seq_branch_adr 30f8 0x30f8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 02 GP02 30f6 30f6 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x30f4 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 30f4 0x30f4 seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 02 GP02 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 30f7 30f7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 30f8 30f8 fiu_mem_start 2 start-rd; Flow J cc=False 0x30fa ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 30fa 0x30fa seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL 30f9 30f9 seq_br_type 8 Return True; Flow C 0x329e seq_branch_adr 329e 0x329e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 1d TOP - 3 30fa 30fa seq_br_type 8 Return True; Flow C 0x329e seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1d TOP - 3 30fb 30fb seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x30f8 seq_branch_adr 30f8 0x30f8 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 02 GP02 30fc ; -------------------------------------------------------------------------------------- 30fc ; 0x03d9 Declare_Variable Float,Visible 30fc ; -------------------------------------------------------------------------------------- 30fc MACRO_Declare_Variable_Float,Visible: 30fc 30fc dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 30fc seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 30fd 30fd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 36 TR08:16 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 30fe ; -------------------------------------------------------------------------------------- 30fe ; 0x03da Declare_Variable Float 30fe ; -------------------------------------------------------------------------------------- 30fe MACRO_Declare_Variable_Float: 30fe 30fe dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 30fe fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 37 TR09:17 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 30ff 30ff <halt> ; Flow R 3100 ; -------------------------------------------------------------------------------------- 3100 ; 0x03d8 Declare_Variable Float,Duplicate 3100 ; -------------------------------------------------------------------------------------- 3100 MACRO_Declare_Variable_Float,Duplicate: 3100 3100 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3100 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3101 3101 <halt> ; Flow R 3102 ; -------------------------------------------------------------------------------------- 3102 ; 0x02bf Declare_Variable Float,With_Value,With_Constraint 3102 ; -------------------------------------------------------------------------------------- 3102 MACRO_Declare_Variable_Float,With_Value,With_Constraint: 3102 3102 dispatch_brk_class 4 ; Flow J cc=True 0x3108 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 3102 dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3108 0x3108 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 3103 3103 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x329e fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 329e 0x329e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3104 ; -------------------------------------------------------------------------------------- 3104 ; 0x03df Declare_Variable Float,With_Value 3104 ; -------------------------------------------------------------------------------------- 3104 MACRO_Declare_Variable_Float,With_Value: 3104 3104 dispatch_brk_class 4 ; Flow R cc=False dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3104 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3105 0x3105 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 3105 3105 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 3106 ; -------------------------------------------------------------------------------------- 3106 ; 0x02be Declare_Variable Float,Visible,With_Value,With_Constraint 3106 ; -------------------------------------------------------------------------------------- 3106 MACRO_Declare_Variable_Float,Visible,With_Value,With_Constraint: 3106 3106 dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 3106 dispatch_uses_tos 1 seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 3107 3107 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x3103 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3103 0x3103 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 8 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 3108 3108 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x329e seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 329e 0x329e seq_cond_sel 20 TYP.ALU_CARRY(late) typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS 3109 3109 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x329e fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type c Dispatch True seq_branch_adr 329e 0x329e seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 310a ; -------------------------------------------------------------------------------------- 310a ; 0x03db Declare_Variable Float,Visible,With_Value 310a ; -------------------------------------------------------------------------------------- 310a MACRO_Declare_Variable_Float,Visible,With_Value: 310a 310a dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 310a fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 31 VR02:11 val_frame 2 310b 310b fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 310c ; -------------------------------------------------------------------------------------- 310c ; Comes from: 310c ; 311a C from color 0x3115 310c ; 311e C from color 0x3115 310c ; 3122 C from color 0x3115 310c ; 3124 C from color 0x3115 310c ; -------------------------------------------------------------------------------------- 310c 310c fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3111 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3111 0x3111 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) seq_latch 1 typ_a_adr 35 TR02:15 typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_rand 5 COUNT_ZEROS 310d 310d fiu_len_fill_lit 1f sign-fill 0x1f; Flow J cc=False 0x3113 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3113 0x3113 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_b_adr 10 TOP val_a_adr 15 ZERO_COUNTER val_b_adr 10 TOP 310e 310e fiu_tivi_src c mar_0xc; Flow J cc=False 0x3110 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3110 0x3110 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 12 NOT_A_OR_B val_b_adr 1f TOP - 1 val_rand 5 COUNT_ZEROS 310f 310f val_alu_func 15 NOT_B val_b_adr 1e TOP - 2 val_rand 5 COUNT_ZEROS 3110 3110 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x32d7 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_en_micro 0 typ_b_adr 10 TOP typ_frame 1c val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3111 3111 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x32d7 fiu_offs_lit 64 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1c val_b_adr 10 TOP 3112 3112 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_rand 8 SPARE_0x08 3113 3113 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x32d7 fiu_offs_lit 64 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 1c val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3114 3114 fiu_mem_start 3 start-wr; Flow R seq_br_type a Unconditional Return typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_rand 8 SPARE_0x08 3115 3115 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32da fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32da 0x32da typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1d TOP - 3 3116 3116 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 17 Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3117 3117 fiu_tivi_src 4 fiu_var; Flow C cc=False 0x32d9 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR01:01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 1f TOP - 1 val_b_adr 10 TOP 3118 3118 seq_br_type 4 Call False; Flow C cc=False 0x32dc seq_branch_adr 32dc 0x32dc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 3119 3119 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 311a ; -------------------------------------------------------------------------------------- 311a ; 0x03fe Declare_Type Discrete,Defined,Visible 311a ; -------------------------------------------------------------------------------------- 311a MACRO_Declare_Type_Discrete,Defined,Visible: 311a 311a dispatch_brk_class 4 ; Flow C 0x310c dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 311a fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 310c 0x310c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 311b 311b fiu_mem_start 4 continue ioc_tvbs 1 typ+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 311c 311c fiu_mem_start 4 continue; Flow C cc=False 0x32da fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 0 TYP VAL BUS seq_random 17 Validate_tos_optimizer+? typ_b_adr 22 TR02:02 typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 311d 311d fiu_tivi_src 4 fiu_var; Flow J 0x3119 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3119 0x3119 typ_alu_func 19 X_XOR_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 1f TOP - 1 val_b_adr 10 TOP 311e ; -------------------------------------------------------------------------------------- 311e ; 0x03fd Declare_Type Discrete,Defined 311e ; -------------------------------------------------------------------------------------- 311e MACRO_Declare_Type_Discrete,Defined: 311e 311e dispatch_brk_class 4 ; Flow C 0x310c dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 311e fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 310c 0x310c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 311f 311f fiu_mem_start 4 continue ioc_tvbs 1 typ+fiu typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3120 3120 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_int_reads 0 TYP VAL BUS seq_random 17 Validate_tos_optimizer+? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 3121 3121 fiu_tivi_src 4 fiu_var; Flow J 0x3119 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3119 0x3119 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1f TOP - 1 val_b_adr 10 TOP 3122 ; -------------------------------------------------------------------------------------- 3122 ; 0x03fb Declare_Type Discrete,Defined,Visible,With_Size 3122 ; -------------------------------------------------------------------------------------- 3122 MACRO_Declare_Type_Discrete,Defined,Visible,With_Size: 3122 3122 dispatch_brk_class 4 ; Flow C 0x310c dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3122 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 310c 0x310c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3123 3123 ioc_tvbs 1 typ+fiu; Flow J 0x3115 seq_br_type 3 Unconditional Branch seq_branch_adr 3115 0x3115 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3124 ; -------------------------------------------------------------------------------------- 3124 ; 0x03fa Declare_Type Discrete,Defined,With_Size 3124 ; -------------------------------------------------------------------------------------- 3124 MACRO_Declare_Type_Discrete,Defined,With_Size: 3124 3124 dispatch_brk_class 4 ; Flow C 0x310c dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3124 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 310c 0x310c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3125 3125 ioc_tvbs 1 typ+fiu; Flow J 0x3115 seq_br_type 3 Unconditional Branch seq_branch_adr 3115 0x3115 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3126 ; -------------------------------------------------------------------------------------- 3126 ; 0x03f9 Declare_Type Discrete,Constrained,Visible 3126 ; -------------------------------------------------------------------------------------- 3126 MACRO_Declare_Type_Discrete,Constrained,Visible: 3126 3126 dispatch_brk_class 4 ; Flow J 0x3127 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 3126 fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 32da 0x32da seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 3127 3127 fiu_mem_start 4 continue; Flow J cc=False 0x312d ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 312d 0x312d seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3128 3128 fiu_mem_start 4 continue; Flow J cc=True 0x312b ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 312b 0x312b seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3129 3129 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 312a 312a fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x313a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 313a 0x313a seq_en_micro 0 typ_a_adr 26 TR06:06 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 6 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 312b 312b ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1e TOP - 2 val_alu_func 12 NOT_A_OR_B val_b_adr 02 GP02 val_rand 5 COUNT_ZEROS 312c 312c fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False ; Flow J cc=True 0x313a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 313a 0x313a seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 312d 312d ioc_fiubs 1 val ; Flow R cc=False ; Flow J cc=True 0x3136 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 9 Return False seq_branch_adr 3136 0x3136 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 312e ; -------------------------------------------------------------------------------------- 312e ; 0x03f8 Declare_Type Discrete,Constrained 312e ; -------------------------------------------------------------------------------------- 312e MACRO_Declare_Type_Discrete,Constrained: 312e 312e dispatch_brk_class 4 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 312e fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 312f 312f fiu_mem_start 4 continue; Flow J cc=False 0x3135 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3135 0x3135 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3130 3130 fiu_mem_start 4 continue; Flow J cc=True 0x3133 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3133 0x3133 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3131 3131 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 3132 3132 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x313a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 313a 0x313a seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3133 3133 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1e TOP - 2 val_alu_func 12 NOT_A_OR_B val_b_adr 02 GP02 val_rand 5 COUNT_ZEROS 3134 3134 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x313a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 313a 0x313a seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3135 3135 ioc_load_wdr 0 ; Flow J 0x3136 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3136 0x3136 typ_a_adr 35 TR02:15 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3136 3136 fiu_mem_start 2 start-rd; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 3137 3137 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a8 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 3b TR02:1b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3138 3138 fiu_mem_start 4 continue; Flow J cc=False 0x313c ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 313c 0x313c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3139 3139 seq_br_type 3 Unconditional Branch; Flow J 0x32a8 seq_branch_adr 32a8 0x32a8 313a 313a fiu_load_tar 1 hold_tar; Flow C 0x329e fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 3b TR02:1b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 313b 313b fiu_mem_start 4 continue; Flow C 0x329e ioc_tvbs 3 fiu+fiu seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 313c 313c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR 313d 313d fiu_load_oreg 1 hold_oreg fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1e TOP - 2 val_b_adr 1f TOP - 1 313e 313e fiu_len_fill_lit 44 zero-fill 0x4; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 6 313f ; -------------------------------------------------------------------------------------- 313f ; Comes from: 313f ; 314e C from color MACRO_Declare_Type_InMicrocode,Discrete 313f ; 3154 C from color MACRO_Declare_Type_InMicrocode,Discrete 313f ; -------------------------------------------------------------------------------------- 313f 313f fiu_mem_start 4 continue; Flow J cc=False 0x3147 ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3147 0x3147 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1b A_OR_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3140 3140 fiu_mem_start 4 continue; Flow J cc=True 0x3143 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3143 0x3143 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3141 3141 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 3142 3142 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3145 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3145 0x3145 seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3143 3143 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 1e TOP - 2 val_alu_func 12 NOT_A_OR_B val_b_adr 02 GP02 val_rand 5 COUNT_ZEROS 3144 3144 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3145 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3145 0x3145 seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3145 3145 fiu_load_tar 1 hold_tar; Flow C 0x329e fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 3b TR02:1b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1f TOP - 1 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3146 3146 fiu_mem_start 4 continue; Flow C 0x329e ioc_tvbs 3 fiu+fiu seq_br_type 8 Return True seq_branch_adr 329e 0x329e seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3147 3147 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3148 3148 fiu_mem_start 2 start-rd; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE 3149 3149 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32a8 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32a8 0x32a8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 3b TR02:1b typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 314a 314a fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x32a8 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32a8 0x32a8 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_mar_cntl 6 INCREMENT_MAR val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 314b 314b <halt> ; Flow R 314c ; -------------------------------------------------------------------------------------- 314c ; 0x03fc Declare_Type InMicrocode,Discrete 314c ; -------------------------------------------------------------------------------------- 314c MACRO_Declare_Type_InMicrocode,Discrete: 314c 314c dispatch_brk_class 0 ; Flow C cc=False 0x32dc dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 314c fiu_len_fill_lit 1f sign-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 1d TOP - 3 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 314d 314d ioc_fiubs 1 val ; Flow C cc=False 0x32da ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 6 314e 314e fiu_len_fill_lit 00 sign-fill 0x0; Flow C 0x313f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 313f 0x313f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 314f 314f fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3150 fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3150 0x3150 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 seq_random 02 ? typ_a_adr 02 GP02 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 3150 3150 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x32d9 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 1f TOP - 1 val_b_adr 10 TOP 3151 3151 fiu_len_fill_lit 44 zero-fill 0x4; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 32 VR06:12 val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 6 3152 ; -------------------------------------------------------------------------------------- 3152 ; 0x03f7 Declare_Type InMicrocode,Discrete 3152 ; -------------------------------------------------------------------------------------- 3152 MACRO_Declare_Type_InMicrocode,Discrete: 3152 3152 dispatch_brk_class 0 ; Flow C cc=False 0x32dc dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3152 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 1d TOP - 3 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 32 VR02:12 val_frame 2 3153 3153 ioc_tvbs 1 typ+fiu typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3154 3154 fiu_len_fill_lit 00 sign-fill 0x0; Flow C 0x313f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 313f 0x313f seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1f TOP - 1 3155 3155 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3150 fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3150 0x3150 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 seq_random 02 ? typ_a_adr 02 GP02 typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 3156 3156 fiu_mem_start 4 continue; Flow J 0x3159 seq_br_type 3 Unconditional Branch seq_branch_adr 3159 0x3159 typ_a_adr 24 TR09:04 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 26 VR11:06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 3157 3157 <halt> ; Flow R 3158 ; -------------------------------------------------------------------------------------- 3158 ; 0x03f5 Declare_Variable Discrete,Incomplete 3158 ; -------------------------------------------------------------------------------------- 3158 MACRO_Declare_Variable_Discrete,Incomplete: 3158 3158 dispatch_brk_class 4 ; Flow J 0x315b dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3158 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 315b 0x315b seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 3159 3159 fiu_mem_start 4 continue; Flow J 0x315d fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 315d 0x315d seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3b VR02:1b val_frame 2 315a ; -------------------------------------------------------------------------------------- 315a ; 0x03f2 Declare_Variable Discrete,Incomplete,Unsigned 315a ; -------------------------------------------------------------------------------------- 315a MACRO_Declare_Variable_Discrete,Incomplete,Unsigned: 315a 315a dispatch_brk_class 4 ; Flow J 0x315b dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 315a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 315b 0x315b seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR00:00 315b 315b fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x3156 fiu_mem_start 3 start-wr fiu_offs_lit 64 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3156 0x3156 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 315c ; -------------------------------------------------------------------------------------- 315c ; 0x03f6 Declare_Variable Discrete,Incomplete,Visible 315c ; -------------------------------------------------------------------------------------- 315c MACRO_Declare_Variable_Discrete,Incomplete,Visible: 315c 315c dispatch_brk_class 4 ; Flow J 0x315f dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 315c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 315f 0x315f seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 315d 315d fiu_tivi_src 4 fiu_var; Flow J 0x3119 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3119 0x3119 seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_b_adr 30 VR02:10 val_frame 2 315e ; -------------------------------------------------------------------------------------- 315e ; 0x03f3 Declare_Variable Discrete,Incomplete,Visible,Unsigned 315e ; -------------------------------------------------------------------------------------- 315e MACRO_Declare_Variable_Discrete,Incomplete,Visible,Unsigned: 315e 315e dispatch_brk_class 4 ; Flow J 0x315f dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 315e fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 315f 0x315f seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 20 VR00:00 315f 315f fiu_len_fill_lit 40 zero-fill 0x0 fiu_mem_start 3 start-wr fiu_offs_lit 64 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 3160 3160 fiu_mem_start 4 continue; Flow J 0x3161 seq_br_type 2 Push (branch address) seq_branch_adr 32da 0x32da typ_a_adr 21 TR08:01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1 A_PLUS_B val_b_adr 26 VR11:06 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 3161 3161 fiu_mem_start 4 continue; Flow R cc=False ; Flow J cc=True 0x315d fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 9 Return False seq_branch_adr 315d 0x315d seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_b_adr 22 TR02:02 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3b VR02:1b val_frame 2 3162 ; -------------------------------------------------------------------------------------- 3162 ; 0x03ef Complete_Type Discrete,By_Defining 3162 ; -------------------------------------------------------------------------------------- 3162 MACRO_Complete_Type_Discrete,By_Defining: 3162 3162 dispatch_brk_class 4 ; Flow C 0x32d7 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3162 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 32d7 0x32d7 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3163 3163 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x3169 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3169 0x3169 seq_cond_sel 0c VAL.SIGN_BITS_EQUAL(med_late) seq_latch 1 val_a_adr 1e TOP - 2 val_alu_func 1b A_OR_B val_b_adr 1d TOP - 3 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_rand 5 COUNT_ZEROS 3164 3164 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x316a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 316a 0x316a seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_b_adr 1f TOP - 1 val_a_adr 15 ZERO_COUNTER val_b_adr 1f TOP - 1 3165 3165 seq_b_timing 1 Latch Condition; Flow J cc=False 0x3167 seq_br_type 0 Branch False seq_branch_adr 3167 0x3167 val_a_adr 1d TOP - 3 val_alu_func 12 NOT_A_OR_B val_b_adr 1e TOP - 2 val_rand 5 COUNT_ZEROS 3166 3166 val_alu_func 15 NOT_B val_b_adr 1d TOP - 3 val_rand 5 COUNT_ZEROS 3167 3167 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 10 TOP val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 3168 3168 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x316b ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 316b 0x316b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3169 3169 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x316b ioc_adrbs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 316b 0x316b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram seq_en_micro 0 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 28 VR06:08 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 316a 316a fiu_mem_start 2 start-rd; Flow C 0x32d7 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_frame 1c typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 2a VR06:0a val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 316b 316b ioc_tvbs 1 typ+fiu typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_rand 8 SPARE_0x08 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 316c 316c fiu_mem_start 7 start_wr_if_true; Flow C cc=False 0x32d9 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 316d 316d fiu_mem_start 4 continue seq_random 02 ? typ_alu_func 19 X_XOR_B typ_b_adr 24 TR09:04 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR 316e 316e fiu_mem_start 4 continue; Flow J 0x316f ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 316f 0x316f typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR 316f 316f fiu_tivi_src 4 fiu_var; Flow J 0x3195 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3195 0x3195 typ_csa_cntl 3 POP_CSA val_a_adr 1f TOP - 1 val_b_adr 10 TOP 3170 ; -------------------------------------------------------------------------------------- 3170 ; 0x03ee Complete_Type Discrete,By_Renaming 3170 ; -------------------------------------------------------------------------------------- 3170 MACRO_Complete_Type_Discrete,By_Renaming: 3170 3170 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3170 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 3171 3171 fiu_mem_start 4 continue ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3172 3172 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 19 X_XOR_B typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 3173 3173 fiu_load_var 1 hold_var; Flow C cc=True 0x32a9 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3174 3174 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3175 3175 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3176 3176 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32d9 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 24 TR09:04 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B 3177 3177 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32d9 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 02 GP02 typ_b_adr 03 GP03 val_a_adr 03 GP03 val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 3178 3178 fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=True 0x32a9 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 3179 3179 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 317a 317a fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 317b 317b ioc_load_wdr 0 ; Flow J 0x3195 seq_br_type 3 Unconditional Branch seq_branch_adr 3195 0x3195 typ_b_adr 01 GP01 typ_csa_cntl 3 POP_CSA val_b_adr 01 GP01 317c ; -------------------------------------------------------------------------------------- 317c ; 0x03ed Complete_Type Discrete,By_Constraining 317c ; -------------------------------------------------------------------------------------- 317c MACRO_Complete_Type_Discrete,By_Constraining: 317c 317c dispatch_brk_class 4 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 317c fiu_len_fill_lit 00 sign-fill 0x0 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 5 RESOLVE RAM seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 6 A_MINUS_B val_b_adr 1d TOP - 3 317d 317d fiu_load_tar 1 hold_tar; Flow J cc=True 0x318a fiu_tivi_src 8 type_var ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 318a 0x318a seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 1e TOP - 2 val_alu_func 1b A_OR_B val_b_adr 1d TOP - 3 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 317e 317e fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 317f 317f seq_b_timing 1 Latch Condition; Flow J cc=True 0x3182 seq_br_type 1 Branch True seq_branch_adr 3182 0x3182 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3180 3180 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3183 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3183 0x3183 typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_rand 5 COUNT_ZEROS 3181 3181 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x3184 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3184 0x3184 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 24 TR09:04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 29 VR06:09 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 3182 3182 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32d9 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 1d TOP - 3 val_alu_func 12 NOT_A_OR_B val_b_adr 01 GP01 val_rand 5 COUNT_ZEROS 3183 3183 fiu_len_fill_lit 1f sign-fill 0x1f; Flow J 0x3184 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3184 0x3184 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 24 TR09:04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 2a VR06:0a val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 3184 3184 fiu_mem_start 4 continue; Flow C cc=False 0x32d9 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR typ_rand 8 SPARE_0x08 val_a_adr 1d TOP - 3 3185 3185 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 02 GP02 typ_b_adr 16 CSA/VAL_BUS 3186 3186 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x329e seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 329e 0x329e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3187 3187 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_op_sel 3 insert ioc_adrbs 2 typ typ_a_adr 10 TOP typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_mar_cntl d LOAD_MAR_TYPE 3188 3188 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert ioc_tvbs 1 typ+fiu seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3189 3189 fiu_mem_start 4 continue; Flow J 0x316f ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 316f 0x316f typ_csa_cntl 3 POP_CSA typ_mar_cntl 6 INCREMENT_MAR val_b_adr 02 GP02 318a 318a fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_mar_cntl d LOAD_MAR_TYPE typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 318b 318b fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_rand a PASS_B_HIGH 318c 318c fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 6 A_MINUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE 318d 318d fiu_len_fill_lit 1f sign-fill 0x1f; Flow C cc=False 0x32d9 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 4 Call False seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_a_adr 24 TR09:04 typ_alu_func 19 X_XOR_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl 6 INCREMENT_MAR val_alu_func 1a PASS_B val_b_adr 28 VR06:08 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 6 318e 318e ioc_fiubs 1 val ; Flow J 0x318f ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 3187 0x3187 typ_a_adr 1e TOP - 2 typ_b_adr 1d TOP - 3 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 318f 318f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 3190 3190 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x32a8 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32a8 0x32a8 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_a_adr 1d TOP - 3 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3191 3191 <halt> ; Flow R 3192 ; -------------------------------------------------------------------------------------- 3192 ; 0x03ea Declare_Variable Discrete,Visible 3192 ; -------------------------------------------------------------------------------------- 3192 MACRO_Declare_Variable_Discrete,Visible: 3192 3192 dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3192 seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 3193 3193 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 3194 ; -------------------------------------------------------------------------------------- 3194 ; 0x03eb Declare_Variable Discrete 3194 ; -------------------------------------------------------------------------------------- 3194 MACRO_Declare_Variable_Discrete: 3194 3194 dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3194 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_b_adr 32 VR06:12 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 6 3195 3195 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 3196 ; -------------------------------------------------------------------------------------- 3196 ; 0x03e9 Declare_Variable Discrete,Duplicate 3196 ; -------------------------------------------------------------------------------------- 3196 MACRO_Declare_Variable_Discrete,Duplicate: 3196 3196 dispatch_brk_class 4 ; Flow R dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3196 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3197 ; -------------------------------------------------------------------------------------- 3197 ; Comes from: 3197 ; 31a8 C from color MACRO_Execute_Immediate_Set_Value,uimmediate 3197 ; -------------------------------------------------------------------------------------- 3197 3197 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32da seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 3198 ; -------------------------------------------------------------------------------------- 3198 ; 0x0600-0x06ff Execute_Immediate Set_Value_Unchecked,uimmediate 3198 ; -------------------------------------------------------------------------------------- 3198 MACRO_Execute_Immediate_Set_Value_Unchecked,uimmediate: 3198 3198 dispatch_brk_class 4 ; Flow R dispatch_csa_valid 1 dispatch_uadr 3198 fiu_len_fill_lit 47 zero-fill 0x7 fiu_mem_start 2 start-rd fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type e Unconditional Dispatch seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 04 Load_save_offset+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_c_adr 2f TOP val_c_source 0 FIU_BUS 3199 ; -------------------------------------------------------------------------------------- 3199 ; Comes from: 3199 ; 319a C True from color MACRO_Execute_Immediate_Set_Value,uimmediate 3199 ; -------------------------------------------------------------------------------------- 3199 3199 seq_br_type a Unconditional Return; Flow R typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 319a ; -------------------------------------------------------------------------------------- 319a ; 0x0700-0x07ff Execute_Immediate Set_Value,uimmediate 319a ; -------------------------------------------------------------------------------------- 319a MACRO_Execute_Immediate_Set_Value,uimmediate: 319a 319a dispatch_brk_class 4 ; Flow C cc=True 0x3199 dispatch_csa_valid 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 319a dispatch_uses_tos 1 fiu_len_fill_lit 47 zero-fill 0x7 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3199 0x3199 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_c_adr 3f GP00 val_c_source 0 FIU_BUS 319b 319b fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 319c 0x319c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS 319c 319c fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 319d 319d fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x32a9 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE 319e 319e ioc_tvbs c mem+mem+csa+dummy; Flow C 0x329e seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 319f 319f seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 31a0 ; -------------------------------------------------------------------------------------- 31a0 ; 0x0400-0x04ff Execute_Immediate Set_Value_Visible_Unchecked,uimmediate 31a0 ; -------------------------------------------------------------------------------------- 31a0 MACRO_Execute_Immediate_Set_Value_Visible_Unchecked,uimmediate: 31a0 31a0 dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 1 dispatch_uadr 31a0 ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 31a1 31a1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 9 PASS_A_HIGH val_alu_func 1a PASS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 31a2 ; -------------------------------------------------------------------------------------- 31a2 ; 0x0500-0x05ff Execute_Immediate Set_Value_Visible,uimmediate 31a2 ; -------------------------------------------------------------------------------------- 31a2 MACRO_Execute_Immediate_Set_Value_Visible,uimmediate: 31a2 31a2 dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 31a2 dispatch_uses_tos 1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 6 IMMEDIATE_OP 31a3 31a3 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x31a9 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 31a9 0x31a9 seq_int_reads 0 TYP VAL BUS seq_random 08 Validate_tos_optimizer+? typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 0 PASS_A val_b_adr 31 VR02:11 val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 31a4 ; -------------------------------------------------------------------------------------- 31a4 ; 0x03ec Declare_Variable Discrete,With_Value,With_Constraint 31a4 ; -------------------------------------------------------------------------------------- 31a4 MACRO_Declare_Variable_Discrete,With_Value,With_Constraint: 31a4 31a4 dispatch_brk_class 4 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 31a4 dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 31a5 31a5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x319c fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 319c 0x319c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 31a6 ; -------------------------------------------------------------------------------------- 31a6 ; 0x03f1 Declare_Variable Discrete,With_Value 31a6 ; -------------------------------------------------------------------------------------- 31a6 MACRO_Declare_Variable_Discrete,With_Value: 31a6 31a6 dispatch_brk_class 4 ; Flow R cc=False dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 31a6 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 31a7 0x31a7 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 31a7 31a7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 10 TOP typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL 31a8 ; -------------------------------------------------------------------------------------- 31a8 ; 0x03e8 Declare_Variable Discrete,Visible,With_Value,With_Constraint 31a8 ; -------------------------------------------------------------------------------------- 31a8 MACRO_Declare_Variable_Discrete,Visible,With_Value,With_Constraint: 31a8 31a8 dispatch_brk_class 4 ; Flow C 0x3197 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_mem_strt 7 TYPE READ, AT TOS TYPE LINK dispatch_uadr 31a8 dispatch_uses_tos 1 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3197 0x3197 seq_random 02 ? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_b_adr 31 VR02:11 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 31a9 31a9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False ; Flow J cc=True 0x319c fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 319c 0x319c seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_random 04 Load_save_offset+? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 31aa ; -------------------------------------------------------------------------------------- 31aa ; 0x03f0 Declare_Variable Discrete,Visible,With_Value 31aa ; -------------------------------------------------------------------------------------- 31aa MACRO_Declare_Variable_Discrete,Visible,With_Value: 31aa 31aa dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 31aa fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 31 VR02:11 val_frame 2 31ab 31ab fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 1f TOP - 1 typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 8 SPARE_0x08 val_b_adr 1f TOP - 1 31ac ; -------------------------------------------------------------------------------------- 31ac ; 0x03ad Declare_Type Heap_Access,Defined 31ac ; -------------------------------------------------------------------------------------- 31ac MACRO_Declare_Type_Heap_Access,Defined: 31ac 31ac dispatch_brk_class 4 ; Flow J cc=False 0x31b1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 31ac fiu_mem_start 6 start_rd_if_false ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 31b1 0x31b1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 22 VR00:02 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31ad 31ad seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 31ae ; -------------------------------------------------------------------------------------- 31ae ; 0x03ae Declare_Type Heap_Access,Defined,Visible 31ae ; -------------------------------------------------------------------------------------- 31ae MACRO_Declare_Type_Heap_Access,Defined,Visible: 31ae 31ae dispatch_brk_class 4 ; Flow C cc=False 0x32da dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 31ae seq_br_type 4 Call False seq_branch_adr 32da 0x32da seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 val_a_adr 22 VR00:02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31af 31af fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x31b1 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 31b1 0x31b1 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x19) Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 19 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 3a VR07:1a val_frame 7 31b0 31b0 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 31b1 31b1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 29 VR06:09 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 6 31b2 31b2 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_c_lit 1 typ_frame c 31b3 31b3 ioc_adrbs 2 typ ; Flow C cc=#0x0 0x31ba seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 31ba 0x31ba seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR00:00 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE 31b4 31b4 fiu_mem_start 3 start-wr fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 38 TR11:18 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 35 VR07:15 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 31b5 31b5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x32d7 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x1c) Null_Subprogram typ_a_adr 01 GP01 typ_b_adr 10 TOP typ_frame 1c typ_mar_cntl 6 INCREMENT_MAR val_b_adr 10 TOP 31b6 31b6 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 1f TOP - 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 21 TR01:01 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 01 GP01 31b7 31b7 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_b_adr 39 VR02:19 val_frame 2 31b8 31b8 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 31b9 31b9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 31ba ; -------------------------------------------------------------------------------------- 31ba ; Comes from: 31ba ; 31b3 C #0x0 from color MACRO_Declare_Type_Heap_Access,Defined 31ba ; -------------------------------------------------------------------------------------- 31ba 31ba seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x31c0 seq_br_type 9 Return False seq_branch_adr 31c0 0x31c0 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR07:0b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 31bb 31bb seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x31c0 seq_br_type 9 Return False seq_branch_adr 31c0 0x31c0 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR07:0b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 31bc 31bc seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x31c0 seq_br_type 9 Return False seq_branch_adr 31c0 0x31c0 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR07:0b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 31bd 31bd seq_br_type 3 Unconditional Branch; Flow J 0x31be seq_branch_adr 31be 0x31be typ_c_adr 3b GP04 31be 31be seq_br_type 4 Call False; Flow C cc=False 0x32d9 seq_branch_adr 32d9 0x32d9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 04 GP04 31bf 31bf seq_b_timing 1 Latch Condition; Flow R cc=False seq_br_type 9 Return False seq_branch_adr 31c0 0x31c0 typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 2b TR07:0b typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 31c0 31c0 seq_br_type a Unconditional Return; Flow R typ_a_adr 1f TOP - 1 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_frame 2 31c1 31c1 <halt> ; Flow R 31c2 ; -------------------------------------------------------------------------------------- 31c2 ; 0x03a8 Declare_Type Heap_Access,Incomplete 31c2 ; -------------------------------------------------------------------------------------- 31c2 MACRO_Declare_Type_Heap_Access,Incomplete: 31c2 31c2 dispatch_brk_class 4 ; Flow J 0x31c3 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 31c2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 31c3 0x31c3 typ_a_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31c3 31c3 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x31d0 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 31d0 0x31d0 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 29 VR06:09 val_frame 6 31c4 ; -------------------------------------------------------------------------------------- 31c4 ; 0x03a9 Declare_Type Heap_Access,Incomplete,Visible 31c4 ; -------------------------------------------------------------------------------------- 31c4 MACRO_Declare_Type_Heap_Access,Incomplete,Visible: 31c4 31c4 dispatch_brk_class 4 ; Flow J cc=True 0x31c3 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 31c4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 31c3 0x31c3 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31c5 31c5 seq_br_type 7 Unconditional Call; Flow C 0x32da seq_branch_adr 32da 0x32da 31c6 ; -------------------------------------------------------------------------------------- 31c6 ; 0x03a5 Declare_Type Heap_Access,Incomplete,Values_Relative 31c6 ; -------------------------------------------------------------------------------------- 31c6 MACRO_Declare_Type_Heap_Access,Incomplete,Values_Relative: 31c6 31c6 dispatch_brk_class 4 ; Flow J 0x31c7 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 31c6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 31c7 0x31c7 typ_a_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31c7 31c7 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x31d0 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 31d0 0x31d0 typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR11:11 val_frame 11 31c8 ; -------------------------------------------------------------------------------------- 31c8 ; 0x03a6 Declare_Type Heap_Access,Incomplete,Visible,Values_Relative 31c8 ; -------------------------------------------------------------------------------------- 31c8 MACRO_Declare_Type_Heap_Access,Incomplete,Visible,Values_Relative: 31c8 31c8 dispatch_brk_class 4 ; Flow J cc=True 0x31c7 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 31c8 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 31c7 0x31c7 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31c9 31c9 seq_br_type 7 Unconditional Call; Flow C 0x32da seq_branch_adr 32da 0x32da 31ca ; -------------------------------------------------------------------------------------- 31ca ; 0x03a4 Declare_Type Heap_Access,Incomplete,Values_Relative,With_Size 31ca ; -------------------------------------------------------------------------------------- 31ca MACRO_Declare_Type_Heap_Access,Incomplete,Values_Relative,With_Size: 31ca 31ca dispatch_brk_class 4 ; Flow J 0x31cb dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 31ca fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 31cb 0x31cb typ_a_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 20 VR00:00 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31cb 31cb fiu_len_fill_lit 46 zero-fill 0x6; Flow C cc=True 0x32d9 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d9 0x32d9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR05:0d val_frame 5 31cc 31cc fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x31d0 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert seq_br_type 1 Branch True seq_branch_adr 31d0 0x31d0 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 21 TR02:01 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 31cd 31cd seq_br_type 7 Unconditional Call; Flow C 0x32d9 seq_branch_adr 32d9 0x32d9 31ce ; -------------------------------------------------------------------------------------- 31ce ; 0x03a7 Declare_Type Heap_Access,Incomplete,Visible,Values_Relative,With_Size 31ce ; -------------------------------------------------------------------------------------- 31ce MACRO_Declare_Type_Heap_Access,Incomplete,Visible,Values_Relative,With_Size: 31ce 31ce dispatch_brk_class 4 ; Flow J cc=True 0x31cb dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 31ce fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 65 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 31cb 0x31cb seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 22 TR02:02 typ_b_adr 22 TR02:02 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 22 VR00:02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 31cf 31cf seq_br_type 7 Unconditional Call; Flow C 0x32da seq_branch_adr 32da 0x32da 31d0 31d0 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 3b TR02:1b typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 31d1 31d1 fiu_mem_start 4 continue ioc_load_wdr 0 typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_b_adr 39 VR02:19 val_frame 2 31d2 31d2 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_b_adr 2c TR07:0c typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_alu_func 1b A_OR_B val_b_adr 39 VR07:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 31d3 31d3 ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_b_adr 39 VR02:19 val_frame 2 31d4 31d4 seq_random 02 ? typ_a_adr 21 TR02:01 typ_alu_func 1 A_PLUS_B typ_b_adr 3f TR02:1f typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 31d5 31d5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1b A_OR_B typ_b_adr 02 GP02 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 31d6 ; -------------------------------------------------------------------------------------- 31d6 ; Comes from: 31d6 ; 31e0 C False from color 0x0000 31d6 ; 31f4 C False from color 0x0000 31d6 ; 3209 C False from color MACRO_Execute_Discrete,Remainder 31d6 ; 3217 C False from color MACRO_Execute_Discrete,Remainder 31d6 ; 3228 C False from color MACRO_Execute_Discrete,Remainder 31d6 ; 3234 C False from color MACRO_Execute_Discrete,Remainder 31d6 ; -------------------------------------------------------------------------------------- 31d6 31d6 ioc_tvbs 1 typ+fiu; Flow R cc=True ; Flow J cc=False 0x31d6 seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 31d6 0x31d6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 31d7 31d7 <halt> ; Flow R 31d8 ; -------------------------------------------------------------------------------------- 31d8 ; 0x0270 Execute Discrete,Divide 31d8 ; -------------------------------------------------------------------------------------- 31d8 MACRO_Execute_Discrete,Divide: 31d8 31d8 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 31d8 ioc_fiubs 1 val seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31d9 31d9 fiu_load_var 1 hold_var; Flow J cc=True 0x31e8 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31e8 0x31e8 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31da 31da fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x31e3 fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31e3 0x31e3 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31db 31db fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x31dd fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31dd 0x31dd seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 val_a_adr 15 ZERO_COUNTER val_alu_func 7 INC_A 31dc 31dc fiu_mem_start 2 start-rd; Flow R fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 31dd 31dd ioc_fiubs 1 val ; Flow J cc=False 0x31e0 ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31e0 0x31e0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 31de 31de fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP 31df 31df fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31e0 31e0 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x31d6 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31d6 0x31d6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 4 CHECK_CLASS_A_LIT val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand b DIVIDE 31e1 31e1 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_mar_cntl b LOAD_MAR_DATA typ_rand 4 CHECK_CLASS_A_LIT val_a_adr 1f TOP - 1 val_alu_func 19 X_XOR_B val_b_adr 10 TOP 31e2 31e2 fiu_mem_start 2 start-rd; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31e3 31e3 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31e4 31e4 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31e5 31e5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x31dd fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31dd 0x31dd seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 val_a_adr 15 ZERO_COUNTER val_alu_func 7 INC_A 31e6 31e6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B 31e7 31e7 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func b PASS_B_ELSE_PASS_A val_b_adr 30 VR02:10 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 31e8 31e8 fiu_vmux_sel 1 fill value; Flow J cc=True 0x31ec ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 31ec 0x31ec seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 01 GP01 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR08:00 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 8 val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31e9 31e9 fiu_load_var 1 hold_var; Flow J cc=True 0x31e4 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31e4 0x31e4 seq_en_micro 0 val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31ea 31ea seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31eb 31eb fiu_load_oreg 1 hold_oreg; Flow J 0x31db fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 31db 0x31db seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 01 GP01 typ_alu_func 1c DEC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 31ec 31ec fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 31ed 0x31ed seq_cond_sel 09 VAL.ALU_OVERFLOW(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31ed 31ed seq_br_type 7 Unconditional Call; Flow C 0x32a8 seq_branch_adr 32a8 0x32a8 seq_en_micro 0 seq_random 02 ? 31ee ; -------------------------------------------------------------------------------------- 31ee ; 0x0140 Execute Discrete,Divide_And_Scale 31ee ; -------------------------------------------------------------------------------------- 31ee MACRO_Execute_Discrete,Divide_And_Scale: 31ee 31ee dispatch_brk_class 8 ; Flow C cc=False 0x31f7 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 31ee fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 31f7 0x31f7 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31ef 31ef fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31f9 fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 31f9 0x31f9 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31f0 31f0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 15 ZERO_COUNTER val_alu_func 1 A_PLUS_B val_b_adr 32 VR02:12 val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 31f1 31f1 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 32 TR02:12 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 15 ZERO_COUNTER 31f2 31f2 ioc_fiubs 0 fiu ; Flow J cc=True 0x31fb seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 31fb 0x31fb seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 05 GP05 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 32 VR06:12 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 6 31f3 31f3 fiu_load_var 1 hold_var; Flow J cc=True 0x31ff fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 31ff 0x31ff seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3a TR02:1a typ_frame 2 val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 31f4 31f4 ioc_tvbs 1 typ+fiu; Flow C cc=False 0x31d6 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31d6 0x31d6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 1f TOP - 1 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 31f5 31f5 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x31fe fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 31fe 0x31fe seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 3 LEFT_I_A typ_mar_cntl b LOAD_MAR_DATA typ_rand 4 CHECK_CLASS_A_LIT 31f6 31f6 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32a8 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a8 0x32a8 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31f7 ; -------------------------------------------------------------------------------------- 31f7 ; Comes from: 31f7 ; 31ee C False from color 0x0000 31f7 ; -------------------------------------------------------------------------------------- 31f7 31f7 seq_br_type 4 Call False; Flow C cc=False 0x32a7 seq_branch_adr 32a7 0x32a7 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_latch 1 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31f8 31f8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 seq_latch 1 typ_csa_cntl 2 PUSH_CSA val_b_adr 01 GP01 31f9 ; -------------------------------------------------------------------------------------- 31f9 ; Comes from: 31f9 ; 31ef C False from color 0x0000 31f9 ; -------------------------------------------------------------------------------------- 31f9 31f9 seq_br_type 1 Branch True; Flow J cc=True 0x31f8 seq_branch_adr 31f8 0x31f8 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 31fa 31fa fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31fb 31fb fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS 31fc 31fc fiu_fill_mode_src 0 ; Flow J cc=True 0x31ff fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 31ff 0x31ff seq_cond_sel 20 TYP.ALU_CARRY(late) typ_a_adr 03 GP03 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 3a TR02:1a typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 31fd 31fd fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x31f6 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 31f6 0x31f6 typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 31fe 31fe fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x32a8 fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 32a8 0x32a8 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 31ff 31ff fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x32a8 fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 32a8 0x32a8 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 20 TOP - 0x1 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3200 ; -------------------------------------------------------------------------------------- 3200 ; 0x026f Execute Discrete,Remainder 3200 ; -------------------------------------------------------------------------------------- 3200 MACRO_Execute_Discrete,Remainder: 3200 3200 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3200 ioc_fiubs 1 val seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3201 3201 fiu_load_var 1 hold_var; Flow J cc=False 0x320f fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 320f 0x320f seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3202 3202 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x3205 fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3205 0x3205 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3203 3203 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3204 3204 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3205 3205 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3208 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3208 0x3208 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 3206 3206 seq_cond_sel 08 VAL.ALU_CARRY(late) val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3207 3207 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func a PASS_A_ELSE_PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3208 3208 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x320e seq_br_type 1 Branch True seq_branch_adr 320e 0x320e seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 03 GP03 3209 3209 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31d6 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31d6 0x31d6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 320a 320a ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand b DIVIDE 320b 320b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x320d fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 320d 0x320d seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 320c 320c fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_b_adr 39 VR02:19 val_frame 2 320d 320d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 320e 320e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 320f 320f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x323a seq_br_type 1 Branch True seq_branch_adr 323a 0x323a seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3210 3210 fiu_load_var 1 hold_var; Flow J cc=True 0x3212 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3212 0x3212 seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3211 3211 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3212 3212 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3213 3213 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3216 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3216 0x3216 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 3214 3214 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3215 0x3215 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B 3215 3215 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 2f TOP val_c_mux_sel 2 ALU 3216 3216 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x321c seq_br_type 1 Branch True seq_branch_adr 321c 0x321c seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 03 GP03 3217 3217 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31d6 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31d6 0x31d6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 3218 3218 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand b DIVIDE 3219 3219 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x321b fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 321b 0x321b seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 321a 321a fiu_len_fill_lit 3f sign-fill 0x3f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_b_adr 39 VR02:19 val_frame 2 321b 321b fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 321c 321c val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 321d 321d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 321e ; -------------------------------------------------------------------------------------- 321e ; 0x026e Execute Discrete,Modulo 321e ; -------------------------------------------------------------------------------------- 321e MACRO_Execute_Discrete,Modulo: 321e 321e dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 321e ioc_fiubs 1 val seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_latch 1 typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 321f 321f fiu_load_var 1 hold_var; Flow J cc=False 0x322d fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 322d 0x322d seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3220 3220 fiu_load_oreg 1 hold_oreg; Flow J cc=True 0x3205 fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3205 0x3205 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3221 3221 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32a7 seq_br_type 5 Call True seq_branch_adr 32a7 0x32a7 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 3222 3222 fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3223 3223 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3227 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3227 0x3227 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 3224 3224 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B 3225 3225 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 3226 0x3226 seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3226 3226 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_mux_sel 2 ALU 3227 3227 val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 03 GP03 3228 3228 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31d6 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31d6 0x31d6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 3229 3229 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x323a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 323a 0x323a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand b DIVIDE 322a 322a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x322c fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 322c 0x322c seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 322b 322b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x323a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 323a 0x323a seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 322c 322c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 322d 322d seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x323a seq_br_type 1 Branch True seq_branch_adr 323a 0x323a seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 322e 322e fiu_load_var 1 hold_var; Flow J cc=False 0x3211 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3211 0x3211 seq_en_micro 0 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 15 ZERO_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_rand 5 COUNT_ZEROS 322f 322f fiu_load_oreg 1 hold_oreg fiu_load_tar 1 hold_tar fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 15 ZERO_COUNTER val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3230 3230 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3233 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3233 0x3233 val_a_adr 01 GP01 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 2 DEC_LOOP_COUNTER 3231 3231 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3232 0x3232 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3232 3232 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 01 GP01 val_c_adr 2f TOP val_c_mux_sel 2 ALU 3233 3233 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3239 seq_br_type 1 Branch True seq_branch_adr 3239 0x3239 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 03 GP03 3234 3234 fiu_load_oreg 1 hold_oreg; Flow C cc=False 0x31d6 fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 31d6 0x31d6 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 0 ALU << 1 val_rand 2 DEC_LOOP_COUNTER 3235 3235 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x323a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 323a 0x323a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 9 MINUS_ELSE_PLUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand b DIVIDE 3236 3236 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3238 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3238 0x3238 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3237 3237 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x323a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 323a 0x323a seq_cond_sel 00 VAL.ALU_ZERO(late) val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 3238 3238 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 3239 3239 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 03 GP03 val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 323a 323a fiu_mem_start 2 start-rd; Flow R cc=True fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type c Dispatch True seq_branch_adr 323b 0x323b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 323b 323b seq_br_type 7 Unconditional Call; Flow C 0x32a7 seq_branch_adr 32a7 0x32a7 seq_en_micro 0 seq_random 02 ? 323c ; -------------------------------------------------------------------------------------- 323c ; 0x7800-0x7fff Jump pcrel,>J 323c ; -------------------------------------------------------------------------------------- 323c MACRO_Jump_pcrel,>J: 323c 323c dispatch_brk_class 1 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 323c 323d 323d ioc_tvbs c mem+mem+csa+dummy; Flow J 0x324c seq_br_type 3 Unconditional Branch seq_branch_adr 324c 0x324c seq_int_reads 0 TYP VAL BUS seq_random 36 Load_ibuff+? 323e ; -------------------------------------------------------------------------------------- 323e ; 0x7000-0x77ff Jump_Nonzero pcrel,>JC 323e ; -------------------------------------------------------------------------------------- 323e MACRO_Jump_Nonzero_pcrel,>JC: 323e 323e dispatch_brk_class 1 ; Flow J 0x3241 dispatch_csa_valid 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 323e seq_br_type 3 Unconditional Branch seq_branch_adr 3241 0x3241 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 323f 323f <halt> ; Flow R 3240 ; -------------------------------------------------------------------------------------- 3240 ; 0x6800-0x6fff Jump_Zero pcrel,>JC 3240 ; -------------------------------------------------------------------------------------- 3240 MACRO_Jump_Zero_pcrel,>JC: 3240 3240 dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 3240 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 3241 3241 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 3242 0x3242 seq_int_reads 0 TYP VAL BUS seq_random 40 Load_ibuff+Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 3242 3242 fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3243 0x3243 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_random 04 Load_save_offset+? typ_a_adr 11 TOP + 1 typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 3243 3243 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 3244 ; -------------------------------------------------------------------------------------- 3244 ; 0x4600-0x47ff Jump_Case case_max 3244 ; -------------------------------------------------------------------------------------- 3244 MACRO_Jump_Case_case_max: 3244 3244 dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_uadr 3244 fiu_len_fill_lit 48 zero-fill 0x8 fiu_offs_lit 77 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_b_adr 10 TOP typ_rand a PASS_B_HIGH val_a_adr 3d VR02:1d val_b_adr 10 TOP val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 3245 3245 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 3246 3246 fiu_tivi_src c mar_0xc; Flow J cc=False 0x324b ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 324b 0x324b seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 3247 3247 ioc_tvbs 1 typ+fiu; Flow C 0x329f seq_br_type 7 Unconditional Call seq_branch_adr 329f 0x329f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_csa_cntl 2 PUSH_CSA 3248 ; -------------------------------------------------------------------------------------- 3248 ; 0x00a7 Action Jump_Extended,abs,>J 3248 ; -------------------------------------------------------------------------------------- 3248 MACRO_Action_Jump_Extended,abs,>J: 3248 3248 dispatch_brk_class 1 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3248 ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION val_a_adr 3d VR02:1d val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 3249 3249 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 324a 324a fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_int_reads 0 TYP VAL BUS seq_random 1a ? 324b 324b ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 324c 324c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 324d 324d <halt> ; Flow R 324e ; -------------------------------------------------------------------------------------- 324e ; 0x00a5 Action Jump_Nonzero_Extended,abs,>JC 324e ; -------------------------------------------------------------------------------------- 324e MACRO_Action_Jump_Nonzero_Extended,abs,>JC: 324e 324e dispatch_brk_class 1 ; Flow J 0x3251 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 324e fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3251 0x3251 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 324f 324f <halt> ; Flow R 3250 ; -------------------------------------------------------------------------------------- 3250 ; 0x00a6 Action Jump_Zero_Extended,abs,>JC 3250 ; -------------------------------------------------------------------------------------- 3250 MACRO_Action_Jump_Zero_Extended,abs,>JC: 3250 3250 dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3250 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 5 val_a_adr 10 TOP val_alu_func 0 PASS_A 3251 3251 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3249 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3249 0x3249 seq_en_micro 0 seq_int_reads 2 DECODING MACRO INSTRUCTION seq_random 02 ? typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR11:12 typ_csa_cntl 3 POP_CSA typ_frame 11 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 3d VR02:1d val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 3252 3252 seq_br_type 1 Branch True; Flow J cc=True 0x324b seq_branch_adr 324b 0x324b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_random 16 ? typ_a_adr 11 TOP + 1 typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_frame 5 3253 3253 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 3254 ; -------------------------------------------------------------------------------------- 3254 ; 0x009f Action Jump_Dynamic 3254 ; -------------------------------------------------------------------------------------- 3254 MACRO_Action_Jump_Dynamic: 3254 3254 dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3254 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_random 02 ? typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 3255 3255 fiu_tivi_src c mar_0xc; Flow J 0x324b ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 324b 0x324b seq_int_reads 0 TYP VAL BUS seq_random 59 ? 3256 ; -------------------------------------------------------------------------------------- 3256 ; 0x009d Action Jump_Nonzero_Dynamic 3256 ; -------------------------------------------------------------------------------------- 3256 MACRO_Action_Jump_Nonzero_Dynamic: 3256 3256 dispatch_brk_class 1 ; Flow J cc=False 0x325b dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3256 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 325b 0x325b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 3257 3257 fiu_tivi_src c mar_0xc; Flow J cc=True 0x324b ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 324b 0x324b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_csa_cntl 3 POP_CSA typ_frame 5 3258 3258 seq_br_type 7 Unconditional Call; Flow C 0x32d7 seq_branch_adr 32d7 0x32d7 seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 3259 3259 <halt> ; Flow R 325a ; -------------------------------------------------------------------------------------- 325a ; 0x009e Action Jump_Zero_Dynamic 325a ; -------------------------------------------------------------------------------------- 325a MACRO_Action_Jump_Zero_Dynamic: 325a 325a dispatch_brk_class 1 ; Flow J cc=True 0x3257 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 325a fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 3257 0x3257 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 325b 325b fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x3258 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3258 0x3258 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 10 TOP typ_alu_func 1e A_AND_B typ_b_adr 3f TR05:1f typ_csa_cntl 3 POP_CSA typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 325c ; -------------------------------------------------------------------------------------- 325c ; 0x3e00-0x3fff Loop_Increasing pcrelneg,>JC 325c ; -------------------------------------------------------------------------------------- 325c MACRO_Loop_Increasing_pcrelneg,>JC: 325c 325c dispatch_brk_class 1 dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 325c fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 325d 325d fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x325f fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 325f 0x325f seq_int_reads 0 TYP VAL BUS seq_random 36 Load_ibuff+? typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 0 PASS_A 325e 325e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 7 INC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 325f 325f fiu_tivi_src c mar_0xc; Flow J 0x324b ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 324b 0x324b seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_csa_cntl 3 POP_CSA 3260 ; -------------------------------------------------------------------------------------- 3260 ; 0x3600-0x37ff Loop_Decreasing pcrelneg,>JC 3260 ; -------------------------------------------------------------------------------------- 3260 MACRO_Loop_Decreasing_pcrelneg,>JC: 3260 3260 dispatch_brk_class 1 dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_mem_strt 5 PROGRAM READ, AT MACRO PC PLUS OFFSET dispatch_uadr 3260 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3261 3261 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x3263 fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3263 0x3263 seq_int_reads 0 TYP VAL BUS seq_random 36 Load_ibuff+? typ_csa_cntl 3 POP_CSA typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 0 PASS_A 3262 3262 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 1c DEC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3263 3263 fiu_tivi_src c mar_0xc; Flow J 0x324b ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 324b 0x324b seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_csa_cntl 3 POP_CSA 3264 ; -------------------------------------------------------------------------------------- 3264 ; 0x00a4 Action Loop_Increasing_Extended,abs,>JC 3264 ; -------------------------------------------------------------------------------------- 3264 MACRO_Action_Loop_Increasing_Extended,abs,>JC: 3264 3264 dispatch_brk_class 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3264 ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 3d VR02:1d val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 3265 3265 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 3266 3266 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 1a ? val_a_adr 10 TOP val_alu_func 6 A_MINUS_B val_b_adr 1f TOP - 1 3267 3267 fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x325f fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 325f 0x325f seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR11:12 typ_csa_cntl 3 POP_CSA typ_frame 11 typ_mar_cntl 9 LOAD_MAR_CODE 3268 3268 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 7 INC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3269 3269 <halt> ; Flow R 326a ; -------------------------------------------------------------------------------------- 326a ; 0x00a3 Action Loop_Decreasing_Extended,abs,>JC 326a ; -------------------------------------------------------------------------------------- 326a MACRO_Action_Loop_Decreasing_Extended,abs,>JC: 326a 326a dispatch_brk_class 1 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 326a ioc_tvbs 5 seq+seq seq_int_reads 2 DECODING MACRO INSTRUCTION typ_a_adr 10 TOP typ_b_adr 1f TOP - 1 typ_rand 8 SPARE_0x08 val_a_adr 3d VR02:1d val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand c START_MULTIPLY 326b 326b fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 326c 326c fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 1a ? val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 10 TOP 326d 326d fiu_load_oreg 1 hold_oreg; Flow J cc=False 0x3263 fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3263 0x3263 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_alu_func 1 A_PLUS_B typ_b_adr 32 TR11:12 typ_csa_cntl 3 POP_CSA typ_frame 11 typ_mar_cntl 9 LOAD_MAR_CODE 326e 326e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 11 TOP + 1 val_alu_func 1c DEC_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 326f ; -------------------------------------------------------------------------------------- 326f ; Comes from: 326f ; 0a81 C from color 0x0a76 326f ; 0a95 C from color 0x0a8a 326f ; 0aa8 C from color 0x0a9e 326f ; 123b C from color 0x10f1 326f ; 123f C from color 0x1106 326f ; 125c C from color 0x1231 326f ; 1469 C from color 0x09ac 326f ; 1521 C from color 0x1521 326f ; 16ce C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 326f ; 1775 C from color 0x09ae 326f ; 17d3 C from color 0x0a32 326f ; 17e1 C from color 0x0a7c 326f ; 17e5 C from color 0x0a90 326f ; 17e9 C from color MACRO_Execute_Variant_Record,Check_In_Type 326f ; 17ef C from color 0x0aa4 326f ; 1847 C from color 0x1847 326f ; 184b C from color 0x09ab 326f ; 19ec C from color 0x19e9 326f ; 1af3 C from color 0x0aa1 326f ; 1b75 C from color 0x09aa 326f ; 1c03 C from color 0x0aa0 326f ; 1de3 C from color 0x1d69 326f ; 1e72 C False from color MACRO_Execute_Matrix,Structure_Write 326f ; 1e76 C False from color MACRO_Execute_Matrix,Structure_Write 326f ; 1eab C from color 0x1eab 326f ; 23ce C from color 0x23c4 326f ; 23e2 C from color 0x23c4 326f ; 24ba C from color 0x24ba 326f ; 24c4 C from color 0x24ba 326f ; 3638 C from color 0x108b 326f ; -------------------------------------------------------------------------------------- 326f 326f seq_en_micro 0 typ_c_adr 36 GP09 3270 3270 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a9 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3271 3271 ioc_fiubs 2 typ ; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3272 0x3272 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 3272 3272 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32a9 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 3273 3273 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32d9 seq_branch_adr 32d9 0x32d9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_b_adr 09 GP09 3274 ; -------------------------------------------------------------------------------------- 3274 ; Comes from: 3274 ; 0503 C from color 0x04fa 3274 ; 1fa5 C from color 0x1f9b 3274 ; 2232 C from color 0x2228 3274 ; -------------------------------------------------------------------------------------- 3274 3274 seq_en_micro 0 typ_c_adr 36 GP09 3275 3275 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3279 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 09 GP09 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3276 3276 ioc_fiubs 2 typ ; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3277 0x3277 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS 3277 3277 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x3279 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3279 0x3279 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU 3278 3278 seq_br_type 8 Return True; Flow R cc=True ; Flow J cc=False 0x32d9 seq_branch_adr 32d9 0x32d9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_b_adr 09 GP09 3279 3279 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32a9 seq_br_type 9 Return False seq_branch_adr 32a9 0x32a9 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_b_adr 0c GP0c 327a ; -------------------------------------------------------------------------------------- 327a ; 0x0001-0x0006 Illegal - 327a ; 0x0009-0x000f Illegal - 327a ; -------------------------------------------------------------------------------------- 327a MACRO_Illegal_-: 327a 327a dispatch_brk_class f ; Flow C 0x32dd dispatch_csa_free 3 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 327a seq_br_type 7 Unconditional Call seq_branch_adr 32dd 0x32dd 327b 327b <halt> ; Flow R 327c ; -------------------------------------------------------------------------------------- 327c ; 0x0007 Action Break_Optional 327c ; -------------------------------------------------------------------------------------- 327c MACRO_Action_Break_Optional: 327c 327c dispatch_brk_class 7 ; Flow R dispatch_csa_free 3 dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 327c fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 327d 327d <halt> ; Flow R 327e ; -------------------------------------------------------------------------------------- 327e ; 0x0107 Execute Exception,Get_Name 327e ; -------------------------------------------------------------------------------------- 327e MACRO_Execute_Exception,Get_Name: 327e 327e dispatch_brk_class 8 ; Flow R dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 327e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 1c ? typ_a_adr 10 TOP typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU 327f 327f <halt> ; Flow R 3280 ; -------------------------------------------------------------------------------------- 3280 ; 0x0106 Execute Exception,Address 3280 ; -------------------------------------------------------------------------------------- 3280 MACRO_Execute_Exception,Address: 3280 3280 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3280 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 2a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 10 TOP typ_c_lit 0 typ_frame 1e typ_rand b CARRY IN = Q BIT FROM VAL val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3281 3281 fiu_len_fill_lit 7b zero-fill 0x3b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value val_alu_func 1e A_AND_B val_b_adr 37 VR0d:17 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame d 3282 3282 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 0 PASS_A val_c_adr 2f TOP val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3283 3283 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3285 seq_br_type 1 Branch True seq_branch_adr 3285 0x3285 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 3284 3284 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU val_frame 2 3285 3285 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3286 ; -------------------------------------------------------------------------------------- 3286 ; 0x010e Execute Exception,Is_Constraint_Error 3286 ; -------------------------------------------------------------------------------------- 3286 MACRO_Execute_Exception,Is_Constraint_Error: 3286 3286 dispatch_brk_class 8 ; Flow J 0x3287 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3286 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3284 0x3284 typ_alu_func 1a PASS_B typ_b_adr 20 TR05:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 2d VR1b:0d val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 1b 3287 3287 ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3283 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3283 0x3283 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 2c VR08:0c val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 3288 ; -------------------------------------------------------------------------------------- 3288 ; 0x010d Execute Exception,Is_Numeric_Error 3288 ; -------------------------------------------------------------------------------------- 3288 MACRO_Execute_Exception,Is_Numeric_Error: 3288 3288 dispatch_brk_class 8 ; Flow J 0x3289 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3288 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3284 0x3284 typ_alu_func 1a PASS_B typ_b_adr 31 TR11:11 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 35 VR08:15 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 3289 3289 ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3283 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3283 0x3283 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 2d VR08:0d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 328a ; -------------------------------------------------------------------------------------- 328a ; 0x010c Execute Exception,Is_Program_Error 328a ; -------------------------------------------------------------------------------------- 328a MACRO_Execute_Exception,Is_Program_Error: 328a 328a dispatch_brk_class 8 ; Flow J 0x328b dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 328a fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3284 0x3284 typ_alu_func 1a PASS_B typ_b_adr 30 TR11:10 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 30 VR05:10 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 5 328b 328b ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3283 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3283 0x3283 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 2e VR08:0e val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 328c ; -------------------------------------------------------------------------------------- 328c ; 0x010b Execute Exception,Is_Storage_Error 328c ; -------------------------------------------------------------------------------------- 328c MACRO_Execute_Exception,Is_Storage_Error: 328c 328c dispatch_brk_class 8 ; Flow J 0x328d dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 328c fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3284 0x3284 typ_alu_func 1a PASS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 36 VR08:16 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 328d 328d ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3283 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3283 0x3283 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 2f VR08:0f val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 328e ; -------------------------------------------------------------------------------------- 328e ; 0x010a Execute Exception,Is_Tasking_Error 328e ; -------------------------------------------------------------------------------------- 328e MACRO_Execute_Exception,Is_Tasking_Error: 328e 328e dispatch_brk_class 8 ; Flow J 0x328f dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 328e fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3284 0x3284 typ_alu_func 1a PASS_B typ_b_adr 2d TR08:0d typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 37 VR08:17 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 8 328f 328f ioc_fiubs 0 fiu ; Flow R cc=True ; Flow J cc=False 0x3283 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3283 0x3283 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 30 VR08:10 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 8 3290 ; -------------------------------------------------------------------------------------- 3290 ; 0x0109 Execute Exception,Is_Instruction_Error 3290 ; -------------------------------------------------------------------------------------- 3290 MACRO_Execute_Exception,Is_Instruction_Error: 3290 3290 dispatch_brk_class 8 dispatch_csa_free 1 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3290 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 30 TR05:10 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 3291 3291 ioc_fiubs 0 fiu ; Flow J 0x3283 seq_br_type 3 Unconditional Branch seq_branch_adr 3283 0x3283 typ_b_adr 10 TOP typ_c_adr 3d GP02 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3292 ; -------------------------------------------------------------------------------------- 3292 ; 0x010f Execute Exception,Equal 3292 ; -------------------------------------------------------------------------------------- 3292 MACRO_Execute_Exception,Equal: 3292 3292 dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 3292 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 3293 3293 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_c_adr 2f TOP typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_source 0 FIU_BUS val_rand 3 CONDITION_TO_FIU 3294 ; -------------------------------------------------------------------------------------- 3294 ; 0x0257 Execute Discrete,Raise,>R 3294 ; -------------------------------------------------------------------------------------- 3294 MACRO_Execute_Discrete,Raise,>R: 3294 3294 dispatch_brk_class 1 dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3294 typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL 3295 3295 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 1d ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3296 3296 seq_br_type 7 Unconditional Call; Flow C 0x32f6 seq_branch_adr 32f6 0x32f6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 typ_csa_cntl 3 POP_CSA val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_frame 4 3297 3297 <halt> ; Flow R 3298 ; -------------------------------------------------------------------------------------- 3298 ; 0x0800-0x08ff Execute_Immediate Raise,uimmediate,>R 3298 ; -------------------------------------------------------------------------------------- 3298 MACRO_Execute_Immediate_Raise,uimmediate,>R: 3298 3298 dispatch_brk_class 1 dispatch_csa_free 1 dispatch_csa_valid 0 dispatch_ibuff_fill 1 dispatch_uadr 3298 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 1d ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 36 VR05:16 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3299 3299 ioc_fiubs 1 val ; Flow C 0x32f6 seq_br_type 7 Unconditional Call seq_branch_adr 32f6 0x32f6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 seq_random 02 ? val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 329a ; -------------------------------------------------------------------------------------- 329a ; Comes from: 329a ; 39b2 C from color 0x39a6 329a ; -------------------------------------------------------------------------------------- 329a 329a fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 329b 329b ioc_fiubs 1 val ; Flow J 0x32f6 seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 329c ; -------------------------------------------------------------------------------------- 329c ; Comes from: 329c ; 0342 C from color MACRO_Action_Increase_Priority 329c ; 1d61 C from color 0x1d61 329c ; 1d63 C from color 0x1d63 329c ; -------------------------------------------------------------------------------------- 329c 329c fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3b VR09:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 329d 329d fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2c VR08:0c val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 329e ; -------------------------------------------------------------------------------------- 329e ; Comes from: 329e ; 0328 C from color MACRO_Action_Set_Priority 329e ; 0334 C from color 0x0331 329e ; 090a C from color 0x0905 329e ; 0b04 C from color MACRO_Declare_Variable_Task,On_Processor 329e ; 0b0a C from color MACRO_Declare_Variable_Task,Visible,On_Processor 329e ; 0b18 C from color MACRO_Declare_Variable_Task,On_Processor,As_Component 329e ; 0b24 C from color MACRO_Declare_Variable_Package,On_Processor 329e ; 0b2b C from color MACRO_Declare_Variable_Package,Visible,On_Processor 329e ; 0b3c C from color 0x0b38 329e ; 0c67 C from color 0x0c67 329e ; 0e72 C from color 0x0e70 329e ; 0e74 C from color 0x0e73 329e ; 0e8a C from color 0x0e8a 329e ; 0f0a C from color 0x0f09 329e ; 0f14 C from color 0x0f14 329e ; 115f C from color 0x113f 329e ; 116a C from color 0x113f 329e ; 116d C from color 0x113f 329e ; 1d91 C from color 0x1cc6 329e ; 1da6 C from color 0x1d5a 329e ; 1db6 C from color 0x1d5b 329e ; 1db7 C from color 0x1db7 329e ; 23a7 C from color 0x23a1 329e ; 2449 C from color 0x2445 329e ; 2857 C from color 0x0a2b 329e ; 2970 C from color MACRO_Action_Push_String_Extended_Indexed,pse 329e ; 2c11 C from color 0x2c11 329e ; 2c18 C from color 0x2c12 329e ; 2cd0 C from color MACRO_Execute_Select,Timed_Duration_Write 329e ; 2ffd C from color MACRO_Execute_Discrete,Successor 329e ; 3003 C from color 0x2ffe 329e ; 3005 C from color MACRO_Execute_Discrete,Predecessor 329e ; 3022 C from color MACRO_Execute_Any,Convert 329e ; 307e C from color MACRO_Execute_Discrete,Insert_Bits 329e ; 307f C from color 0x307f 329e ; 3083 C from color MACRO_Execute_Discrete,Extract_Bits 329e ; 3084 C from color MACRO_Execute_Discrete,Extract_Bits 329e ; 3087 C from color MACRO_Execute_Discrete,Extract_Bits 329e ; 30c5 C from color 0x30be 329e ; 30c6 C from color 0x30be 329e ; 30f9 C from color 0x30f2 329e ; 30fa C from color 0x30f2 329e ; 3103 C from color MACRO_Declare_Variable_Float,With_Value,With_Constraint 329e ; 3108 C from color MACRO_Declare_Variable_Float,With_Value,With_Constraint 329e ; 3109 C from color 0x3109 329e ; 313b C from color 0x313b 329e ; 3146 C from color 0x3146 329e ; 319e C from color MACRO_Execute_Immediate_Set_Value,uimmediate 329e ; 3606 C from color 0x35f7 329e ; 360b C from color 0x360b 329e ; -------------------------------------------------------------------------------------- 329e 329e fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 329f ; -------------------------------------------------------------------------------------- 329f ; Comes from: 329f ; 3247 C from color MACRO_Execute_Discrete,Remainder 329f ; -------------------------------------------------------------------------------------- 329f 329f fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 32a0 32a0 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 32a1 ; -------------------------------------------------------------------------------------- 32a1 ; Comes from: 32a1 ; 0c20 C True from color MACRO_Execute_Heap_Access,Element_Type 32a1 ; 0c2a C True from color MACRO_Execute_Heap_Access,All_Write 32a1 ; 0c30 C True from color MACRO_Execute_Heap_Access,All_Reference 32a1 ; 1b10 C True from color MACRO_Execute_Access,Element_Type 32a1 ; 1b1a C True from color MACRO_Execute_Access,All_Write 32a1 ; 1b20 C True from color MACRO_Execute_Access,All_Reference 32a1 ; 3611 C True from color 0x3611 32a1 ; 3635 C True from color 0x108b 32a1 ; -------------------------------------------------------------------------------------- 32a1 32a1 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3e VR03:1e val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 3 32a2 ; -------------------------------------------------------------------------------------- 32a2 ; Comes from: 32a2 ; 0508 C from color 0x04fa 32a2 ; 0c4e C from color 0x0a35 32a2 ; 1177 C False from color 0x113f 32a2 ; 11a5 C True from color 0x114d 32a2 ; 11a9 C from color 0x114d 32a2 ; 11ac C True from color 0x114d 32a2 ; 11ad C True from color 0x114d 32a2 ; 11c5 C False from color 0x114d 32a2 ; 11ea C from color 0x114d 32a2 ; 11ef C False from color 0x114d 32a2 ; 11f9 C False from color 0x114d 32a2 ; 1244 C False from color 0x1106 32a2 ; 1248 C from color 0x1106 32a2 ; 1269 C True from color 0x1231 32a2 ; 12ac C False from color 0x1106 32a2 ; 12d7 C True from color 0x128f 32a2 ; 12d8 C True from color 0x128f 32a2 ; 13b3 C False from color MACRO_Declare_Variable_Array,With_Constraint 32a2 ; 13b4 C False from color MACRO_Declare_Variable_Array,With_Constraint 32a2 ; 13d9 C False from color MACRO_Declare_Variable_Array,With_Constraint 32a2 ; 13da C False from color MACRO_Declare_Variable_Array,With_Constraint 32a2 ; 13fe C False from color MACRO_Declare_Variable_Array,With_Constraint 32a2 ; 13ff C False from color MACRO_Declare_Variable_Array,With_Constraint 32a2 ; 1449 C True from color 0x1441 32a2 ; 144c C True from color 0x1441 32a2 ; 145b C True from color 0x1441 32a2 ; 14eb C from color 0x0aa2 32a2 ; 1529 C True from color MACRO_Execute_Matrix,Field_Write 32a2 ; 152e C from color MACRO_Execute_Matrix,Field_Write 32a2 ; 152f C True from color MACRO_Execute_Matrix,Field_Write 32a2 ; 1532 C True from color MACRO_Execute_Matrix,Field_Write 32a2 ; 1538 C from color 0x1538 32a2 ; 1566 C True from color 0x1561 32a2 ; 156d C True from color 0x1561 32a2 ; 1576 C True from color 0x1561 32a2 ; 157e C True from color 0x1561 32a2 ; 1619 C True from color MACRO_Execute_Matrix,Subarray 32a2 ; 161c C True from color MACRO_Execute_Matrix,Subarray 32a2 ; 16e4 C False from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32a2 ; 1743 C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32a2 ; 1744 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32a2 ; 18e2 C True from color MACRO_Execute_Vector,Field_Read 32a2 ; 18eb C from color MACRO_Execute_Vector,Field_Read 32a2 ; 18f0 C True from color MACRO_Execute_Vector,Field_Read 32a2 ; 18f2 C True from color MACRO_Execute_Vector,Field_Read 32a2 ; 18fa C from color MACRO_Execute_Vector,Field_Write 32a2 ; 18fb C True from color MACRO_Execute_Vector,Field_Write 32a2 ; 1904 C from color MACRO_Execute_Vector,Field_Write 32a2 ; 1909 C True from color MACRO_Execute_Vector,Field_Write 32a2 ; 190b C True from color MACRO_Execute_Vector,Field_Write 32a2 ; 1914 C from color MACRO_Execute_Vector,Field_Reference 32a2 ; 191e C False from color MACRO_Execute_Vector,Field_Reference 32a2 ; 1924 C False from color MACRO_Execute_Vector,Field_Reference 32a2 ; 199d C False from color MACRO_Execute_Vector,Slice_Read 32a2 ; 199e C True from color MACRO_Execute_Vector,Slice_Read 32a2 ; 19cc C False from color MACRO_Execute_Vector,Slice_Write 32a2 ; 19cd C True from color MACRO_Execute_Vector,Slice_Write 32a2 ; 1a1a C True from color MACRO_Execute_Vector,Catenate 32a2 ; 1a47 C False from color MACRO_Execute_Vector,Append 32a2 ; 1a57 C False from color MACRO_Execute_Vector,Append 32a2 ; 1a69 C False from color MACRO_Execute_Vector,Prepend 32a2 ; 1a77 C False from color MACRO_Execute_Vector,Prepend 32a2 ; 1a8d C True from color 0x0a2f 32a2 ; 1acf C from color 0x0a2f 32a2 ; 1aec C from color 0x0aa1 32a2 ; 1aee C False from color 0x0aa1 32a2 ; 1af2 C from color 0x0aa1 32a2 ; 1b3d C from color 0x0a33 32a2 ; 1bf8 C from color 0x0aa0 32a2 ; 1bfb C from color 0x0aa0 32a2 ; 1bff C from color 0x0aa0 32a2 ; 1c02 C from color 0x0aa0 32a2 ; 1cbb C True from color MACRO_Execute_Array,Subarray 32a2 ; 1dc2 C from color 0x1d5c 32a2 ; 1faa C from color 0x1f9b 32a2 ; 1fc0 C True from color MACRO_Complete_Type_Array,By_Constraining 32a2 ; 1fc4 C True from color MACRO_Complete_Type_Array,By_Constraining 32a2 ; 1fdf C True from color MACRO_Complete_Type_Array,By_Constraining 32a2 ; 1fe3 C True from color MACRO_Complete_Type_Array,By_Constraining 32a2 ; 1fe8 C True from color MACRO_Complete_Type_Array,By_Constraining 32a2 ; 1ff5 C False from color 0x1ff5 32a2 ; 2022 C True from color MACRO_Complete_Type_Array,By_Constraining 32a2 ; 2023 C True from color MACRO_Complete_Type_Array,By_Constraining 32a2 ; 217b C True from color MACRO_Declare_Type_Array,Constrained 32a2 ; 217f C True from color MACRO_Declare_Type_Array,Constrained 32a2 ; 2184 C True from color MACRO_Declare_Type_Array,Constrained 32a2 ; 2191 C True from color 0x2191 32a2 ; 21c1 C True from color MACRO_Declare_Type_Array,Constrained 32a2 ; 21c2 C True from color MACRO_Declare_Type_Array,Constrained 32a2 ; 2237 C from color 0x2228 32a2 ; -------------------------------------------------------------------------------------- 32a2 32a2 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 22 VR05:02 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 32a3 ; -------------------------------------------------------------------------------------- 32a3 ; Comes from: 32a3 ; 193f C True from color MACRO_Execute_Vector,And 32a3 ; 19d2 C True from color MACRO_Execute_Vector,Slice_Write 32a3 ; 19e1 C True from color MACRO_Execute_Vector,Slice_Write 32a3 ; 19e5 C True from color MACRO_Execute_Vector,Slice_Write 32a3 ; 19f5 C True from color MACRO_Execute_Vector,Slice_Reference 32a3 ; 19f7 C True from color MACRO_Execute_Vector,Slice_Reference 32a3 ; 1e77 C False from color MACRO_Execute_Matrix,Structure_Write 32a3 ; 1e78 C False from color MACRO_Execute_Matrix,Structure_Write 32a3 ; -------------------------------------------------------------------------------------- 32a3 32a3 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 23 VR05:03 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 32a4 ; -------------------------------------------------------------------------------------- 32a4 ; Comes from: 32a4 ; 0c4d C True from color 0x0a35 32a4 ; 119e C from color 0x119b 32a4 ; 1350 C True from color 0x1346 32a4 ; 17d1 C False from color 0x0a32 32a4 ; 17ec C from color MACRO_Execute_Variant_Record,Check_In_Type 32a4 ; 17f1 C True from color 0x0aa4 32a4 ; 1b3c C True from color 0x0a33 32a4 ; 1dc1 C True from color 0x1d5c 32a4 ; 2528 C from color 0x24ba 32a4 ; -------------------------------------------------------------------------------------- 32a4 32a4 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 24 VR05:04 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 32a5 ; -------------------------------------------------------------------------------------- 32a5 ; Comes from: 32a5 ; 1176 C True from color 0x113f 32a5 ; 1310 C True from color 0x1307 32a5 ; 1312 C True from color 0x1307 32a5 ; 1631 C from color 0x098b 32a5 ; 1666 C from color 0x165f 32a5 ; 1678 C from color 0x1677 32a5 ; 16ae C from color 0x098b 32a5 ; -------------------------------------------------------------------------------------- 32a5 32a5 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 25 VR05:05 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 32a6 ; -------------------------------------------------------------------------------------- 32a6 ; Comes from: 32a6 ; 2cad C False from color MACRO_Execute_Select,Member_Write,fieldnum 32a6 ; 2cb0 C True from color MACRO_Execute_Select,Member_Write,fieldnum 32a6 ; 2cb3 C False from color 0x2cb2 32a6 ; 2cb9 C True from color MACRO_Execute_Select,Member_Write,fieldnum 32a6 ; 2cbd C from color MACRO_Execute_Select,Member_Write,fieldnum 32a6 ; 2cc0 C from color MACRO_Execute_Select,Member_Write,fieldnum 32a6 ; 3855 C True from color 0x3833 32a6 ; -------------------------------------------------------------------------------------- 32a6 32a6 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 26 VR05:06 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 32a7 ; -------------------------------------------------------------------------------------- 32a7 ; Comes from: 32a7 ; 28e0 C True from color 0x28d6 32a7 ; 31f7 C False from color 0x31f7 32a7 ; 3203 C True from color MACRO_Execute_Discrete,Remainder 32a7 ; 3211 C True from color MACRO_Execute_Discrete,Remainder 32a7 ; 3221 C True from color MACRO_Execute_Discrete,Remainder 32a7 ; 323b C from color MACRO_Execute_Discrete,Remainder 32a7 ; -------------------------------------------------------------------------------------- 32a7 32a7 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2d VR05:0d val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 32a8 ; -------------------------------------------------------------------------------------- 32a8 ; Comes from: 32a8 ; 1160 C from color 0x113f 32a8 ; 116b C from color 0x113f 32a8 ; 116c C True from color 0x113f 32a8 ; 116e C from color 0x113f 32a8 ; 1d92 C from color 0x1cc6 32a8 ; 204c C False from color 0x2042 32a8 ; 204d C False from color 0x2042 32a8 ; 2067 C False from color 0x2042 32a8 ; 2068 C False from color 0x2042 32a8 ; 207f C False from color 0x2042 32a8 ; 2080 C False from color 0x2042 32a8 ; 20ba C False from color 0x2042 32a8 ; 20bb C False from color 0x2042 32a8 ; 20f0 C False from color 0x2042 32a8 ; 20f1 C False from color 0x2042 32a8 ; 2105 C False from color 0x2042 32a8 ; 2125 C False from color 0x2042 32a8 ; 2126 C False from color 0x2042 32a8 ; 2815 C False from color 0x2815 32a8 ; 2862 C True from color MACRO_Execute_Float,Plus 32a8 ; 28b2 C True from color MACRO_Execute_Float,Times 32a8 ; 28d9 C from color MACRO_Execute_Float,Exponentiate 32a8 ; 28ec C True from color 0x28d6 32a8 ; 28ed C True from color 0x28d6 32a8 ; 28f2 C False from color 0x28d6 32a8 ; 28fc C True from color 0x28d6 32a8 ; 2913 C from color MACRO_Execute_Float,Truncate_To_Discrete 32a8 ; 2fe9 C from color MACRO_Execute_Discrete,Unary_Minus 32a8 ; 2fed C from color MACRO_Execute_Discrete,Plus 32a8 ; 2fef C from color MACRO_Execute_Discrete,Plus 32a8 ; 2ff1 C from color MACRO_Execute_Discrete,Plus 32a8 ; 2ff3 C from color MACRO_Execute_Discrete,Plus 32a8 ; 3023 C from color 0x2ffe 32a8 ; 319f C from color 0x319f 32a8 ; -------------------------------------------------------------------------------------- 32a8 32a8 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2f VR07:0f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 32a9 ; -------------------------------------------------------------------------------------- 32a9 ; Comes from: 32a9 ; 0221 C False from color MACRO_Action_Accept_Activation 32a9 ; 0224 C False from color MACRO_Action_Accept_Activation 32a9 ; 092a C False from color 0x0921 32a9 ; 092c C False from color 0x0921 32a9 ; 092f C False from color 0x092f 32a9 ; 09d0 C from color MACRO_Execute_Any,Size 32a9 ; 09d4 C from color MACRO_Execute_Any,Size 32a9 ; 09e5 C True from color MACRO_Execute_Any,Size 32a9 ; 0a14 C from color 0x09c9 32a9 ; 0a18 C True from color 0x0a18 32a9 ; 0a1d C True from color 0x0a18 32a9 ; 0a6e C True from color 0x0a50 32a9 ; 0c12 C True from color 0x0c07 32a9 ; 10cf C from color 0x10c9 32a9 ; 10d6 C from color 0x10c9 32a9 ; 11cd C True from color 0x11ca 32a9 ; 11fc C True from color 0x114d 32a9 ; 12fc C True from color 0x12f9 32a9 ; 130a C True from color 0x1307 32a9 ; 1342 C True from color 0x133f 32a9 ; 13c4 C True from color MACRO_Declare_Variable_Array,With_Constraint 32a9 ; 13e7 C True from color MACRO_Declare_Variable_Array,With_Constraint 32a9 ; 1466 C False from color MACRO_Declare_Variable_Array,With_Constraint 32a9 ; 147b C True from color 0x09ac 32a9 ; 148f C True from color 0x09ac 32a9 ; 164b C from color 0x098b 32a9 ; 1654 C True from color 0x098b 32a9 ; 16a7 C True from color 0x098b 32a9 ; 16ab C from color 0x098b 32a9 ; 17dc C True from color 0x17db 32a9 ; 17de C True from color 0x17db 32a9 ; 181a C from color MACRO_Execute_Record,Field_Type,fieldnum 32a9 ; 181e C from color MACRO_Execute_Record,Field_Type_Dynamic 32a9 ; 183b C True from color 0x0a31 32a9 ; 183d C True from color 0x0a31 32a9 ; 1857 C True from color 0x09ab 32a9 ; 1863 C True from color 0x09ab 32a9 ; 1a0a C True from color MACRO_Execute_Vector,Catenate 32a9 ; 1a40 C True from color MACRO_Execute_Vector,Append 32a9 ; 1a64 C True from color MACRO_Execute_Vector,Prepend 32a9 ; 1a8e C True from color 0x0a2f 32a9 ; 1aa6 C True from color 0x0a2f 32a9 ; 1aa8 C True from color 0x0a2f 32a9 ; 1abc C True from color 0x0a2f 32a9 ; 1b80 C True from color 0x09aa 32a9 ; 1b91 C True from color 0x09aa 32a9 ; 1b93 C True from color 0x09aa 32a9 ; 1c5e C True from color 0x1c57 32a9 ; 1d90 C True from color 0x1cc6 32a9 ; 1ec4 C False from color MACRO_Declare_Type_Record,Defined 32a9 ; 1ec6 C False from color MACRO_Declare_Type_Record,Defined 32a9 ; 1ed2 C False from color MACRO_Declare_Type_Record,Incomplete 32a9 ; 1ed6 C True from color 0x1ed6 32a9 ; 1ee4 C True from color MACRO_Complete_Type_Record,By_Renaming 32a9 ; 1ee9 C True from color MACRO_Complete_Type_Record,By_Renaming 32a9 ; 1f11 C True from color 0x098b 32a9 ; 1f19 C True from color 0x1f17 32a9 ; 1f84 C False from color MACRO_Declare_Type_Access,Constrained 32a9 ; 1f88 C False from color MACRO_Declare_Type_Access,Constrained 32a9 ; 1f8d C True from color MACRO_Declare_Type_Access,Constrained 32a9 ; 1fb5 C from color MACRO_Complete_Type_Array,By_Constraining 32a9 ; 1fcb C from color 0x1fc9 32a9 ; 1fcf C from color 0x1fce 32a9 ; 203f C True from color 0x203c 32a9 ; 20cc C False from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible 32a9 ; 20d4 C False from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible,Bounds_With_Object 32a9 ; 20fe C True from color 0x2042 32a9 ; 2144 C False from color MACRO_Declare_Type_Array,Defined,Visible 32a9 ; 2148 C from color 0x2042 32a9 ; 214d C from color 0x2042 32a9 ; 214e C False from color 0x2042 32a9 ; 2152 C from color 0x2042 32a9 ; 2167 C from color 0x2165 32a9 ; 216b C from color 0x216a 32a9 ; 21e0 C False from color MACRO_Declare_Type_Array,Constrained 32a9 ; 21e2 C False from color MACRO_Declare_Type_Array,Constrained 32a9 ; 21e8 C False from color MACRO_Declare_Type_Array,Constrained 32a9 ; 21ea C False from color MACRO_Declare_Type_Array,Constrained 32a9 ; 220a C True from color 0x2035 32a9 ; 221a C True from color 0x2035 32a9 ; 223c C True from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 32a9 ; 223e C True from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 32a9 ; 2246 C from color 0x2035 32a9 ; 2336 C False from color MACRO_Declare_Type_Array,Incomplete 32a9 ; 233a C False from color MACRO_Declare_Type_Array,Incomplete 32a9 ; 2345 C True from color 0x233d 32a9 ; 2363 C True from color 0x2360 32a9 ; 2365 C True from color 0x2360 32a9 ; 23cd C True from color 0x23c4 32a9 ; 23f6 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a9 ; 23f8 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32a9 ; 2422 C False from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 32a9 ; 2427 C True from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 32a9 ; 2534 C False from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32a9 ; 2549 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32a9 ; 2552 C False from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32a9 ; 2561 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32a9 ; 2618 C from color 0x2611 32a9 ; 265d C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 32a9 ; 2662 C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 32a9 ; 266c C False from color 0x266c 32a9 ; 2683 C True from color 0x2680 32a9 ; 2713 C from color 0x2712 32a9 ; 2779 C False from color MACRO_Declare_Variable_Entry 32a9 ; 277d C False from color MACRO_Declare_Variable_Entry 32a9 ; 2930 C True from color 0x292f 32a9 ; 2c6d C True from color 0x2c6d 32a9 ; 2ce8 C from color MACRO_Declare_Subprogram_For_Call,subp 32a9 ; 3001 C True from color 0x2ffe 32a9 ; 3021 C True from color MACRO_Execute_Any,Convert 32a9 ; 3030 C True from color 0x302f 32a9 ; 3042 C True from color MACRO_Execute_Discrete,Test_And_Set_Previous 32a9 ; 30e1 C True from color 0x30db 32a9 ; 30e5 C True from color 0x30db 32a9 ; 30ed C True from color 0x30db 32a9 ; 30ee C True from color 0x30db 32a9 ; 3173 C True from color 0x3163 32a9 ; 3178 C True from color 0x3163 32a9 ; 319d C True from color MACRO_Execute_Immediate_Set_Value,uimmediate 32a9 ; 3338 C from color 0x0921 32a9 ; 333c C from color 0x0921 32a9 ; 3340 C from color 0x0921 32a9 ; 3397 C True from color 0x0921 32a9 ; 361b C from color 0x108b 32a9 ; -------------------------------------------------------------------------------------- 32a9 32a9 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 25 VR08:05 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32aa 32aa fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2f VR05:0f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 32ab 32ab fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2f VR06:0f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 32ac ; -------------------------------------------------------------------------------------- 32ac ; Comes from: 32ac ; 0f52 C True from color 0x0f29 32ac ; -------------------------------------------------------------------------------------- 32ac 32ac fiu_len_fill_lit 4a zero-fill 0xa fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 05 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 32ad 32ad fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x37a2 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_br_type 0 Branch False seq_branch_adr 37a2 0x37a2 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 7 INC_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 20 VR0d:00 val_frame d 32ae 32ae ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B 32af 32af seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x32b1 seq_br_type 1 Branch True seq_branch_adr 32b1 0x32b1 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1e A_AND_B typ_b_adr 3b TR05:1b typ_frame 5 32b0 32b0 seq_br_type 3 Unconditional Branch; Flow J 0x32af seq_branch_adr 32af 0x32af seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1c DEC_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_csa_cntl 4 DEC_CSA_BOTTOM typ_rand 0 NO_OP 32b1 32b1 fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 32b2 32b2 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? 32b3 32b3 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 32b4 32b4 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 2a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_a_adr 14 ZEROS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 32b5 32b5 ioc_tvbs 2 fiu+val; Flow J cc=True 0x32bc seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32bc 0x32bc seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 32b6 32b6 ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 32b7 32b7 seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 6a ? typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 2a TR08:0a typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 8 typ_rand 6 CHECK_CLASS_A_??_B 32b8 32b8 ioc_fiubs 2 typ ; Flow J cc=True 0x32be seq_br_type 1 Branch True seq_branch_adr 32be 0x32be seq_cond_sel 20 TYP.ALU_CARRY(late) seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 32b9 32b9 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 32ba 32ba ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 02 GP02 32bb 32bb fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3321 fiu_offs_lit 48 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3321 0x3321 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 32bc 32bc ioc_adrbs 2 typ ioc_fiubs 2 typ seq_random 0f Load_control_top+? typ_a_adr 3e TR09:1e typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_frame 9 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 32bd 32bd seq_br_type 3 Unconditional Branch; Flow J 0x32f8 seq_branch_adr 32f8 0x32f8 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_csa_cntl 7 FINISH_POP_DOWN 32be 32be fiu_load_tar 1 hold_tar; Flow C cc=False 0x32c8 fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32c8 0x32c8 seq_cond_sel 3a TYP.D_BUS_BIT_33_34_OR_36 (med_late) seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_b_adr 22 TR02:02 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 32bf 32bf fiu_mem_start 4 continue ioc_tvbs 2 fiu+val seq_random 0a ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT 32c0 32c0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 32c1 32c1 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU 32c2 32c2 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 48 Load_current_lex+? typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN typ_rand 0 NO_OP val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 32c3 32c3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 09 GP09 val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 32c4 32c4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x32c5 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 32be 0x32be seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? 32c5 32c5 ioc_fiubs 2 typ ; Flow J cc=True 0x32bc seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 32bc 0x32bc seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 0f Load_control_top+? typ_a_adr 02 GP02 val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 32c6 32c6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x32b9 seq_br_type 0 Branch False seq_branch_adr 32b9 0x32b9 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_a_adr 02 GP02 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 04 GP04 val_b_adr 03 GP03 32c7 32c7 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 32c8 ; -------------------------------------------------------------------------------------- 32c8 ; Comes from: 32c8 ; 32be C False from color 0x0000 32c8 ; -------------------------------------------------------------------------------------- 32c8 32c8 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 32c9 32c9 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type a Unconditional Return seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 32ca 32ca seq_br_type 3 Unconditional Branch; Flow J 0x32b1 seq_branch_adr 32b1 0x32b1 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 32cb ; -------------------------------------------------------------------------------------- 32cb ; Comes from: 32cb ; 0f62 C True from color 0x0f29 32cb ; 2074 C True from color 0x2042 32cb ; 211a C True from color 0x2042 32cb ; -------------------------------------------------------------------------------------- 32cb 32cb fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 34 VR06:14 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 32cc ; -------------------------------------------------------------------------------------- 32cc ; Comes from: 32cc ; 0f75 C True from color 0x0f29 32cc ; 12fb C False from color 0x12f9 32cc ; 1301 C from color 0x12f9 32cc ; 1309 C False from color 0x1307 32cc ; 1316 C from color 0x1307 32cc ; 1341 C False from color 0x133f 32cc ; 13c3 C from color MACRO_Declare_Variable_Array,With_Constraint 32cc ; 13ca C False from color 0x13c9 32cc ; 1418 C from color MACRO_Declare_Variable_Array,With_Constraint 32cc ; 141c C False from color MACRO_Declare_Variable_Array,With_Constraint 32cc ; 1425 C False from color MACRO_Declare_Variable_Array,With_Constraint 32cc ; 1438 C from color MACRO_Declare_Variable_Array,With_Constraint 32cc ; 143e C from color 0x143c 32cc ; 1655 C from color 0x098b 32cc ; 16a8 C from color 0x098b 32cc ; 17dd C from color 0x17db 32cc ; 183c C from color 0x0a31 32cc ; 199c C False from color MACRO_Execute_Vector,Slice_Read 32cc ; 19a9 C from color MACRO_Execute_Vector,Slice_Read 32cc ; 19ad C False from color MACRO_Execute_Vector,Slice_Read 32cc ; 19b7 C False from color MACRO_Execute_Vector,Slice_Read 32cc ; 1a41 C False from color MACRO_Execute_Vector,Append 32cc ; 1a4b C False from color MACRO_Execute_Vector,Append 32cc ; 1a50 C False from color MACRO_Execute_Vector,Append 32cc ; 1a65 C False from color MACRO_Execute_Vector,Prepend 32cc ; 1a68 C False from color MACRO_Execute_Vector,Prepend 32cc ; 1a6d C False from color MACRO_Execute_Vector,Prepend 32cc ; 1a72 C False from color MACRO_Execute_Vector,Prepend 32cc ; 1a91 C False from color 0x0a2f 32cc ; 1aab C False from color 0x0a2f 32cc ; 1aad C False from color 0x0a2f 32cc ; 1ac3 C False from color 0x0a2f 32cc ; 1c66 C False from color 0x1c57 32cc ; 1c67 C False from color 0x1c57 32cc ; 1f10 C from color 0x098b 32cc ; 1f13 C from color 0x098b 32cc ; 1f1a C False from color 0x1f17 32cc ; 1f63 C True from color 0x098b 32cc ; 1f71 C True from color 0x098b 32cc ; 275e C True from color 0x272c 32cc ; 2769 C True from color 0x272c 32cc ; -------------------------------------------------------------------------------------- 32cc 32cc fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3a VR06:1a val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 6 32cd 32cd fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR07:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 32ce ; -------------------------------------------------------------------------------------- 32ce ; Comes from: 32ce ; 0f6b C True from color 0x0f29 32ce ; -------------------------------------------------------------------------------------- 32ce 32ce fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR07:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 32cf 32cf fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3e VR07:1e val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 32d0 ; -------------------------------------------------------------------------------------- 32d0 ; Comes from: 32d0 ; 35c9 C False from color 0x35c9 32d0 ; -------------------------------------------------------------------------------------- 32d0 32d0 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR09:1c val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32d1 32d1 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2d VR13:0d val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 13 32d2 ; -------------------------------------------------------------------------------------- 32d2 ; Comes from: 32d2 ; 1104 C from color 0x1104 32d2 ; 11f2 C False from color 0x114d 32d2 ; 11fd C False from color 0x114d 32d2 ; 1262 C False from color 0x1231 32d2 ; 1300 C True from color 0x12f9 32d2 ; 1315 C True from color 0x1307 32d2 ; 13bc C from color MACRO_Declare_Variable_Array,With_Constraint 32d2 ; 1406 C from color MACRO_Declare_Variable_Array,With_Constraint 32d2 ; 1437 C True from color MACRO_Declare_Variable_Array,With_Constraint 32d2 ; 143d C True from color 0x143c 32d2 ; 1f12 C True from color 0x098b 32d2 ; -------------------------------------------------------------------------------------- 32d2 32d2 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3e VR09:1e val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32d3 ; -------------------------------------------------------------------------------------- 32d3 ; Comes from: 32d3 ; 0b5b C True from color 0x0b53 32d3 ; -------------------------------------------------------------------------------------- 32d3 32d3 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR08:1c val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32d4 ; -------------------------------------------------------------------------------------- 32d4 ; Comes from: 32d4 ; 0215 C True from color MACRO_Action_Accept_Activation 32d4 ; 0217 C True from color MACRO_Action_Accept_Activation 32d4 ; 022c C True from color MACRO_Action_Signal_Activated 32d4 ; 0230 C from color MACRO_Action_Signal_Activated 32d4 ; 397a C True from color 0x0913 32d4 ; 3986 C True from color 0x06b7 32d4 ; 3998 C False from color 0x03fa 32d4 ; -------------------------------------------------------------------------------------- 32d4 32d4 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR09:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32d5 32d5 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR09:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32d6 32d6 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 31 VR09:11 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32d7 ; -------------------------------------------------------------------------------------- 32d7 ; Comes from: 32d7 ; 01a9 C from color UE_CLASS 32d7 ; 03fc C from color 0x03f9 32d7 ; 04b5 C from color 0x04b0 32d7 ; 04d1 C from color 0x04b0 32d7 ; 0525 C from color 0x0525 32d7 ; 053f C from color MACRO_Action_Swap_Control 32d7 ; 0540 C from color MACRO_Action_Spare6_Action 32d7 ; 0542 C from color 0x0541 32d7 ; 054f C from color MACRO_Action_Pop_Auxiliary 32d7 ; 055a C from color MACRO_Action_Pop_Auxiliary_Range 32d7 ; 090c C from color 0x090b 32d7 ; 0917 C from color 0x0917 32d7 ; 0920 C from color MACRO_Execute_Module,Elaborate 32d7 ; 0928 C from color MACRO_Execute_Module,Check_Elaborated 32d7 ; 092e C from color MACRO_Execute_Module,Activate 32d7 ; 0932 C from color 0x092f 32d7 ; 094a C from color 0x0921 32d7 ; 0950 C from color MACRO_Execute_Module,Is_Callable 32d7 ; 095e C from color MACRO_Execute_Module,Is_Terminated 32d7 ; 096d C from color MACRO_0966_QQUnknown_InMicrocode 32d7 ; 0972 C from color MACRO_Execute_Module,Get_Name 32d7 ; 0983 C from color MACRO_Declare_Variable_Any 32d7 ; 0993 C from color MACRO_Declare_Variable_Any,Visible 32d7 ; 09a5 C from color MACRO_Execute_Any,Equal 32d7 ; 09a8 C from color 0x09a8 32d7 ; 09a9 C from color 0x09a9 32d7 ; 09b5 C from color MACRO_Execute_Any,Not_Equal 32d7 ; 09b8 C from color 0x09b8 32d7 ; 09b9 C from color 0x09b9 32d7 ; 09ca C from color MACRO_Execute_Any,Address_Of_Type 32d7 ; 09cd C from color MACRO_Execute_Any,Size 32d7 ; 09f8 C from color MACRO_Execute_Any,Change_Utility 32d7 ; 09fa C from color 0x09f9 32d7 ; 09fc C from color 0x09fb 32d7 ; 0a03 C from color MACRO_Execute_Any,Make_Visible 32d7 ; 0a05 C from color MACRO_0a04_QQUnknown_InMicrocode 32d7 ; 0a0a C from color MACRO_Execute_Any,Is_Constrained 32d7 ; 0a0d C from color MACRO_Execute_Any,Make_Constrained 32d7 ; 0a0e C from color MACRO_Execute_Any,Make_Aligned 32d7 ; 0a10 C from color 0x0a0f 32d7 ; 0a16 C from color MACRO_Execute_Any,Make_Root_Type 32d7 ; 0a17 C from color 0x0a17 32d7 ; 0a1f C from color 0x0a1f 32d7 ; 0a22 C from color MACRO_Execute_Any,Is_Value 32d7 ; 0a24 C from color MACRO_Execute_Any,Is_Scalar 32d7 ; 0a29 C from color MACRO_Execute_Any,Convert 32d7 ; 0a2c C from color 0x0a2c 32d7 ; 0a2d C from color 0x0a2d 32d7 ; 0a3b C from color MACRO_Execute_Any,Convert 32d7 ; 0a3e C from color 0x0a3e 32d7 ; 0a3f C from color 0x0a3f 32d7 ; 0a4d C from color MACRO_Execute_Any,Convert_Unchecked 32d7 ; 0a51 C from color 0x0a50 32d7 ; 0a5e C from color 0x0a59 32d7 ; 0a73 C from color 0x0a50 32d7 ; 0a87 C from color 0x0a50 32d7 ; 0a9b C from color MACRO_Execute_Any,Convert 32d7 ; 0aab C from color 0x0aab 32d7 ; 0aae C from color 0x0aae 32d7 ; 0ab8 C from color MACRO_Execute_Any,Structure_Query 32d7 ; 0ae2 C from color MACRO_Execute_Any,Has_Default_Initialization 32d7 ; 0ae4 C from color 0x0ae3 32d7 ; 0ae6 C from color MACRO_Execute_Any,Has_Repeated_Initialization 32d7 ; 0ae8 C from color MACRO_Execute_Any,Is_Initialization_Repeated 32d7 ; 0ae9 C from color 0x0ae9 32d7 ; 0aea C from color MACRO_Execute_Any,Spare14 32d7 ; 0aeb C from color 0x0aeb 32d7 ; 0b3f C from color 0x0b3d 32d7 ; 0b46 C from color 0x0b32 32d7 ; 0b4a C from color 0x0b4a 32d7 ; 0c0f C from color 0x0c07 32d7 ; 0c10 C from color 0x0c10 32d7 ; 0d6c C from color 0x0d6b 32d7 ; 0d80 C from color 0x0d7f 32d7 ; 0e6d C from color 0x0e6b 32d7 ; 0e76 C from color 0x0e75 32d7 ; 0e77 C from color 0x0e77 32d7 ; 0e9e C from color 0x0e8e 32d7 ; 0e9f C from color 0x0e9f 32d7 ; 12f8 C from color 0x099c 32d7 ; 1304 C from color 0x098c 32d7 ; 1306 C from color MACRO_Declare_Variable_Variant_Record,Visible,With_Constraint 32d7 ; 133c C from color MACRO_Declare_Variable_Variant_Record,With_Constraint 32d7 ; 133e C from color MACRO_Declare_Variable_Variant_Record,Duplicate 32d7 ; 136c C from color 0x0998 32d7 ; 1370 C from color MACRO_Declare_Variable_Array,Duplicate 32d7 ; 1802 C from color MACRO_Execute_Any,Set_Constraint 32d7 ; 1b00 C from color 0x1b00 32d7 ; 1d34 C from color 0x1cc6 32d7 ; 1d36 C from color MACRO_Execute_Package,Field_Write_Dynamic 32d7 ; 1d3b C from color MACRO_Execute_Package,Field_Write,fieldnum 32d7 ; 1d4b C from color 0x1cc6 32d7 ; 1eb3 C from color MACRO_Declare_Type_Record,Defined 32d7 ; 1ed5 C from color MACRO_Complete_Type_Record,By_Defining 32d7 ; 1f06 C from color 0x099b 32d7 ; 1f14 C from color 0x098b 32d7 ; 1f16 C from color MACRO_Declare_Variable_Record,Duplicate 32d7 ; 203b C from color MACRO_Complete_Type_Array,By_Defining 32d7 ; 2040 C from color 0x203c 32d7 ; 2056 C from color 0x2042 32d7 ; 208d C from color 0x2042 32d7 ; 209c C from color MACRO_Declare_Type_Array,Defined_Incomplete 32d7 ; 20c4 C from color 0x2042 32d7 ; 20cd C from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible 32d7 ; 20d0 C from color 0x20cf 32d7 ; 20d5 C from color MACRO_Declare_Type_Array,Defined_Incomplete,Visible,Bounds_With_Object 32d7 ; 20fc C from color MACRO_Declare_Type_Array,Defined 32d7 ; 2110 C from color 0x2042 32d7 ; 2133 C from color 0x2042 32d7 ; 2136 C from color 0x2042 32d7 ; 2145 C from color MACRO_Declare_Type_Array,Defined,Visible 32d7 ; 214a C from color MACRO_Declare_Type_Array,Defined,Bounds_With_Object 32d7 ; 214f C from color 0x2042 32d7 ; 21f1 C from color 0x2035 32d7 ; 21f2 C from color 0x21f2 32d7 ; 233c C from color MACRO_Complete_Type_Array,By_Component_Completion 32d7 ; 235f C from color MACRO_Complete_Type_Array,By_Renaming 32d7 ; 2568 C from color MACRO_Complete_Type_Variant_Record,By_Defining 32d7 ; 25a5 C from color MACRO_Complete_Type_Variant_Record,By_Defining 32d7 ; 25a6 C from color 0x25a6 32d7 ; 2670 C from color 0x266c 32d7 ; 2676 C from color 0x266c 32d7 ; 26eb C from color 0x26e8 32d7 ; 2710 C from color 0x26e8 32d7 ; 292e C from color MACRO_Execute_Float,Write_Unchecked 32d7 ; 2b18 C from color MACRO_Declare_Type_Access,Defined 32d7 ; 2b1d C from color MACRO_Declare_Type_Access,Defined,Visible 32d7 ; 2b20 C from color MACRO_Declare_Type_Access,Defined,Accesses_Protected 32d7 ; 2b25 C from color MACRO_Declare_Type_Access,Defined,Visible,Accesses_Protected 32d7 ; 2b2e C from color 0x2b2b 32d7 ; 2b61 C from color 0x2b4d 32d7 ; 2b88 C from color MACRO_Declare_Type_Package,Defined 32d7 ; 2bb3 C from color MACRO_Action_Load_Dynamic 32d7 ; 2c08 C from color MACRO_Action_Load_Dynamic 32d7 ; 2c0a C from color MACRO_Execute_Package,Field_Read_Dynamic 32d7 ; 2c10 C from color MACRO_Action_Load_Dynamic 32d7 ; 2c17 C from color 0x2c12 32d7 ; 2c35 C from color MACRO_Execute_Package,Field_Execute_Dynamic 32d7 ; 2c3a C from color MACRO_Execute_Immediate_Run_Utility,uimmediate 32d7 ; 2c3b C from color 0x2c3b 32d7 ; 2c46 C from color MACRO_Execute_Any,Run_Initialization_Utility 32d7 ; 2c47 C from color 0x2c47 32d7 ; 2c7e C from color 0x2c7e 32d7 ; 2c8b C from color 0x2c8b 32d7 ; 2c8f C from color MACRO_Execute_Package,Field_Reference,fieldnum 32d7 ; 2c97 C from color 0x2c97 32d7 ; 2c9c C from color MACRO_Execute_Package,Field_Reference_Dynamic 32d7 ; 2d06 C from color MACRO_Action_Elaborate_Subprogram 32d7 ; 2d0a C from color MACRO_Action_Check_Subprogram_Elaborated 32d7 ; 2d43 C from color 0x2d43 32d7 ; 302e C from color MACRO_Execute_Discrete,Write_Unchecked 32d7 ; 30b9 C from color 0x30b9 32d7 ; 30da C from color MACRO_Complete_Type_Float,By_Defining 32d7 ; 3110 C from color 0x310c 32d7 ; 3111 C from color 0x310c 32d7 ; 3113 C from color 0x310c 32d7 ; 3162 C from color MACRO_Complete_Type_Discrete,By_Defining 32d7 ; 316a C from color 0x3163 32d7 ; 31ad C from color MACRO_Declare_Type_Heap_Access,Defined 32d7 ; 31b0 C from color MACRO_Declare_Type_Heap_Access,Defined 32d7 ; 31b5 C from color 0x31b4 32d7 ; 3243 C from color MACRO_Jump_Nonzero_pcrel,>JC 32d7 ; 3253 C from color MACRO_Execute_Discrete,Remainder 32d7 ; 3258 C from color MACRO_Execute_Discrete,Remainder 32d7 ; 3610 C from color 0x108b 32d7 ; 3934 C from color 0x0b32 32d7 ; -------------------------------------------------------------------------------------- 32d7 32d7 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 32d8 32d8 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR02:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 32d9 ; -------------------------------------------------------------------------------------- 32d9 ; Comes from: 32d9 ; 04bb C from color 0x04bb 32d9 ; 04bf C from color 0x04b0 32d9 ; 0501 C False from color 0x04fa 32d9 ; 0515 C from color 0x0515 32d9 ; 09f9 C False from color 0x09f9 32d9 ; 09fb C False from color 0x09fb 32d9 ; 0c1f C from color MACRO_Execute_Heap_Access,Element_Type 32d9 ; 0c3b C from color 0x0a7e 32d9 ; 0cf2 C True from color MACRO_Execute_Heap_Access,Adaptive_Balanced_Tree_Lookup 32d9 ; 10cd C True from color 0x10c9 32d9 ; 10d4 C True from color 0x10c9 32d9 ; 10fc C False from color 0x10f1 32d9 ; 118c C True from color 0x1147 32d9 ; 1192 C True from color 0x1148 32d9 ; 11a2 C True from color 0x114c 32d9 ; 11e5 C True from color 0x114d 32d9 ; 1216 C from color 0x1216 32d9 ; 121a C from color 0x121a 32d9 ; 121e C from color 0x121e 32d9 ; 1222 C from color 0x1222 32d9 ; 1223 C from color 0x1222 32d9 ; 1224 C from color 0x1222 32d9 ; 1225 C from color 0x1222 32d9 ; 1226 C from color 0x1222 32d9 ; 122a C from color 0x10f1 32d9 ; 122b C from color 0x10f1 32d9 ; 1237 C True from color 0x10f1 32d9 ; 1239 C True from color 0x10f1 32d9 ; 123a C False from color 0x10f1 32d9 ; 1281 C from color 0x1280 32d9 ; 1282 C from color 0x1280 32d9 ; 1283 C from color 0x1280 32d9 ; 1284 C from color 0x1280 32d9 ; 130c C True from color 0x1307 32d9 ; 14b1 C True from color MACRO_Execute_Matrix,Length 32d9 ; 14c7 C True from color 0x14b6 32d9 ; 1617 C True from color MACRO_Execute_Matrix,Subarray 32d9 ; 161a C True from color MACRO_Execute_Matrix,Subarray 32d9 ; 1630 C True from color 0x098b 32d9 ; 1665 C True from color 0x165f 32d9 ; 1677 C True from color 0x1677 32d9 ; 16ad C True from color 0x098b 32d9 ; 16c7 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32d9 ; 1701 C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32d9 ; 170f C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32d9 ; 1727 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32d9 ; 1728 C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32d9 ; 1729 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32d9 ; 172a C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32d9 ; 1732 C from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32d9 ; 175e C True from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32d9 ; 175f C True from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32d9 ; 1761 C False from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32d9 ; 1762 C False from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32d9 ; 1768 C False from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32d9 ; 176a C False from color MACRO_Execute_Variant_Record,Set_Variant,fieldnum 32d9 ; 178f C from color MACRO_Execute_Variant_Record,Read_Variant 32d9 ; 17a2 C True from color MACRO_Execute_Variant_Record,Read_Discriminant_Constraint 32d9 ; 17a3 C False from color MACRO_Execute_Variant_Record,Read_Discriminant_Constraint 32d9 ; 17a4 C True from color MACRO_Execute_Variant_Record,Read_Discriminant_Constraint 32d9 ; 17a5 C True from color MACRO_Execute_Variant_Record,Read_Discriminant_Constraint 32d9 ; 17ae C True from color MACRO_Execute_Variant_Record,Reference_Makes_Copy 32d9 ; 17b5 C True from color MACRO_Execute_Variant_Record,Structure_Query 32d9 ; 17b6 C True from color MACRO_Execute_Variant_Record,Structure_Query 32d9 ; 17ca C True from color MACRO_Execute_Variant_Record,Component_Offset 32d9 ; 1831 C True from color 0x0a31 32d9 ; 1b0f C from color MACRO_Execute_Access,Element_Type 32d9 ; 1b2b C from color 0x0a7d 32d9 ; 1bb2 C True from color 0x1bb0 32d9 ; 1bbd C False from color 0x1bb0 32d9 ; 1cb1 C True from color MACRO_Execute_Array,Subarray 32d9 ; 1cb2 C True from color MACRO_Execute_Array,Subarray 32d9 ; 1cb3 C False from color MACRO_Execute_Array,Subarray 32d9 ; 1eb4 C True from color 0x1eb4 32d9 ; 1ecb C True from color MACRO_Declare_Type_Record,Incomplete 32d9 ; 1ed8 C True from color 0x1ed6 32d9 ; 1ee7 C True from color MACRO_Complete_Type_Record,By_Renaming 32d9 ; 1eea C True from color MACRO_Complete_Type_Record,By_Renaming 32d9 ; 1ef4 C from color MACRO_Complete_Type_Record,By_Renaming 32d9 ; 1f8f C True from color MACRO_Declare_Type_Access,Constrained 32d9 ; 1fa3 C False from color 0x1f9b 32d9 ; 1fb0 C True from color MACRO_Complete_Type_Array,By_Constraining 32d9 ; 1fba C from color MACRO_Complete_Type_Array,By_Constraining 32d9 ; 203a C True from color MACRO_Complete_Type_Array,By_Defining 32d9 ; 2072 C True from color 0x2042 32d9 ; 20b1 C from color 0x2042 32d9 ; 20b3 C from color 0x2042 32d9 ; 20ea C from color 0x2042 32d9 ; 20ec C from color 0x2042 32d9 ; 2118 C True from color 0x2042 32d9 ; 21ee C False from color 0x2035 32d9 ; 21fd C False from color 0x21f9 32d9 ; 2204 C False from color 0x2035 32d9 ; 2214 C False from color 0x2035 32d9 ; 221c C True from color 0x2035 32d9 ; 2230 C True from color 0x2228 32d9 ; 2243 C from color 0x2035 32d9 ; 2323 C True from color MACRO_Declare_Type_Array,Incomplete 32d9 ; 2325 C True from color MACRO_Declare_Type_Array,Incomplete 32d9 ; 2343 C from color 0x233d 32d9 ; 235e C True from color MACRO_Complete_Type_Array,By_Renaming 32d9 ; 2368 C True from color 0x2360 32d9 ; 237c C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32d9 ; 237d C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32d9 ; 2381 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32d9 ; 2382 C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32d9 ; 23e1 C False from color 0x23c4 32d9 ; 23f3 C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32d9 ; 23f7 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32d9 ; 2428 C True from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 32d9 ; 24be C True from color 0x24ba 32d9 ; 24c0 C True from color 0x24ba 32d9 ; 24c8 C True from color 0x24ba 32d9 ; 2564 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32d9 ; 2566 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32d9 ; 25e5 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32d9 ; 25e6 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32d9 ; 265f C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 32d9 ; 2660 C False from color MACRO_Complete_Type_Variant_Record,By_Renaming 32d9 ; 2664 C True from color MACRO_Complete_Type_Variant_Record,By_Renaming 32d9 ; 266d C True from color 0x266c 32d9 ; 2674 C True from color 0x266c 32d9 ; 271c C True from color 0x2715 32d9 ; 2b19 C False from color 0x2b19 32d9 ; 2b1e C False from color 0x2b19 32d9 ; 2b21 C False from color 0x2b19 32d9 ; 2b26 C False from color 0x2b19 32d9 ; 2b28 C True from color 0x2b19 32d9 ; 2b6e C False from color MACRO_Declare_Type_Access,Incomplete 32d9 ; 2b6f C True from color MACRO_Declare_Type_Access,Incomplete 32d9 ; 30e3 C False from color 0x30db 32d9 ; 30eb C False from color 0x30db 32d9 ; 3117 C False from color 0x3115 32d9 ; 3150 C False from color MACRO_Declare_Type_InMicrocode,Discrete 32d9 ; 3167 C True from color 0x3163 32d9 ; 316c C False from color 0x3163 32d9 ; 3176 C False from color 0x3163 32d9 ; 3177 C True from color 0x3163 32d9 ; 31be C False from color 0x31ba 32d9 ; 31cb C True from color MACRO_Declare_Type_Heap_Access,Incomplete 32d9 ; 31cd C from color MACRO_Declare_Type_Heap_Access,Incomplete 32d9 ; -------------------------------------------------------------------------------------- 32d9 32d9 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 31 VR08:11 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32da ; -------------------------------------------------------------------------------------- 32da ; Comes from: 32da ; 099d C False from color 0x099d 32da ; 099f C False from color 0x099f 32da ; 0a00 C False from color MACRO_Execute_Any,Make_Visible 32da ; 0b2a C False from color MACRO_Declare_Variable_Package,Visible,On_Processor 32da ; 10c0 C False from color MACRO_Declare_Variable_Access,Visible 32da ; 10c6 C False from color MACRO_Declare_Variable_Heap_Access,Visible 32da ; 10cb C False from color 0x10c9 32da ; 10d2 C False from color 0x10c9 32da ; 12f9 C False from color 0x12f9 32da ; 1307 C False from color 0x1307 32da ; 1d3a C True from color MACRO_Execute_Package,Field_Write,fieldnum 32da ; 1d45 C from color 0x1cc6 32da ; 1f1d C from color 0x098b 32da ; 2b1c C False from color MACRO_Declare_Type_Access,Defined,Visible 32da ; 2b24 C False from color MACRO_Declare_Type_Access,Defined,Visible,Accesses_Protected 32da ; 2b68 C False from color MACRO_Declare_Type_Access,Incomplete 32da ; 2b6c C False from color MACRO_Declare_Type_Access,Incomplete 32da ; 2c0f C True from color MACRO_Action_Load_Dynamic 32da ; 2c13 C False from color 0x2c12 32da ; 2c6e C from color 0x2c6d 32da ; 2c9a C from color MACRO_Execute_Package,Field_Reference,fieldnum 32da ; 30b7 C False from color MACRO_Declare_Type_Float,Defined,Visible 32da ; 30cd C False from color MACRO_Declare_Type_Float,Constrained,Visible 32da ; 30d3 C False from color MACRO_Declare_Type_Float,Incomplete,Visible 32da ; 30fc C False from color 0x0995 32da ; 3106 C False from color MACRO_Declare_Variable_Float,With_Value,With_Constraint 32da ; 310a C False from color MACRO_Declare_Variable_Float,Visible,With_Value 32da ; 3115 C False from color 0x3115 32da ; 311c C False from color 0x3115 32da ; 314d C False from color MACRO_Declare_Type_InMicrocode,Discrete 32da ; 3192 C False from color MACRO_Declare_Variable_Any,Visible 32da ; 31a0 C False from color 0x319f 32da ; 31a2 C False from color MACRO_Execute_Immediate_Set_Value,uimmediate 32da ; 31aa C False from color MACRO_Declare_Variable_Discrete,Visible,With_Value 32da ; 31ae C False from color MACRO_Declare_Type_Heap_Access,Defined 32da ; 31c5 C from color MACRO_Declare_Type_Heap_Access,Incomplete 32da ; 31c9 C from color MACRO_Declare_Type_Heap_Access,Incomplete 32da ; 31cf C from color MACRO_Declare_Type_Heap_Access,Incomplete 32da ; -------------------------------------------------------------------------------------- 32da 32da fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 32 VR08:12 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32db ; -------------------------------------------------------------------------------------- 32db ; Comes from: 32db ; 0921 C True from color 0x0921 32db ; 0923 C True from color 0x0921 32db ; 0924 C True from color 0x0921 32db ; 0933 C True from color 0x0921 32db ; 0937 C True from color 0x0921 32db ; 0939 C True from color 0x0921 32db ; 0943 C True from color 0x0921 32db ; 0944 C True from color 0x0921 32db ; 0a0f C True from color 0x0a0f 32db ; 0a4e C from color 0x0a4e 32db ; 0a6c C False from color 0x0a50 32db ; 0a6f C from color 0x0a50 32db ; 1142 C from color 0x1142 32db ; 16ca C False from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32db ; 1792 C False from color MACRO_Execute_Variant_Record,Indirects_Appended 32db ; 1793 C True from color MACRO_Execute_Variant_Record,Indirects_Appended 32db ; 1827 C True from color MACRO_Execute_Record,Structure_Write 32db ; 1828 C True from color MACRO_Execute_Record,Structure_Write 32db ; 19e9 C True from color 0x19e9 32db ; 19eb C from color 0x19e9 32db ; 1d5e C from color 0x1d5e 32db ; 1d5f C from color 0x1d5e 32db ; 1d6e C from color 0x1d6e 32db ; 1d7c C from color 0x1d7c 32db ; 1edb C False from color 0x1ed6 32db ; 1ee8 C False from color MACRO_Complete_Type_Record,By_Renaming 32db ; 1fae C True from color MACRO_Complete_Type_Array,By_Constraining 32db ; 1fb3 C True from color MACRO_Complete_Type_Array,By_Constraining 32db ; 2038 C True from color MACRO_Complete_Type_Array,By_Defining 32db ; 203e C True from color 0x203c 32db ; 21ed C True from color 0x2035 32db ; 2203 C True from color 0x2035 32db ; 2213 C True from color 0x2035 32db ; 223a C True from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 32db ; 2245 C True from color 0x2035 32db ; 235c C True from color MACRO_Complete_Type_Array,By_Renaming 32db ; 2362 C True from color 0x2360 32db ; 23f0 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32db ; 23f5 C True from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32db ; 2562 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32db ; 2565 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32db ; 2663 C False from color MACRO_Complete_Type_Variant_Record,By_Renaming 32db ; 2d61 C True from color 0x2d26 32db ; -------------------------------------------------------------------------------------- 32db 32db fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR08:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32dc ; -------------------------------------------------------------------------------------- 32dc ; Comes from: 32dc ; 0907 C False from color 0x0905 32dc ; 093a C True from color 0x0921 32dc ; 10db C from color 0x10da 32dc ; 10df C from color 0x10da 32dc ; 10e3 C from color 0x10da 32dc ; 10e7 C from color 0x10da 32dc ; 1111 C False from color 0x1106 32dc ; 11b0 C False from color 0x114d 32dc ; 11bb C from color 0x114d 32dc ; 1245 C False from color 0x1106 32dc ; 1249 C False from color 0x1106 32dc ; 124c C False from color 0x1106 32dc ; 1274 C from color 0x1274 32dc ; 1278 C from color 0x1278 32dc ; 127c C from color 0x127c 32dc ; 1280 C from color 0x1280 32dc ; 12bc C False from color 0x1106 32dc ; 12ce C False from color 0x128f 32dc ; 12d2 C False from color 0x128f 32dc ; 12d5 C False from color 0x128f 32dc ; 12f5 C False from color 0x12f5 32dc ; 13a6 C False from color MACRO_Declare_Variable_Array,With_Constraint 32dc ; 13aa C False from color MACRO_Declare_Variable_Array,With_Constraint 32dc ; 13d1 C False from color MACRO_Declare_Variable_Array,With_Constraint 32dc ; 13d5 C False from color MACRO_Declare_Variable_Array,With_Constraint 32dc ; 13f8 C False from color MACRO_Declare_Variable_Array,With_Constraint 32dc ; 13fc C False from color MACRO_Declare_Variable_Array,With_Constraint 32dc ; 142d C False from color MACRO_Declare_Variable_Array,With_Constraint 32dc ; 1445 C False from color 0x1441 32dc ; 1740 C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32dc ; 174d C False from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32dc ; 19a2 C False from color MACRO_Execute_Vector,Slice_Read 32dc ; 19aa C False from color MACRO_Execute_Vector,Slice_Read 32dc ; 19b6 C False from color MACRO_Execute_Vector,Slice_Read 32dc ; 19bb C False from color MACRO_Execute_Vector,Slice_Read 32dc ; 19c2 C False from color MACRO_Execute_Vector,Slice_Read 32dc ; 1a15 C False from color MACRO_Execute_Vector,Catenate 32dc ; 1a28 C False from color MACRO_Execute_Vector,Catenate 32dc ; 1a37 C True from color MACRO_Execute_Vector,Catenate 32dc ; 1a48 C False from color MACRO_Execute_Vector,Append 32dc ; 1a60 C False from color MACRO_Execute_Vector,Append 32dc ; 1a6a C False from color MACRO_Execute_Vector,Prepend 32dc ; 1aaf C False from color 0x0a2f 32dc ; 1ab6 C True from color 0x0a2f 32dc ; 1ab8 C False from color 0x0a2f 32dc ; 20ed C True from color 0x2042 32dc ; 225c C False from color 0x2258 32dc ; 2268 C False from color 0x2258 32dc ; 227a C False from color 0x2258 32dc ; 227b C False from color 0x2258 32dc ; 2778 C False from color MACRO_Declare_Variable_Entry 32dc ; 2a3d C False from color 0x2a34 32dc ; 2a54 C False from color 0x2a34 32dc ; 2ce7 C True from color MACRO_Declare_Subprogram_For_Call,subp 32dc ; 2ced C True from color MACRO_Declare_Subprogram_For_Accept,subp 32dc ; 3118 C False from color 0x3115 32dc ; 314c C False from color MACRO_Declare_Type_InMicrocode,Discrete 32dc ; 3152 C False from color MACRO_Declare_Type_InMicrocode,Discrete 32dc ; 3b4d C True from color 0x371b 32dc ; 3b4f C True from color 0x371b 32dc ; -------------------------------------------------------------------------------------- 32dc 32dc fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 37 VR12:17 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32dd ; -------------------------------------------------------------------------------------- 32dd ; Comes from: 32dd ; 01f8 C from color MACRO_Illegal_- 32dd ; 2387 C False from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 32dd ; 23ca C True from color 0x23c4 32dd ; 23d1 C True from color 0x23c4 32dd ; 242d C False from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 32dd ; 2452 C True from color MACRO_Declare_Type_Variant_Record,Constrained,Visible 32dd ; 2538 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32dd ; 2539 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32dd ; 253a C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32dd ; 253b C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32dd ; 253c C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32dd ; 2555 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32dd ; 2556 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32dd ; 2557 C True from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 32dd ; 2563 C True from color MACRO_Complete_Type_Variant_Record,By_Defining 32dd ; 2569 C True from color 0x2569 32dd ; 257d C True from color 0x2569 32dd ; 257e C True from color 0x2569 32dd ; 258f C True from color 0x258e 32dd ; 25a7 C True from color 0x25a7 32dd ; 25a8 C True from color 0x25a7 32dd ; 25aa C False from color 0x25a7 32dd ; 25c9 C True from color 0x2569 32dd ; 25ca C True from color 0x2569 32dd ; 25cb C True from color 0x2569 32dd ; 25cd C True from color 0x25cd 32dd ; 25ce C True from color 0x25cd 32dd ; 25d0 C True from color 0x25cd 32dd ; 267c C True from color 0x2671 32dd ; 2692 C True from color MACRO_Declare_Type_Variant_Record,Defined 32dd ; 2693 C True from color MACRO_Declare_Type_Variant_Record,Defined 32dd ; 269d C True from color 0x269c 32dd ; 26d6 C True from color MACRO_Declare_Type_Variant_Record,Defined 32dd ; 26d7 C True from color MACRO_Declare_Type_Variant_Record,Defined 32dd ; 26d8 C True from color MACRO_Declare_Type_Variant_Record,Defined 32dd ; 26da C True from color 0x26da 32dd ; 26db C True from color 0x26da 32dd ; 26dd C True from color 0x26da 32dd ; 2d46 C True from color ML_break_class 32dd ; 327a C from color MACRO_Illegal_- 32dd ; -------------------------------------------------------------------------------------- 32dd 32dd fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 34 VR08:14 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 8 32de ; -------------------------------------------------------------------------------------- 32de ; Comes from: 32de ; 0498 C True from color 0x0496 32de ; 0fd2 C True from color 0x0f29 32de ; 0fdf C True from color 0x0f29 32de ; 0fe4 C True from color 0x0f29 32de ; 1627 C from color MACRO_Execute_Variant_Record,Field_Read,Fixed,Direct,fieldnum 32de ; 165f C from color 0x165f 32de ; 1672 C from color 0x166c 32de ; 1675 C from color 0x166c 32de ; 167a C True from color MACRO_Execute_Variant_Record,Field_Reference,Fixed,Direct,fieldnum 32de ; 167c C True from color MACRO_Execute_Variant_Record,Field_Reference,Fixed,Indirect,fieldnum 32de ; 1682 C True from color 0x098b 32de ; 1696 C from color 0x098b 32de ; 1699 C from color 0x098b 32de ; 16af C True from color 0x098b 32de ; 16b2 C from color 0x098b 32de ; 16cb C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32de ; 16d1 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32de ; 16d6 C False from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32de ; 1704 C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32de ; 1717 C from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32de ; 1726 C True from color MACRO_Execute_Variant_Record,Set_Bounds,fieldnum 32de ; 1797 C from color MACRO_Execute_Variant_Record,Indirects_Appended 32de ; 179a C True from color MACRO_Execute_Variant_Record,Indirects_Appended 32de ; 179e C True from color MACRO_Execute_Variant_Record,Indirects_Appended 32de ; 17c8 C False from color MACRO_Execute_Variant_Record,Component_Offset 32de ; 17cc C from color MACRO_Execute_Variant_Record,Component_Offset 32de ; 17f9 C from color MACRO_Execute_Any,Set_Constraint 32de ; 1804 C True from color MACRO_Execute_Record,Field_Read,fieldnum 32de ; 1810 C True from color MACRO_Execute_Record,Field_Write,fieldnum 32de ; 1814 C True from color MACRO_Execute_Record,Field_Reference,fieldnum 32de ; 1821 C True from color 0x09ad 32de ; 182c C from color MACRO_Execute_Record,Structure_Write 32de ; 182e C False from color 0x0a31 32de ; 1833 C from color 0x0a31 32de ; 1841 C True from color 0x1841 32de ; 1842 C True from color 0x1841 32de ; 1845 C from color 0x1841 32de ; 1994 C True from color MACRO_Execute_Vector,Slice_Read 32de ; 19e7 C True from color MACRO_Execute_Vector,Slice_Write 32de ; 19f2 C True from color MACRO_Execute_Vector,Slice_Reference 32de ; 1cc9 C from color 0x1cc9 32de ; 1cd0 C from color 0x1cc6 32de ; 1d37 C True from color MACRO_Execute_Package,Field_Write,fieldnum 32de ; 2516 C False from color 0x24ba 32de ; 2a93 C True from color ML_Resolve Reference 32de ; 2ba1 C from color MACRO_Action_Load_Dynamic 32de ; 2ba7 C from color MACRO_Action_Load_Dynamic 32de ; 2ba8 C from color MACRO_Action_Load_Dynamic 32de ; 2c01 C from color MACRO_Action_Load_Dynamic 32de ; 2c0b C True from color MACRO_Action_Load_Dynamic 32de ; 2c34 C False from color MACRO_Execute_Package,Field_Execute_Dynamic 32de ; 2c9d C True from color MACRO_Execute_Package,Field_Reference,fieldnum 32de ; 2ca1 C False from color 0x2ca0 32de ; 2ca6 C True from color 0x2ca0 32de ; 2cac C False from color MACRO_Execute_Select,Member_Write,fieldnum 32de ; 2cbe C False from color MACRO_Execute_Select,Member_Write,fieldnum 32de ; 2cc4 C False from color MACRO_Execute_Select,Guard_Write,fieldnum 32de ; 2ccf C True from color MACRO_Execute_Select,Timed_Duration_Write 32de ; 35de C True from color 0x35dc 32de ; 35e0 C from color 0x35dc 32de ; 3805 C True from color MACRO_Execute_Entry,Count 32de ; 380b C True from color MACRO_Execute_Family,Count 32de ; 38e3 C True from color 0x38e0 32de ; -------------------------------------------------------------------------------------- 32de 32de fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3b VR11:1b val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 32df ; -------------------------------------------------------------------------------------- 32df ; Comes from: 32df ; 019a C from color UE_CHK_EXIT 32df ; 01e2 C from color UE_NEW_PAK 32df ; 2e86 C False from color MACRO_Exit_Subprogram_From_Utility,With_Result,>R,topoffset 32df ; -------------------------------------------------------------------------------------- 32df 32df fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2e VR11:0e val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 32e0 ; -------------------------------------------------------------------------------------- 32e0 ; Comes from: 32e0 ; 01a2 C from color UE_FIELD_ERROR 32e0 ; 16c9 C from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32e0 ; 16cc C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32e0 ; 16e6 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32e0 ; 16ec C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32e0 ; 16ed C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32e0 ; 16f1 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32e0 ; 16f3 C True from color MACRO_Execute_Variant_Record,Field_Type_Dynamic 32e0 ; 1703 C from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32e0 ; 1708 C from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32e0 ; 1709 C True from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32e0 ; 1710 C from color MACRO_Execute_Variant_Record,Field_Type,fieldnum 32e0 ; -------------------------------------------------------------------------------------- 32e0 32e0 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3c VR11:1c val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 32e1 ; -------------------------------------------------------------------------------------- 32e1 ; Comes from: 32e1 ; 0c58 C True from color MACRO_Execute_Heap_Access,Construct_Segment 32e1 ; 0c59 C True from color MACRO_Execute_Heap_Access,Construct_Segment 32e1 ; 1186 C False from color 0x1186 32e1 ; 1dde C False from color 0x1dde 32e1 ; 35eb C from color 0x35e4 32e1 ; 35f0 C False from color 0x35ed 32e1 ; 35f2 C False from color 0x35ed 32e1 ; 35f3 C True from color 0x35ed 32e1 ; 35f7 C False from color 0x35f7 32e1 ; 35f8 C True from color 0x35f7 32e1 ; 35f9 C False from color 0x35f7 32e1 ; 35ff C from color 0x35f7 32e1 ; 3600 C False from color 0x35f7 32e1 ; 3601 C True from color 0x35f7 32e1 ; 3602 C False from color 0x35f7 32e1 ; 3605 C from color 0x35f7 32e1 ; 3617 C from color 0x108b 32e1 ; 3640 C from color 0x108b 32e1 ; -------------------------------------------------------------------------------------- 32e1 32e1 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 3f VR11:1f val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 11 32e2 ; -------------------------------------------------------------------------------------- 32e2 ; Comes from: 32e2 ; 03ab C True from color 0x0398 32e2 ; 2ccb C False from color MACRO_Execute_Select,Timed_Duration_Write 32e2 ; 2cd2 C False from color MACRO_Execute_Select,Timed_Guard_Write 32e2 ; 2cd6 C False from color MACRO_Execute_Select,Terminate_Guard_Write 32e2 ; -------------------------------------------------------------------------------------- 32e2 32e2 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR05:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 32e3 32e3 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 32e4 32e4 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 30 VR09:10 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32e5 32e5 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 23 VR12:03 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32e6 ; -------------------------------------------------------------------------------------- 32e6 ; Comes from: 32e6 ; 0f85 C from color 0x0f29 32e6 ; 0fd8 C False from color 0x0f29 32e6 ; 0fdd C from color 0x0f29 32e6 ; -------------------------------------------------------------------------------------- 32e6 32e6 fiu_mem_start 2 start-rd; Flow C 0x332f ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 332f 0x332f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR18:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 32e7 32e7 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0f TR18:10 typ_c_mux_sel 0 ALU typ_frame 18 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 0f VR18:10 val_c_mux_sel 2 ALU val_frame 18 32e8 32e8 ioc_adrbs 1 val ; Flow C 0x34cd ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 32e9 32e9 fiu_len_fill_lit 52 zero-fill 0x12; Flow J cc=False 0x32ed fiu_load_var 1 hold_var fiu_offs_lit 14 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 32ed 0x32ed seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 27 ? val_a_adr 22 VR02:02 val_frame 2 32ea 32ea ioc_adrbs 1 val ; Flow C 0x34cd ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34cd 0x34cd seq_en_micro 0 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 32eb 32eb fiu_tivi_src 1 tar_val; Flow J cc=False 0x32ee ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 32ee 0x32ee seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 24 VR12:04 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32ec 32ec seq_br_type 3 Unconditional Branch; Flow J 0x32f6 seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 32ed 32ed fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 24 VR12:04 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32ee 32ee fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 38 TR07:18 typ_frame 7 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 32ef 32ef fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 2a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 15 ? typ_a_adr 14 ZEROS val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_frame 8 32f0 32f0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_b_adr 02 GP02 32f1 32f1 seq_br_type 3 Unconditional Branch; Flow J 0x3313 seq_branch_adr 3313 0x3313 seq_int_reads 0 TYP VAL BUS seq_random 1a ? val_b_adr 32 VR02:12 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 32f2 ; -------------------------------------------------------------------------------------- 32f2 ; Comes from: 32f2 ; 0fae C False from color 0x0f29 32f2 ; -------------------------------------------------------------------------------------- 32f2 32f2 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 25 VR12:05 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32f3 ; -------------------------------------------------------------------------------------- 32f3 ; Comes from: 32f3 ; 1f80 C from color 0x1f7e 32f3 ; -------------------------------------------------------------------------------------- 32f3 32f3 seq_br_type 7 Unconditional Call; Flow C 0x211 seq_branch_adr 0211 0x0211 seq_en_micro 0 32f4 32f4 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR12:13 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 12 32f5 ; -------------------------------------------------------------------------------------- 32f5 ; Comes from: 32f5 ; 0346 C from color 0x0345 32f5 ; 034a C from color 0x0349 32f5 ; 097c C from color MACRO_Execute_Module,Is_Callable 32f5 ; 0b71 C from color 0x0b70 32f5 ; 0ceb C from color MACRO_Execute_Heap_Access,Diana_Find_Permanent_Attribute 32f5 ; 0d06 C from color MACRO_Execute_Heap_Access,Adaptive_Balanced_Tree_Lookup 32f5 ; 0e6a C from color 0x0e6a 32f5 ; 0e6f C from color 0x0e6e 32f5 ; 0ea3 C from color 0x0ea1 32f5 ; 0ea4 C from color 0x0ea4 32f5 ; 0eab C from color 0x0ea9 32f5 ; 0eac C from color 0x0eac 32f5 ; 0eae C from color 0x0ead 32f5 ; 2e0a C from color 0x2e04 32f5 ; 3c4a C from color 0x3c4a 32f5 ; 3c4b C from color 0x3c4b 32f5 ; 3c4c C from color 0x3c4c 32f5 ; 3c4d C from color 0x3c4d 32f5 ; 3c4e C from color 0x3c4e 32f5 ; 3c4f C from color 0x3c4f 32f5 ; 3c50 C from color 0x3c50 32f5 ; 3c51 C from color 0x3c51 32f5 ; 3c52 C from color 0x3c52 32f5 ; 3c54 C from color 0x3c54 32f5 ; -------------------------------------------------------------------------------------- 32f5 32f5 fiu_tivi_src 1 tar_val; Flow J 0x32f6 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f6 0x32f6 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 05 ? typ_alu_func 1a PASS_B typ_b_adr 36 TR02:16 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 39 VR09:19 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 9 32f6 ; -------------------------------------------------------------------------------------- 32f6 ; Comes from: 32f6 ; 3296 C from color MACRO_Execute_Discrete,Raise,>R 32f6 ; -------------------------------------------------------------------------------------- 32f6 32f6 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 1b ? 32f7 32f7 fiu_len_fill_lit 4e zero-fill 0xe; Flow J 0x32f9 fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 32f9 0x32f9 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 32f8 32f8 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 32f9 32f9 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_tar 1 hold_tar fiu_offs_lit 2a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 16 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 32fa 32fa fiu_len_fill_lit 52 zero-fill 0x12; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 14 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 6a ? typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR02:02 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 32fb 32fb fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 32fc 32fc fiu_len_fill_lit 4e zero-fill 0xe; Flow J cc=True 0x330c fiu_offs_lit 2a fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 330c 0x330c typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 3e GP01 val_c_source 0 FIU_BUS 32fd 32fd fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 seq_lex_adr 3 seq_random 6a ? val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 8 32fe 32fe fiu_len_fill_lit 56 zero-fill 0x16; Flow J cc=False 0x3313 fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3313 0x3313 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_lex_adr 2 seq_random 0b ? typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 32ff 32ff fiu_len_fill_lit 4f zero-fill 0xf; Flow J cc=False 0x3313 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3313 0x3313 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 01 GP01 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3300 3300 fiu_len_fill_lit 7b zero-fill 0x3b; Flow J cc=True 0x3313 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3313 0x3313 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_b_adr 01 GP01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 03 GP03 3301 3301 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3313 seq_br_type 1 Branch True seq_branch_adr 3313 0x3313 seq_cond_sel 5f (VAL.ALU_32_CO(late)) nand (TYP.ALU_32_CARRY_OUT(late)) typ_a_adr 3e TR11:1e typ_alu_func 6 A_MINUS_B typ_b_adr 03 GP03 typ_frame 11 val_a_adr 38 VR02:18 val_alu_func 6 A_MINUS_B val_b_adr 04 GP04 val_frame 2 3302 3302 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_int_reads 0 TYP VAL BUS seq_random 1a ? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3303 3303 ioc_fiubs 2 typ ; Flow J cc=True 0x330a seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 330a 0x330a seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 03 GP03 typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 06 GP06 val_alu_func 0 PASS_A 3304 3304 seq_en_micro 0 3305 3305 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x3308 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3308 0x3308 seq_int_reads 5 RESOLVE RAM typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 3306 3306 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x3329 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3329 0x3329 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2a VR05:0a val_frame 5 3307 3307 seq_br_type 3 Unconditional Branch; Flow J 0x3321 seq_branch_adr 3321 0x3321 3308 3308 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x3329 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3329 0x3329 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2b VR05:0b val_frame 5 3309 3309 seq_br_type 3 Unconditional Branch; Flow J 0x3321 seq_branch_adr 3321 0x3321 330a 330a seq_en_micro 0 330b 330b fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x331a fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 331a 0x331a seq_int_reads 5 RESOLVE RAM typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 330c 330c seq_br_type 3 Unconditional Branch; Flow J 0x3313 seq_branch_adr 3313 0x3313 seq_lex_adr 3 seq_random 6a ? val_c_adr 39 GP06 val_c_mux_sel 2 ALU 330d 330d seq_en_micro 0 seq_random 27 ? typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 22 TR01:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 1 val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 330e 330e fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_offs_lit 6d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 330f 330f ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 16 ? typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3310 3310 fiu_len_fill_lit 52 zero-fill 0x12; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 14 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION seq_random 6a ? typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_a_adr 22 VR02:02 val_frame 2 3311 3311 fiu_mem_start 2 start-rd; Flow C 0x332f ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332f 0x332f seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 39 TR02:19 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 3312 3312 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x32fe fiu_load_var 1 hold_var fiu_offs_lit 10 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 32fe 0x32fe seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_latch 1 seq_lex_adr 3 seq_random 6a ? val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 8 3313 3313 fiu_load_tar 1 hold_tar; Flow J cc=True 0x3319 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3319 0x3319 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3314 3314 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x3317 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3317 0x3317 seq_int_reads 0 TYP VAL BUS seq_random 1a ? val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3315 3315 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x3329 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3329 0x3329 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2a VR05:0a val_frame 5 3316 3316 seq_br_type 3 Unconditional Branch; Flow J 0x3321 seq_branch_adr 3321 0x3321 3317 3317 fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x3329 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3329 0x3329 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2b VR05:0b val_frame 5 3318 3318 seq_br_type 3 Unconditional Branch; Flow J 0x3321 seq_branch_adr 3321 0x3321 3319 3319 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_int_reads 0 TYP VAL BUS seq_random 1a ? val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 331a 331a fiu_len_fill_lit 78 zero-fill 0x38; Flow C cc=True 0x3329 fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3329 0x3329 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 26 TR05:06 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 331b 331b seq_br_type 3 Unconditional Branch; Flow J 0x3321 seq_branch_adr 3321 0x3321 331c ; -------------------------------------------------------------------------------------- 331c ; 0x0101 Execute Exception,Reraise,>R 331c ; -------------------------------------------------------------------------------------- 331c MACRO_Execute_Exception,Reraise,>R: 331c 331c dispatch_brk_class 8 ; Flow J cc=True 0x330d dispatch_csa_valid 1 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 331c fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 330d 0x330d seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1e typ_rand a PASS_B_HIGH val_alu_func 13 ONES val_c_adr 39 GP06 val_c_mux_sel 2 ALU 331d 331d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_latch 1 seq_random 27 ? typ_a_adr 10 TOP typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 2c VR08:0c val_alu_func 5 DEC_A_MINUS_B val_b_adr 10 TOP val_frame 8 331e 331e fiu_mem_start 2 start-rd; Flow J cc=True 0x3320 ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3320 0x3320 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 32 TR11:12 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 331f 331f ioc_fiubs 2 typ ; Flow J 0x3321 seq_br_type 3 Unconditional Branch seq_branch_adr 3321 0x3321 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 01 GP01 typ_c_adr 3d GP02 typ_csa_cntl 3 POP_CSA val_b_adr 28 VR05:08 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 3320 3320 ioc_fiubs 2 typ ; Flow J 0x3321 seq_br_type 3 Unconditional Branch seq_branch_adr 3321 0x3321 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 01 GP01 typ_c_adr 3d GP02 typ_csa_cntl 3 POP_CSA val_b_adr 29 VR05:09 val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_frame 5 3321 3321 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3324 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3324 0x3324 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 3322 3322 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3323 3323 ioc_tvbs 1 typ+fiu; Flow J 0x3328 seq_br_type 3 Unconditional Branch seq_branch_adr 3328 0x3328 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? val_a_adr 36 VR13:16 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 13 3324 3324 fiu_mem_start 2 start-rd; Flow C 0x332f ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332f 0x332f seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1a PASS_B typ_b_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 3325 3325 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_random 15 ? typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2e TOP + 1 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1 typ_mar_cntl 9 LOAD_MAR_CODE typ_rand 1 INC_LOOP_COUNTER val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 3326 3326 ioc_tvbs 1 typ+fiu seq_int_reads 0 TYP VAL BUS seq_random 6e Load_break_mask+? 3327 3327 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3328 seq_br_type 3 Unconditional Branch seq_branch_adr 3328 0x3328 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? val_a_adr 36 VR13:16 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 13 3328 3328 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR02:01 val_alu_func 1d A_AND_NOT_B val_b_adr 0f GP0f val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 3329 ; -------------------------------------------------------------------------------------- 3329 ; Comes from: 3329 ; 3306 C True from color 0x0000 3329 ; 3308 C True from color 0x0000 3329 ; 3315 C True from color 0x0000 3329 ; 3317 C True from color 0x0000 3329 ; 331a C True from color 0x0000 3329 ; -------------------------------------------------------------------------------------- 3329 3329 ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 332a 332a typ_a_adr 04 GP04 typ_alu_func 1c DEC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 332b 332b fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 05 GP05 typ_alu_func 6 A_MINUS_B typ_b_adr 04 GP04 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL 332c 332c ioc_load_wdr 0 typ_b_adr 14 BOT - 1 val_b_adr 14 BOT - 1 332d 332d fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type a Unconditional Return seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 332e ; -------------------------------------------------------------------------------------- 332e ; Comes from: 332e ; 0222 C from color MACRO_Action_Accept_Activation 332e ; 0223 C from color MACRO_Action_Accept_Activation 332e ; 026f C from color MACRO_Action_Accept_Activation 332e ; 031a C from color MACRO_Action_Name_Partner 332e ; 0345 C from color 0x0345 332e ; 0349 C from color 0x0349 332e ; 03d5 C from color 0x03d4 332e ; 0402 C from color 0x03f0 332e ; 067f C from color 0x066a 332e ; 068a C from color 0x066a 332e ; 090f C from color 0x090b 332e ; 0911 C from color 0x090b 332e ; 0913 C from color 0x0913 332e ; 092b C from color 0x0921 332e ; 0949 C from color 0x0921 332e ; 0961 C from color MACRO_Execute_Module,Is_Callable 332e ; 0977 C from color MACRO_Execute_Module,Is_Callable 332e ; 0a5a C from color 0x0a50 332e ; 0b45 C from color 0x0b32 332e ; 0cec C from color MACRO_Execute_Heap_Access,Adaptive_Balanced_Tree_Lookup 332e ; 0d0e C from color MACRO_Execute_Vector,Hash 332e ; 11a7 C from color 0x114d 332e ; 1349 C from color 0x1346 332e ; 147c C from color 0x09ac 332e ; 1490 C from color 0x09ac 332e ; 14b4 C from color MACRO_Execute_Matrix,Length 332e ; 14c9 C from color 0x14b6 332e ; 14f2 C from color 0x0aa2 332e ; 14f3 C from color 0x0aa2 332e ; 14f7 C from color 0x0aa2 332e ; 14f8 C from color 0x0aa2 332e ; 14ff C from color 0x0aa2 332e ; 1504 C from color 0x0aa2 332e ; 164d C from color 0x098b 332e ; 1684 C from color 0x098b 332e ; 1782 C from color MACRO_Execute_Variant_Record,Is_Constrained_Object 332e ; 17c9 C from color MACRO_Execute_Variant_Record,Component_Offset 332e ; 184d C from color 0x09ab 332e ; 1859 C from color 0x09ab 332e ; 1ab2 C from color 0x0a2f 332e ; 1b3b C from color 0x0a33 332e ; 1b3f C from color 0x0a33 332e ; 1b71 C from color MACRO_1b70_QQUnknown_InMicrocode 332e ; 1cb7 C from color MACRO_Execute_Array,Subarray 332e ; 1cdd C from color MACRO_Store_llvl,ldelta 332e ; 1d8e C from color 0x1cc6 332e ; 1d8f C from color 0x1cc6 332e ; 1da5 C from color 0x1d5a 332e ; 1dc0 C from color 0x1d5c 332e ; 1e43 C from color MACRO_Execute_Matrix,Structure_Write 332e ; 1e5f C from color MACRO_Execute_Matrix,Structure_Write 332e ; 1eee C from color MACRO_Complete_Type_Record,By_Renaming 332e ; 1f4b C from color 0x098b 332e ; 1f4c C from color 0x098b 332e ; 1f67 C from color 0x098b 332e ; 223d C from color MACRO_Complete_Type_Heap_Access,By_Component_Completion 332e ; 234b C from color 0x233d 332e ; 23bb C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 332e ; 23cf C from color 0x23c4 332e ; 2404 C from color MACRO_Complete_Type_Variant_Record,By_Constraining_Incomplete 332e ; 2447 C from color 0x2445 332e ; 2448 C from color 0x2445 332e ; 244e C from color 0x2445 332e ; 247f C from color 0x243b 332e ; 2548 C from color MACRO_Declare_Type_Variant_Record,Incomplete,Visible 332e ; 2560 C from color MACRO_Complete_Type_Variant_Record,By_Defining 332e ; 2587 C from color 0x2585 332e ; 2589 C from color 0x2585 332e ; 258b C from color 0x2585 332e ; 265c C from color MACRO_Complete_Type_Variant_Record,By_Renaming 332e ; 2669 C from color MACRO_Complete_Type_Variant_Record,By_Renaming 332e ; 2682 C from color 0x2680 332e ; 26aa C from color 0x26a8 332e ; 26ac C from color 0x26a8 332e ; 26ae C from color 0x26a8 332e ; 2722 C from color 0x2715 332e ; 29d3 C from color MACRO_Action_Push_Structure_Extended,abs,mark 332e ; 2b32 C from color 0x2b32 332e ; 2c71 C from color 0x2c6d 332e ; 2ce9 C from color MACRO_Declare_Subprogram_For_Call,subp 332e ; 2e24 C from color 0x2e22 332e ; 2eaf C from color 0x2eaf 332e ; 2f4d C from color 0x06b7 332e ; 2f76 C from color 0x06b7 332e ; 3020 C from color MACRO_Execute_Any,Convert 332e ; 3039 C from color MACRO_Execute_Discrete,Test_And_Set_Previous 332e ; 303a C from color MACRO_Execute_Discrete,Test_And_Set_Previous 332e ; 303b C from color MACRO_Execute_Discrete,Test_And_Set_Previous 332e ; 3056 C from color MACRO_Execute_Discrete,Instruction_Read 332e ; 30a6 C from color 0x30a6 332e ; 30a8 C from color 0x30a6 332e ; 30aa C from color 0x30aa 332e ; 30b0 C from color 0x30aa 332e ; 30b1 C from color 0x30aa 332e ; 30b2 C from color 0x30aa 332e ; 30b3 C from color 0x30aa 332e ; 30e2 C from color 0x30db 332e ; 30e8 C from color 0x30db 332e ; 319c C from color MACRO_Execute_Immediate_Set_Value,uimmediate 332e ; 35e1 C from color 0x35dc 332e ; 35fe C from color 0x35f7 332e ; 3607 C from color 0x3607 332e ; 360c C from color 0x360c 332e ; 37cb C from color 0x37c7 332e ; 3837 C from color 0x3832 332e ; 38e7 C from color 0x38e7 332e ; 3908 C from color 0x38fc 332e ; 3946 C from color 0x3940 332e ; 3965 C from color 0x062d 332e ; 39e3 C from color 0x39e2 332e ; 3a51 C from color 0x03fa 332e ; 3a6b C from color 0x3a6b 332e ; -------------------------------------------------------------------------------------- 332e 332e seq_br_type a Unconditional Return; Flow R 332f ; -------------------------------------------------------------------------------------- 332f ; Comes from: 332f ; 0754 C from color 0x0203 332f ; 0f01 C from color 0x0000 332f ; 32e6 C from color 0x0000 332f ; 3311 C from color 0x0000 332f ; 3324 C from color 0x0000 332f ; 3ae0 C from color 0x0000 332f ; -------------------------------------------------------------------------------------- 332f 332f seq_br_type a Unconditional Return; Flow R seq_en_micro 0 3330 ; -------------------------------------------------------------------------------------- 3330 ; Comes from: 3330 ; 0b4e C from color 0x0b32 3330 ; -------------------------------------------------------------------------------------- 3330 3330 fiu_tivi_src c mar_0xc; Flow J 0x3335 ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3335 0x3335 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3331 ; -------------------------------------------------------------------------------------- 3331 ; Comes from: 3331 ; 0b4b C from color 0x0b32 3331 ; -------------------------------------------------------------------------------------- 3331 3331 fiu_tivi_src c mar_0xc; Flow J 0x3332 ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 3335 0x3335 seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_int_reads 5 RESOLVE RAM seq_latch 1 seq_random 13 ? typ_a_adr 27 TR02:07 typ_alu_func 1b A_OR_B typ_b_adr 22 TR02:02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3332 3332 fiu_mem_start 7 start_wr_if_true; Flow R cc=False fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 3333 0x3333 seq_cond_sel 56 SEQ.LATCHED_COND seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3333 3333 ioc_load_wdr 0 typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 3334 3334 seq_br_type a Unconditional Return; Flow R seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 3335 3335 fiu_mem_start 2 start-rd; Flow J 0x3336 ioc_adrbs 3 seq seq_br_type 2 Push (branch address) seq_branch_adr 3341 0x3341 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 26 TR11:06 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL 3336 3336 fiu_tivi_src c mar_0xc; Flow J cc=True 0x3397 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 3397 0x3397 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3337 3337 fiu_load_tar 1 hold_tar; Flow J cc=False 0x3366 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3366 0x3366 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 06 Pop_stack+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3338 3338 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 3339 3339 fiu_mem_start 2 start-rd; Flow J 0x333a fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 3345 0x3345 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 27 TR11:07 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 333a 333a fiu_tivi_src c mar_0xc; Flow J cc=True 0x3397 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 3397 0x3397 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 333b 333b fiu_load_tar 1 hold_tar; Flow J cc=False 0x3366 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3366 0x3366 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 seq_random 06 Pop_stack+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 333c 333c seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 333d ; -------------------------------------------------------------------------------------- 333d ; Comes from: 333d ; 353c C from color 0x0000 333d ; -------------------------------------------------------------------------------------- 333d 333d fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x333e fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 3348 0x3348 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 28 TR11:08 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 3b GP04 val_c_source 0 FIU_BUS 333e 333e fiu_tivi_src c mar_0xc; Flow J cc=True 0x3397 ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 3397 0x3397 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 333f 333f fiu_load_tar 1 hold_tar; Flow J cc=False 0x3366 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3366 0x3366 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 seq_random 06 Pop_stack+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3340 3340 seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 3341 3341 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3353 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3353 0x3353 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3342 3342 ioc_adrbs 1 val ; Flow J cc=True 0x3344 ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3344 0x3344 typ_a_adr 2a TR11:0a typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 3343 3343 seq_b_timing 0 Early Condition; Flow J cc=True 0x3344 ; Flow J cc=#0x0 0x334b seq_br_type b Case False seq_branch_adr 334b 0x334b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 32 TR02:12 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3344 3344 seq_b_timing 0 Early Condition; Flow J cc=True 0x3345 ; Flow J cc=#0x0 0x334b seq_br_type b Case False seq_branch_adr 334b 0x334b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3345 3345 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3356 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3356 0x3356 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3346 3346 ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 2a TR11:0a typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 3347 3347 seq_b_timing 0 Early Condition; Flow J cc=True 0x3348 ; Flow J cc=#0x0 0x334b seq_br_type b Case False seq_branch_adr 334b 0x334b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 31 TR11:11 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 3a VR02:1a val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3348 3348 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3358 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 3e fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3358 0x3358 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3349 3349 ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 2a TR11:0a typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 334a 334a seq_b_timing 0 Early Condition; Flow J cc=True 0x334b ; Flow J cc=#0x0 0x334b seq_br_type b Case False seq_branch_adr 334b 0x334b seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 30 TR11:10 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 21 VR05:01 val_alu_func 0 PASS_A val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 5 334b 334b seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 334c 334c fiu_mem_start 3 start-wr; Flow J 0x334f ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 334f 0x334f seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 2 INC_A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 05 GP05 val_c_adr 38 GP07 val_c_mux_sel 2 ALU 334d 334d fiu_mem_start 3 start-wr; Flow J 0x3350 seq_br_type 3 Unconditional Branch seq_branch_adr 3350 0x3350 seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1b A_OR_B typ_b_adr 09 GP09 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 0e GP0e val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 334e 334e seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 334f 334f ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 07 GP07 val_b_adr 07 GP07 3350 3350 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 07 GP07 val_a_adr 0f GP0f val_b_adr 05 GP05 3351 3351 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 3352 3352 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_a_adr 21 TR02:01 typ_alu_func 7 INC_A typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 0 NO_OP 3353 3353 fiu_mem_start 2 start-rd; Flow J cc=True 0x3355 ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3355 0x3355 typ_a_adr 2f TR11:0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 3354 3354 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3355 ; Flow J cc=#0x0 0x335a fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 335a 0x335a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 21 TR00:01 typ_alu_func 0 PASS_A typ_b_adr 09 GP09 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU 3355 3355 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3356 ; Flow J cc=#0x0 0x335a fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 335a 0x335a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2b TR11:0b typ_alu_func 0 PASS_A typ_b_adr 09 GP09 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 3356 3356 fiu_mem_start 2 start-rd ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 2f TR11:0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 3357 3357 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3358 ; Flow J cc=#0x0 0x335a fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 335a 0x335a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2c TR11:0c typ_alu_func 0 PASS_A typ_b_adr 09 GP09 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 3358 3358 fiu_mem_start 2 start-rd ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 2f TR11:0f typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 3359 3359 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x335a ; Flow J cc=#0x0 0x335a fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 335a 0x335a seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2d TR11:0d typ_alu_func 0 PASS_A typ_b_adr 09 GP09 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 11 335a 335a fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x3360 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 3c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3360 0x3360 typ_a_adr 04 GP04 val_a_adr 04 GP04 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 335b 335b fiu_len_fill_lit 41 zero-fill 0x1; Flow J 0x335e fiu_load_tar 1 hold_tar fiu_offs_lit 3a fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 335e 0x335e typ_a_adr 04 GP04 335c 335c fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x3363 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3363 0x3363 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 04 GP04 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 335d 335d seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 335e 335e fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 04 GP04 val_c_adr 3b GP04 335f 335f ioc_load_wdr 0 ; Flow J 0x3361 seq_br_type 3 Unconditional Branch seq_branch_adr 3361 0x3361 seq_en_micro 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 3360 3360 ioc_load_wdr 0 ; Flow J 0x3361 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3361 0x3361 seq_en_micro 0 val_b_adr 04 GP04 3361 3361 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 0 PASS_A 3362 3362 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 07 GP07 val_b_adr 05 GP05 3363 3363 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 04 GP04 val_b_adr 05 GP05 3364 3364 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_alu_func 1a PASS_B typ_b_adr 09 GP09 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 3365 3365 ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return typ_a_adr 21 TR02:01 typ_alu_func 7 INC_A typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 0 NO_OP 3366 3366 ioc_adrbs 2 typ ; Flow J cc=True 0x3369 ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3369 0x3369 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 04 GP04 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3367 3367 fiu_mem_start 3 start-wr; Flow C cc=False 0x20a fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 21 TR02:01 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR02:02 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3f VR1e:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1e 3368 3368 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x336b fiu_load_mdr 1 hold_mdr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 336b 0x336b seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 07 GP07 val_b_adr 07 GP07 3369 3369 fiu_mem_start 3 start-wr; Flow C cc=False 0x20a fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 21 TR02:01 typ_alu_func 6 A_MINUS_B typ_b_adr 22 TR02:02 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3f VR1e:1f val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1e 336a 336a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x336b fiu_load_mdr 1 hold_mdr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 336b 0x336b seq_en_micro 0 typ_a_adr 0f GP0f typ_b_adr 29 TR11:09 typ_frame 11 val_b_adr 07 GP07 336b 336b fiu_len_fill_lit 4c zero-fill 0xc fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert ioc_adrbs 3 seq seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 21 TR02:01 typ_alu_func 7 INC_A typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 336c 336c fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_a_adr 3c TR02:1c typ_alu_func 1b A_OR_B typ_b_adr 22 TR02:02 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 336d 336d ioc_load_wdr 0 typ_b_adr 22 TR02:02 typ_frame 2 val_b_adr 22 VR02:02 val_frame 2 336e 336e seq_br_type a Unconditional Return; Flow R 336f ; -------------------------------------------------------------------------------------- 336f ; Comes from: 336f ; 0236 C from color 0x0000 336f ; -------------------------------------------------------------------------------------- 336f 336f fiu_tivi_src c mar_0xc; Flow C 0x3396 ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3396 0x3396 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3370 3370 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x337a fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 3e fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 337a 0x337a seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 3371 3371 fiu_load_oreg 1 hold_oreg; Flow J 0x337a fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 337a 0x337a typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 3372 3372 fiu_mem_start 4 continue; Flow J 0x3373 seq_br_type 2 Push (branch address) seq_branch_adr 3378 0x3378 typ_mar_cntl 6 INCREMENT_MAR 3373 3373 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3374 3374 fiu_tivi_src c mar_0xc; Flow J cc=True 0x33a0 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 33a0 0x33a0 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_b_adr 16 CSA/VAL_BUS 3375 3375 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 seq_random 06 Pop_stack+? 3376 3376 seq_br_type a Unconditional Return; Flow R 3377 ; -------------------------------------------------------------------------------------- 3377 ; Comes from: 3377 ; 024e C from color 0x0000 3377 ; 02c0 C from color 0x0000 3377 ; 2f9b C from color 0x0000 3377 ; 38a4 C from color 0x0000 3377 ; -------------------------------------------------------------------------------------- 3377 3377 fiu_tivi_src c mar_0xc; Flow C 0x3396 ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3396 0x3396 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3378 3378 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x338c fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 3e fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 338c 0x338c seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 6 CHECK_CLASS_A_??_B 3379 3379 fiu_load_oreg 1 hold_oreg; Flow J 0x338c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 338c 0x338c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS 337a ; -------------------------------------------------------------------------------------- 337a ; Comes from: 337a ; 0239 C False from color 0x0000 337a ; 0251 C False from color 0x0000 337a ; -------------------------------------------------------------------------------------- 337a 337a fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 337b 337b fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 337c 337c ioc_fiubs 0 fiu ; Flow J cc=True 0x337d ; Flow J cc=#0x0 0x3382 seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 3382 0x3382 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 337d 337d seq_b_timing 0 Early Condition; Flow J cc=True 0x337e ; Flow J cc=#0x0 0x337e seq_br_type b Case False seq_branch_adr 337e 0x337e seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 337e 337e seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 337f 337f fiu_load_oreg 1 hold_oreg; Flow R fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type a Unconditional Return seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Access_Ref Interface_Key Subprogram_For_Call_Elaborated Subvector_Var Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Record_Var Accept_Subprogram Interface_Subprogram Utility_Subprogram Matrix_Var Null_Subprogram seq_en_micro 0 seq_latch 1 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 3380 3380 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x337f fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 337f 0x337f seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3381 3381 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 3382 3382 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3386 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3386 0x3386 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation seq_en_micro 0 seq_latch 1 typ_a_adr 32 TR1e:12 typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1e val_a_adr 04 GP04 3383 3383 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x338b fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 338b 0x338b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Access_Ref Interface_Key Subprogram_For_Call_Elaborated Subvector_Var Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Record_Var Accept_Subprogram Interface_Subprogram Utility_Subprogram Matrix_Var Null_Subprogram seq_en_micro 0 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 1c DEC_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 3384 3384 fiu_load_oreg 1 hold_oreg; Flow R cc=False ; Flow J cc=True 0x338a fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 338a 0x338a seq_cond_sel 28 TYP.OF_KIND_MATCH(0x44) Access_Var Static_Connection Subprogram_Ref_For_Call_Elaborated Access_Ref Interface_Key Subprogram_For_Call_Elaborated Task_Var Dependence_Link Task_Ref Select_Var Auxiliary_Mark Interface_Subprogram_Ref Interface_Subprogram Package_Var Accept_Link seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 4 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 05 GP05 val_alu_func 1c DEC_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3385 3385 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 3386 3386 fiu_load_oreg 1 hold_oreg; Flow R cc=False fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3387 0x3387 seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3387 3387 fiu_mem_start 2 start-rd; Flow J cc=False 0x337a ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 337a 0x337a seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3388 3388 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3389 3389 fiu_mem_start 2 start-rd; Flow J 0x337a ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 337a 0x337a seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 07 GP07 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 338a 338a fiu_load_oreg 1 hold_oreg; Flow R cc=False fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 338b 0x338b seq_cond_sel 28 TYP.OF_KIND_MATCH(0x41) Discrete_Ref Module_Key Subprogram_For_Call Mark_Word_Flag Access_Ref Interface_Key Subprogram_For_Call_Elaborated Subvector_Var Subprogram_For_Call_Visible Subprogram_For_Call_Visible_Elaborated Record_Var Accept_Subprogram Interface_Subprogram Utility_Subprogram Matrix_Var Null_Subprogram seq_en_micro 0 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 1c DEC_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 338b 338b fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3386 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3386 0x3386 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x3e) Control_State Module_Key Slice_Stuff Deletion_Key Static_Connection Interface_Key Dependence_Link Micro_State1 Micro_state2 Control_Allocation Scheduling_Allocation seq_en_micro 0 seq_latch 1 typ_a_adr 32 TR1e:12 typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1e val_a_adr 04 GP04 338c ; -------------------------------------------------------------------------------------- 338c ; Comes from: 338c ; 02c4 C from color 0x02c2 338c ; 063a C from color 0x0000 338c ; 2f9f C from color 0x0000 338c ; 38a8 C from color 0x0000 338c ; -------------------------------------------------------------------------------------- 338c 338c fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 338d 338d fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 7e fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 338e 338e seq_b_timing 0 Early Condition; Flow J cc=True 0x338f ; Flow J cc=#0x0 0x338f seq_br_type b Case False seq_branch_adr 338f 0x338f seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 338f 338f fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3393 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3393 0x3393 seq_en_micro 0 typ_a_adr 2e TR11:0e typ_alu_func 1b A_OR_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 04 GP04 3390 3390 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=False ; Flow J cc=True 0x3395 fiu_load_oreg 1 hold_oreg fiu_offs_lit 3c fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3395 0x3395 seq_en_micro 0 typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 1c DEC_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 3391 3391 fiu_len_fill_lit 41 zero-fill 0x1; Flow R fiu_load_oreg 1 hold_oreg fiu_offs_lit 3a fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3392 3392 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 3393 3393 fiu_len_fill_lit 41 zero-fill 0x1; Flow R cc=False fiu_load_oreg 1 hold_oreg fiu_offs_lit 3e fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3394 0x3394 typ_a_adr 05 GP05 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT 3394 3394 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a 3395 3395 fiu_len_fill_lit 41 zero-fill 0x1; Flow R fiu_load_oreg 1 hold_oreg fiu_offs_lit 3c fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 04 GP04 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 04 GP04 val_rand a PASS_B_HIGH 3396 ; -------------------------------------------------------------------------------------- 3396 ; Comes from: 3396 ; 336f C from color MACRO_Action_Accept_Activation 3396 ; 3377 C from color 0x2f17 3396 ; -------------------------------------------------------------------------------------- 3396 3396 fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x3398 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3398 0x3398 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3397 3397 fiu_len_fill_lit 53 zero-fill 0x13; Flow C cc=True 0x32a9 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a9 0x32a9 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3398 3398 ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 39 GP06 val_c_source 0 FIU_BUS 3399 3399 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_a_adr 33 TR11:13 typ_alu_func 1e A_AND_B typ_b_adr 09 GP09 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 339a 339a ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3f VR1e:1f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1e 339b ; -------------------------------------------------------------------------------------- 339b ; Comes from: 339b ; 2f17 C from color 0x2f17 339b ; 3968 C from color 0x03fa 339b ; -------------------------------------------------------------------------------------- 339b 339b fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME 339c 339c fiu_len_fill_lit 53 zero-fill 0x13; Flow J 0x33a0 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 33a0 0x33a0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 339d ; -------------------------------------------------------------------------------------- 339d ; Comes from: 339d ; 2df9 C from color 0x2def 339d ; -------------------------------------------------------------------------------------- 339d 339d fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 339e 339e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 339f 339f fiu_tivi_src c mar_0xc; Flow J 0x33a0 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 33a0 0x33a0 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_b_adr 16 CSA/VAL_BUS 33a0 33a0 ioc_fiubs 2 typ typ_a_adr 06 GP06 val_c_adr 39 GP06 val_c_source 0 FIU_BUS 33a1 33a1 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 33a2 33a2 ioc_fiubs 1 val ; Flow R seq_br_type a Unconditional Return typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3f VR1e:1f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 1e 33a3 ; -------------------------------------------------------------------------------------- 33a3 ; Comes from: 33a3 ; 0331 C from color 0x0331 33a3 ; 033e C from color 0x033e 33a3 ; 2f54 C from color 0x06b7 33a3 ; 3919 C from color 0x0b32 33a3 ; 3972 C from color 0x0913 33a3 ; 39ae C from color 0x39a6 33a3 ; 3a9e C from color 0x3a9e 33a3 ; -------------------------------------------------------------------------------------- 33a3 33a3 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x33b2 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 33b2 0x33b2 seq_cond_sel 4c SEQ.ME_dispatch seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 33a4 33a4 fiu_len_fill_lit 78 zero-fill 0x38; Flow C 0x2ab4 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_random d disable slice timer seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 33a5 33a5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 19 VR02:06 val_c_mux_sel 2 ALU val_frame 2 33a6 33a6 fiu_len_fill_lit 6f zero-fill 0x2f; Flow C cc=True 0x33b1 fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 33b1 0x33b1 seq_cond_sel 53 SEQ.E_MACRO_EVENT~5 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_frame 2 33a7 33a7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x33bc fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 33bc 0x33bc seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 21 VR02:01 val_frame 2 33a8 33a8 fiu_len_fill_lit 6b zero-fill 0x2b; Flow J cc=True 0x33ae fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 33ae 0x33ae seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1c DEC_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_b_adr 26 VR02:06 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 33a9 33a9 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 33aa 33aa fiu_mem_start 3 start-wr; Flow J cc=True 0x33ac ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 33ac 0x33ac seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 33ab 33ab fiu_mem_start 4 continue; Flow J cc=False 0x33ab ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 33ab 0x33ab seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 14 BOT - 1 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 33ac 33ac ioc_load_wdr 0 typ_b_adr 14 BOT - 1 val_b_adr 14 BOT - 1 33ad 33ad seq_br_type a Unconditional Return; Flow R 33ae 33ae ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 33af ; -------------------------------------------------------------------------------------- 33af ; Comes from: 33af ; 022a C from color MACRO_Action_Signal_Activated 33af ; 0233 C from color 0x0000 33af ; 0249 C from color 0x0000 33af ; 0278 C from color 0x0000 33af ; 036d C from color 0x0000 33af ; 055f C from color 0x0000 33af ; 069b C from color 0x0698 33af ; 0756 C from color 0x0203 33af ; 0adf C from color 0x0adf 33af ; 2fc0 C from color 0x0000 33af ; 37ec C from color 0x0000 33af ; 385c C from color 0x0000 33af ; 3868 C from color 0x0000 33af ; 3884 C from color 0x0000 33af ; 3916 C from color 0x0b32 33af ; 3a10 C from color 0x0000 33af ; 3a6e C from color 0x0000 33af ; 3a72 C from color 0x0000 33af ; 3b1f C from color 0x0000 33af ; 3b2d C from color 0x0000 33af ; 3b3b C from color 0x0000 33af ; 3b4a C from color MACRO_3b46_QQUnknown_InMicrocode 33af ; 3b59 C from color 0x0000 33af ; 3b67 C from color 0x0000 33af ; -------------------------------------------------------------------------------------- 33af 33af fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x2ab4 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 10 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 33b0 33b0 fiu_len_fill_lit 78 zero-fill 0x38; Flow R cc=True ; Flow J cc=False 0x33aa fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 33aa 0x33aa seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_rand 2 DEC_LOOP_COUNTER 33b1 ; -------------------------------------------------------------------------------------- 33b1 ; Comes from: 33b1 ; 33a6 C True from color 0x33a5 33b1 ; -------------------------------------------------------------------------------------- 33b1 33b1 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x3681 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3681 0x3681 seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 3c VR12:1c val_frame 12 33b2 33b2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 33b3 33b3 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 27 TR02:07 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 33b4 33b4 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 70 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 16 CSA/VAL_BUS 33b5 33b5 ioc_load_wdr 0 ; Flow J 0x33b6 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 33b6 0x33b6 seq_en_micro 0 typ_b_adr 0e GP0e 33b6 33b6 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x33a4 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 33a4 0x33a4 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 33b7 33b7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 33b8 33b8 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 27 TR02:07 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 33b9 33b9 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 70 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 16 CSA/VAL_BUS 33ba 33ba ioc_load_wdr 0 ; Flow J 0x33bb ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 33bb 0x33bb seq_en_micro 0 typ_b_adr 0e GP0e 33bb 33bb fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x33c1 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 33c1 0x33c1 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 33bc 33bc fiu_len_fill_lit 6b zero-fill 0x2b fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1c DEC_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR typ_rand 0 NO_OP val_b_adr 26 VR02:06 val_frame 2 33bd 33bd fiu_mem_start 4 continue; Flow C 0x210 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 33be 33be fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 23 TR02:03 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 23 VR02:03 val_frame 2 33bf 33bf ioc_load_wdr 0 ; Flow R cc=True ; Flow J cc=False 0x33aa seq_b_timing 0 Early Condition seq_br_type 8 Return True seq_branch_adr 33aa 0x33aa seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_b_adr 24 TR02:04 typ_frame 2 val_b_adr 24 VR02:04 val_frame 2 val_rand 2 DEC_LOOP_COUNTER 33c0 33c0 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x33b7 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 33b7 0x33b7 seq_cond_sel 4c SEQ.ME_dispatch seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 33c1 33c1 fiu_len_fill_lit 78 zero-fill 0x38; Flow C 0x2ab4 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 33c2 33c2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 15 ? typ_a_adr 0f GP0f typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2f VR02:0f val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 19 VR02:06 val_c_mux_sel 2 ALU val_frame 2 33c3 33c3 fiu_len_fill_lit 6f zero-fill 0x2f; Flow J 0x33a7 fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 33a7 0x33a7 seq_en_micro 0 typ_a_adr 20 TR02:00 typ_frame 2 33c4 ; -------------------------------------------------------------------------------------- 33c4 ; Comes from: 33c4 ; 0877 C from color 0x0821 33c4 ; 2f57 C from color 0x06b7 33c4 ; 374e C from color 0x374d 33c4 ; 39b0 C from color 0x39a6 33c4 ; -------------------------------------------------------------------------------------- 33c4 33c4 fiu_mem_start a start_continue_if_false; Flow J cc=True 0x33d8 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 33d8 0x33d8 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 04 TR02:1b typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 30 VR02:10 val_c_adr 03 VR02:1c val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 33c5 33c5 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_tivi_src 8 type_var ioc_random 6 load slice timer ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 42 Load_current_lex+Load_control_pred+? typ_a_adr 20 TR02:00 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 33c6 33c6 fiu_len_fill_lit 5a zero-fill 0x1a; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 typ_a_adr 21 TR02:01 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 33c7 33c7 fiu_len_fill_lit 43 zero-fill 0x3 fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 2 33c8 33c8 fiu_mem_start 6 start_rd_if_false; Flow C cc=True 0x33da ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 33da 0x33da seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_en_micro 0 typ_a_adr 3e TR02:1e typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 33c9 33c9 fiu_tivi_src 4 fiu_var; Flow J cc=True 0x33d5 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 33d5 0x33d5 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 45 Load_current_name+? typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 21 TR02:01 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 33ca 33ca fiu_load_var 1 hold_var; Flow J cc=False 0x33e4 fiu_mem_start 5 start_rd_if_true fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 33e4 0x33e4 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 46 ? typ_a_adr 39 TR02:19 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS 33cb 33cb fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 0e GP0e typ_b_adr 0d GP0d typ_c_adr 28 LOOP_COUNTER typ_c_lit 0 typ_c_source 0 FIU_BUS typ_frame 1f val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 6 33cc 33cc fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=False 0x33e4 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 33e4 0x33e4 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 3f Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 33cd 33cd fiu_mem_start 2 start-rd; Flow J cc=False 0x33d0 ioc_adrbs 3 seq ioc_tvbs 5 seq+seq seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 33d0 0x33d0 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_lex_adr 2 seq_random 53 ? typ_a_adr 0e GP0e typ_alu_func 1e A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 9 LOAD_MAR_CODE val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 6 33ce 33ce ioc_adrbs 3 seq ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 13 ? typ_a_adr 3a TR02:1a typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 28 LOOP_COUNTER typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_a_adr 0d GP0d val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e 33cf 33cf ioc_random c enable slice timer; Flow R cc=True ; Flow J cc=False 0x33e8 ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 33e8 0x33e8 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 21 TR02:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B 33d0 33d0 ioc_adrbs 3 seq ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_latch 1 seq_random 13 ? typ_a_adr 3a TR02:1a typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 28 LOOP_COUNTER typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_a_adr 0d GP0d val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e 33d1 33d1 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x33e8 ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 33e8 0x33e8 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 33d2 33d2 fiu_mem_start 4 continue seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 33d3 33d3 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 typ_a_adr 23 TR02:03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 33d4 33d4 ioc_random c enable slice timer; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 typ_a_adr 24 TR02:04 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 33d5 33d5 ioc_adrbs 3 seq ; Flow J 0x33d6 seq_br_type 2 Push (branch address) seq_branch_adr 07e9 0x07e9 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 1a TR02:05 typ_c_mux_sel 0 ALU typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_c_adr 1a VR02:05 val_frame 2 33d6 33d6 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 21 TR02:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR02:1d typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 33d7 33d7 ioc_random c enable slice timer; Flow R seq_br_type a Unconditional Return seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 33d8 33d8 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 33d9 33d9 fiu_mem_start 2 start-rd; Flow J 0x33c4 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 33c4 0x33c4 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 7 33da ; -------------------------------------------------------------------------------------- 33da ; Comes from: 33da ; 33c8 C True from color 0x33c7 33da ; -------------------------------------------------------------------------------------- 33da 33da fiu_mem_start 6 start_rd_if_false; Flow R cc=True ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 33db 0x33db seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 21 TR02:01 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 33db 33db ioc_fiubs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_a_adr 0f GP0f val_b_adr 39 VR02:19 val_frame 2 33dc 33dc fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x33df fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 33df 0x33df seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 33dd 33dd fiu_mem_start 2 start-rd; Flow R cc=True ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 33de 0x33de seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_c_adr 33 GP0c val_a_adr 31 VR05:11 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 5 33de 33de fiu_mem_start 2 start-rd; Flow R ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 27 TR02:07 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A 33df 33df ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_c_adr 33 GP0c typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 33e0 33e0 fiu_mem_start 3 start-wr seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 0c GP0c typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 18 NOT_A_AND_B val_b_adr 0c GP0c val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 5 33e1 33e1 ioc_load_wdr 0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_b_adr 0c GP0c val_a_adr 25 VR09:05 val_alu_func 1d A_AND_NOT_B val_b_adr 0c GP0c val_frame 9 33e2 33e2 fiu_mem_start 6 start_rd_if_false; Flow R cc=False ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 33e3 0x33e3 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A 33e3 33e3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 27 TR02:07 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 0f GP0f val_alu_func 0 PASS_A 33e4 33e4 seq_en_micro 0 seq_int_reads 5 RESOLVE RAM seq_random 6b ? typ_a_adr 3a TR02:1a typ_alu_func 0 PASS_A typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 33e5 33e5 seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 33e6 33e6 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 31 ? val_a_adr 0f GP0f 33e7 33e7 seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 31 ? typ_b_adr 3b TR02:1b typ_frame 2 33e8 33e8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 33e9 33e9 fiu_mem_start 4 continue seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR 33ea 33ea ioc_adrbs 3 seq ; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_a_adr 23 TR02:03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 33eb 33eb ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) seq_en_micro 0 typ_a_adr 24 TR02:04 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 33ec ; -------------------------------------------------------------------------------------- 33ec ; Comes from: 33ec ; 0738 C from color 0x0738 33ec ; 2f59 C from color 0x06b7 33ec ; 39b1 C True from color 0x39a6 33ec ; -------------------------------------------------------------------------------------- 33ec 33ec fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 40 SEQ.macro_restartable seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 33ed 33ed seq_en_micro 0 33ee 33ee fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x33f5 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 33f5 0x33f5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 5 RESOLVE RAM typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 33ef 33ef seq_en_micro 0 33f0 33f0 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x33f2 ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 33f2 0x33f2 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 7 INC_A typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 33f1 33f1 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x33c4 fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 33c4 0x33c4 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 33f2 33f2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 33f3 33f3 seq_en_micro 0 33f4 33f4 seq_br_type 3 Unconditional Branch; Flow J 0x33ec seq_branch_adr 33ec 0x33ec 33f5 33f5 ioc_adrbs 3 seq ; Flow C 0x34cd seq_br_type 7 Unconditional Call seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 33f6 33f6 ioc_fiubs 2 typ ; Flow J cc=True 0x33ec seq_br_type 1 Branch True seq_branch_adr 33ec 0x33ec seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 38 TR07:18 typ_frame 7 val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 33f7 33f7 seq_br_type 3 Unconditional Branch; Flow J 0x33ec seq_branch_adr 33ec 0x33ec seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 59 ? val_b_adr 0f GP0f 33f8 ; -------------------------------------------------------------------------------------- 33f8 ; Comes from: 33f8 ; 3413 C from color 0x3411 33f8 ; 3417 C from color 0x3411 33f8 ; 3432 C from color 0x22fd 33f8 ; 344a C from color 0x0b53 33f8 ; 344e C from color 0x0b53 33f8 ; -------------------------------------------------------------------------------------- 33f8 33f8 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 33f9 ; -------------------------------------------------------------------------------------- 33f9 ; Comes from: 33f9 ; 0d6f C from color 0x0000 33f9 ; 0d82 C from color 0x0000 33f9 ; 0db4 C from color 0x0000 33f9 ; 0dda C from color 0x0dd0 33f9 ; 0de9 C from color 0x0de2 33f9 ; 3419 C from color 0x3411 33f9 ; 341b C from color 0x3411 33f9 ; 343b C from color 0x22fd 33f9 ; 3450 C from color 0x0b53 33f9 ; 34eb C from color 0x0000 33f9 ; 34fb C from color 0x0000 33f9 ; -------------------------------------------------------------------------------------- 33f9 33f9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 11 start_tag_query fiu_op_sel 3 insert ioc_tvbs 3 fiu+fiu seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR0d:02 val_c_mux_sel 2 ALU val_frame d 33fa 33fa fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 33fb 33fb ioc_tvbs 2 fiu+val; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU val_a_adr 30 VR12:10 val_alu_func 18 NOT_A_AND_B val_b_adr 0b GP0b val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 33fc 33fc fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 13 start_available_query fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 0b GP0b val_b_adr 0b GP0b val_c_adr 1c VR0d:03 val_c_source 0 FIU_BUS val_frame d 33fd 33fd fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 73 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 11 val_a_adr 0b GP0b val_alu_func 1e A_AND_B val_b_adr 25 VR05:05 val_frame 5 33fe 33fe seq_br_type 7 Unconditional Call; Flow C 0x3525 seq_branch_adr 3525 0x3525 seq_en_micro 0 33ff 33ff fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3409 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3409 0x3409 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 30 VR12:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 3400 3400 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 33 GP0c typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 3401 3401 fiu_len_fill_lit 40 zero-fill 0x0 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 29 TR0d:09 typ_alu_func 1b A_OR_B typ_b_adr 0c GP0c typ_frame d typ_mar_cntl b LOAD_MAR_DATA 3402 3402 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS 3403 3403 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 3404 3404 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3405 3405 fiu_load_tar 1 hold_tar; Flow C 0x352c fiu_load_var 1 hold_var fiu_mem_start f start_physical_tag_rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 352c 0x352c seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 0c GP0c typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_b_adr 0c GP0c 3406 3406 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 30 VR12:10 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 3407 3407 fiu_mem_start 10 start_physical_tag_wr; Flow J 0x3408 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 340c 0x340c seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 3408 3408 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0x34fd fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 34fd 0x34fd seq_en_micro 0 val_b_adr 0b GP0b 3409 3409 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x1001 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 1001 0x1001 seq_en_micro 0 val_c_adr 1a VR0d:05 val_c_source 0 FIU_BUS val_frame d 340a 340a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x33fa fiu_load_tar 1 hold_tar fiu_mem_start 11 start_tag_query fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 33fa 0x33fa seq_en_micro 0 val_a_adr 23 VR0d:03 val_alu_func 1a PASS_B val_b_adr 25 VR0d:05 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame d 340b 340b seq_b_timing 0 Early Condition; Flow C cc=True 0x107d seq_br_type 5 Call True seq_branch_adr 107d 0x107d seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 340c 340c fiu_load_tar 1 hold_tar; Flow C 0x2ab4 fiu_load_var 1 hold_var fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d val_a_adr 22 VR0d:02 val_b_adr 0b GP0b val_frame d 340d 340d fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_len_fill_reg_ctl 2 fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 340e 0x340e seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_b_adr 23 VR0d:03 val_frame d 340e ; -------------------------------------------------------------------------------------- 340e ; Comes from: 340e ; 3425 C from color 0x3411 340e ; 3480 C from color 0x02c9 340e ; 349b C from color 0x0000 340e ; 34a2 C from color 0x34a2 340e ; 34c3 C from color 0x0e8e 340e ; 3505 C from color 0x3505 340e ; 350e C from color 0x350e 340e ; -------------------------------------------------------------------------------------- 340e 340e seq_br_type a Unconditional Return; Flow R seq_en_micro 0 340f ; -------------------------------------------------------------------------------------- 340f ; Comes from: 340f ; 3411 C from color 0x3411 340f ; 3431 C from color 0x22fd 340f ; 3448 C from color 0x0b53 340f ; -------------------------------------------------------------------------------------- 340f 340f seq_en_micro 0 3410 3410 fiu_len_fill_reg_ctl 2 ; Flow R fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 3411 3411 seq_br_type 7 Unconditional Call; Flow C 0x340f seq_branch_adr 340f 0x340f typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 3412 ; -------------------------------------------------------------------------------------- 3412 ; Comes from: 3412 ; 3917 C from color 0x0b32 3412 ; -------------------------------------------------------------------------------------- 3412 3412 fiu_tivi_src c mar_0xc ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR0d:01 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR0d:01 val_c_mux_sel 2 ALU val_frame d 3413 3413 fiu_mem_start 2 start-rd; Flow C 0x33f8 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33f8 0x33f8 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3414 3414 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3411 seq_br_type 0 Branch False seq_branch_adr 3411 0x3411 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 3415 3415 fiu_tivi_src c mar_0xc; Flow C 0x3526 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3526 0x3526 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 3416 3416 ioc_tvbs 8 typ+mem seq_en_micro 0 typ_a_adr 3a TR1b:1a typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1b val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 3417 3417 fiu_mem_start 2 start-rd; Flow C 0x33f8 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33f8 0x33f8 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3418 3418 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 3419 3419 ioc_adrbs 1 val ; Flow C 0x33f9 ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 33f9 0x33f9 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 341a 341a fiu_len_fill_reg_ctl 2 ; Flow J cc=True 0x3412 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3412 0x3412 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 341b 341b ioc_adrbs 1 val ; Flow C 0x33f9 seq_br_type 7 Unconditional Call seq_branch_adr 33f9 0x33f9 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR0d:01 val_alu_func 13 ONES val_frame d val_rand 9 PASS_A_HIGH 341c 341c fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x3429 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3429 0x3429 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 341d 341d fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3a VR1b:1a val_frame 1b 341e 341e fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 3b TR1b:1b typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3b VR1b:1b val_frame 1b 341f 341f fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_a_adr 28 TR05:08 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS val_b_adr 39 VR02:19 val_frame 2 3420 3420 fiu_mem_start 4 continue; Flow J cc=False 0x3420 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3420 0x3420 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT 3421 3421 fiu_len_fill_lit 50 zero-fill 0x10; Flow J cc=True 0x3424 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3424 0x3424 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 3422 3422 fiu_mem_start 3 start-wr; Flow J cc=True 0x3420 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 3420 0x3420 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 3d TR08:1d typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3423 3423 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 3424 3424 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3428 seq_br_type 1 Branch True seq_branch_adr 3428 0x3428 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 3425 3425 fiu_mem_start 2 start-rd; Flow C 0x340e ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 340e 0x340e seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame c 3426 3426 fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 3 start-wr fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 3d VR06:1d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 3427 3427 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 val_b_adr 0f GP0f 3428 3428 fiu_len_fill_reg_ctl 2 ; Flow C 0x2ab4 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 21 TR0d:01 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl 4 RESTORE_MAR val_alu_func 1a PASS_B val_b_adr 21 VR0d:01 val_frame d 3429 3429 fiu_mem_start 11 start_tag_query ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR0d:01 val_c_adr 1d VR0d:02 val_c_source 0 FIU_BUS val_frame d val_rand 9 PASS_A_HIGH 342a 342a seq_br_type 7 Unconditional Call; Flow C 0x352b seq_branch_adr 352b 0x352b seq_en_micro 0 342b 342b ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 342c 342c fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 342d 342d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x350a fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 350a 0x350a seq_en_micro 0 val_b_adr 0b GP0b val_c_adr 1c VR0d:03 val_c_source 0 FIU_BUS val_frame d 342e 342e ioc_adrbs 1 val ; Flow C 0x107d seq_br_type 7 Unconditional Call seq_branch_adr 107d 0x107d seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR0d:01 val_alu_func 13 ONES val_frame d val_rand 9 PASS_A_HIGH 342f 342f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d val_b_adr 22 VR0d:02 val_frame d 3430 3430 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3412 fiu_len_fill_reg_ctl 2 fiu_load_mdr 1 hold_mdr fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3412 0x3412 seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 23 VR0d:03 val_alu_func 1a PASS_B val_b_adr 21 VR0d:01 val_frame d 3431 3431 seq_br_type 7 Unconditional Call; Flow C 0x340f seq_branch_adr 340f 0x340f typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 3432 3432 fiu_mem_start 2 start-rd; Flow C 0x33f8 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 33f8 0x33f8 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR0d:01 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR0d:01 val_c_source 0 FIU_BUS val_frame d val_rand a PASS_B_HIGH 3433 3433 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3431 seq_br_type 0 Branch False seq_branch_adr 3431 0x3431 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 3434 3434 fiu_tivi_src c mar_0xc; Flow C 0x3526 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3526 0x3526 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 3435 3435 ioc_tvbs 8 typ+mem seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 3436 3436 fiu_mem_start 11 start_tag_query; Flow C 0x3523 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3523 0x3523 seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 3437 3437 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x343b fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 343b 0x343b seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 36 VR12:16 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 3438 3438 fiu_mem_start 10 start_physical_tag_wr; Flow J cc=False 0x343a fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 343a 0x343a seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 0d GP0d typ_frame 2 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3439 3439 ioc_load_wdr 0 ; Flow J 0x343a seq_br_type 3 Unconditional Branch seq_branch_adr 343a 0x343a seq_en_micro 0 val_b_adr 0d GP0d 343a 343a fiu_mem_start 2 start-rd; Flow J 0x343e fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 343e 0x343e seq_en_micro 0 typ_a_adr 33 TR02:13 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR0d:01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_frame d val_rand 9 PASS_A_HIGH 343b 343b seq_br_type 7 Unconditional Call; Flow C 0x33f9 seq_branch_adr 33f9 0x33f9 seq_en_micro 0 343c 343c fiu_len_fill_reg_ctl 2 ; Flow J cc=True 0x3432 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3432 0x3432 seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 343d 343d fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 343e 343e fiu_mem_start 4 continue ioc_fiubs 0 fiu seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 1d VR0d:02 val_c_source 0 FIU_BUS val_frame d 343f 343f fiu_load_var 1 hold_var; Flow J cc=False 0x3446 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3446 0x3446 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3440 3440 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 3441 3441 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 21 TR00:01 typ_alu_func 1e A_AND_B typ_b_adr 0f GP0f val_a_adr 21 VR07:01 val_alu_func 1e A_AND_B val_b_adr 0e GP0e val_frame 7 3442 3442 fiu_mem_start 3 start-wr; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 21 TR00:01 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 3443 3443 fiu_mem_start 9 start_continue_if_true; Flow C 0x210 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_lit 1 typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 34 VR12:14 val_alu_func 1b A_OR_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 12 3444 3444 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 3445 3445 fiu_len_fill_reg_ctl 2 ; Flow R fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_br_type a Unconditional Return seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_b_adr 22 VR0d:02 val_frame d 3446 3446 fiu_mem_start 11 start_tag_query; Flow C 0x34c5 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34c5 0x34c5 seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 3447 3447 fiu_len_fill_reg_ctl 2 ; Flow J 0x3432 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3432 0x3432 seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 3448 3448 seq_br_type 7 Unconditional Call; Flow C 0x340f seq_branch_adr 340f 0x340f typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 3449 3449 fiu_tivi_src c mar_0xc ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR0d:01 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR0d:01 val_c_mux_sel 2 ALU val_frame d 344a 344a fiu_mem_start 2 start-rd; Flow C 0x33f8 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33f8 0x33f8 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 344b 344b ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3448 seq_br_type 0 Branch False seq_branch_adr 3448 0x3448 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 344c 344c fiu_tivi_src c mar_0xc; Flow C 0x3526 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3526 0x3526 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 344d 344d ioc_tvbs 8 typ+mem seq_en_micro 0 typ_a_adr 3a TR1b:1a typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1b val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 344e 344e fiu_mem_start 2 start-rd; Flow C 0x33f8 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33f8 0x33f8 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 344f 344f ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 3450 3450 ioc_adrbs 1 val ; Flow C 0x33f9 ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 33f9 0x33f9 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d typ_mar_cntl a LOAD_MAR_IMPORT typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 3451 3451 fiu_len_fill_reg_ctl 2 ; Flow J cc=True 0x3449 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3449 0x3449 seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 21 VR0d:01 val_alu_func 0 PASS_A val_frame d 3452 3452 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 37 TR07:17 typ_alu_func 1c DEC_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl a LOAD_MAR_IMPORT val_a_adr 21 VR0d:01 val_frame d val_rand 9 PASS_A_HIGH 3453 3453 fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 39 VR02:19 val_frame 2 3454 3454 fiu_mem_start 4 continue; Flow J cc=False 0x3454 ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3454 0x3454 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 39 VR02:19 val_frame 2 3455 3455 fiu_len_fill_reg_ctl 2 ; Flow C 0x2ab4 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 21 TR0d:01 typ_frame d val_alu_func 1a PASS_B val_b_adr 21 VR0d:01 val_frame d 3456 ; -------------------------------------------------------------------------------------- 3456 ; Comes from: 3456 ; 3489 C from color 0x02c9 3456 ; 34b2 C from color 0x340d 3456 ; 34b8 C from color 0x340d 3456 ; 34bb C from color 0x340d 3456 ; -------------------------------------------------------------------------------------- 3456 3456 fiu_tivi_src c mar_0xc; Flow C 0x2ab4 ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 33 VR02:13 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3457 3457 fiu_mem_start 11 start_tag_query fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 2 fiu+val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_mar_cntl 6 INCREMENT_MAR val_a_adr 33 VR02:13 val_alu_func 18 NOT_A_AND_B val_b_adr 0e GP0e val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 2 3458 3458 fiu_vmux_sel 1 fill value; Flow R cc=True ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3459 0x3459 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 5 DEC_A_MINUS_B val_b_adr 0e GP0e val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3459 3459 fiu_tivi_src c mar_0xc; Flow J cc=True 0x3466 ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3466 0x3466 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 33 TR12:13 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 12 typ_rand c WRITE_OUTER_FRAME val_a_adr 0c GP0c val_alu_func 6 A_MINUS_B val_b_adr 3b VR12:1b val_frame 12 345a 345a seq_br_type 7 Unconditional Call; Flow C 0x3525 seq_branch_adr 3525 0x3525 seq_en_micro 0 345b 345b fiu_tivi_src 1 tar_val; Flow J cc=False 0x3460 ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3460 0x3460 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 2c VR12:0c val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 345c 345c fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x345f fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 345f 0x345f seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_alu_func 1d A_AND_NOT_B typ_b_adr 0f GP0f typ_frame 6 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 345d 345d fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x345f ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 345f 0x345f seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 32 TR11:12 typ_alu_func 1e A_AND_B typ_b_adr 0f GP0f typ_frame 11 val_a_adr 39 VR06:19 val_alu_func 1b A_OR_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 345e 345e ioc_load_wdr 0 ; Flow J 0x3460 seq_br_type 3 Unconditional Branch seq_branch_adr 3460 0x3460 seq_en_micro 0 val_b_adr 0f GP0f 345f 345f ioc_load_wdr 0 ; Flow C 0x350a seq_br_type 7 Unconditional Call seq_branch_adr 350a 0x350a seq_en_micro 0 val_b_adr 0f GP0f 3460 3460 fiu_mem_start 11 start_tag_query; Flow J cc=False 0x3463 fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3463 0x3463 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 0e GP0e typ_mar_cntl 4 RESTORE_MAR val_a_adr 0e GP0e val_alu_func 1 A_PLUS_B val_b_adr 3f VR06:1f val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 6 3461 3461 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 3462 3462 fiu_mem_start 11 start_tag_query seq_en_micro 0 3463 3463 seq_br_type 1 Branch True; Flow J cc=True 0x345a seq_branch_adr 345a 0x345a seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 6 A_MINUS_B val_b_adr 0d GP0d 3464 3464 fiu_tivi_src 2 tar_fiu; Flow R cc=True ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 3465 0x3465 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3465 3465 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_c_adr 32 GP0d val_c_mux_sel 2 ALU 3466 3466 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 3f TR06:1f typ_frame 6 val_a_adr 2c VR0d:0c val_b_adr 16 CSA/VAL_BUS val_frame d val_rand c START_MULTIPLY 3467 3467 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3479 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3479 0x3479 seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 16 PRODUCT val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3468 3468 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x346b seq_br_type 0 Branch False seq_branch_adr 346b 0x346b seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 3469 3469 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 346a 346a fiu_mem_start 14 start_name_query; Flow J 0x3468 seq_br_type 3 Unconditional Branch seq_branch_adr 3468 0x3468 seq_en_micro 0 346b 346b fiu_tivi_src 3 tar_frame; Flow J cc=False 0x3479 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3479 0x3479 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 4 346c 346c fiu_mem_start f start_physical_tag_rd fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 31 TR05:11 typ_frame 5 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 346d 346d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3470 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3470 0x3470 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 14 ZEROS 346e 346e seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 346f 346f fiu_mem_start f start_physical_tag_rd; Flow J 0x346d seq_br_type 3 Unconditional Branch seq_branch_adr 346d 0x346d seq_en_micro 0 3470 3470 fiu_mem_start 15 setup_tag_read; Flow J cc=False 0x3478 seq_br_type 0 Branch False seq_branch_adr 3478 0x3478 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3471 3471 fiu_len_fill_lit 5c zero-fill 0x1c; Flow J cc=False 0x3478 fiu_mem_start 15 setup_tag_read fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_br_type 0 Branch False seq_branch_adr 3478 0x3478 seq_cond_sel 07 VAL.ALU_32_CO(late) seq_en_micro 0 typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS val_a_adr 0e GP0e val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 3472 3472 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3478 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_br_type 1 Branch True seq_branch_adr 3478 0x3478 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 19 X_XOR_B typ_b_adr 0c GP0c typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_c_adr 30 GP0f 3473 3473 fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x3475 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 3475 0x3475 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 2b TR06:0b typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_a_adr 0f GP0f val_alu_func 1d A_AND_NOT_B val_b_adr 2c VR12:0c val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3474 3474 fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x3478 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3478 0x3478 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) seq_en_micro 0 typ_a_adr 0b GP0b typ_frame 1 3475 3475 ioc_load_wdr 0 ; Flow J cc=True 0x347c seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 347c 0x347c seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 2e TR11:0e typ_frame 11 val_a_adr 39 VR06:19 val_alu_func 1b A_OR_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 6 3476 3476 seq_br_type 0 Branch False; Flow J cc=False 0x3478 seq_branch_adr 3478 0x3478 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3477 3477 seq_br_type 5 Call True; Flow C cc=True 0x350a seq_branch_adr 350a 0x350a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 3478 3478 fiu_mem_start f start_physical_tag_rd; Flow J cc=True 0x346d fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 346d 0x346d seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 31 TR05:11 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 0b GP0b val_alu_func 6 A_MINUS_B val_b_adr 29 VR08:09 val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 8 3479 3479 fiu_mem_start 14 start_name_query; Flow J cc=True 0x3468 fiu_tivi_src 4 fiu_var ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 3468 0x3468 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl f LOAD_MAR_RESERVED typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 0c GP0c val_alu_func 6 A_MINUS_B val_b_adr 3f VR06:1f val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 6 val_rand 9 PASS_A_HIGH 347a 347a fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 347b 0x347b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_b_adr 0d GP0d val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 0e GP0e val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 347b 347b seq_br_type a Unconditional Return; Flow R seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1c DEC_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU 347c 347c fiu_mem_start 10 start_physical_tag_wr; Flow J cc=True 0x3477 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3477 0x3477 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1e A_AND_B val_b_adr 3d VR02:1d val_frame 2 347d 347d ioc_load_wdr 0 ; Flow J 0x3478 seq_br_type 3 Unconditional Branch seq_branch_adr 3478 0x3478 seq_en_micro 0 val_b_adr 0f GP0f 347e 347e fiu_len_fill_reg_ctl 2 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 347f ; -------------------------------------------------------------------------------------- 347f ; Comes from: 347f ; 3497 C True from color 0x0000 347f ; -------------------------------------------------------------------------------------- 347f 347f fiu_tivi_src c mar_0xc; Flow C 0x365a ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 365a 0x365a seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 3480 3480 fiu_mem_start 2 start-rd; Flow C 0x340e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 340e 0x340e seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3f TR09:1f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3481 3481 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3482 seq_br_type 2 Push (branch address) seq_branch_adr 347e 0x347e seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 3482 3482 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3483 3483 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3486 seq_br_type 1 Branch True seq_branch_adr 3486 0x3486 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 0d GP0d val_frame 5 3484 3484 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 39 VR12:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 12 3485 3485 ioc_load_wdr 0 seq_en_micro 0 seq_random 06 Pop_stack+? typ_b_adr 0c GP0c val_b_adr 0c GP0c 3486 3486 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x365c fiu_load_var 1 hold_var fiu_offs_lit 76 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 365c 0x365c seq_en_micro 0 typ_b_adr 0d GP0d typ_mar_cntl 1 RESTORE_RDR val_b_adr 0d GP0d 3487 3487 seq_en_micro 0 3488 3488 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3489 3489 fiu_load_oreg 1 hold_oreg; Flow C 0x3456 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3456 0x3456 seq_en_micro 0 val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 348a 348a fiu_tivi_src c mar_0xc; Flow R cc=False ; Flow J cc=True 0x347f ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 347f 0x347f seq_en_micro 0 typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 348b 348b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x348c fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 3 Unconditional Branch seq_branch_adr 348c 0x348c typ_mar_cntl 6 INCREMENT_MAR 348c ; -------------------------------------------------------------------------------------- 348c ; Comes from: 348c ; 3496 C from color 0x0000 348c ; -------------------------------------------------------------------------------------- 348c 348c fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 348d 348d ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 348e 348e fiu_load_oreg 1 hold_oreg ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_c_adr 1b TR0d:04 typ_frame d val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 348f 348f ioc_adrbs 2 typ ; Flow C 0x3456 ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3456 0x3456 seq_en_micro 0 typ_a_adr 2c TR12:0c typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3490 3490 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d 3491 3491 fiu_load_oreg 1 hold_oreg; Flow C 0x3456 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3456 0x3456 seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3492 3492 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d val_b_adr 24 VR0d:04 val_frame d 3493 3493 fiu_load_oreg 1 hold_oreg; Flow C 0x3456 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3456 0x3456 seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3494 3494 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d val_b_adr 24 VR0d:04 val_frame d 3495 3495 fiu_load_oreg 1 hold_oreg; Flow J 0x3456 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3456 0x3456 seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3496 3496 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x348c fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc seq_br_type 7 Unconditional Call seq_branch_adr 348c 0x348c typ_mar_cntl 6 INCREMENT_MAR 3497 3497 fiu_tivi_src c mar_0xc; Flow C cc=True 0x347f ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 347f 0x347f seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d val_rand a PASS_B_HIGH 3498 3498 ioc_adrbs 1 val ; Flow J 0x3499 seq_br_type 3 Unconditional Branch seq_branch_adr 3499 0x3499 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 3499 3499 fiu_mem_start 11 start_tag_query; Flow C 0x34c5 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34c5 0x34c5 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_source 0 FIU_BUS val_rand a PASS_B_HIGH 349a 349a fiu_len_fill_lit 50 zero-fill 0x10; Flow J cc=True 0x349e fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 349e 0x349e seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_b_adr 0e GP0e val_frame 3 349b 349b fiu_mem_start 2 start-rd; Flow C 0x340e ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 340e 0x340e seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame c 349c 349c fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 7 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 349d 349d ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 0b GP0b 349e 349e fiu_mem_start 2 start-rd; Flow J 0x349f ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 34ac 0x34ac seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 0e GP0e val_frame 4 val_rand a PASS_B_HIGH 349f 349f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 36 TR07:16 typ_frame 7 typ_mar_cntl 6 INCREMENT_MAR 34a0 34a0 fiu_len_fill_lit 48 zero-fill 0x8; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 val_b_adr 16 CSA/VAL_BUS 34a1 34a1 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 34a2 34a2 fiu_mem_start 2 start-rd; Flow C 0x340e fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 340e 0x340e seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 5 val_rand a PASS_B_HIGH 34a3 34a3 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 23 TR01:03 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU typ_frame 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 34a4 34a4 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0c GP0c typ_c_lit 1 typ_frame 1 val_b_adr 0c GP0c 34a5 34a5 fiu_mem_start 3 start-wr; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 34a6 34a6 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR 34a7 34a7 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0d GP0d val_b_adr 0d GP0d 34a8 34a8 fiu_mem_start f start_physical_tag_rd fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 34a9 34a9 fiu_mem_start 15 setup_tag_read fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_a_adr 31 TR02:11 typ_frame 2 val_a_adr 2b VR12:0b val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 34aa 34aa ioc_tvbs a fiu+mem; Flow J cc=False 0x34c8 seq_br_type 0 Branch False seq_branch_adr 34c8 0x34c8 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 0f GP0f val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 34ab 34ab fiu_mem_start 10 start_physical_tag_wr; Flow J 0x34cc seq_br_type 3 Unconditional Branch seq_branch_adr 34cc 0x34cc seq_en_micro 0 val_a_adr 0f GP0f val_alu_func 1b A_OR_B val_b_adr 2d VR04:0d val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 4 34ac 34ac ioc_adrbs 1 val ; Flow J 0x3ba5 seq_br_type 3 Unconditional Branch seq_branch_adr 3ba5 0x3ba5 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 0e GP0e val_rand a PASS_B_HIGH 34ad ; -------------------------------------------------------------------------------------- 34ad ; Comes from: 34ad ; 027c C from color 0x0000 34ad ; -------------------------------------------------------------------------------------- 34ad 34ad fiu_mem_start 4 continue ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 10 typ_mar_cntl 6 INCREMENT_MAR 34ae 34ae fiu_len_fill_lit 5a zero-fill 0x1a; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 34af 34af ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1a TR0d:05 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0d:05 val_c_mux_sel 2 ALU val_frame d 34b0 34b0 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f 34b1 34b1 ioc_tvbs 2 fiu+val; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 1 34b2 34b2 fiu_load_oreg 1 hold_oreg; Flow C 0x3456 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3456 0x3456 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 34b3 34b3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 11 start_tag_query fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_alu_func 13 ONES typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0d GP0d 34b4 34b4 fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x3524 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var seq_br_type 7 Unconditional Call seq_branch_adr 3524 0x3524 seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d 34b5 34b5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x34cb fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 34cb 0x34cb seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 2d VR05:0d val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 5 34b6 34b6 fiu_len_fill_lit 5a zero-fill 0x1a fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_en_micro 0 typ_b_adr 25 TR0d:05 typ_frame d val_b_adr 25 VR0d:05 val_frame d 34b7 34b7 ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 21 TR02:01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT 34b8 34b8 fiu_load_oreg 1 hold_oreg; Flow C 0x3456 ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3456 0x3456 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 34b9 34b9 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 0d GP0d val_alu_func 1a PASS_B val_b_adr 25 VR0d:05 val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame d val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 34ba 34ba fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 25 TR0d:05 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame d val_a_adr 21 VR02:01 val_frame 2 34bb 34bb fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3456 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3456 0x3456 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1a TR0d:05 typ_c_source 0 FIU_BUS typ_frame d typ_mar_cntl b LOAD_MAR_DATA typ_rand 5 CHECK_CLASS_B_LIT 34bc 34bc fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 25 VR0d:05 val_alu_func 1a PASS_B val_b_adr 0d GP0d val_c_adr 1a VR0d:05 val_c_mux_sel 2 ALU val_frame d val_rand 9 PASS_A_HIGH 34bd 34bd fiu_mem_start 4 continue ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR0d:04 typ_frame d typ_mar_cntl 6 INCREMENT_MAR val_b_adr 24 VR0d:04 val_frame d 34be 34be ioc_load_wdr 0 ; Flow J 0x340e seq_br_type 3 Unconditional Branch seq_branch_adr 340e 0x340e seq_en_micro 0 typ_b_adr 25 TR0d:05 typ_frame d val_b_adr 25 VR0d:05 val_frame d 34bf ; -------------------------------------------------------------------------------------- 34bf ; Comes from: 34bf ; 2af8 C from color 0x2aef 34bf ; -------------------------------------------------------------------------------------- 34bf 34bf fiu_mem_start 4 continue fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR 34c0 34c0 ioc_tvbs c mem+mem+csa+dummy typ_a_adr 21 TR00:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 34c1 34c1 fiu_len_fill_lit 5a zero-fill 0x1a; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 21 VR07:01 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 7 34c2 34c2 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 1 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 0f GP0f 34c3 34c3 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x340e fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 340e 0x340e seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 34c4 34c4 fiu_load_oreg 1 hold_oreg; Flow J 0x3456 ioc_adrbs 2 typ ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3456 0x3456 seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 33 VR02:13 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 34c5 ; -------------------------------------------------------------------------------------- 34c5 ; Comes from: 34c5 ; 027d C True from color 0x0000 34c5 ; 0dce C False from color 0x0000 34c5 ; 0dde C from color 0x0dd0 34c5 ; 3446 C from color 0x22fd 34c5 ; 3499 C from color 0x0000 34c5 ; -------------------------------------------------------------------------------------- 34c5 34c5 seq_br_type 7 Unconditional Call; Flow C 0x3524 seq_branch_adr 3524 0x3524 seq_en_micro 0 34c6 34c6 fiu_mem_start 15 setup_tag_read; Flow R cc=False ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 9 Return False seq_branch_adr 34c7 0x34c7 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 2c VR12:0c val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 34c7 34c7 fiu_tivi_src 4 fiu_var; Flow C 0x210 ioc_fiubs 1 val ioc_tvbs a fiu+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 34c8 34c8 fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 34c9 34c9 ioc_load_wdr 0 ; Flow C 0x350a seq_br_type 7 Unconditional Call seq_branch_adr 350a 0x350a seq_en_micro 0 val_b_adr 0f GP0f 34ca 34ca seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 34cb ; -------------------------------------------------------------------------------------- 34cb ; Comes from: 34cb ; 34b5 C True from color 0x340d 34cb ; -------------------------------------------------------------------------------------- 34cb 34cb fiu_mem_start 10 start_physical_tag_wr fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 34cc 34cc ioc_load_wdr 0 ; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_b_adr 0f GP0f 34cd ; -------------------------------------------------------------------------------------- 34cd ; Comes from: 34cd ; 0305 C from color 0x0000 34cd ; 0405 C from color 0x03f0 34cd ; 05b8 C from color 0x05a7 34cd ; 06e0 C from color 0x06ce 34cd ; 0919 C from color 0x0000 34cd ; 0959 C from color MACRO_Execute_Module,Is_Callable 34cd ; 0963 C from color MACRO_Execute_Module,Is_Callable 34cd ; 097d C from color MACRO_Execute_Module,Is_Callable 34cd ; 0b6e C from color 0x0000 34cd ; 0de2 C from color 0x0de2 34cd ; 2d71 C from color ML_break_class 34cd ; 2ed9 C from color 0x0000 34cd ; 2f12 C from color 0x2ef9 34cd ; 2f79 C from color 0x06b7 34cd ; 32e8 C from color 0x0000 34cd ; 32ea C from color 0x0000 34cd ; 33f5 C from color 0x0000 34cd ; 34ee C from color 0x0000 34cd ; 399b C from color 0x03fa 34cd ; 39dc C from color 0x0000 34cd ; 39f1 C from color 0x0000 34cd ; 3a4d C from color 0x0000 34cd ; 3a69 C from color 0x3a69 34cd ; 3a9a C from color 0x0000 34cd ; 3b0a C from color 0x3b09 34cd ; 3b73 C from color 0x0000 34cd ; -------------------------------------------------------------------------------------- 34cd 34cd fiu_mem_start 11 start_tag_query ioc_tvbs 3 fiu+fiu seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR0d:02 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR0d:02 val_c_mux_sel 2 ALU val_frame d 34ce 34ce fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame d typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame d 34cf 34cf seq_br_type 7 Unconditional Call; Flow C 0x3525 seq_branch_adr 3525 0x3525 seq_en_micro 0 34d0 34d0 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x34d9 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 34d9 0x34d9 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_c_adr 1e TR0d:01 typ_frame d val_c_adr 1e VR0d:01 val_frame d 34d1 34d1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x34d2 ; Flow J cc=#0x0 0x34d2 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 34d2 0x34d2 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 val_c_adr 1c VR0d:03 val_c_source 0 FIU_BUS val_frame d 34d2 34d2 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 34d3 34d3 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d val_b_adr 21 VR0d:01 val_frame d 34d4 34d4 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d val_b_adr 21 VR0d:01 val_frame d 34d5 34d5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0xf2b fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame seq_br_type 7 Unconditional Call seq_branch_adr 0f2b 0x0f2b seq_en_micro 0 val_c_adr 30 GP0f 34d6 34d6 fiu_len_fill_reg_ctl 2 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 34d7 34d7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_tivi_src 9 type_val seq_en_micro 0 typ_b_adr 22 TR0d:02 typ_frame d val_b_adr 22 VR0d:02 val_frame d 34d8 34d8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x34cd fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 34cd 0x34cd seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_b_adr 21 TR0d:01 typ_frame d val_a_adr 23 VR0d:03 val_b_adr 21 VR0d:01 val_frame d 34d9 34d9 seq_b_timing 1 Latch Condition; Flow C cc=False 0xfe9 seq_br_type 4 Call False seq_branch_adr 0fe9 0x0fe9 seq_en_micro 0 34da 34da fiu_len_fill_reg_ctl 2 ; Flow J 0x34d7 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 8 type_var ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 34d7 0x34d7 seq_en_micro 0 typ_b_adr 20 TR0d:00 typ_frame d typ_mar_cntl 4 RESTORE_MAR val_a_adr 20 VR0d:00 val_alu_func 0 PASS_A val_frame d 34db 34db fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34dc ; -------------------------------------------------------------------------------------- 34dc ; Comes from: 34dc ; 2f55 C from color 0x06b7 34dc ; 3699 C from color 0x0200 34dc ; 3964 C from color 0x062d 34dc ; 3a54 C from color 0x03fa 34dc ; -------------------------------------------------------------------------------------- 34dc 34dc seq_en_micro 0 34dd 34dd fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34de ; -------------------------------------------------------------------------------------- 34de ; Comes from: 34de ; 2f75 C from color 0x06b7 34de ; 39c7 C from color 0x39bf 34de ; -------------------------------------------------------------------------------------- 34de 34de seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 34df 34df seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 34e0 0x34e0 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 34e0 34e0 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x34e3 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 34e3 0x34e3 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 34e1 34e1 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 34e2 34e2 fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 34e3 34e3 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 34e4 34e4 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 34e5 34e5 fiu_tivi_src c mar_0xc; Flow C 0x3526 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3526 0x3526 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 34e6 34e6 ioc_tvbs 8 typ+mem; Flow C 0x210 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 34e7 34e7 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34db ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34db 0x34db seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 0f GP0f val_rand a PASS_B_HIGH 34e8 34e8 fiu_mem_start 11 start_tag_query; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 34e9 0x34e9 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 0b GP0b val_frame 5 34e9 34e9 seq_en_micro 0 34ea 34ea fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34db seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34db 0x34db seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 34eb 34eb seq_br_type 7 Unconditional Call; Flow C 0x33f9 seq_branch_adr 33f9 0x33f9 seq_en_micro 0 34ec 34ec fiu_mem_start 5 start_rd_if_true; Flow R cc=False ; Flow J cc=True 0x34dc fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 34dc 0x34dc seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34ed 34ed fiu_tivi_src c mar_0xc; Flow J 0x34ee ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 34ee 0x34ee seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34ee 34ee seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_en_micro 0 34ef 34ef fiu_mem_start 5 start_rd_if_true; Flow R cc=False ; Flow J cc=True 0x34f1 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 34f1 0x34f1 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34f0 ; -------------------------------------------------------------------------------------- 34f0 ; Comes from: 34f0 ; 0378 C from color 0x0377 34f0 ; 2f23 C from color 0x2f17 34f0 ; 2f3d C from color 0x2ef9 34f0 ; 3973 C from color 0x0913 34f0 ; 3991 C from color 0x03fa 34f0 ; -------------------------------------------------------------------------------------- 34f0 34f0 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 34f1 34f1 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x34ed fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 34ed 0x34ed seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34f2 34f2 fiu_mem_start 6 start_rd_if_false; Flow R cc=True fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 8 Return True seq_branch_adr 34f3 0x34f3 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 34f3 34f3 fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 34f4 34f4 ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_mar_cntl 1 RESTORE_RDR 34f5 34f5 fiu_tivi_src c mar_0xc; Flow C 0x3526 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3526 0x3526 seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 34f6 34f6 ioc_tvbs 8 typ+mem; Flow C 0x210 seq_b_timing 0 Early Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 val_a_adr 2d VR12:0d val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU val_frame 12 34f7 34f7 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34ee ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34ee 0x34ee seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 13 ONES val_b_adr 0f GP0f val_rand a PASS_B_HIGH 34f8 34f8 fiu_mem_start 11 start_tag_query; Flow R cc=True fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 34f9 0x34f9 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 31 TR02:11 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 0b GP0b val_alu_func 1e A_AND_B val_b_adr 2d VR05:0d val_frame 5 34f9 34f9 seq_en_micro 0 34fa 34fa fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34ee seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 34ee 0x34ee seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 34fb 34fb seq_br_type 7 Unconditional Call; Flow C 0x33f9 seq_branch_adr 33f9 0x33f9 seq_en_micro 0 34fc 34fc fiu_mem_start 6 start_rd_if_false; Flow R cc=False ; Flow J cc=True 0x34f0 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 34f0 0x34f0 seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 34fd ; -------------------------------------------------------------------------------------- 34fd ; Comes from: 34fd ; 08a7 C from color 0x08a5 34fd ; 0fbb C from color 0x0f29 34fd ; -------------------------------------------------------------------------------------- 34fd 34fd fiu_mem_start f start_physical_tag_rd; Flow C 0x3513 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3513 0x3513 seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED 34fe ; -------------------------------------------------------------------------------------- 34fe ; Comes from: 34fe ; 0e04 C from color 0x0000 34fe ; -------------------------------------------------------------------------------------- 34fe 34fe fiu_len_fill_lit 52 zero-fill 0x12 fiu_offs_lit 0c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_a_adr 21 VR11:01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 11 34ff 34ff fiu_load_var 1 hold_var; Flow J cc=False 0x3501 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3501 0x3501 seq_cond_sel 0f VAL.PREVIOUS(early) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1d A_AND_NOT_B typ_b_adr 33 TR12:13 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 3e VR03:1e val_frame 3 3500 3500 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value seq_en_micro 0 val_b_adr 2f VR02:0f val_frame 2 3501 3501 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_source 0 FIU_BUS 3502 3502 fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_en_micro 0 3503 3503 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2a TR04:0a typ_alu_func 7 INC_A typ_c_adr 15 TR04:0a typ_c_mux_sel 0 ALU typ_frame 4 3504 3504 fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x2ab4 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 3505 3505 fiu_mem_start 2 start-rd; Flow C 0x340e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 340e 0x340e seq_en_micro 0 typ_a_adr 2e TR0d:0e typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_frame d typ_mar_cntl b LOAD_MAR_DATA 3506 3506 fiu_load_var 1 hold_var; Flow C 0x210 fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 26 TR07:06 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 7 3507 3507 fiu_load_tar 1 hold_tar fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_b_adr 0d GP0d val_a_adr 0d GP0d 3508 3508 ioc_adrbs 2 typ ; Flow R ioc_tvbs 2 fiu+val seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 3d TR12:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl f LOAD_MAR_RESERVED 3509 3509 fiu_len_fill_lit 52 zero-fill 0x12; Flow J 0x350b fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 350b 0x350b seq_en_micro 0 typ_b_adr 0d GP0d typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_b_adr 0d GP0d 350a ; -------------------------------------------------------------------------------------- 350a ; Comes from: 350a ; 1021 C from color 0x1021 350a ; 1052 C from color 0x1004 350a ; 10aa C from color 0x10aa 350a ; 342d C from color 0x3411 350a ; 345f C from color 0x3457 350a ; 3477 C True from color 0x3457 350a ; 34c9 C from color 0x34a6 350a ; -------------------------------------------------------------------------------------- 350a 350a fiu_len_fill_lit 52 zero-fill 0x12; Flow C 0x3511 fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 3 tar_frame fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3511 0x3511 seq_en_micro 0 typ_b_adr 0d GP0d typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS val_b_adr 0d GP0d 350b 350b fiu_len_fill_lit 47 zero-fill 0x7 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 2a TR0d:0a typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_frame d typ_mar_cntl b LOAD_MAR_DATA 350c 350c fiu_len_fill_lit 47 zero-fill 0x7; Flow C 0x210 fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 2a TR04:0a typ_alu_func 1c DEC_A typ_c_adr 15 TR04:0a typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 24 VR05:04 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 350d 350d fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_length_src 0 length_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS 350e 350e fiu_mem_start 2 start-rd; Flow C 0x340e fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 340e 0x340e seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 1 A_PLUS_B typ_b_adr 2e TR0d:0e typ_frame d typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR02:18 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 350f 350f fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 33 TR06:13 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 6 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 3510 3510 ioc_load_wdr 0 ; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 0d GP0d typ_c_adr 32 GP0d val_b_adr 0d GP0d val_c_adr 32 GP0d 3511 ; -------------------------------------------------------------------------------------- 3511 ; Comes from: 3511 ; 350a C from color 0x0000 3511 ; -------------------------------------------------------------------------------------- 3511 3511 seq_en_micro 0 typ_c_adr 1c TR0c:03 typ_frame c val_c_adr 1c VR0c:03 val_frame c 3512 3512 fiu_mem_start f start_physical_tag_rd; Flow J 0x3514 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3514 0x3514 seq_en_micro 0 typ_alu_func 13 ONES typ_c_adr 1d TR0c:02 typ_c_mux_sel 0 ALU typ_frame c typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3513 ; -------------------------------------------------------------------------------------- 3513 ; Comes from: 3513 ; 34fd C from color 0x0f36 3513 ; -------------------------------------------------------------------------------------- 3513 3513 fiu_mem_start 15 setup_tag_read; Flow J 0x3515 ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3515 0x3515 seq_en_micro 0 typ_c_adr 1d TR0c:02 typ_c_source 0 FIU_BUS typ_frame c val_a_adr 31 VR02:11 val_frame 2 3514 3514 fiu_mem_start 15 setup_tag_read seq_en_micro 0 3515 3515 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0x351d fiu_mem_start 15 setup_tag_read fiu_offs_lit 7d fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 351d 0x351d seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 29 VR0c:09 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1a VR0c:05 val_c_source 0 FIU_BUS val_frame c 3516 3516 fiu_len_fill_lit 50 zero-fill 0x10; Flow J cc=True 0x351d fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 8 typ+mem seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 351d 0x351d seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 25 VR0c:05 val_alu_func 19 X_XOR_B val_b_adr 26 VR0c:06 val_c_adr 1a VR0c:05 val_c_source 0 FIU_BUS val_frame c 3517 3517 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3522 seq_br_type 1 Branch True seq_branch_adr 3522 0x3522 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_frame 3 3518 3518 fiu_mem_start 2 start-rd; Flow J 0x3519 ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 351c 0x351c seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 22 TR0c:02 typ_alu_func 1c DEC_A typ_frame c typ_mar_cntl b LOAD_MAR_DATA val_a_adr 22 VR0c:02 val_alu_func 1 A_PLUS_B val_b_adr 25 VR0c:05 val_frame c 3519 3519 seq_b_timing 0 Early Condition; Flow J cc=True 0x351f seq_br_type 1 Branch True seq_branch_adr 351f 0x351f seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 351a 351a fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x351e fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 351e 0x351e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 27 TR0c:07 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0c:04 typ_c_source 0 FIU_BUS typ_frame c val_a_adr 28 VR0c:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0c:04 val_c_mux_sel 2 ALU val_frame c 351b 351b fiu_mem_start 7 start_wr_if_true; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 351c 351c ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 24 TR0c:04 typ_frame c val_b_adr 24 VR0c:04 val_frame c 351d 351d ioc_load_wdr 0 ; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 23 TR0c:03 typ_frame c val_b_adr 23 VR0c:03 val_frame c 351e 351e fiu_mem_start 7 start_wr_if_true; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 24 TR0c:04 typ_alu_func 6 A_MINUS_B typ_b_adr 27 TR0c:07 typ_c_adr 1b TR0c:04 typ_c_mux_sel 0 ALU typ_frame c 351f 351f fiu_tivi_src 1 tar_val; Flow J cc=True 0x3521 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3521 0x3521 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0c:04 typ_c_mux_sel 0 ALU typ_frame c val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0c:04 val_c_source 0 FIU_BUS val_frame c val_rand 9 PASS_A_HIGH 3520 3520 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x351e seq_br_type 1 Branch True seq_branch_adr 351e 0x351e seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 27 TR0c:07 typ_alu_func 1e A_AND_B typ_b_adr 24 TR0c:04 typ_frame c val_a_adr 24 VR0c:04 val_alu_func 1c DEC_A val_c_adr 1b VR0c:04 val_c_mux_sel 2 ALU val_frame c 3521 3521 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3522 3522 seq_br_type 3 Unconditional Branch; Flow J 0x351d seq_branch_adr 351d 0x351d seq_en_micro 0 typ_a_adr 25 TR0c:05 typ_alu_func 1 A_PLUS_B typ_b_adr 22 TR0c:02 typ_c_adr 1a TR0c:05 typ_c_mux_sel 0 ALU typ_frame c 3523 ; -------------------------------------------------------------------------------------- 3523 ; Comes from: 3523 ; 0d84 C from color 0x0000 3523 ; 0e32 C from color 0x0000 3523 ; 0ed9 C from color 0x0000 3523 ; 0f07 C from color 0x0f07 3523 ; 103a C from color 0x1004 3523 ; 3436 C from color 0x22fd 3523 ; -------------------------------------------------------------------------------------- 3523 3523 seq_en_micro 0 3524 ; -------------------------------------------------------------------------------------- 3524 ; Comes from: 3524 ; 0fab C from color 0x0f29 3524 ; 2af6 C from color 0x2aef 3524 ; 34b4 C from color 0x340d 3524 ; 34c5 C from color 0x34c5 3524 ; 3b8f C from color 0x3b8f 3524 ; -------------------------------------------------------------------------------------- 3524 3524 seq_en_micro 0 3525 ; -------------------------------------------------------------------------------------- 3525 ; Comes from: 3525 ; 084a C from color 0x0820 3525 ; 0d74 C from color 0x0000 3525 ; 0db8 C from color 0x0000 3525 ; 0f21 C from color 0x0000 3525 ; 0faf C from color 0x0f29 3525 ; 0fd4 C from color 0x0f29 3525 ; 0fe0 C from color 0x0f29 3525 ; 1062 C from color 0x1004 3525 ; 106a C from color 0x1004 3525 ; 33fe C from color 0x0f36 3525 ; 345a C from color 0x3457 3525 ; 34cf C from color 0x34cd 3525 ; -------------------------------------------------------------------------------------- 3525 3525 fiu_tivi_src c mar_0xc ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 11 TR0c:0e typ_c_mux_sel 0 ALU typ_frame c val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 11 VR0c:0e val_c_mux_sel 2 ALU val_frame c 3526 ; -------------------------------------------------------------------------------------- 3526 ; Comes from: 3526 ; 104e C from color 0x1004 3526 ; 108f C from color 0x108b 3526 ; 3415 C from color 0x3411 3526 ; 3434 C from color 0x22fd 3526 ; 344c C from color 0x0b53 3526 ; 34e5 C from color 0x0000 3526 ; 34f5 C from color 0x0000 3526 ; -------------------------------------------------------------------------------------- 3526 3526 fiu_mem_start f start_physical_tag_rd; Flow J cc=False 0x3529 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 3529 0x3529 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3527 3527 seq_en_micro 0 typ_mar_cntl 3 SPARE_0x03 3528 3528 fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_mem_start 15 setup_tag_read fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 26 TYP.TRUE (early) seq_en_micro 0 typ_b_adr 2e TR0c:0e typ_frame c typ_mar_cntl 4 RESTORE_MAR val_a_adr 2e VR0c:0e val_alu_func 0 PASS_A val_frame c 3529 3529 seq_en_micro 0 typ_mar_cntl 3 SPARE_0x03 352a 352a fiu_len_fill_lit 42 zero-fill 0x2; Flow R fiu_mem_start 15 setup_tag_read fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type a Unconditional Return seq_cond_sel 25 TYP.FALSE (early) seq_en_micro 0 typ_b_adr 2e TR0c:0e typ_frame c typ_mar_cntl 4 RESTORE_MAR val_a_adr 2e VR0c:0e val_alu_func 0 PASS_A val_frame c 352b ; -------------------------------------------------------------------------------------- 352b ; Comes from: 352b ; 342a C from color 0x3411 352b ; 3a1f C from color 0x0000 352b ; 3a44 C from color 0x0000 352b ; -------------------------------------------------------------------------------------- 352b 352b fiu_mem_start f start_physical_tag_rd fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 4 352c ; -------------------------------------------------------------------------------------- 352c ; Comes from: 352c ; 08e1 C from color 0x0127 352c ; 0b88 C from color 0x0b85 352c ; 0b8b C from color 0x0b85 352c ; 0e3f C from color 0x0000 352c ; 0f3c C from color 0x0000 352c ; 0fcd C from color 0x0f29 352c ; 1027 C from color 0x1004 352c ; 102d C from color 0x1004 352c ; 10a7 C from color 0x109e 352c ; 10b0 C from color 0x10ad 352c ; 3405 C from color 0x0f36 352c ; -------------------------------------------------------------------------------------- 352c 352c fiu_mem_start 15 setup_tag_read; Flow R seq_br_type a Unconditional Return seq_en_micro 0 352d ; -------------------------------------------------------------------------------------- 352d ; Comes from: 352d ; 04c9 C from color 0x04b0 352d ; 04cd C from color 0x04b0 352d ; 2b2f C from color 0x2b2f 352d ; -------------------------------------------------------------------------------------- 352d 352d fiu_len_fill_reg_ctl 1 len=literal, fill=literal; Flow J cc=True 0x3541 fiu_load_oreg 1 hold_oreg fiu_offs_lit 7f ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3541 0x3541 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 21 VR02:01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 352e 352e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x3536 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3536 0x3536 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR05:00 typ_frame 5 val_alu_func 1b A_OR_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 352f 352f ioc_fiubs 0 fiu ; Flow C cc=False 0x32cc ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32cc 0x32cc seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 2f TR08:0f typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 8 typ_rand c WRITE_OUTER_FRAME val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3530 3530 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3531 3531 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x3537 fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3537 0x3537 typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 32 TR11:12 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 0 PASS_A 3532 3532 ioc_fiubs 0 fiu ; Flow J cc=False 0x3534 seq_br_type 0 Branch False seq_branch_adr 3534 0x3534 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 33 VR02:13 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 2 3533 3533 fiu_mem_start 3 start-wr; Flow J cc=True 0x3534 ; Flow J cc=#0x0 0x3539 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3539 0x3539 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_random 02 ? val_a_adr 04 GP04 val_alu_func 1d A_AND_NOT_B val_b_adr 33 VR02:13 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 3534 3534 ioc_fiubs 0 fiu 3535 3535 seq_b_timing 0 Early Condition; Flow J cc=True 0x3536 ; Flow J cc=#0x0 0x3539 seq_br_type b Case False seq_branch_adr 3539 0x3539 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_random 02 ? val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 3536 3536 seq_br_type a Unconditional Return; Flow R val_alu_func 1a PASS_B val_b_adr 38 VR02:18 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3537 3537 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 3538 0x3538 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 04 GP04 val_alu_func 1 A_PLUS_B val_b_adr 03 GP03 val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3538 3538 seq_br_type 7 Unconditional Call; Flow C 0x32cc seq_branch_adr 32cc 0x32cc 3539 3539 ioc_load_wdr 0 ; Flow J 0x3540 seq_br_type 3 Unconditional Branch seq_branch_adr 3540 0x3540 typ_b_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 37 VR07:17 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 353a 353a ioc_load_wdr 0 ; Flow J 0x3540 seq_br_type 3 Unconditional Branch seq_branch_adr 3540 0x3540 typ_b_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 37 VR07:17 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 353b 353b ioc_load_wdr 0 ; Flow J 0x3540 seq_br_type 3 Unconditional Branch seq_branch_adr 3540 0x3540 typ_b_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 37 VR07:17 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 7 353c 353c seq_br_type 7 Unconditional Call; Flow C 0x333d seq_branch_adr 333d 0x333d seq_random 05 ? 353d 353d fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_random 02 ? val_a_adr 06 GP06 353e 353e fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 45 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 38 VR07:18 val_alu_func 1a PASS_B val_frame 7 353f 353f ioc_load_wdr 0 ; Flow J 0x3540 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3540 0x3540 typ_b_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3540 3540 fiu_mem_start 3 start-wr; Flow R ioc_adrbs 2 typ seq_br_type a Unconditional Return seq_cond_sel 5c (VAL.LOOP_COUNTER_ZERO(early)) nand (TYP.LOOP_COUNTER_ZERO(early)) seq_latch 1 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 3541 3541 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=True 0x32cc fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32cc 0x32cc seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 32 TR11:12 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 21 VR02:01 val_alu_func 1c DEC_A val_frame 2 3542 3542 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 3c TR07:1c typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 7 3543 3543 ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP seq_random 02 ? typ_a_adr 39 TR02:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3b VR02:1b val_alu_func 0 PASS_A val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 3544 3544 fiu_mem_start 3 start-wr; Flow J cc=True 0x3545 ; Flow J cc=#0x0 0x3539 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3539 0x3539 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3545 3545 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32dc fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 06 GP06 val_a_adr 3b VR02:1b val_alu_func 6 A_MINUS_B val_b_adr 07 GP07 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3546 3546 ioc_fiubs 0 fiu ; Flow C cc=True 0x354a ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 354a 0x354a seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_latch 1 typ_a_adr 20 TR00:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3547 3547 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=False fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3548 0x3548 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_b_adr 06 GP06 val_a_adr 09 GP09 val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 3548 3548 seq_br_type 4 Call False; Flow C cc=False 0x32d0 seq_branch_adr 32d0 0x32d0 seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 3a VR02:1a val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 3549 3549 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x32d0 seq_br_type 9 Return False seq_branch_adr 32d0 0x32d0 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 354a ; -------------------------------------------------------------------------------------- 354a ; Comes from: 354a ; 3546 C True from color 0x0000 354a ; -------------------------------------------------------------------------------------- 354a 354a seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3550 seq_br_type 1 Branch True seq_branch_adr 3550 0x3550 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 354b 354b typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 354c 354c typ_a_adr 3f TR07:1f typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 7 354d 354d typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 354e 354e fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 354f 354f ioc_tvbs 1 typ+fiu; Flow R seq_br_type a Unconditional Return val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3550 3550 seq_br_type a Unconditional Return; Flow R val_a_adr 08 GP08 val_alu_func 7 INC_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3551 3551 typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3552 3552 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_var 1 hold_var fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 06 GP06 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3553 3553 ioc_fiubs 0 fiu ; Flow J cc=True 0x35a6 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35a6 0x35a6 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 06 GP06 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 3554 3554 seq_br_type 3 Unconditional Branch; Flow J 0x3556 seq_branch_adr 3556 0x3556 typ_a_adr 08 GP08 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3d VR07:1d val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 3555 3555 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x35a7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35a7 0x35a7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 0e GP0e val_rand 9 PASS_A_HIGH 3556 3556 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val typ_b_adr 35 TR02:15 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_b_adr 0f GP0f 3557 3557 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x355e ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 355e 0x355e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 08 GP08 3558 3558 fiu_load_tar 1 hold_tar; Flow J cc=False 0x3561 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3561 0x3561 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3559 3559 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_tivi_src 1 tar_val ioc_fiubs 1 val seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 07 GP07 val_b_adr 06 GP06 355a 355a fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu seq_en_micro 0 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 355b 355b fiu_length_src 0 length_register; Flow J cc=False 0x3573 fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 0 Branch False seq_branch_adr 3573 0x3573 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_c_adr 31 GP0e val_c_source 0 FIU_BUS 355c 355c seq_br_type 2 Push (branch address); Flow J 0x355d seq_branch_adr 3555 0x3555 seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU 355d 355d seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 0e GP0e val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 355e 355e fiu_load_var 1 hold_var; Flow J cc=False 0x356b fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 356b 0x356b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 355f 355f fiu_load_tar 1 hold_tar; Flow J cc=True 0x3559 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3559 0x3559 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3560 3560 seq_br_type 3 Unconditional Branch; Flow C 0x210 seq_branch_adr 0210 0x0210 3561 3561 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C 0x35a5 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 35a5 0x35a5 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_b_adr 06 GP06 val_rand 1 INC_LOOP_COUNTER 3562 3562 fiu_tivi_src 1 tar_val; Flow J cc=True 0x356f ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 356f 0x356f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 val_c_adr 32 GP0d val_c_source 0 FIU_BUS 3563 3563 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 3564 3564 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3568 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3568 0x3568 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3d VR07:1d val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 3565 3565 fiu_length_src 0 length_register; Flow J cc=False 0x3571 fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3571 0x3571 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 3566 3566 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x3571 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3571 0x3571 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 0e GP0e val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 3567 3567 fiu_load_oreg 1 hold_oreg; Flow J 0x3559 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_oreg_src 0 rotator output fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3559 0x3559 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_b_adr 0d GP0d val_a_adr 08 GP08 val_alu_func 0 PASS_A val_b_adr 0d GP0d 3568 3568 fiu_load_var 1 hold_var; Flow J cc=False 0x3571 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3571 0x3571 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3569 3569 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 356a 356a fiu_length_src 0 length_register; Flow J 0x3566 fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_br_type 3 Unconditional Branch seq_branch_adr 3566 0x3566 val_a_adr 08 GP08 val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 356b 356b fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 08 GP08 val_alu_func 0 PASS_A val_rand 1 INC_LOOP_COUNTER 356c 356c fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow C 0x210 fiu_mem_start a start_continue_if_false fiu_tivi_src 1 tar_val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_b_adr 06 GP06 356d 356d ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU 356e 356e ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3563 seq_br_type 1 Branch True seq_branch_adr 3563 0x3563 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 356f 356f fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 14 ZEROS typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3570 3570 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3552 seq_br_type 3 Unconditional Branch seq_branch_adr 3552 0x3552 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 3571 3571 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 3572 3572 seq_br_type 3 Unconditional Branch; Flow J 0x3552 seq_branch_adr 3552 0x3552 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 3573 3573 fiu_length_src 0 length_register; Flow J cc=True 0x357c fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 357c 0x357c seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 09 GP09 3574 3574 fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 3575 3575 fiu_fill_mode_src 0 ; Flow J cc=False 0x3578 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3578 0x3578 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 3576 3576 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 3577 3577 ioc_load_wdr 0 ; Flow J 0x357e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 357e 0x357e seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 3578 3578 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3579 3579 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 31 GP0e typ_mar_cntl b LOAD_MAR_DATA val_a_adr 09 GP09 val_alu_func 1 A_PLUS_B val_b_adr 05 GP05 357a 357a fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_c_adr 31 GP0e 357b 357b ioc_load_wdr 0 ; Flow J 0x357e ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 357e 0x357e val_b_adr 0e GP0e 357c 357c fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 357d 357d ioc_load_wdr 0 typ_b_adr 06 GP06 val_b_adr 06 GP06 357e 357e fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A val_a_adr 06 GP06 val_alu_func 1e A_AND_B val_b_adr 3d VR07:1d val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 357f 357f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val val_a_adr 07 GP07 3580 3580 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 5 fiu_val ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 35 TR02:15 typ_alu_func 1a PASS_B typ_b_adr 07 GP07 typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 0f GP0f 3581 3581 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3584 ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3584 0x3584 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 07 GP07 typ_mar_cntl 6 INCREMENT_MAR val_c_adr 37 GP08 val_c_source 0 FIU_BUS 3582 3582 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 07 GP07 typ_mar_cntl b LOAD_MAR_DATA 3583 3583 ioc_load_wdr 0 ; Flow J 0x3588 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3588 0x3588 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 3584 3584 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU 3585 3585 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 07 GP07 typ_mar_cntl b LOAD_MAR_DATA val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU 3586 3586 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR 3587 3587 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_b_adr 0e GP0e 3588 3588 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x35c4 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 35c4 0x35c4 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_b_adr 07 GP07 3589 3589 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 358a 358a fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 2 typ typ_a_adr 21 TR10:01 typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_frame 10 val_b_adr 06 GP06 358b 358b fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 09 GP09 358c 358c seq_en_micro 0 typ_alu_func 1e A_AND_B typ_b_adr 29 TR13:09 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 13 358d 358d seq_en_micro 0 typ_a_adr 3e TR12:1e typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU typ_frame 12 358e 358e fiu_fill_mode_src 0 ; Flow J cc=True 0x359a fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 359a 0x359a seq_cond_sel 22 TYP.ALU_LT_ZERO(late) typ_a_adr 0d GP0d typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 06 GP06 val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 358f 358f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_fiubs 2 typ typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3590 3590 fiu_fill_mode_src 0 ; Flow J cc=False 0x359c fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 359c 0x359c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3591 3591 fiu_fill_mode_src 0 ; Flow C cc=False 0x35a3 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 35a3 0x35a3 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3592 3592 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 3593 3593 fiu_mem_start 7 start_wr_if_true ioc_adrbs 1 val seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 3594 3594 ioc_load_wdr 0 ; Flow J cc=True 0x35c4 seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 35c4 0x35c4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 06 GP06 val_b_adr 06 GP06 3595 3595 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 3596 3596 fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output ioc_adrbs 2 typ typ_a_adr 21 TR10:01 typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_frame 10 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3597 3597 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 3598 3598 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 09 GP09 3599 3599 fiu_fill_mode_src 0 ; Flow J 0x358f fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 358f 0x358f val_a_adr 3d VR07:1d val_alu_func 1e A_AND_B val_b_adr 06 GP06 val_c_adr 30 GP0f val_c_mux_sel 0 ALU << 1 val_frame 7 359a 359a seq_br_type 0 Branch False; Flow J cc=False 0x35c4 seq_branch_adr 35c4 0x35c4 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) typ_a_adr 09 GP09 typ_alu_func 6 A_MINUS_B typ_b_adr 0d GP0d typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU 359b 359b seq_br_type 3 Unconditional Branch; Flow J 0x3598 seq_branch_adr 3598 0x3598 typ_alu_func 1 A_PLUS_B typ_b_adr 0d GP0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 359c 359c fiu_fill_mode_src 0 ; Flow C cc=False 0x35a0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 35a0 0x35a0 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 06 GP06 val_alu_func 1a PASS_B val_b_adr 0f GP0f val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 359d 359d fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_mar_cntl b LOAD_MAR_DATA 359e 359e fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_c_adr 31 GP0e 359f 359f ioc_load_wdr 0 ; Flow J 0x3593 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3593 0x3593 val_b_adr 0e GP0e 35a0 ; -------------------------------------------------------------------------------------- 35a0 ; Comes from: 35a0 ; 359c C False from color 0x0000 35a0 ; -------------------------------------------------------------------------------------- 35a0 35a0 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 1 INC_LOOP_COUNTER 35a1 35a1 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 35a2 35a2 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return 35a3 ; -------------------------------------------------------------------------------------- 35a3 ; Comes from: 35a3 ; 3591 C False from color 0x0000 35a3 ; -------------------------------------------------------------------------------------- 35a3 35a3 fiu_mem_start 2 start-rd; Flow C 0x35a5 ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 35a5 0x35a5 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_rand 1 INC_LOOP_COUNTER 35a4 35a4 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 35a5 ; -------------------------------------------------------------------------------------- 35a5 ; Comes from: 35a5 ; 1b55 C from color MACRO_Execute_Access,Deallocate 35a5 ; 3561 C from color 0x0000 35a5 ; 35a3 C from color 0x35a3 35a5 ; -------------------------------------------------------------------------------------- 35a5 35a5 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 35a6 35a6 fiu_len_fill_lit 7e zero-fill 0x3e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS 35a7 35a7 ioc_tvbs 1 typ+fiu val_a_adr 07 GP07 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 35a8 35a8 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32dc fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 32dc 0x32dc seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 val_a_adr 3b VR02:1b val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35a9 35a9 ioc_fiubs 0 fiu typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS 35aa 35aa ioc_tvbs 1 typ+fiu; Flow C cc=True 0x35ba seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 35ba 0x35ba seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 35ab 35ab seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32d0 seq_br_type 5 Call True seq_branch_adr 32d0 0x32d0 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1e A_AND_B typ_b_adr 29 TR13:09 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 09 GP09 val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 35ac 35ac seq_en_micro 0 typ_a_adr 3e TR12:1e typ_alu_func 6 A_MINUS_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 12 35ad 35ad ioc_fiubs 2 typ ; Flow J cc=True 0x35b4 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35b4 0x35b4 seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 val_c_adr 30 GP0f val_c_source 0 FIU_BUS 35ae 35ae fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_b_adr 06 GP06 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_b_adr 08 GP08 35af 35af ioc_load_wdr 0 ; Flow J cc=False 0x35b7 ioc_tvbs 2 fiu+val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 35b7 0x35b7 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_b_adr 06 GP06 35b0 35b0 fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36); Flow J cc=False 0x35b7 fiu_load_oreg 1 hold_oreg fiu_mem_start 5 start_rd_if_true fiu_oreg_src 0 rotator output fiu_tivi_src 6 fiu_fiu ioc_adrbs 2 typ ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 35b7 0x35b7 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 35b1 35b1 fiu_fill_mode_src 0 ; Flow J cc=False 0x35c0 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 35c0 0x35c0 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 07 GP07 35b2 35b2 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 35b3 35b3 ioc_load_wdr 0 ; Flow J 0x35c4 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 35c4 0x35c4 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 35b4 35b4 seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 0f GP0f typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 0f GP0f val_c_adr 37 GP08 val_c_mux_sel 2 ALU 35b5 35b5 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x35ae seq_br_type 0 Branch False seq_branch_adr 35ae 0x35ae seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 09 GP09 val_alu_func 6 A_MINUS_B val_b_adr 08 GP08 35b6 35b6 seq_br_type 7 Unconditional Call; Flow C 0x32d0 seq_branch_adr 32d0 0x32d0 35b7 35b7 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A 35b8 35b8 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 35b9 35b9 fiu_load_var 1 hold_var; Flow J 0x35a7 fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 35a7 0x35a7 typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 35ba ; -------------------------------------------------------------------------------------- 35ba ; Comes from: 35ba ; 35aa C True from color 0x0000 35ba ; -------------------------------------------------------------------------------------- 35ba 35ba seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3550 seq_br_type 1 Branch True seq_branch_adr 3550 0x3550 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 07 GP07 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 35bb 35bb typ_a_adr 07 GP07 typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 35bc 35bc typ_a_adr 3f TR07:1f typ_alu_func 6 A_MINUS_B typ_b_adr 0e GP0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 7 35bd 35bd typ_a_adr 0e GP0e typ_alu_func 1e A_AND_B typ_b_adr 39 TR02:19 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 35be 35be fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 0e GP0e typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU 35bf 35bf ioc_tvbs 1 typ+fiu; Flow R seq_br_type a Unconditional Return typ_a_adr 07 GP07 typ_alu_func 6 A_MINUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_a_adr 08 GP08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 37 GP08 val_c_mux_sel 2 ALU 35c0 35c0 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 35c1 35c1 fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_mar_cntl b LOAD_MAR_DATA 35c2 35c2 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_c_adr 31 GP0e 35c3 35c3 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_b_adr 08 GP08 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU val_b_adr 0e GP0e 35c4 35c4 ioc_fiubs 2 typ typ_a_adr 07 GP07 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_c_adr 3f GP00 val_c_source 0 FIU_BUS 35c5 35c5 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT val_alu_func 6 A_MINUS_B val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU 35c6 ; -------------------------------------------------------------------------------------- 35c6 ; Comes from: 35c6 ; 10f8 C from color 0x10da 35c6 ; 10fd C from color 0x10f1 35c6 ; 1112 C from color 0x1106 35c6 ; 1126 C from color 0x1107 35c6 ; 1154 C from color 0x113f 35c6 ; 1164 C from color 0x113f 35c6 ; 1172 C from color 0x113f 35c6 ; 117c C from color 0x113f 35c6 ; 118b C from color 0x1147 35c6 ; 1194 C from color 0x1194 35c6 ; 11af C from color 0x114d 35c6 ; 11c6 C from color 0x114d 35c6 ; 11f3 C from color 0x114d 35c6 ; 11fe C from color 0x114d 35c6 ; 123c C from color 0x10f1 35c6 ; 1250 C from color 0x1106 35c6 ; 1263 C from color 0x1231 35c6 ; 126c C from color 0x1231 35c6 ; 12b9 C from color 0x1106 35c6 ; 12e0 C from color 0x128f 35c6 ; -------------------------------------------------------------------------------------- 35c6 35c6 fiu_len_fill_lit 49 zero-fill 0x9; Flow J 0x35c7 fiu_load_var 1 hold_var fiu_offs_lit 56 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 35c9 0x35c9 seq_cond_sel 5e (VAL.ALU_NONZERO(late)) nand (TYP.ALU_ZERO(late, combo)) seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1e A_AND_B typ_b_adr 27 TR02:07 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 07 GP07 35c7 35c7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3545 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3545 0x3545 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_a_adr 21 VR13:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 13 35c8 35c8 seq_br_type 3 Unconditional Branch; Flow J 0x3551 seq_branch_adr 3551 0x3551 seq_random 06 Pop_stack+? val_c_adr 39 GP06 35c9 35c9 fiu_mem_start 3 start-wr; Flow C cc=False 0x32d0 ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 32d0 0x32d0 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) seq_random 02 ? typ_a_adr 07 GP07 typ_alu_func 1 A_PLUS_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 01 GP01 val_alu_func 0 PASS_A val_c_adr 39 GP06 35ca 35ca ioc_fiubs 2 typ ; Flow R cc=True ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 35cb 0x35cb typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_b_adr 06 GP06 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 35cb 35cb ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return typ_a_adr 07 GP07 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 35cc 35cc fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_fiubs 0 fiu typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_source 0 FIU_BUS 35cd 35cd ioc_fiubs 1 val ; Flow J 0x35ce seq_br_type 2 Push (branch address) seq_branch_adr 35d2 0x35d2 seq_cond_sel 25 TYP.FALSE (early) seq_latch 1 typ_c_adr 36 GP09 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 32 VR02:12 val_c_adr 38 GP07 val_c_mux_sel 2 ALU val_frame 2 35ce 35ce ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x35d1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35d1 0x35d1 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 37 VR13:17 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 13 35cf 35cf fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3545 fiu_load_mdr 1 hold_mdr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3545 0x3545 seq_cond_sel 0a VAL.ALU_LT_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 35d0 35d0 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 35d1 35d1 seq_br_type 3 Unconditional Branch; Flow J 0x332e seq_branch_adr 332e 0x332e seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 seq_random 06 Pop_stack+? 35d2 35d2 fiu_load_var 1 hold_var; Flow C 0x210 fiu_tivi_src 1 tar_val ioc_load_wdr 0 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 1f TYP.ALU_32_CARRY_OUT(late) typ_a_adr 09 GP09 typ_alu_func 1 A_PLUS_B typ_b_adr 07 GP07 typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 06 GP06 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 35d3 35d3 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 09 GP09 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35d4 35d4 ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU val_b_adr 06 GP06 35d5 35d5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_fiubs 0 fiu typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand c WRITE_OUTER_FRAME 35d6 35d6 fiu_fill_mode_src 0 ; Flow J cc=False 0x35d8 fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 35d8 0x35d8 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_a_adr 03 GP03 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 05 GP05 35d7 35d7 fiu_fill_mode_src 0 ; Flow J 0x35db fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 35db 0x35db typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35d8 35d8 fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 35d9 35d9 fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_mar_cntl b LOAD_MAR_DATA val_c_adr 30 GP0f val_c_source 0 FIU_BUS 35da 35da fiu_load_var 1 hold_var; Flow J 0x35db fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 35db 0x35db seq_en_micro 0 typ_b_adr 0f GP0f typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f 35db 35db ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 35dc 35dc fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 3a VR05:1a val_alu_func 1e A_AND_B val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 35dd 35dd fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35de 35de seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x32de seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_alu_func 6 A_MINUS_B val_b_adr 2e VR04:0e val_frame 4 35df 35df fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 35e0 0x35e0 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 27 VR11:07 val_frame 11 35e0 35e0 seq_br_type 7 Unconditional Call; Flow C 0x32de seq_branch_adr 32de 0x32de 35e1 35e1 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_b_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand a PASS_B_HIGH val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_rand a PASS_B_HIGH 35e2 35e2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy 35e3 35e3 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 38 VR02:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 35e4 35e4 fiu_len_fill_lit 49 zero-fill 0x9; Flow J cc=True 0x35ec fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35ec 0x35ec seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_frame 2 val_rand 9 PASS_A_HIGH 35e5 35e5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x35e9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val seq_br_type 0 Branch False seq_branch_adr 35e9 0x35e9 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 1e TOP - 2 val_alu_func 5 DEC_A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 35e6 35e6 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand a PASS_B_HIGH val_c_adr 3e GP01 val_c_source 0 FIU_BUS 35e7 35e7 ioc_tvbs 2 fiu+val seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_latch 1 seq_random 02 ? typ_a_adr 20 TR00:00 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_a_adr 01 GP01 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 35e8 35e8 fiu_mem_start 2 start-rd; Flow R cc=False ; Flow J cc=True 0x35eb fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 35eb 0x35eb seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 5 DEC_A_MINUS_B val_b_adr 01 GP01 val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 35e9 35e9 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA 35ea 35ea fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 35eb 0x35eb seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS val_frame 4 35eb 35eb seq_br_type 7 Unconditional Call; Flow C 0x32e1 seq_branch_adr 32e1 0x32e1 typ_csa_cntl 3 POP_CSA 35ec 35ec fiu_load_var 1 hold_var; Flow J 0x35ea fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 35ea 0x35ea seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA val_a_adr 2d VR04:0d val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 4 35ed 35ed ioc_fiubs 2 typ ; Flow J cc=True 0x35f6 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35f6 0x35f6 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 35ee 35ee seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1f TOP - 1 35ef 35ef seq_b_timing 1 Latch Condition; Flow J cc=True 0x35f5 seq_br_type 1 Branch True seq_branch_adr 35f5 0x35f5 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_latch 1 typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_frame 18 typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 19 X_XOR_B val_b_adr 1e TOP - 2 35f0 35f0 fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x32e1 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 32e1 0x32e1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 35f1 35f1 val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 35f2 35f2 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=False 0x32e1 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 32e1 0x32e1 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 35f3 35f3 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32e1 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32e1 0x32e1 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS 35f4 35f4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_alu_func 1a PASS_B typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU 35f5 35f5 fiu_mem_start 2 start-rd; Flow J 0x35f1 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 35f1 0x35f1 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 1e TOP - 2 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 35f6 35f6 seq_br_type 3 Unconditional Branch; Flow J 0x35f4 seq_branch_adr 35f4 0x35f4 seq_random 02 ? typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_lit 2 typ_csa_cntl 3 POP_CSA typ_frame 18 typ_rand 8 SPARE_0x08 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 35f7 35f7 seq_br_type 4 Call False; Flow C cc=False 0x32e1 seq_branch_adr 32e1 0x32e1 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 35f8 35f8 fiu_mem_start 2 start-rd; Flow C cc=True 0x32e1 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32e1 0x32e1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 35f9 35f9 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32e1 fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32e1 0x32e1 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 35fa 35fa fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 35fb 35fb fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x35fd fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 35fd 0x35fd seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 35fc 35fc ioc_load_wdr 0 ; Flow J cc=False 0x35fe ioc_tvbs 3 fiu+fiu seq_br_type 0 Branch False seq_branch_adr 35fe 0x35fe seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B 35fd 35fd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 35fe 35fe fiu_mem_start 3 start-wr; Flow C 0x332e ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e 35ff 35ff seq_br_type 7 Unconditional Call; Flow C 0x32e1 seq_branch_adr 32e1 0x32e1 3600 3600 seq_br_type 4 Call False; Flow C cc=False 0x32e1 seq_branch_adr 32e1 0x32e1 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 6 A_MINUS_B val_b_adr 38 VR02:18 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 3601 3601 fiu_mem_start 2 start-rd; Flow C cc=True 0x32e1 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32e1 0x32e1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_c_lit 2 typ_frame 18 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 10 TOP val_rand a PASS_B_HIGH 3602 3602 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=False 0x32e1 fiu_load_mdr 1 hold_mdr fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 32e1 0x32e1 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 3603 3603 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU 3604 3604 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x35fc fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 1 Branch True seq_branch_adr 35fc 0x35fc seq_cond_sel 20 TYP.ALU_CARRY(late) seq_random 02 ? typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3605 3605 seq_br_type 7 Unconditional Call; Flow C 0x32e1 seq_branch_adr 32e1 0x32e1 3606 3606 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x329e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 3607 3607 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 1f TOP - 1 typ_c_lit 2 typ_frame 18 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 3608 3608 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3609 3609 ioc_load_wdr 0 typ_csa_cntl 3 POP_CSA 360a 360a fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 360b 360b fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x329e fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 329e 0x329e seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_a_adr 10 TOP typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A 360c 360c fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 30 TR0b:10 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 360d 360d fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 360e 0x360e seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_random 04 Load_save_offset+? typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 31 VR02:11 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 360e 360e fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2f TOP val_c_mux_sel 2 ALU 360f 360f fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x3618 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 0 Branch False seq_branch_adr 3618 0x3618 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2b) Variant_Record_Var typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_lit 2 typ_frame b typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3610 3610 fiu_mem_start 6 start_rd_if_false; Flow C 0x32d7 ioc_adrbs 2 typ seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 1f TOP - 1 typ_frame 1 typ_mar_cntl d LOAD_MAR_TYPE 3611 3611 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x32a1 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 5 Call True seq_branch_adr 32a1 0x32a1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 2b TR02:0b typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3612 3612 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 0 len=TI(25:31) fill=TI(36) fiu_mem_start 2 start-rd fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 3613 3613 fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3614 3614 fiu_len_fill_lit 5f zero-fill 0x1f fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_c_adr 39 GP06 val_c_source 0 FIU_BUS 3615 3615 val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 3616 3616 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x1d78 fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 1d78 0x1d78 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 3617 3617 seq_br_type 7 Unconditional Call; Flow C 0x32e1 seq_branch_adr 32e1 0x32e1 3618 3618 ioc_fiubs 0 fiu ; Flow J cc=True 0x3634 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3634 0x3634 seq_cond_sel 29 TYP.CLASS_A_EQ_LIT (med_late) typ_a_adr 1f TOP - 1 typ_c_lit 1 typ_frame c val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3619 3619 fiu_load_tar 1 hold_tar; Flow J cc=False 0x361c fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 361c 0x361c seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 1f TOP - 1 typ_alu_func 7 INC_A typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 361a 361a fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=False 0x3635 fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3635 0x3635 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_source 0 FIU_BUS 361b 361b seq_br_type 7 Unconditional Call; Flow C 0x32a9 seq_branch_adr 32a9 0x32a9 seq_en_micro 0 seq_random 02 ? 361c 361c fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_latch 1 typ_b_adr 1f TOP - 1 typ_c_lit 0 typ_frame c val_a_adr 32 VR02:12 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 361d 361d fiu_len_fill_lit 45 zero-fill 0x5 fiu_load_oreg 1 hold_oreg fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 48 fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_frame 11 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 361e 361e fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3621 ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3621 0x3621 seq_cond_sel 65 CROSS_WORD_FIELD~ typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl 6 INCREMENT_MAR val_c_adr 3c GP03 val_c_source 0 FIU_BUS 361f 361f fiu_fill_mode_src 0 ; Flow C cc=False 0x3630 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3630 0x3630 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 3620 3620 seq_br_type 3 Unconditional Branch; Flow J 0x3624 seq_branch_adr 3624 0x3624 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_rand c START_MULTIPLY 3621 3621 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 3622 3622 fiu_fill_mode_src 0 ; Flow C cc=False 0x3630 fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_length_src 0 length_register fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_offset_src 0 offset_register fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 3630 0x3630 typ_alu_func 1 A_PLUS_B typ_b_adr 2d TR05:0d typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_b_adr 3f VR02:1f val_c_adr 3e GP01 val_c_source 0 FIU_BUS val_frame 2 val_rand c START_MULTIPLY 3623 3623 seq_br_type 3 Unconditional Branch; Flow J 0x3624 seq_branch_adr 3624 0x3624 seq_cond_sel 11 VAL.ALU_40_ZERO(late) seq_latch 1 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 04 GP04 val_rand c START_MULTIPLY 3624 3624 seq_b_timing 1 Latch Condition; Flow J cc=True 0x3627 seq_br_type 1 Branch True seq_branch_adr 3627 0x3627 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_a_src 2 Bits 32…47 3625 3625 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_m_b_src 2 Bits 32…47 val_rand d PRODUCT_LEFT_16 3626 3626 seq_en_micro 0 val_a_adr 16 PRODUCT val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand d PRODUCT_LEFT_16 3627 3627 seq_br_type 1 Branch True; Flow J cc=True 0x3635 seq_branch_adr 3635 0x3635 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1 A_PLUS_B typ_b_adr 31 TR11:11 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B 3628 3628 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 01 GP01 val_a_adr 03 GP03 val_alu_func 1c DEC_A val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3629 3629 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x362e fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 6 start_rd_if_false fiu_oreg_src 0 rotator output ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 362e 0x362e typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 362a 362a fiu_mem_start a start_continue_if_false; Flow J cc=False 0x362c seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 362c 0x362c seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 362b 362b fiu_fill_mode_src 0 ; Flow J 0x3628 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3628 0x3628 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 362c 362c fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 362d 362d fiu_fill_mode_src 0 ; Flow J 0x3628 fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3628 0x3628 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS 362e 362e seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 01 GP01 362f 362f seq_br_type 3 Unconditional Branch; Flow J 0x3635 seq_branch_adr 3635 0x3635 seq_en_micro 0 val_alu_func a PASS_A_ELSE_PASS_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3630 ; -------------------------------------------------------------------------------------- 3630 ; Comes from: 3630 ; 361f C False from color 0x108b 3630 ; 3622 C False from color 0x108b 3630 ; -------------------------------------------------------------------------------------- 3630 3630 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x3632 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3632 0x3632 seq_cond_sel 65 CROSS_WORD_FIELD~ seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 16 PRODUCT val_alu_func 6 A_MINUS_B val_b_adr 2d VR05:0d val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3631 3631 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3632 3632 fiu_load_var 1 hold_var; Flow C cc=False 0x30a7 fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30a7 0x30a7 seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 3633 3633 fiu_fill_mode_src 0 ; Flow R fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3634 3634 fiu_mem_start 2 start-rd; Flow C 0x2484 ioc_adrbs 2 typ ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 2484 0x2484 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3635 3635 fiu_mem_start 2 start-rd; Flow C cc=True 0x32a1 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a1 0x32a1 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 10 TOP typ_c_adr 3e GP01 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 18 typ_mar_cntl d LOAD_MAR_TYPE typ_rand a PASS_B_HIGH val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 10 TOP 3636 3636 ioc_fiubs 1 val typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 1f TOP - 1 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3637 3637 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x363a ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 363a 0x363a seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 1f TOP - 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 9 PASS_A_HIGH val_a_adr 10 TOP val_rand 9 PASS_A_HIGH 3638 3638 fiu_mem_start 2 start-rd; Flow C 0x326f ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 326f 0x326f typ_a_adr 06 GP06 typ_alu_func 1c DEC_A typ_b_adr 1f TOP - 1 typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP 3639 3639 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 10 TOP val_rand 9 PASS_A_HIGH 363a 363a fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu val_a_adr 10 TOP val_alu_func 1 A_PLUS_B val_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 363b 363b fiu_len_fill_lit 5f zero-fill 0x1f fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 1f TOP - 1 typ_alu_func 1c DEC_A typ_mar_cntl d LOAD_MAR_TYPE typ_rand 0 NO_OP val_c_adr 39 GP06 val_c_source 0 FIU_BUS 363c 363c val_a_adr 06 GP06 val_alu_func 1 A_PLUS_B val_b_adr 38 VR02:18 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 363d 363d ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_latch 1 typ_a_adr 20 TR05:00 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 5 363e 363e seq_br_type 5 Call True; Flow C cc=True 0x1f1e seq_branch_adr 1f1e 0x1f1e seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 02 ? typ_csa_cntl 3 POP_CSA val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 363f 363f fiu_mem_start 2 start-rd; Flow R cc=True ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 3640 0x3640 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 06 GP06 3640 3640 seq_br_type 7 Unconditional Call; Flow C 0x32e1 seq_branch_adr 32e1 0x32e1 3641 3641 fiu_len_fill_lit 4c zero-fill 0xc; Flow C cc=True 0x211 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 32 VR03:12 val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3642 3642 fiu_len_fill_lit 75 zero-fill 0x35 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 32 TR03:12 typ_frame 3 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 19 3643 3643 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x3646 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 44 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3646 0x3646 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_frame 19 val_a_adr 38 VR12:18 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 12 3644 3644 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 3645 3645 fiu_mem_start 3 start-wr seq_en_micro 0 3646 3646 ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_c_adr 1e TR19:01 typ_frame 19 val_b_adr 0d GP0d val_c_adr 1e VR19:01 val_c_mux_sel 2 ALU val_frame 19 3647 3647 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=False 0x3649 fiu_load_tar 1 hold_tar fiu_offs_lit 38 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3649 0x3649 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_b_adr 20 TR08:00 typ_frame 8 val_a_adr 25 VR05:05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3648 3648 fiu_tivi_src 2 tar_fiu; Flow C cc=True 0x211 ioc_fiubs 2 typ ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 39 TR12:19 typ_alu_func 15 NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 12 val_a_adr 20 VR19:00 val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 19 3649 3649 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 3e TR02:1e typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2b VR11:0b val_frame 11 364a 364a ioc_load_wdr 0 ; Flow C cc=True 0x211 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_frame 2 364b 364b fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 06 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_a_adr 23 TR0d:03 typ_alu_func 7 INC_A typ_b_adr 34 TR0d:14 typ_c_adr 1c TR0d:03 typ_c_mux_sel 0 ALU typ_frame d val_a_adr 29 VR0d:09 val_alu_func 0 PASS_A val_c_adr 15 VR0d:0a val_c_mux_sel 2 ALU val_frame d 364c 364c fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_offs_lit 7f fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? typ_a_adr 21 TR11:01 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 11 val_b_adr 30 VR02:10 val_c_adr 33 GP0c val_c_source 0 FIU_BUS val_frame 2 364d 364d fiu_tivi_src c mar_0xc; Flow C cc=True 0xbab ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0bab 0x0bab seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 0f GP0f typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 16 VR0d:09 val_c_source 0 FIU_BUS val_frame d 364e 364e seq_br_type 7 Unconditional Call; Flow C 0x7b6 seq_branch_adr 07b6 0x07b6 seq_en_micro 0 364f 364f fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 22 TR11:02 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_csa_cntl 0 LOAD_CONTROL_TOP typ_frame 11 val_a_adr 3d VR02:1d val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 3650 3650 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 3d Load_ibuff+? typ_b_adr 0e GP0e val_a_adr 2f VR02:0f val_b_adr 39 VR02:19 val_frame 2 3651 3651 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 24 TR0d:04 typ_frame d val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_frame 3 val_rand a PASS_B_HIGH 3652 3652 ioc_fiubs 0 fiu ; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 45 Load_current_name+? typ_b_adr 0e GP0e val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3653 3653 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3743 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3743 0x3743 seq_en_micro 0 seq_random 0a ? typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3654 ; -------------------------------------------------------------------------------------- 3654 ; Comes from: 3654 ; 0feb C from color 0x0fea 3654 ; -------------------------------------------------------------------------------------- 3654 3654 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=False 0x3641 fiu_load_mdr 1 hold_mdr fiu_offs_lit 02 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3641 0x3641 seq_cond_sel 23 TYP.ALU_LE_ZERO(late) seq_en_micro 0 typ_a_adr 20 TR0d:00 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 2a VR05:0a val_frame 5 3655 3655 fiu_len_fill_lit 4c zero-fill 0xc; Flow C cc=True 0x211 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 3d fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 32 VR03:12 val_frame 3 3656 3656 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 36 fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 3a VR02:1a val_frame 2 3657 3657 ioc_fiubs 0 fiu ; Flow J 0x3643 ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3643 0x3643 seq_en_micro 0 typ_b_adr 32 TR03:12 typ_frame 3 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 19 3658 3658 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x3641 fiu_load_mdr 1 hold_mdr fiu_offs_lit 03 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3641 0x3641 seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 2b VR05:0b val_frame 5 3659 3659 fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x3641 fiu_load_mdr 1 hold_mdr fiu_offs_lit 04 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3641 0x3641 seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 21 VR06:01 val_frame 6 365a ; -------------------------------------------------------------------------------------- 365a ; Comes from: 365a ; 347f C from color 0x02c9 365a ; -------------------------------------------------------------------------------------- 365a 365a fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x3641 fiu_load_mdr 1 hold_mdr fiu_offs_lit 05 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3641 0x3641 seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 3d VR02:1d val_frame 2 365b 365b fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x3641 fiu_load_mdr 1 hold_mdr fiu_offs_lit 06 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3641 0x3641 seq_en_micro 0 typ_b_adr 34 TR0d:14 typ_c_adr 1b TR0d:04 typ_c_source 0 FIU_BUS typ_frame d val_a_adr 23 VR07:03 val_frame 7 365c 365c ioc_tvbs 1 typ+fiu; Flow J cc=True 0x365d ; Flow J cc=#0x0 0x365d seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 365d 0x365d seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 28 VR05:08 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 365d 365d seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 365e 365e fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x366a fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 366a 0x366a seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 365f 365f fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x366a fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 366a 0x366a seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3660 3660 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x366a fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 366a 0x366a seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3661 3661 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x366a fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 366a 0x366a seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3662 3662 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x366a fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 366a 0x366a seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3663 3663 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x366a fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 366a 0x366a seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3664 3664 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x366f fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 366f 0x366f seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3665 3665 seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 3666 3666 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x366d fiu_load_mdr 1 hold_mdr fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 366d 0x366d seq_en_micro 0 val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3667 3667 fiu_len_fill_lit 42 zero-fill 0x2; Flow J 0x3674 fiu_offs_lit 73 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3674 0x3674 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS val_a_adr 31 VR12:11 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 12 3668 3668 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3676 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3676 0x3676 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 14 ZEROS 3669 ; -------------------------------------------------------------------------------------- 3669 ; Comes from: 3669 ; 366a C from color 0x365e 3669 ; 3671 C from color 0x1004 3669 ; -------------------------------------------------------------------------------------- 3669 3669 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 366a 366a fiu_mem_start 2 start-rd; Flow C 0x3669 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3669 0x3669 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 366b 366b fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 39 VR12:19 val_alu_func 18 NOT_A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 12 366c 366c ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0c GP0c typ_c_lit 2 typ_frame 1f val_b_adr 0c GP0c 366d 366d fiu_len_fill_lit 42 zero-fill 0x2 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 7d fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f 366e 366e ioc_load_wdr 0 ; Flow J 0x3b8d ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b8d 0x3b8d seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 366f 366f ioc_adrbs 1 val ; Flow C 0x1001 seq_br_type 7 Unconditional Call seq_branch_adr 1001 0x1001 seq_en_micro 0 typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 3670 3670 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3671 0x3671 seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 3671 3671 fiu_mem_start 2 start-rd; Flow C 0x3669 fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3669 0x3669 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 32 TR12:12 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 12 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3672 3672 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 44 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 3673 3673 ioc_adrbs 2 typ ; Flow R cc=True ; Flow J cc=False 0x1080 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 1080 0x1080 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 typ_a_adr 0d GP0d typ_alu_func 0 PASS_A typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_a_adr 25 VR05:05 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3674 3674 ioc_adrbs 1 val ; Flow C 0x1001 seq_br_type 7 Unconditional Call seq_branch_adr 1001 0x1001 seq_en_micro 0 typ_b_adr 0e GP0e typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 3675 3675 seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 3676 3676 seq_en_micro 0 val_a_adr 32 VR03:12 val_alu_func 0 PASS_A val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3677 3677 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 44 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 3678 3678 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3679 3679 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 60 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 32 VR03:12 val_frame 3 367a 367a ioc_load_wdr 0 ; Flow J 0x3b7e ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b7e 0x3b7e seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 32 TR02:12 typ_frame 2 367b ; -------------------------------------------------------------------------------------- 367b ; Comes from: 367b ; 0141 C from color 0x0141 367b ; 08f6 C from color 0x0127 367b ; -------------------------------------------------------------------------------------- 367b 367b fiu_load_var 1 hold_var; Flow C 0x367d fiu_vmux_sel 1 fill value ioc_random f disable delay timer seq_br_type 7 Unconditional Call seq_branch_adr 367d 0x367d seq_en_micro 0 367c 367c fiu_load_var 1 hold_var; Flow J 0x3680 fiu_vmux_sel 1 fill value ioc_random d disable slice timer seq_br_type 3 Unconditional Branch seq_branch_adr 3680 0x3680 seq_en_micro 0 367d ; -------------------------------------------------------------------------------------- 367d ; Comes from: 367d ; 367b C from color 0x33b1 367d ; -------------------------------------------------------------------------------------- 367d 367d fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_offs_lit 10 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 val_a_adr 14 ZEROS 367e 367e ioc_random 7 load delay timer ioc_tvbs 2 fiu+val seq_en_micro 0 367f 367f ioc_random b clear delay event; Flow R seq_br_type a Unconditional Return seq_en_micro 0 3680 3680 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_en_micro 0 val_a_adr 14 ZEROS 3681 ; -------------------------------------------------------------------------------------- 3681 ; Comes from: 3681 ; 0763 C from color 0x0000 3681 ; 07bd C from color 0x07b9 3681 ; 0fa7 C from color 0x0f93 3681 ; -------------------------------------------------------------------------------------- 3681 3681 ioc_random 6 load slice timer ioc_tvbs 2 fiu+val seq_en_micro 0 3682 3682 ioc_random a clear slice event; Flow R seq_br_type a Unconditional Return seq_en_micro 0 3683 ; -------------------------------------------------------------------------------------- 3683 ; Comes from: 3683 ; 0567 C from color 0x0567 3683 ; 05a0 C from color 0x0599 3683 ; 0812 C from color 0x0000 3683 ; 0f17 C from color 0x0f17 3683 ; -------------------------------------------------------------------------------------- 3683 3683 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_random 9 read timer/checkbits/errorid ioc_tvbs 4 ioc+ioc seq_en_micro 0 3684 3684 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 14 ZEROS val_alu_func 2 INC_A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3685 3685 fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 35 VR04:15 val_frame 4 3686 3686 ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 39 VR03:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3687 3687 fiu_len_fill_lit 7b zero-fill 0x3b fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_en_micro 0 val_a_adr 39 VR03:19 val_frame 3 3688 3688 ioc_tvbs 1 typ+fiu; Flow R seq_br_type a Unconditional Return seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR03:19 val_c_mux_sel 2 ALU val_frame 3 3689 3689 fiu_len_fill_lit 7a zero-fill 0x3a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP 368a 368a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 3b VR04:1b val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 368b 368b fiu_len_fill_lit 5f zero-fill 0x1f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA val_a_adr 39 VR04:19 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 368c 368c seq_en_micro 0 368d 368d fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 368e 368e ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_c_adr 05 TR04:1a typ_frame 4 val_c_adr 05 VR04:1a val_frame 4 368f 368f fiu_fill_mode_src 0 ; Flow C 0x210 fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 3a TR04:1a typ_frame 4 val_b_adr 3a VR04:1a val_frame 4 3690 3690 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J cc=True 0x3697 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3697 0x3697 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 05 VR04:1a val_c_mux_sel 2 ALU val_frame 4 3691 3691 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 06 VR04:19 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 3692 3692 seq_en_micro 0 3693 3693 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 05 TR04:1a typ_c_mux_sel 0 ALU typ_frame 4 3694 3694 seq_br_type 7 Unconditional Call; Flow C 0x6b4 seq_branch_adr 06b4 0x06b4 seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 3c VR04:1c val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3695 3695 seq_br_type 0 Branch False; Flow J cc=False 0x3697 seq_branch_adr 3697 0x3697 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 3a TR04:1a typ_b_adr 2d TR04:0d typ_frame 4 3696 3696 fiu_mem_start 2 start-rd; Flow J 0x3692 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3692 0x3692 seq_en_micro 0 typ_a_adr 2d TR04:0d typ_alu_func 0 PASS_A typ_b_adr 3a TR04:1a typ_frame 4 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3697 3697 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3698 3698 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value typ_b_adr 10 TOP typ_rand 1 INC_LOOP_COUNTER val_b_adr 10 TOP 3699 3699 fiu_mem_start 2 start-rd; Flow C 0x34dc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34dc 0x34dc seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 369a 369a fiu_len_fill_lit 50 zero-fill 0x10 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val seq_en_micro 0 seq_random 02 ? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 369b 369b ioc_tvbs 1 typ+fiu seq_en_micro 0 val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 4 369c 369c fiu_load_tar 1 hold_tar; Flow C cc=False 0x20a fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_a_adr 21 VR06:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 6 369d 369d fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x36a6 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 36a6 0x36a6 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_a_adr 3d VR02:1d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 2 369e 369e fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 0 PASS_A 369f 369f seq_en_micro 0 36a0 36a0 fiu_len_fill_lit 42 zero-fill 0x2; Flow C cc=False 0x20a fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS 36a1 36a1 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x36a6 seq_br_type 1 Branch True seq_branch_adr 36a6 0x36a6 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_alu_func 19 X_XOR_B typ_b_adr 06 GP06 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 36a2 36a2 fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 36a3 36a3 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 04 GP04 36a4 36a4 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 1c fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 36a5 36a5 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 36a6 36a6 fiu_mem_start 5 start_rd_if_true; Flow C cc=False 0x20a ioc_adrbs 1 val ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 1e TR17:01 typ_c_source 0 FIU_BUS typ_frame 17 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 36a7 36a7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 14 ZEROS 36a8 36a8 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=False 0x20a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 12 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 36a9 36a9 fiu_len_fill_lit 44 zero-fill 0x4 fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 36aa 36aa ioc_load_wdr 0 ; Flow J cc=True 0x36b2 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 36b2 0x36b2 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 28 VR09:08 val_frame 9 36ab 36ab seq_br_type 4 Call False; Flow C cc=False 0x20a seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 36ac 36ac ioc_tvbs 2 fiu+val; Flow J cc=True 0x36b0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 36b0 0x36b0 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS 36ad 36ad seq_b_timing 1 Latch Condition; Flow J cc=True 0x36b4 seq_br_type 1 Branch True seq_branch_adr 36b4 0x36b4 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR02:0a typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 28 VR05:08 val_frame 5 36ae 36ae seq_b_timing 1 Latch Condition; Flow J cc=True 0x36bc seq_br_type 1 Branch True seq_branch_adr 36bc 0x36bc seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR11:12 typ_frame 11 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 20 VR11:00 val_frame 11 36af 36af seq_b_timing 1 Latch Condition; Flow J cc=True 0x36bc seq_br_type 1 Branch True seq_branch_adr 36bc 0x36bc seq_en_micro 0 36b0 36b0 seq_br_type 7 Unconditional Call; Flow C 0x6b4 seq_branch_adr 06b4 0x06b4 seq_en_micro 0 36b1 36b1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 36b2 36b2 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3b86 fiu_load_mdr 1 hold_mdr fiu_offs_lit 13 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 3b86 0x3b86 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2e TR11:0e typ_frame 11 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 28 VR09:08 val_frame 9 36b3 36b3 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36b4 36b4 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x36b8 seq_br_type 1 Branch True seq_branch_adr 36b8 0x36b8 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 24 VR08:04 val_frame 8 36b5 36b5 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 27 TR05:07 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 36b6 36b6 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 36b7 36b7 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x20a ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 36b8 36b8 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 36b9 36b9 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 36ba 36ba seq_br_type 1 Branch True; Flow J cc=True 0x36b0 seq_branch_adr 36b0 0x36b0 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 36bb 36bb seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36bc 36bc fiu_mem_start 2 start-rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 36bd 36bd seq_en_micro 0 36be 36be fiu_load_tar 1 hold_tar; Flow C cc=False 0x20a fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 36bf 36bf fiu_len_fill_lit 71 zero-fill 0x31; Flow C 0x58b fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 058b 0x058b seq_en_micro 0 val_c_adr 1c VR17:03 val_c_source 0 FIU_BUS val_frame 17 36c0 36c0 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 36c1 ; -------------------------------------------------------------------------------------- 36c1 ; Comes from: 36c1 ; 0e3e C from color 0x0000 36c1 ; 10a0 C from color 0x109e 36c1 ; 3b9e C from color 0x0bab 36c1 ; -------------------------------------------------------------------------------------- 36c1 36c1 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_c_adr 1c TR04:03 typ_c_mux_sel 0 ALU typ_frame 4 36c2 36c2 fiu_mem_start 11 start_tag_query ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 23 VR04:03 val_frame 4 val_rand a PASS_B_HIGH 36c3 36c3 seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 0 PASS_A typ_c_adr 33 GP0c typ_c_mux_sel 0 ALU val_a_adr 17 LOOP_COUNTER val_alu_func 0 PASS_A val_c_adr 33 GP0c val_c_mux_sel 2 ALU 36c4 36c4 fiu_tivi_src 3 tar_frame; Flow C cc=False 0x20a ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 36c5 36c5 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 36c6 36c6 fiu_mem_start 4 continue ioc_fiubs 1 val seq_en_micro 0 typ_c_adr 1a TR04:05 typ_c_source 0 FIU_BUS typ_frame 4 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 23 VR04:03 val_frame 4 36c7 36c7 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x36ca fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 36ca 0x36ca seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 3d TR09:1d typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 02 VR04:1d val_c_mux_sel 2 ALU val_frame 4 36c8 36c8 seq_br_type 7 Unconditional Call; Flow C 0x6ec seq_branch_adr 06ec 0x06ec seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 36c9 36c9 seq_br_type 3 Unconditional Branch; Flow J 0x36e0 seq_branch_adr 36e0 0x36e0 seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 36ca 36ca fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x36d4 fiu_offs_lit 13 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 36d4 0x36d4 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 3c TR09:1c typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 36cb 36cb ioc_adrbs 1 val ; Flow C cc=#0x0 0x36d0 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 36d0 0x36d0 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 23 VR04:03 val_alu_func 0 PASS_A val_frame 4 36cc 36cc fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 36cd 36cd fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 14 ZEROS 36ce 36ce fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start e start_physical_wr fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 36cf 36cf ioc_load_wdr 0 ; Flow J 0x36e0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 36e0 0x36e0 seq_en_micro 0 typ_c_adr 1c TR04:03 typ_c_mux_sel 0 ALU typ_frame 4 36d0 ; -------------------------------------------------------------------------------------- 36d0 ; Comes from: 36d0 ; 36cb C #0x0 from color 0x05a7 36d0 ; -------------------------------------------------------------------------------------- 36d0 36d0 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36d1 36d1 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36d2 36d2 seq_br_type 3 Unconditional Branch; Flow J 0x3bb9 seq_branch_adr 3bb9 0x3bb9 seq_en_micro 0 36d3 36d3 seq_br_type 3 Unconditional Branch; Flow J 0x3bbb seq_branch_adr 3bbb 0x3bbb seq_en_micro 0 36d4 36d4 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x36c8 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 36c8 0x36c8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 36d5 36d5 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x36d6 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 36d9 0x36d9 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 36d6 36d6 seq_br_type 1 Branch True; Flow J cc=True 0x5c7 seq_branch_adr 05c7 0x05c7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 2a TR02:0a typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 28 VR05:08 val_frame 5 36d7 36d7 seq_br_type 1 Branch True; Flow J cc=True 0x5c7 seq_branch_adr 05c7 0x05c7 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 17 LOOP_COUNTER typ_alu_func 19 X_XOR_B typ_b_adr 32 TR11:12 typ_frame 11 val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 20 VR11:00 val_frame 11 36d8 36d8 seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36d9 36d9 fiu_mem_start 11 start_tag_query ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 23 VR04:03 val_frame 4 val_rand a PASS_B_HIGH 36da 36da seq_en_micro 0 typ_a_adr 0c GP0c typ_alu_func 0 PASS_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU val_a_adr 0c GP0c val_alu_func 0 PASS_A val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 36db 36db fiu_tivi_src 3 tar_frame; Flow C cc=False 0x20a ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 36dc 36dc fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 30 VR04:10 val_frame 4 36dd 36dd fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_mdr 1 hold_mdr fiu_offs_lit 36 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 val_a_adr 31 VR02:11 val_frame 2 36de 36de fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x20a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 36 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_en_micro 0 36df 36df fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x36e0 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 36e0 0x36e0 seq_en_micro 0 typ_c_adr 1c TR04:03 typ_c_source 0 FIU_BUS typ_frame 4 36e0 36e0 fiu_mem_start 11 start_tag_query ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 3b TR05:1b typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 23 VR04:03 val_c_adr 13 VR04:0c val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 36e1 36e1 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 seq_latch 1 val_a_adr 26 VR04:06 val_alu_func 6 A_MINUS_B val_b_adr 2c VR04:0c val_frame 4 36e2 36e2 fiu_tivi_src 3 tar_frame; Flow C cc=False 0x20a ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 020a 0x020a seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 val_a_adr 32 VR04:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 16 VR04:09 val_c_mux_sel 2 ALU val_frame 4 36e3 36e3 fiu_mem_start d start_physical_rd ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 36e4 36e4 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_mdr 1 hold_mdr fiu_mem_start 4 continue fiu_offs_lit 12 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_en_micro 0 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 31 VR02:11 val_frame 2 36e5 36e5 fiu_len_fill_lit 40 zero-fill 0x0; Flow C cc=True 0x20a fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 12 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 020a 0x020a seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 3b TR09:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 36e6 36e6 ioc_fiubs 1 val ; Flow J cc=False 0x36ee ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 36ee 0x36ee seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 13 TR04:0c typ_c_source 0 FIU_BUS typ_frame 4 val_a_adr 38 VR05:18 val_frame 5 36e7 36e7 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 2c TR04:0c typ_alu_func 0 PASS_A typ_c_adr 1c TR04:03 typ_c_mux_sel 0 ALU typ_frame 4 val_a_adr 3c VR12:1c val_frame 12 36e8 36e8 fiu_mem_start e start_physical_wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2e VR04:0e val_frame 4 36e9 36e9 ioc_load_wdr 0 ; Flow J cc=True 0x36f0 ioc_tvbs 3 fiu+fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 36f0 0x36f0 seq_en_micro 0 36ea 36ea fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 25 VR04:05 val_alu_func 1 A_PLUS_B val_b_adr 26 VR04:06 val_frame 4 36eb 36eb ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 23 TR04:03 typ_frame 4 val_b_adr 23 VR04:03 val_frame 4 36ec 36ec seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 36ed 0x36ed seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 26 VR04:06 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 19 VR04:06 val_c_mux_sel 2 ALU val_frame 4 36ed 36ed seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36ee 36ee ioc_tvbs 2 fiu+val; Flow J cc=False 0x36e8 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 36e8 0x36e8 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 36ef 36ef fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x36e8 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 36e8 0x36e8 seq_en_micro 0 typ_a_adr 27 TR05:07 typ_frame 5 36f0 36f0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start d start_physical_rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 22 TR04:02 typ_frame 4 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 2f VR04:0f val_frame 4 36f1 36f1 seq_en_micro 0 36f2 36f2 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start e start_physical_wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 val_a_adr 31 VR04:11 val_alu_func 0 PASS_A val_c_adr 13 VR04:0c val_c_mux_sel 2 ALU val_frame 4 36f3 36f3 ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_c_adr 1d TR04:02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 4 typ_rand c WRITE_OUTER_FRAME val_a_adr 23 VR04:03 val_frame 4 36f4 36f4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start d start_physical_rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 23 TR04:03 typ_frame 4 typ_mar_cntl f LOAD_MAR_RESERVED val_a_adr 29 VR04:09 val_alu_func 1 A_PLUS_B val_b_adr 30 VR04:10 val_frame 4 36f5 36f5 seq_en_micro 0 val_a_adr 2c VR04:0c val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 19 VR04:06 val_c_mux_sel 2 ALU val_frame 4 36f6 36f6 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start e start_physical_wr fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 36f7 36f7 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 36f8 36f8 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 25 VR04:05 val_alu_func 1 A_PLUS_B val_b_adr 2c VR04:0c val_frame 4 36f9 36f9 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 23 TR04:03 typ_frame 4 val_b_adr 23 VR04:03 val_frame 4 36fa 36fa seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 36fb 0x36fb seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 36fb 36fb seq_br_type 7 Unconditional Call; Flow C 0x20a seq_branch_adr 020a 0x020a seq_en_micro 0 36fc ; -------------------------------------------------------------------------------------- 36fc ; 0x0010 Halt InMicrocode 36fc ; -------------------------------------------------------------------------------------- 36fc MACRO_Halt_InMicrocode: 36fc 36fc dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36fc ioc_random 14 clear cpu running seq_en_micro 0 seq_random 01 Halt+? 36fd 36fd fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 36fe ; -------------------------------------------------------------------------------------- 36fe ; 0x0011 QQUnknown InMicrocode 36fe ; -------------------------------------------------------------------------------------- 36fe MACRO_36fe_QQUnknown_InMicrocode: 36fe 36fe dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 36fe fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 36ff 36ff <halt> ; Flow R 3700 ; -------------------------------------------------------------------------------------- 3700 ; 0x0012 QQUnknown InMicrocode 3700 ; -------------------------------------------------------------------------------------- 3700 MACRO_3700_QQUnknown_InMicrocode: 3700 3700 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3700 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 3701 3701 <halt> ; Flow R 3702 ; -------------------------------------------------------------------------------------- 3702 ; 0x0013 QQUnknown InMicrocode 3702 ; -------------------------------------------------------------------------------------- 3702 MACRO_3702_QQUnknown_InMicrocode: 3702 3702 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3702 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 3703 3703 <halt> ; Flow R 3704 ; -------------------------------------------------------------------------------------- 3704 ; 0x0014 QQUnknown InMicrocode 3704 ; -------------------------------------------------------------------------------------- 3704 MACRO_3704_QQUnknown_InMicrocode: 3704 3704 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3704 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 3705 3705 <halt> ; Flow R 3706 ; -------------------------------------------------------------------------------------- 3706 ; 0x0015 QQUnknown InMicrocode 3706 ; -------------------------------------------------------------------------------------- 3706 MACRO_3706_QQUnknown_InMicrocode: 3706 3706 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3706 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 3707 3707 <halt> ; Flow R 3708 ; -------------------------------------------------------------------------------------- 3708 ; 0x0016 QQUnknown InMicrocode 3708 ; -------------------------------------------------------------------------------------- 3708 MACRO_3708_QQUnknown_InMicrocode: 3708 3708 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3708 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 3709 3709 <halt> ; Flow R 370a ; -------------------------------------------------------------------------------------- 370a ; 0x0017 QQUnknown InMicrocode 370a ; -------------------------------------------------------------------------------------- 370a MACRO_370a_QQUnknown_InMicrocode: 370a 370a dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 370a fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 370b 370b <halt> ; Flow R 370c ; -------------------------------------------------------------------------------------- 370c ; 0x0018 QQUnknown InMicrocode 370c ; -------------------------------------------------------------------------------------- 370c MACRO_370c_QQUnknown_InMicrocode: 370c 370c dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 370c fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 370d 370d <halt> ; Flow R 370e ; -------------------------------------------------------------------------------------- 370e ; 0x0019 QQUnknown InMicrocode 370e ; -------------------------------------------------------------------------------------- 370e MACRO_370e_QQUnknown_InMicrocode: 370e 370e dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 370e fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 370f 370f <halt> ; Flow R 3710 ; -------------------------------------------------------------------------------------- 3710 ; 0x001a QQUnknown InMicrocode 3710 ; -------------------------------------------------------------------------------------- 3710 MACRO_3710_QQUnknown_InMicrocode: 3710 3710 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3710 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 3711 3711 <halt> ; Flow R 3712 ; -------------------------------------------------------------------------------------- 3712 ; 0x001b QQUnknown InMicrocode 3712 ; -------------------------------------------------------------------------------------- 3712 MACRO_3712_QQUnknown_InMicrocode: 3712 3712 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3712 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 3713 3713 <halt> ; Flow R 3714 ; -------------------------------------------------------------------------------------- 3714 ; 0x001c QQUnknown InMicrocode 3714 ; -------------------------------------------------------------------------------------- 3714 MACRO_3714_QQUnknown_InMicrocode: 3714 3714 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3714 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 3715 3715 <halt> ; Flow R 3716 ; -------------------------------------------------------------------------------------- 3716 ; 0x001d QQUnknown InMicrocode 3716 ; -------------------------------------------------------------------------------------- 3716 MACRO_3716_QQUnknown_InMicrocode: 3716 3716 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3716 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 3717 3717 <halt> ; Flow R 3718 ; -------------------------------------------------------------------------------------- 3718 ; 0x001e QQUnknown InMicrocode 3718 ; -------------------------------------------------------------------------------------- 3718 MACRO_3718_QQUnknown_InMicrocode: 3718 3718 dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 3718 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 3719 3719 <halt> ; Flow R 371a ; -------------------------------------------------------------------------------------- 371a ; 0x001f QQUnknown InMicrocode 371a ; -------------------------------------------------------------------------------------- 371a MACRO_371a_QQUnknown_InMicrocode: 371a 371a dispatch_brk_class 0 ; Flow R dispatch_csa_valid 0 dispatch_ignore 1 dispatch_uadr 371a fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_int_reads 0 TYP VAL BUS seq_random 24 Load_save_offset+Validate_tos_optimizer+? typ_b_adr 10 TOP typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 10 TOP 371b 371b fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x371d fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 371d 0x371d typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 27 VR05:07 val_frame 5 371c 371c fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x371d fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 371d 0x371d typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 25 VR05:05 val_frame 5 371d 371d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 2f VR02:0f val_frame 2 371e 371e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 2b TYP.CLASS_A_EQ_B (med_late) typ_a_adr 20 TR02:00 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 371f 371f fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x3721 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3721 0x3721 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_random 02 ? typ_a_adr 39 TR08:19 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_c_adr 3f GP00 val_frame 7 val_rand 9 PASS_A_HIGH 3720 3720 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3721 ; Flow J cc=#0x0 0x3725 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3725 0x3725 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 2e TR1b:0e typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 1b val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3721 3721 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3724 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3724 0x3724 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3722 3722 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x42f seq_br_type 1 Branch True seq_branch_adr 042f 0x042f seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 18 NOT_A_AND_B typ_b_adr 25 TR05:05 typ_frame 5 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3723 3723 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3724 3724 seq_br_type 3 Unconditional Branch; Flow J 0x32d6 seq_branch_adr 32d6 0x32d6 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3725 3725 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3cb fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 03cb 0x03cb seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3726 3726 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x372d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 372d 0x372d seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3727 3727 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3731 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3731 0x3731 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3728 3728 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x372d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 372d 0x372d seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3729 3729 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x372f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 372f 0x372f seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 372a 372a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 372b 372b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 372c 372c seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 372d 372d ioc_tvbs c mem+mem+csa+dummy; Flow C 0x380 seq_br_type 7 Unconditional Call seq_branch_adr 0380 0x0380 typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 372e 372e seq_br_type 3 Unconditional Branch; Flow J 0x3d8 seq_branch_adr 03d8 0x03d8 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 372f 372f ioc_tvbs c mem+mem+csa+dummy; Flow C 0x380 seq_br_type 7 Unconditional Call seq_branch_adr 0380 0x0380 typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 3730 3730 seq_br_type 3 Unconditional Branch; Flow J 0x3d8 seq_branch_adr 03d8 0x03d8 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 3731 3731 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x380 seq_br_type 7 Unconditional Call seq_branch_adr 0380 0x0380 typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 3732 3732 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 2c TR02:0c typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 3733 3733 ioc_adrbs 1 val ; Flow C 0x5a7 seq_br_type 7 Unconditional Call seq_branch_adr 05a7 0x05a7 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 0 PASS_A 3734 3734 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_a_adr 01 GP01 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3735 3735 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 03 GP03 3736 3736 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3b TR09:1b typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 val_b_adr 16 CSA/VAL_BUS 3737 3737 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x3741 fiu_offs_lit 65 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3741 0x3741 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS 3738 3738 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3739 3739 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x373b fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 373b 0x373b seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 3c TR09:1c typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 9 373a 373a fiu_len_fill_lit 53 zero-fill 0x13; Flow C 0x3ba5 fiu_offs_lit 65 fiu_op_sel 3 insert ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3ba5 0x3ba5 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 09 GP09 val_rand a PASS_B_HIGH 373b 373b ioc_adrbs 1 val ; Flow C 0x6cf seq_br_type 7 Unconditional Call seq_branch_adr 06cf 0x06cf typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 09 GP09 val_rand a PASS_B_HIGH 373c 373c fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3738 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3738 0x3738 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 373d 373d seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3c TR09:1c typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 373e 373e ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3741 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3741 0x3741 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 373f 373f fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3740 3740 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3741 3741 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 3742 3742 seq_br_type 3 Unconditional Branch; Flow J 0x3d8 seq_branch_adr 03d8 0x03d8 typ_a_adr 35 TR13:15 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 3743 3743 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP 3744 3744 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x3761 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3761 0x3761 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 3745 3745 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x211 seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3746 3746 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x3748 fiu_mem_start 2 start-rd fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3748 0x3748 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 39 TR08:19 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 3747 3747 seq_b_timing 0 Early Condition; Flow J cc=True 0x3748 ; Flow J cc=#0x0 0x3753 seq_br_type b Case False seq_branch_adr 3753 0x3753 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 2e TR1b:0e typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_frame 1b 3748 3748 ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) typ_alu_func 18 NOT_A_AND_B typ_b_adr 25 TR05:05 typ_frame 5 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3749 3749 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x470 seq_br_type 0 Branch False seq_branch_adr 0470 0x0470 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 32 VR03:12 val_alu_func 19 X_XOR_B val_b_adr 09 GP09 val_frame 3 374a 374a fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR09:0f val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 9 val_rand a PASS_B_HIGH 374b 374b ioc_load_wdr 0 typ_b_adr 32 TR02:12 typ_frame 2 val_b_adr 2b VR09:0b val_frame 9 374c 374c fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR02:1e val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 2 val_rand a PASS_B_HIGH 374d 374d ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x211 seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_b_adr 16 CSA/VAL_BUS 374e 374e fiu_mem_start 2 start-rd; Flow C 0x33c4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 33c4 0x33c4 typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 08 GP08 val_frame 4 val_rand a PASS_B_HIGH 374f 374f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=True 0x211 fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 0211 0x0211 3750 3750 fiu_len_fill_lit 46 zero-fill 0x6; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 25 TR02:05 typ_b_adr 20 TR02:00 typ_frame 2 3751 3751 fiu_len_fill_lit 4f zero-fill 0xf fiu_offs_lit 50 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_b_adr 23 TR02:03 typ_frame 2 val_b_adr 23 VR02:03 val_frame 2 3752 3752 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3753 ; Flow J cc=#0x0 0x0 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_b_timing 0 Early Condition seq_br_type b Case False seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_c_adr 1a TR02:05 typ_c_source 0 FIU_BUS typ_frame 2 3753 3753 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3754 3754 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x375b fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 375b 0x375b seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3755 3755 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x375d fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 375d 0x375d seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3756 3756 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3757 3757 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3758 3758 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3759 3759 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 375a 375a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 375b 375b ioc_tvbs c mem+mem+csa+dummy; Flow C 0x3ad seq_br_type 7 Unconditional Call seq_branch_adr 03ad 0x03ad typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 375c 375c seq_br_type 3 Unconditional Branch; Flow J 0x412 seq_branch_adr 0412 0x0412 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 375d 375d ioc_tvbs c mem+mem+csa+dummy; Flow C 0x3ad seq_br_type 7 Unconditional Call seq_branch_adr 03ad 0x03ad typ_a_adr 2e TR1b:0e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_b_adr 16 CSA/VAL_BUS 375e 375e ioc_adrbs 1 val ; Flow C 0x5a7 seq_br_type 7 Unconditional Call seq_branch_adr 05a7 0x05a7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 0 PASS_A 375f 375f seq_b_timing 1 Latch Condition; Flow J cc=True 0x412 seq_br_type 1 Branch True seq_branch_adr 0412 0x0412 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 3760 3760 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3761 3761 seq_br_type 9 Return False; Flow R cc=False ; Flow J cc=True 0x3749 seq_branch_adr 3749 0x3749 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 20 VR02:00 val_alu_func 19 X_XOR_B val_b_adr 3d VR02:1d val_frame 2 3762 3762 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 1 val typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3763 3763 fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS 3764 3764 fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=False 0x3783 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3783 0x3783 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3765 3765 fiu_len_fill_lit 42 zero-fill 0x2; Flow J cc=True 0x37ce fiu_load_var 1 hold_var fiu_offs_lit 17 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 37ce 0x37ce seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 28 VR09:08 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 9 3766 3766 fiu_len_fill_lit 44 zero-fill 0x4; Flow C cc=#0x0 0x3793 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 3793 0x3793 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 02 GP02 typ_alu_func 1 A_PLUS_B typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 3767 3767 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_load_wdr 0 typ_b_adr 02 GP02 3768 3768 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x379f ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 379f 0x379f seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) seq_random 02 ? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3769 3769 ioc_fiubs 0 fiu ; Flow C 0x210 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 31 TR02:11 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 2b VR05:0b val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 val_frame 5 376a 376a fiu_load_tar 1 hold_tar; Flow J cc=False 0x376d fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 376d 0x376d seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS val_rand 2 DEC_LOOP_COUNTER 376b 376b seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 376c 376c fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL 376d 376d ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x01) Discrete_Var Discrete_Ref Float_Var Float_Ref Access_Var Access_Ref Task_Var Task_Ref Subvector_Var Subarray_Var Heap_Access_Var Heap_Access_Ref Record_Var Variant_Record_Var Package_Var Vector_Var Matrix_Var Array_Var typ_b_adr 16 CSA/VAL_BUS typ_frame 1 376e 376e fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 06 GP06 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 376f 376f ioc_fiubs 0 fiu ; Flow J cc=False 0x376a seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 376a 0x376a seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3770 3770 fiu_len_fill_lit 41 zero-fill 0x1 fiu_offs_lit 18 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 3771 3771 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C cc=#0x0 0x379b fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 379b 0x379b seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_b_adr 32 TR02:12 typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_a_adr 02 GP02 val_b_adr 39 VR02:19 val_frame 2 3772 3772 fiu_len_fill_lit 6b zero-fill 0x2b fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED seq_random 21 ? typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 3773 3773 fiu_mem_start 4 continue ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 3774 3774 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 48 Load_current_lex+? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_source 0 FIU_BUS val_frame 2 3775 3775 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3789 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3789 0x3789 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 3776 3776 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 2f VR02:0f val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 3777 3777 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3786 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3786 0x3786 seq_lex_adr 2 seq_random 23 Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 3778 3778 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x3779 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 378c 0x378c typ_b_adr 20 TR02:00 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 20 VR02:00 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 3779 3779 fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x34dc ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 34dc 0x34dc seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_rand a PASS_B_HIGH 377a 377a fiu_mem_start 2 start-rd; Flow C 0x34dc ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 34dc 0x34dc typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 1f TOP - 0x0 val_c_source 0 FIU_BUS val_frame 2 val_rand a PASS_B_HIGH 377b 377b fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 377c 377c ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x37d1 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 37d1 0x37d1 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 377d 377d seq_br_type 7 Unconditional Call; Flow C 0x33a3 seq_branch_adr 33a3 0x33a3 seq_en_micro 0 377e 377e ioc_adrbs 3 seq ; Flow C 0x6b7 seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_a_adr 06 GP06 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL 377f 377f fiu_mem_start 2 start-rd; Flow C 0x33c4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 33c4 0x33c4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3780 3780 fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type d Dispatch False seq_branch_adr 3781 0x3781 seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 3781 3781 seq_br_type 7 Unconditional Call; Flow C 0x33ec seq_branch_adr 33ec 0x33ec 3782 3782 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 3783 3783 fiu_tivi_src c mar_0xc; Flow J cc=False 0x3785 ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3785 0x3785 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3784 3784 seq_br_type 3 Unconditional Branch; Flow J 0x37bf seq_branch_adr 37bf 0x37bf seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3785 3785 fiu_len_fill_lit 44 zero-fill 0x4; Flow R fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3786 3786 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3787 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 378c 0x378c typ_a_adr 06 GP06 3787 3787 ioc_fiubs 0 fiu typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 3788 3788 fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x3779 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3779 0x3779 typ_b_adr 20 TR02:00 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 20 VR02:00 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 2 3789 3789 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? val_a_adr 2f VR02:0f val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 378a 378a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 378b 378b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3777 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3777 0x3777 seq_lex_adr 2 seq_random 23 Load_control_pred+? typ_alu_func 1a PASS_B typ_b_adr 05 GP05 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 378c 378c fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 378d 378d fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x37d1 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 37d1 0x37d1 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 378e 378e ioc_load_wdr 0 ; Flow C 0x6b7 ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 378f 378f fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 3790 3790 seq_random 03 ? 3791 3791 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 3792 3792 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3793 ; -------------------------------------------------------------------------------------- 3793 ; Comes from: 3793 ; 3766 C #0x0 from color 0x0000 3793 ; -------------------------------------------------------------------------------------- 3793 3793 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3794 3794 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3795 3795 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs 1 typ+fiu seq_br_type a Unconditional Return typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3796 3796 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 3797 3797 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 3798 3798 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 3799 3799 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x37b2 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_fiubs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 37b2 0x37b2 seq_random 06 Pop_stack+? typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 32 VR03:12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 3 379a 379a seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 379b ; -------------------------------------------------------------------------------------- 379b ; Comes from: 379b ; 3771 C #0x0 from color 0x376a 379b ; -------------------------------------------------------------------------------------- 379b 379b seq_br_type a Unconditional Return; Flow R seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 seq_random 05 ? typ_b_adr 06 GP06 379c 379c ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 0e Load_control_top+? typ_b_adr 06 GP06 379d 379d ioc_tvbs 2 fiu+val; Flow R seq_br_type a Unconditional Return seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_int_reads 0 TYP VAL BUS seq_latch 1 seq_random 0e Load_control_top+? typ_b_adr 06 GP06 379e 379e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 379f 379f ioc_fiubs 0 fiu ; Flow C 0x210 ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) typ_a_adr 31 TR02:11 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_frame 2 val_a_adr 2b VR05:0b val_alu_func 5 DEC_A_MINUS_B val_b_adr 03 GP03 val_frame 5 37a0 37a0 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 06 GP06 37a1 37a1 ioc_fiubs 0 fiu ; Flow J 0x3770 seq_br_type 3 Unconditional Branch seq_branch_adr 3770 0x3770 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 37a2 37a2 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 02 GP02 typ_alu_func 1d A_AND_NOT_B typ_b_adr 3b TR05:1b typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 5 37a3 37a3 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 02 GP02 typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 20 VR0d:00 val_frame d 37a4 37a4 ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 3b TR05:1b typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 5 37a5 37a5 seq_br_type 0 Branch False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 32 TYP.PRIVACY_PATHS_EQ (med_late) typ_a_adr 0f GP0f typ_b_adr 0e GP0e 37a6 37a6 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_b_adr 06 GP06 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 37a7 37a7 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 0 fiu typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 37a8 37a8 ioc_load_wdr 0 ; Flow J 0x37a9 seq_br_type 2 Push (branch address) seq_branch_adr 32ca 0x32ca typ_b_adr 02 GP02 37a9 37a9 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 5 seq+seq typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 37aa 37aa ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_random 06 Pop_stack+? typ_b_adr 2e TR02:0e typ_frame 2 37ab 37ab ioc_adrbs 1 val seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_latch 1 typ_b_adr 06 GP06 typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 37ac 37ac fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3772 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3772 0x3772 seq_en_micro 0 seq_random 0f Load_control_top+? typ_csa_cntl 7 FINISH_POP_DOWN val_a_adr 02 GP02 37ad 37ad seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 06 GP06 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_mux_sel 2 ALU 37ae 37ae ioc_fiubs 0 fiu ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 2b VR05:0b val_frame 5 37af 37af fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 06 GP06 37b0 37b0 ioc_fiubs 0 fiu val_c_adr 3b GP04 val_c_source 0 FIU_BUS 37b1 37b1 fiu_vmux_sel 1 fill value; Flow J 0x3771 ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3771 0x3771 typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 37b2 37b2 ioc_tvbs 5 seq+seq; Flow J cc=True 0x37ad seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 37ad 0x37ad seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_b_adr 16 CSA/VAL_BUS 37b3 37b3 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_random 02 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 06 GP06 val_alu_func 0 PASS_A 37b4 37b4 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x211 seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 3f TR09:1f typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 17 LOOP_COUNTER val_alu_func 19 X_XOR_B val_b_adr 31 VR02:11 val_frame 2 37b5 37b5 fiu_mem_start 3 start-wr; Flow C cc=False 0x211 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 16 CSA/VAL_BUS 37b6 37b6 fiu_mem_start 2 start-rd; Flow C cc=False 0x211 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3e VR02:1e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 2 val_rand a PASS_B_HIGH 37b7 37b7 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 37b8 37b8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x37bd fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 37bd 0x37bd seq_cond_sel 00 VAL.ALU_ZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 04 GP04 val_alu_func 19 X_XOR_B val_b_adr 32 VR07:12 val_frame 7 37b9 37b9 fiu_len_fill_lit 46 zero-fill 0x6; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 37ba 37ba fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x37bb fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 37bf 0x37bf typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 37bb 37bb seq_br_type 7 Unconditional Call; Flow C 0x6b7 seq_branch_adr 06b7 0x06b7 typ_a_adr 17 LOOP_COUNTER typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR05:10 typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 37bc 37bc ioc_adrbs 1 val ; Flow J 0x3ba5 seq_br_type 3 Unconditional Branch seq_branch_adr 3ba5 0x3ba5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_frame 3 val_rand a PASS_B_HIGH 37bd 37bd ioc_adrbs 1 val ; Flow C 0x3499 seq_br_type 7 Unconditional Call seq_branch_adr 3499 0x3499 seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_rand a PASS_B_HIGH 37be 37be ioc_adrbs 1 val ; Flow C 0x3ba5 seq_br_type 7 Unconditional Call seq_branch_adr 3ba5 0x3ba5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 32 VR03:12 val_frame 3 val_rand a PASS_B_HIGH 37bf 37bf fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_random 02 ? typ_a_adr 06 GP06 typ_b_adr 06 GP06 37c0 37c0 ioc_adrbs 1 val typ_csa_cntl 1 START_POP_DOWN val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 2d VR04:0d val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 4 37c1 37c1 ioc_tvbs 1 typ+fiu seq_en_micro 0 typ_csa_cntl 7 FINISH_POP_DOWN val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 37c2 37c2 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED seq_random 21 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 37c3 37c3 ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 22 VR02:02 val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 37c4 37c4 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 48 Load_current_lex+? typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 37c5 37c5 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_b_adr 05 GP05 typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 37c6 37c6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 3 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_frame 2 37c7 37c7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_lex_adr 2 seq_random 23 Load_control_pred+? typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 37c8 37c8 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_b_adr 05 GP05 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 37c9 37c9 ioc_fiubs 0 fiu typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_c_adr 2f TOP val_c_source 0 FIU_BUS 37ca 37ca fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 04 GP04 37cb 37cb fiu_len_fill_lit 6b zero-fill 0x2b; Flow C 0x332e fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_random 15 ? typ_a_adr 06 GP06 typ_mar_cntl 9 LOAD_MAR_CODE 37cc 37cc ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x211 seq_br_type 4 Call False seq_branch_adr 0211 0x0211 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? 37cd 37cd fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq ioc_tvbs 1 typ+fiu seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 37ce 37ce ioc_adrbs 1 val ; Flow C 0x3ba5 seq_br_type 7 Unconditional Call seq_branch_adr 3ba5 0x3ba5 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_rand a PASS_B_HIGH 37cf 37cf fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_alu_func 1d A_AND_NOT_B typ_b_adr 3d TR09:1d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 37d0 37d0 ioc_load_wdr 0 ; Flow J 0x37bf seq_br_type 3 Unconditional Branch seq_branch_adr 37bf 0x37bf 37d1 37d1 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2f VR04:0f val_frame 4 val_rand 9 PASS_A_HIGH 37d2 37d2 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x37da seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 37da 0x37da seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS 37d3 37d3 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 37d4 37d4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 37d5 37d5 fiu_load_tar 1 hold_tar; Flow J cc=False 0x37d8 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 37d8 0x37d8 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 37d6 37d6 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_tivi_src 9 type_val 37d7 37d7 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x378e fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 378e 0x378e typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 37d8 37d8 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 2 fiu+val typ_a_adr 22 TR01:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 37d9 37d9 ioc_load_wdr 0 ; Flow J 0x378f ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 378f 0x378f typ_b_adr 06 GP06 37da 37da fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 3a VR13:1a val_frame 13 val_rand 9 PASS_A_HIGH 37db 37db fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 37dc 37dc fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 37dd 37dd fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_tvbs 2 fiu+val typ_a_adr 22 TR01:02 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 3a VR13:1a val_frame 13 val_rand 9 PASS_A_HIGH 37de 37de ioc_load_wdr 0 ; Flow J 0x378f ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 378f 0x378f typ_b_adr 06 GP06 37df 37df <halt> ; Flow R 37e0 ; -------------------------------------------------------------------------------------- 37e0 ; Comes from: 37e0 ; 380c C from color MACRO_Execute_Family,Count 37e0 ; -------------------------------------------------------------------------------------- 37e0 37e0 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_oreg 1 hold_oreg fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 37e1 37e1 fiu_len_fill_lit 58 zero-fill 0x18; Flow C cc=True 0x32a6 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32a6 0x32a6 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS val_a_adr 22 VR06:02 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_frame 6 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 37e2 37e2 fiu_len_fill_lit 66 zero-fill 0x26 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 37e3 37e3 ioc_tvbs 1 typ+fiu; Flow R cc=False ; Flow J cc=True 0x32a6 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32a6 0x32a6 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) val_a_adr 02 GP02 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS 37e4 ; -------------------------------------------------------------------------------------- 37e4 ; 0x0137 Execute Entry,Rendezvous 37e4 ; -------------------------------------------------------------------------------------- 37e4 MACRO_Execute_Entry,Rendezvous: 37e4 37e4 dispatch_brk_class 5 ; Flow J cc=True 0x390c dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 37e4 fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 390c 0x390c seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 0 PASS_A 37e5 37e5 ioc_tvbs 5 seq+seq; Flow C cc=True 0x32de seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_b_adr 16 CSA/VAL_BUS typ_frame a typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 20 TOP - 0x1 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 37e6 37e6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 37e7 37e7 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x37e8 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 37e4 MACRO_Execute_Entry,Rendezvous seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame e typ_rand a PASS_B_HIGH val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 37e8 37e8 fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=False 0x37f0 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 37f0 0x37f0 typ_a_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_lit 1 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 37e9 37e9 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x390c fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 390c 0x390c seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_b_adr 2e VR12:0e val_c_adr 3f GP00 val_frame 12 37ea 37ea fiu_mem_start 3 start-wr; Flow J 0x37eb ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 37eb 0x37eb seq_random 02 ? typ_alu_func 1b A_OR_B typ_b_adr 2d TR02:0d typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 37eb 37eb fiu_len_fill_lit 40 zero-fill 0x0; Flow J 0x37ec fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_alu_func 1a PASS_B typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 1a PASS_B val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 37ec 37ec fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x33af fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 39 VR02:19 val_frame 2 37ed 37ed fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 37ee 37ee seq_br_type 7 Unconditional Call; Flow C 0x3914 seq_branch_adr 3914 0x3914 typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 37ef 37ef seq_br_type 3 Unconditional Branch; Flow J 0x33a3 seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 37f0 37f0 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x390c fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 390c 0x390c seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 02 GP02 typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 31 VR02:11 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 37f1 37f1 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x37f3 seq_br_type 1 Branch True seq_branch_adr 37f3 0x37f3 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_random 02 ? typ_a_adr 2c TR05:0c typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 37f2 37f2 seq_br_type a Unconditional Return; Flow R seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 37f3 37f3 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_rand 9 PASS_A_HIGH 37f4 37f4 ioc_tvbs 5 seq+seq seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A 37f5 37f5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 37f6 37f6 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x37f8 fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 65 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 37f8 0x37f8 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 03 GP03 37f7 37f7 ioc_load_wdr 0 ; Flow J 0x38c6 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 38c6 0x38c6 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 37f8 37f8 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 1 val typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_b_adr 39 VR02:19 val_frame 2 37f9 37f9 fiu_tivi_src 2 tar_fiu; Flow J 0x38c6 ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 38c6 0x38c6 typ_a_adr 14 ZEROS val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_c_adr 3a GP05 val_c_mux_sel 2 ALU 37fa ; -------------------------------------------------------------------------------------- 37fa ; 0x0133 Execute Family,Rendezvous 37fa ; -------------------------------------------------------------------------------------- 37fa MACRO_Execute_Family,Rendezvous: 37fa 37fa dispatch_brk_class 5 ; Flow J cc=True 0x390e dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 37fa fiu_mem_start 6 start_rd_if_false ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 390e 0x390e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 10 TOP typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_alu_func 0 PASS_A val_b_adr 10 TOP 37fb 37fb ioc_tvbs 5 seq+seq; Flow C cc=True 0x32de seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 03 GP03 typ_b_adr 16 CSA/VAL_BUS typ_frame a typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1e TOP - 2 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 21 TOP - 0x2 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 37fc 37fc seq_br_type 7 Unconditional Call; Flow C 0x37e0 seq_branch_adr 37e0 0x37e0 typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 37fd 37fd fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x37fe fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 37fa MACRO_Execute_Family,Rendezvous seq_cond_sel 0a VAL.ALU_LT_ZERO(late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame e typ_rand 1 INC_LOOP_COUNTER val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 37fe 37fe fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=False 0x3801 fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3801 0x3801 seq_random 02 ? typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 1e TOP - 2 val_alu_func 0 PASS_A val_b_adr 1f TOP - 1 37ff 37ff fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x390e fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 390e 0x390e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand c WRITE_OUTER_FRAME val_a_adr 1f TOP - 1 val_b_adr 2e VR12:0e val_c_adr 3f GP00 val_frame 12 3800 3800 fiu_mem_start 3 start-wr; Flow J 0x37eb ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 37eb 0x37eb typ_alu_func 1b A_OR_B typ_b_adr 29 TR09:09 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 03 GP03 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 3801 3801 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x390e fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 390e 0x390e seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 02 GP02 typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 31 VR02:11 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 3802 3802 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x37f3 seq_br_type 1 Branch True seq_branch_adr 37f3 0x37f3 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 2c TR05:0c typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3803 3803 seq_br_type 3 Unconditional Branch; Flow J 0x37f2 seq_branch_adr 37f2 0x37f2 seq_en_micro 0 typ_csa_cntl 2 PUSH_CSA 3804 ; -------------------------------------------------------------------------------------- 3804 ; 0x0136 Execute Entry,Count 3804 ; -------------------------------------------------------------------------------------- 3804 MACRO_Execute_Entry,Count: 3804 3804 dispatch_brk_class 8 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 3804 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 10 TOP 3805 3805 ioc_tvbs 5 seq+seq; Flow C cc=True 0x32de seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS 3806 3806 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_b_adr 16 CSA/VAL_BUS 3807 3807 ioc_tvbs 2 fiu+val typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_rand a PASS_B_HIGH 3808 3808 fiu_len_fill_lit 53 zero-fill 0x13; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand a PASS_B_HIGH val_c_adr 2f TOP val_c_source 0 FIU_BUS 3809 3809 <halt> ; Flow R 380a ; -------------------------------------------------------------------------------------- 380a ; 0x0132 Execute Family,Count 380a ; -------------------------------------------------------------------------------------- 380a MACRO_Execute_Family,Count: 380a 380a dispatch_brk_class 8 dispatch_csa_valid 2 dispatch_ignore 1 dispatch_uadr 380a fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 10 TOP typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame a typ_mar_cntl e LOAD_MAR_CONTROL typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 1a PASS_B val_b_adr 10 TOP 380b 380b ioc_tvbs 5 seq+seq; Flow C cc=True 0x32de seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS 380c 380c seq_br_type 7 Unconditional Call; Flow C 0x37e0 seq_branch_adr 37e0 0x37e0 typ_b_adr 1f TOP - 1 typ_rand a PASS_B_HIGH val_a_adr 1f TOP - 1 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 380d 380d fiu_len_fill_lit 53 zero-fill 0x13; Flow R fiu_mem_start 2 start-rd fiu_offs_lit 4c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type e Unconditional Dispatch seq_random 1c ? typ_b_adr 16 CSA/VAL_BUS typ_c_adr 20 TOP - 0x1 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame e typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_c_adr 20 TOP - 0x1 val_c_source 0 FIU_BUS 380e ; -------------------------------------------------------------------------------------- 380e ; 0x013f Execute Select,Rendezvous 380e ; -------------------------------------------------------------------------------------- 380e MACRO_Execute_Select,Rendezvous: 380e 380e dispatch_brk_class 5 ; Flow J cc=True 0x3910 dispatch_csa_valid 1 dispatch_ignore 1 dispatch_uadr 380e fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3910 0x3910 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 31 VR02:11 val_frame 2 380f 380f fiu_len_fill_lit 4e zero-fill 0xe; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 10 TOP val_alu_func 1e A_AND_B val_b_adr 2e VR02:0e val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 3810 3810 fiu_len_fill_lit 4e zero-fill 0xe fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_tvbs 1 typ+fiu typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1e typ_rand a PASS_B_HIGH val_a_adr 20 VR07:00 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 3811 3811 ioc_fiubs 1 val ; Flow J cc=True 0x3821 ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3821 0x3821 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME val_a_adr 10 TOP val_b_adr 16 CSA/VAL_BUS 3812 3812 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 3813 3813 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3814 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3814 0x3814 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 val_b_adr 20 VR02:00 val_frame 2 3814 3814 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x3818 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3818 0x3818 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_b_adr 16 CSA/VAL_BUS typ_c_lit 1 typ_frame 6 typ_rand 1 INC_LOOP_COUNTER 3815 3815 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 3816 3816 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 3817 3817 ioc_fiubs 0 fiu seq_en_micro 0 3818 3818 seq_b_timing 0 Early Condition; Flow J cc=True 0x3819 ; Flow J cc=#0x0 0x3819 seq_br_type b Case False seq_branch_adr 3819 0x3819 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 3819 3819 fiu_load_var 1 hold_var; Flow J 0x381d fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 381d 0x381d val_b_adr 22 VR07:02 val_frame 7 381a 381a seq_br_type 3 Unconditional Branch; Flow J 0x3857 seq_branch_adr 3857 0x3857 seq_en_micro 0 381b 381b fiu_load_var 1 hold_var; Flow J 0x381d fiu_tivi_src 1 tar_val seq_br_type 3 Unconditional Branch seq_branch_adr 381d 0x381d typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 31 VR06:11 val_frame 6 381c 381c seq_br_type 3 Unconditional Branch; Flow J 0x3857 seq_branch_adr 3857 0x3857 seq_en_micro 0 381d 381d fiu_mem_start 2 start-rd; Flow J cc=True 0x381f ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 381f 0x381f seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 381e 381e seq_br_type 3 Unconditional Branch; Flow J 0x3814 seq_branch_adr 3814 0x3814 381f 381f seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 3820 3820 seq_br_type 7 Unconditional Call; Flow C 0x3857 seq_branch_adr 3857 0x3857 seq_en_micro 0 3821 3821 ioc_tvbs 3 fiu+fiu; Flow J cc=False 0x382f seq_br_type 0 Branch False seq_branch_adr 382f 0x382f seq_cond_sel 0b VAL.ALU_LE_ZERO(late) seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3822 3822 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 7 3823 3823 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 3824 3824 fiu_mem_start 2 start-rd; Flow J 0x3825 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3825 0x3825 typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA 3825 3825 seq_br_type 3 Unconditional Branch; Flow J 0x3826 seq_branch_adr 3826 0x3826 typ_a_adr 08 GP08 typ_alu_func 1e A_AND_B typ_b_adr 3e TR02:1e typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 3826 3826 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x382a fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 382a 0x382a seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 3d TR06:1d typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 6 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3827 3827 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 3828 3828 fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA 3829 3829 ioc_fiubs 0 fiu seq_en_micro 0 382a 382a fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=#0x0 0x3831 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 3831 0x3831 seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 382b 382b fiu_len_fill_lit 4e zero-fill 0xe; Flow C cc=True 0x3857 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3857 0x3857 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 20 TR02:00 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 382c 382c ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x3826 seq_br_type 1 Branch True seq_branch_adr 3826 0x3826 seq_cond_sel 0b VAL.ALU_LE_ZERO(late) typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 2f TOP typ_c_mux_sel 0 ALU val_a_adr 04 GP04 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 382d 382d fiu_mem_start 2 start-rd ioc_adrbs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 382e 382e seq_br_type 3 Unconditional Branch; Flow J 0x3826 seq_branch_adr 3826 0x3826 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 6 382f 382f ioc_adrbs 2 typ ; Flow C 0x210 seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 15 VAL.M_BIT(early) seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA val_a_adr 29 VR07:09 val_alu_func 0 PASS_A val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 3830 3830 fiu_mem_start 2 start-rd; Flow J 0x3825 seq_br_type 3 Unconditional Branch seq_branch_adr 3825 0x3825 typ_a_adr 10 TOP typ_alu_func 1d A_AND_NOT_B typ_b_adr 31 TR06:11 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 6 3831 ; -------------------------------------------------------------------------------------- 3831 ; Comes from: 3831 ; 382a C #0x0 from color 0x3810 3831 ; -------------------------------------------------------------------------------------- 3831 3831 fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type a Unconditional Return typ_b_adr 30 TR07:10 typ_frame 7 val_b_adr 22 VR07:02 val_frame 7 3832 3832 fiu_load_tar 1 hold_tar; Flow J 0x3836 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3836 0x3836 typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_b_adr 30 TR07:10 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 22 VR07:02 val_frame 7 3833 3833 fiu_load_tar 1 hold_tar; Flow R cc=True ; Flow J cc=False 0x3835 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 8 Return True seq_branch_adr 3835 0x3835 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 31 TR07:11 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 3834 3834 fiu_load_tar 1 hold_tar; Flow J cc=True 0x3844 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_tivi_src 9 type_val ioc_adrbs 2 typ seq_br_type 1 Branch True seq_branch_adr 3844 0x3844 seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 04 GP04 typ_alu_func 7 INC_A typ_b_adr 30 TR07:10 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 7 typ_mar_cntl b LOAD_MAR_DATA typ_rand 0 NO_OP val_a_adr 01 GP01 val_alu_func 6 A_MINUS_B val_b_adr 31 VR06:11 val_frame 6 3835 3835 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3836 3836 ioc_load_wdr 0 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_b_adr 10 TOP val_b_adr 10 TOP 3837 3837 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_mux_sel 0 ALU typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B val_b_adr 16 CSA/VAL_BUS 3838 3838 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3839 0x3839 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_rand a PASS_B_HIGH val_a_adr 21 VR07:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3839 3839 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 383a 383a fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 383b 383b fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_frame 6 383c 383c fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 383d 383d fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_fiubs 0 fiu typ_b_adr 01 GP01 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 383e 383e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 383f 383f seq_b_timing 1 Latch Condition; Flow J cc=True 0x3842 seq_br_type 1 Branch True seq_branch_adr 3842 0x3842 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 3840 3840 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_c_adr 3e GP01 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 02 GP02 3841 3841 ioc_load_wdr 0 ; Flow J 0x38c6 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 38c6 0x38c6 typ_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3842 3842 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_c_adr 3e GP01 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 39 VR02:19 val_frame 2 3843 3843 ioc_load_wdr 0 ; Flow J 0x38c6 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 38c6 0x38c6 val_b_adr 39 VR02:19 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 3844 3844 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1 A_PLUS_B typ_b_adr 30 TR07:10 typ_c_adr 2f TOP typ_c_mux_sel 0 ALU typ_frame 7 3845 3845 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3853 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3853 0x3853 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_a_adr 04 GP04 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 36 GP09 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_frame e typ_mar_cntl b LOAD_MAR_DATA typ_rand 6 CHECK_CLASS_A_??_B 3846 3846 ioc_load_wdr 0 typ_b_adr 10 TOP val_b_adr 10 TOP 3847 3847 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3848 0x3848 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_frame e typ_rand 1 INC_LOOP_COUNTER val_a_adr 21 VR07:01 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3848 3848 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 08 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 28 VR07:08 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 7 3849 3849 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_random 02 ? typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 10 TOP typ_c_adr 37 GP08 typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 384a 384a fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 71 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 22 VR06:02 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_frame 6 384b 384b fiu_mem_start 2 start-rd fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 384c 384c ioc_fiubs 0 fiu typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS 384d 384d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 384e 384e seq_b_timing 1 Latch Condition; Flow J cc=True 0x3851 seq_br_type 1 Branch True seq_branch_adr 3851 0x3851 typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 04 GP04 typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU 384f 384f fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 65 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_adrbs 2 typ typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_b_adr 02 GP02 3850 3850 ioc_load_wdr 0 ; Flow J 0x38c6 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 38c6 0x38c6 typ_b_adr 02 GP02 val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3851 3851 fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_adrbs 2 typ typ_a_adr 09 GP09 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_mar_cntl b LOAD_MAR_DATA val_b_adr 39 VR02:19 val_frame 2 3852 3852 ioc_load_wdr 0 ; Flow J 0x38c6 ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 38c6 0x38c6 val_b_adr 39 VR02:19 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 3853 3853 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 2 3854 3854 ioc_tvbs 2 fiu+val; Flow C 0x3914 seq_br_type 7 Unconditional Call seq_branch_adr 3914 0x3914 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1e A_AND_B val_b_adr 36 VR07:16 val_frame 7 3855 3855 seq_br_type 5 Call True; Flow C cc=True 0x32a6 seq_branch_adr 32a6 0x32a6 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) typ_b_adr 09 GP09 typ_c_lit 0 typ_frame 1e 3856 3856 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3857 ; -------------------------------------------------------------------------------------- 3857 ; Comes from: 3857 ; 3820 C from color 0x3810 3857 ; 382b C True from color 0x3810 3857 ; -------------------------------------------------------------------------------------- 3857 3857 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 08 GP08 typ_alu_func 1b A_OR_B typ_b_adr 2e TR07:0e typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 7 3858 3858 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_var 1 hold_var fiu_offs_lit 21 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_c_adr 3f GP00 typ_frame 1 3859 3859 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x385a ; Flow J cc=#0x0 0x3861 fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 3861 0x3861 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 1 385a 385a fiu_load_var 1 hold_var; Flow J cc=True 0x385b ; Flow J cc=#0x0 0x3877 fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type b Case False seq_branch_adr 3877 0x3877 seq_en_micro 0 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 34 VR11:14 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 11 385b 385b fiu_mem_start 3 start-wr; Flow J 0x385c ioc_adrbs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_a_adr 20 TR07:00 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_csa_cntl 3 POP_CSA typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1e A_AND_B val_b_adr 36 VR07:16 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 385c 385c fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x33af fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 385d 385d fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x3914 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3914 0x3914 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 385e 385e seq_b_timing 1 Latch Condition; Flow J cc=True 0x33a3 seq_br_type 1 Branch True seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 385f 385f seq_br_type 5 Call True; Flow C cc=True 0x32ab seq_branch_adr 32ab 0x32ab seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 3860 3860 seq_br_type 7 Unconditional Call; Flow C 0x32e2 seq_branch_adr 32e2 0x32e2 3861 3861 seq_br_type 3 Unconditional Branch; Flow J 0x3864 seq_branch_adr 3864 0x3864 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 23 TR01:03 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 1 3862 3862 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3866 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3866 0x3866 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 10 TOP typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 02 GP02 3863 3863 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 3864 3864 fiu_load_var 1 hold_var; Flow J cc=True 0x385b fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 385b 0x385b typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_b_adr 34 VR11:14 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 11 3865 3865 seq_br_type 7 Unconditional Call; Flow C 0x385b seq_branch_adr 385b 0x385b val_alu_func 13 ONES val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3866 3866 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 3 POP_CSA typ_mar_cntl b LOAD_MAR_DATA 3867 3867 fiu_load_tar 1 hold_tar; Flow J cc=True 0x3873 fiu_load_var 1 hold_var fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3873 0x3873 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 25 VR07:05 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 3868 3868 seq_br_type 7 Unconditional Call; Flow C 0x33af seq_branch_adr 33af 0x33af 3869 3869 ioc_tvbs 5 seq+seq; Flow C 0x56b seq_br_type 7 Unconditional Call seq_branch_adr 056b 0x056b seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1e TR17:01 typ_c_mux_sel 0 ALU typ_frame 17 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 04 GP04 val_alu_func 0 PASS_A val_c_adr 1e VR17:01 val_c_mux_sel 2 ALU val_frame 17 386a 386a fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x386b fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_fiubs 2 typ seq_br_type 2 Push (branch address) seq_branch_adr 386f 0x386f typ_a_adr 20 TR02:00 typ_b_adr 20 TR02:00 typ_frame 2 val_b_adr 20 VR11:00 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 11 386b 386b ioc_tvbs 2 fiu+val; Flow C 0x3914 seq_br_type 7 Unconditional Call seq_branch_adr 3914 0x3914 typ_a_adr 21 TR01:01 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 386c 386c fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x33a3 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 386d 386d seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_b_adr 20 TR02:00 typ_frame 2 386e 386e seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 386f 386f fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x3871 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3871 0x3871 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 24 TR02:04 typ_alu_func 1a PASS_B typ_b_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 3870 3870 seq_br_type 3 Unconditional Branch; Flow J 0x3875 seq_branch_adr 3875 0x3875 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 3871 3871 seq_br_type 2 Push (branch address); Flow J 0x3872 seq_branch_adr 386f 0x386f 3872 3872 seq_br_type 3 Unconditional Branch; Flow J 0x3912 seq_branch_adr 3912 0x3912 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3873 3873 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3f GP00 val_c_source 0 FIU_BUS 3874 3874 seq_br_type 7 Unconditional Call; Flow C 0x3914 seq_branch_adr 3914 0x3914 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1e A_AND_B val_b_adr 36 VR07:16 val_frame 7 3875 3875 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3876 3876 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_mar_cntl e LOAD_MAR_CONTROL val_c_adr 2e TOP + 1 val_c_source 0 FIU_BUS 3877 3877 seq_br_type 3 Unconditional Branch; Flow J 0x3864 seq_branch_adr 3864 0x3864 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_latch 1 typ_a_adr 21 TR01:01 typ_alu_func 1e A_AND_B typ_b_adr 10 TOP typ_frame 1 3878 3878 fiu_load_tar 1 hold_tar; Flow J 0x3879 fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3879 0x3879 seq_int_reads 5 RESOLVE RAM typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3879 3879 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x387b fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 387b 0x387b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_b_adr 22 TR02:02 typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 2 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 387a 387a ioc_tvbs 3 fiu+fiu; Flow J cc=True 0x388b seq_br_type 1 Branch True seq_branch_adr 388b 0x388b seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 23 TR02:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 387b 387b fiu_len_fill_lit 53 zero-fill 0x13 fiu_offs_lit 65 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val typ_a_adr 23 TR02:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 387c 387c fiu_mem_start 2 start-rd; Flow J cc=False 0x3889 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 0 Branch False seq_branch_adr 3889 0x3889 seq_cond_sel 07 VAL.ALU_32_CO(late) typ_a_adr 23 TR02:03 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 23 VR02:03 val_alu_func 1 A_PLUS_B val_b_adr 37 VR02:17 val_frame 2 387d 387d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3887 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3887 0x3887 seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 23 TR02:03 typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR 387e 387e fiu_len_fill_lit 4c zero-fill 0xc fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 387f 387f fiu_len_fill_lit 53 zero-fill 0x13 fiu_load_tar 1 hold_tar fiu_offs_lit 25 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_latch 1 typ_a_adr 3e TR02:1e typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3880 3880 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x3881 fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 387c 0x387c typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 04 GP04 3881 3881 ioc_tvbs 1 typ+fiu; Flow R cc=False seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3882 0x3882 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 3882 3882 ioc_fiubs 2 typ ; Flow R cc=True ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 3883 0x3883 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 3883 3883 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x3884 fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 23 VR02:03 val_frame 2 3884 3884 ioc_fiubs 0 fiu ; Flow C 0x33af seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af typ_alu_func 1b A_OR_B typ_b_adr 20 TR11:00 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 11 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 3885 3885 seq_br_type 7 Unconditional Call; Flow C 0x3914 seq_branch_adr 3914 0x3914 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 37 TR02:17 typ_frame 2 3886 3886 seq_br_type 3 Unconditional Branch; Flow J 0x33a3 seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3887 3887 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 05 ? 3888 3888 seq_br_type 3 Unconditional Branch; Flow J 0x387c seq_branch_adr 387c 0x387c 3889 3889 fiu_tivi_src 8 type_var ioc_adrbs 2 typ seq_en_micro 0 typ_b_adr 22 TR06:02 typ_frame 6 typ_mar_cntl 4 RESTORE_MAR 388a 388a fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 388b 388b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x388c fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 388d 0x388d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_c_adr 36 GP09 val_c_source 0 FIU_BUS 388c 388c fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x39e6 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 39e6 0x39e6 typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 388d 388d typ_a_adr 21 TR07:01 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 7 388e 388e seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 388f 388f seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x389e seq_br_type 1 Branch True seq_branch_adr 389e 0x389e seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 22 TR02:02 typ_frame 2 3890 3890 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 7c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP 3891 3891 ioc_tvbs 1 typ+fiu; Flow J cc=False 0x38c2 seq_br_type 0 Branch False seq_branch_adr 38c2 0x38c2 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3892 3892 fiu_mem_start 2 start-rd ioc_adrbs 3 seq seq_int_reads 7 CONTROL PRED seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 3893 3893 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 62 ? typ_a_adr 3d TR02:1d typ_alu_func 18 NOT_A_AND_B typ_b_adr 22 TR02:02 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl 6 INCREMENT_MAR typ_rand 6 CHECK_CLASS_A_??_B 3894 3894 ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 4d Load_current_lex+? typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_lit 0 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 22 VR02:02 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 1e VR02:01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3895 3895 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3899 fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3899 0x3899 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 3896 3896 fiu_len_fill_lit 3f sign-fill 0x3f fiu_offs_lit 40 fiu_op_sel 3 insert ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_int_reads 7 CONTROL PRED seq_random 57 Load_control_pred+? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_csa_cntl 1 START_POP_DOWN 3897 3897 ioc_fiubs 2 typ seq_en_micro 0 seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 05 GP05 typ_c_adr 1d TR02:02 typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 3898 3898 seq_br_type 3 Unconditional Branch; Flow J 0x388f seq_branch_adr 388f 0x388f typ_b_adr 02 GP02 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 3899 3899 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_int_reads 7 CONTROL PRED seq_random 4f ? typ_a_adr 05 GP05 typ_alu_func 0 PASS_A typ_csa_cntl 1 START_POP_DOWN 389a 389a fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val seq_en_micro 0 typ_a_adr 21 TR10:01 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_csa_cntl 7 FINISH_POP_DOWN typ_frame 10 typ_mar_cntl e LOAD_MAR_CONTROL 389b 389b ioc_fiubs 2 typ seq_lex_adr 2 seq_random 64 Load_control_top+? typ_a_adr 05 GP05 389c 389c fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 1b fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_int_reads 0 TYP VAL BUS seq_lex_adr 3 seq_random 22 ? typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 389d 389d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3898 fiu_offs_lit 40 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3898 0x3898 seq_random 41 Load_control_pred+? typ_c_adr 1d TR02:02 typ_frame 2 val_c_adr 1d VR02:02 val_frame 2 389e 389e fiu_mem_start 2 start-rd; Flow C 0x339b ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 339b 0x339b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 389f 389f ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x38a4 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38a4 0x38a4 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 06 GP06 typ_alu_func 1e A_AND_B typ_b_adr 2b TR02:0b typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 38a0 38a0 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 23 VR05:03 val_frame 5 38a1 38a1 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x38a2 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_tvbs 2 fiu+val seq_br_type 2 Push (branch address) seq_branch_adr 389e 0x389e typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 21 VR02:01 val_frame 2 38a2 38a2 fiu_len_fill_lit 4f zero-fill 0xf; Flow J 0x38a3 fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 38a3 38a3 ioc_tvbs 1 typ+fiu; Flow J 0x33a3 seq_br_type 3 Unconditional Branch seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1c VR02:03 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 38a4 38a4 fiu_mem_start 2 start-rd; Flow C 0x3377 ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 3377 0x3377 seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_a_adr 23 TR02:03 typ_alu_func 1b A_OR_B typ_b_adr 2e TR02:0e typ_c_adr 1c TR02:03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 38a5 38a5 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x38ab fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 38ab 0x38ab seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 38a6 38a6 ioc_fiubs 2 typ ; Flow J 0x38a7 seq_br_type 3 Unconditional Branch seq_branch_adr 38a7 0x38a7 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 38a7 38a7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x38c0 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38c0 0x38c0 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 23 VR02:03 val_alu_func 1e A_AND_B val_b_adr 3b VR02:1b val_frame 2 38a8 38a8 fiu_load_oreg 1 hold_oreg; Flow C 0x338c fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 338c 0x338c typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 23 VR02:03 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 38a9 38a9 fiu_load_var 1 hold_var; Flow C cc=#0x0 0x38ab fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type f Unconditional Case Call seq_branch_adr 38ab 0x38ab seq_en_micro 0 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 38aa 38aa ioc_fiubs 2 typ ; Flow J 0x38a7 seq_br_type 3 Unconditional Branch seq_branch_adr 38a7 0x38a7 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 38ab 38ab seq_br_type 3 Unconditional Branch; Flow J 0x38af seq_branch_adr 38af 0x38af 38ac 38ac seq_br_type 3 Unconditional Branch; Flow J 0x38af seq_branch_adr 38af 0x38af 38ad 38ad fiu_mem_start 2 start-rd; Flow J 0x3487 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3487 0x3487 typ_mar_cntl a LOAD_MAR_IMPORT val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 38ae 38ae fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x38b2 fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 38b2 0x38b2 seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand c WRITE_OUTER_FRAME 38af 38af seq_br_type 2 Push (branch address); Flow J 0x38b0 seq_branch_adr 38a7 0x38a7 38b0 38b0 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_tvbs 5 seq+seq 38b1 38b1 ioc_fiubs 0 fiu ; Flow J 0x3a10 seq_br_type 3 Unconditional Branch seq_branch_adr 3a10 0x3a10 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 38b2 38b2 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl b LOAD_MAR_DATA val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 38b3 38b3 ioc_fiubs 2 typ val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 38b4 38b4 fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 38b5 38b5 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 32 VR06:12 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 6 38b6 38b6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x38bf seq_br_type 1 Branch True seq_branch_adr 38bf 0x38bf seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3b VR02:1b val_alu_func 1e A_AND_B val_b_adr 24 VR02:04 val_frame 2 38b7 38b7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_frame 2 38b8 38b8 fiu_mem_start a start_continue_if_false; Flow J cc=False 0x38ba seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 38ba 0x38ba seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR 38b9 38b9 fiu_fill_mode_src 0 ; Flow J 0x38bc fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 38bc 0x38bc typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 38ba 38ba fiu_load_var 1 hold_var fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy 38bb 38bb fiu_fill_mode_src 0 ; Flow J 0x38bc fiu_length_src 0 length_register fiu_offset_src 0 offset_register fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 38bc 0x38bc typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 38bc 38bc ioc_fiubs 2 typ ; Flow J 0x38bd seq_br_type 2 Push (branch address) seq_branch_adr 38b6 0x38b6 val_a_adr 24 VR02:04 val_alu_func 0 PASS_A val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 38bd 38bd fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_tvbs 5 seq+seq val_a_adr 23 VR02:03 val_frame 2 38be 38be ioc_fiubs 0 fiu ; Flow J 0x3a10 seq_br_type 3 Unconditional Branch seq_branch_adr 3a10 0x3a10 val_c_adr 1c VR02:03 val_c_source 0 FIU_BUS val_frame 2 38bf 38bf seq_br_type 3 Unconditional Branch; Flow J 0x38a7 seq_branch_adr 38a7 0x38a7 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38c0 38c0 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 38c1 38c1 seq_br_type 3 Unconditional Branch; Flow J 0x3890 seq_branch_adr 3890 0x3890 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38c2 38c2 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 2a VR05:0a val_frame 5 38c3 38c3 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 38c4 38c4 ioc_load_wdr 0 ; Flow J 0x38c5 ioc_tvbs 3 fiu+fiu seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38c5 38c5 fiu_mem_start 2 start-rd; Flow J 0x3496 ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3496 0x3496 seq_int_reads 6 CONTROL TOP typ_a_adr 33 TR02:13 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 38c6 38c6 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 05 GP05 val_c_adr 3a GP05 val_c_mux_sel 2 ALU val_frame 2 38c7 38c7 fiu_len_fill_lit 78 zero-fill 0x38 fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_a_adr 02 GP02 val_alu_func 1e A_AND_B val_b_adr 3e VR02:1e val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 38c8 38c8 fiu_load_tar 1 hold_tar fiu_tivi_src 8 type_var typ_a_adr 02 GP02 typ_alu_func 1c DEC_A typ_b_adr 08 GP08 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 38c9 38c9 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x38cb fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 38cb 0x38cb seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 37 GP08 typ_c_source 0 FIU_BUS typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL typ_rand d SET_PASS_PRIVACY_BIT val_a_adr 05 GP05 val_b_adr 20 VR02:00 val_frame 2 38ca 38ca fiu_mem_start a start_continue_if_false; Flow J cc=False 0x38ca ioc_load_wdr 0 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 38ca 0x38ca seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_b_adr 14 BOT - 1 typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl 6 INCREMENT_MAR typ_rand d SET_PASS_PRIVACY_BIT val_b_adr 14 BOT - 1 38cb 38cb fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x38d3 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 38d3 0x38d3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 2f VR02:0f val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 38cc 38cc fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x38cd fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 38cd 0x38cd typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 02 GP02 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 38cd 38cd ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_b_adr 03 GP03 typ_csa_cntl 0 LOAD_CONTROL_TOP 38ce 38ce fiu_mem_start 8 start_wr_if_false; Flow C 0x210 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 03 GP03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame f typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 38cf 38cf seq_b_timing 0 Early Condition; Flow J cc=True 0x38d4 seq_br_type 1 Branch True seq_branch_adr 38d4 0x38d4 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 2d VR04:0d val_c_adr 3c GP03 val_c_mux_sel 2 ALU val_frame 4 38d0 38d0 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x38cd ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 38cd 0x38cd seq_cond_sel 67 REFRESH_MACRO_EVENT typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 0 PASS_A 38d1 38d1 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 38d2 38d2 fiu_mem_start 2 start-rd; Flow J 0x38cd ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 38cd 0x38cd seq_en_micro 0 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 03 GP03 val_alu_func 0 PASS_A 38d3 38d3 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 14 fiu_op_sel 3 insert fiu_rdata_src 0 rotator 38d4 38d4 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM seq_random 2e Load_save_offset+Load_control_pred+? typ_a_adr 03 GP03 typ_alu_func 1 A_PLUS_B typ_b_adr 21 TR10:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 10 38d5 38d5 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 2f TR05:0f typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_csa_cntl 2 PUSH_CSA typ_frame 5 typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 38d6 38d6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_int_reads 0 TYP VAL BUS seq_lex_adr 1 seq_random 49 Load_current_lex+? typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_c_adr 2e TOP + 1 typ_c_lit 0 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 38d7 38d7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 59 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 7 CONTROL PRED seq_random 33 ? typ_a_adr 22 TR02:02 typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2f TOP val_c_mux_sel 2 ALU 38d8 38d8 fiu_len_fill_lit 4b zero-fill 0xb; Flow J 0x38d9 fiu_offs_lit 54 fiu_op_sel 3 insert ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 38e0 0x38e0 seq_int_reads 0 TYP VAL BUS seq_random 31 ? typ_b_adr 03 GP03 val_a_adr 21 VR02:01 val_alu_func 0 PASS_A val_c_adr 1d VR02:02 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 2 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 38d9 38d9 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_offs_lit 39 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 seq_random 39 ? typ_a_adr 22 TR02:02 typ_alu_func 1b A_OR_B typ_b_adr 30 TR02:10 typ_c_adr 1d TR02:02 typ_c_mux_sel 0 ALU typ_frame 2 val_b_adr 22 VR02:02 val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 2 38da 38da fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=False 0x38dd fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_br_type 0 Branch False seq_branch_adr 38dd 0x38dd seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 22 TR02:02 typ_alu_func 0 PASS_A typ_b_adr 20 TR02:00 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 2 val_a_adr 20 VR02:00 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 2e TOP + 1 val_frame 2 38db 38db fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 01 GP01 38dc 38dc fiu_mem_start 2 start-rd; Flow J 0x2aef ioc_adrbs 2 typ ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2aef 0x2aef typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 38dd 38dd fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val val_a_adr 01 GP01 38de 38de ioc_tvbs 1 typ+fiu val_a_adr 2e VR02:0e val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 10 VR02:0f val_c_mux_sel 2 ALU val_frame 2 38df 38df fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x2aef fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 3 Unconditional Branch seq_branch_adr 2aef 0x2aef typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl c LOAD_MAR_QUEUE typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 05 GP05 val_alu_func 0 PASS_A val_c_adr 1f TOP - 0x0 val_c_mux_sel 2 ALU val_frame 2 38e0 38e0 ioc_adrbs 1 val ; Flow C cc=True 0x38e7 ioc_fiubs 2 typ seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 38e7 0x38e7 typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_rand a PASS_B_HIGH 38e1 38e1 seq_br_type 3 Unconditional Branch; Flow J 0x38e5 seq_branch_adr 38e5 0x38e5 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2f TR12:0f typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1e A_AND_B val_b_adr 36 VR07:16 val_frame 7 38e2 38e2 typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 38e3 38e3 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=True 0x32de seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32de 0x32de seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_int_reads 0 TYP VAL BUS seq_random 0c Load_ibuff+? typ_a_adr 08 GP08 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 38e4 38e4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 38e5 38e5 seq_br_type 7 Unconditional Call; Flow C 0x3914 seq_branch_adr 3914 0x3914 seq_en_micro 0 38e6 38e6 fiu_mem_start 2 start-rd; Flow J 0x38e2 ioc_adrbs 3 seq seq_br_type 3 Unconditional Branch seq_branch_adr 38e2 0x38e2 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 38e7 ; -------------------------------------------------------------------------------------- 38e7 ; Comes from: 38e7 ; 38e0 C True from color 0x38e0 38e7 ; -------------------------------------------------------------------------------------- 38e7 38e7 fiu_mem_start 2 start-rd; Flow C 0x332e fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 38e8 38e8 seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 38e9 38e9 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x38ed ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 38ed 0x38ed seq_cond_sel 56 SEQ.LATCHED_COND typ_a_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 38ea 38ea fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_mdr 1 hold_mdr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 2 typ typ_a_adr 24 TR05:04 typ_frame 5 38eb 38eb fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 38ec 38ec ioc_load_wdr 0 ; Flow R ioc_tvbs 3 fiu+fiu seq_br_type a Unconditional Return 38ed 38ed fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38ee 38ee <default> 38ef 38ef fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x38f8 fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 38f8 0x38f8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 38f0 38f0 seq_br_type 7 Unconditional Call; Flow C 0x6cf seq_branch_adr 06cf 0x06cf 38f1 38f1 fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x38f7 ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 38f7 0x38f7 seq_cond_sel 56 SEQ.LATCHED_COND typ_a_adr 20 TR02:00 typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 38f2 38f2 <default> 38f3 38f3 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_a_adr 36 TR13:16 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 38f4 38f4 ioc_load_wdr 0 typ_b_adr 02 GP02 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 38f5 38f5 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 38f6 0x38f6 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 39 VR02:19 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 38f6 38f6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 38f7 38f7 fiu_mem_start 2 start-rd; Flow J 0x38ee ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 38ee 0x38ee typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 38f8 38f8 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 13 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 38f9 38f9 seq_b_timing 0 Early Condition; Flow J cc=True 0x38fa ; Flow J cc=#0x0 0x38fa seq_br_type b Case False seq_branch_adr 38fa 0x38fa seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 02 GP02 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 2 38fa 38fa seq_br_type 3 Unconditional Branch; Flow J 0x38ff seq_branch_adr 38ff 0x38ff 38fb 38fb seq_br_type 3 Unconditional Branch; Flow J 0x3904 seq_branch_adr 3904 0x3904 38fc 38fc seq_br_type 3 Unconditional Branch; Flow J 0x3908 seq_branch_adr 3908 0x3908 38fd 38fd seq_br_type 3 Unconditional Branch; Flow J 0x38fe seq_branch_adr 38fe 0x38fe 38fe 38fe ioc_adrbs 2 typ ; Flow C 0x3ba5 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3ba5 0x3ba5 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 38ff 38ff ioc_adrbs 1 val ; Flow C 0x6cf seq_br_type 7 Unconditional Call seq_branch_adr 06cf 0x06cf typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 01 GP01 val_rand a PASS_B_HIGH 3900 3900 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_a_adr 02 GP02 typ_alu_func 1b A_OR_B typ_b_adr 37 TR13:17 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 13 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3901 3901 ioc_load_wdr 0 typ_b_adr 02 GP02 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 3902 3902 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3903 3903 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 03 GP03 typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_b_adr 03 GP03 3904 3904 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 01 GP01 val_b_adr 39 VR02:19 val_frame 2 3905 3905 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu 3906 3906 fiu_mem_start 3 start-wr; Flow C 0x3b7e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b7e 0x3b7e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3907 3907 fiu_mem_start 2 start-rd; Flow J 0x38ee ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 38ee 0x38ee typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3908 3908 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 11 val_rand a PASS_B_HIGH 3909 3909 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 390a 390a fiu_mem_start 3 start-wr; Flow C 0x3b8d ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b8d 0x3b8d seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 390b 390b fiu_mem_start 2 start-rd; Flow J 0x38ee ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 38ee 0x38ee typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 390c 390c seq_br_type 7 Unconditional Call; Flow C 0x3912 seq_branch_adr 3912 0x3912 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 390d 390d seq_br_type 3 Unconditional Branch; Flow J 0x37e4 seq_branch_adr 37e4 MACRO_Execute_Entry,Rendezvous 390e 390e seq_br_type 7 Unconditional Call; Flow C 0x3912 seq_branch_adr 3912 0x3912 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 390f 390f seq_br_type 3 Unconditional Branch; Flow J 0x37fa seq_branch_adr 37fa MACRO_Execute_Family,Rendezvous 3910 3910 seq_br_type 7 Unconditional Call; Flow C 0x3912 seq_branch_adr 3912 0x3912 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 37 TR02:17 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3911 3911 seq_br_type 3 Unconditional Branch; Flow J 0x380e seq_branch_adr 380e MACRO_Execute_Select,Rendezvous 3912 ; -------------------------------------------------------------------------------------- 3912 ; Comes from: 3912 ; 3910 C from color MACRO_Execute_Select,Rendezvous 3912 ; -------------------------------------------------------------------------------------- 3912 3912 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT 3913 3913 fiu_mem_start 3 start-wr; Flow J 0x3b7e fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 2 typ ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3b7e 0x3b7e seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 23 TR11:03 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 3914 ; -------------------------------------------------------------------------------------- 3914 ; Comes from: 3914 ; 37ee C from color 0x0000 3914 ; 3854 C from color 0x3833 3914 ; 385d C from color 0x0000 3914 ; 386b C from color 0x0000 3914 ; 3874 C from color 0x0000 3914 ; 3885 C from color 0x0000 3914 ; 38e5 C from color 0x38e0 3914 ; -------------------------------------------------------------------------------------- 3914 3914 ioc_adrbs 2 typ ; Flow C 0x3ba5 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3ba5 0x3ba5 seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3915 3915 seq_br_type a Unconditional Return; Flow R seq_cond_sel 45 SEQ.saved_latched_cond seq_latch 1 typ_alu_func 1d A_AND_NOT_B typ_b_adr 37 TR02:17 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 3916 3916 seq_br_type 7 Unconditional Call; Flow C 0x33af seq_branch_adr 33af 0x33af 3917 3917 ioc_adrbs 1 val ; Flow C 0x3412 seq_br_type 7 Unconditional Call seq_branch_adr 3412 0x3412 typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 09 GP09 3918 3918 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 31 VR02:11 val_frame 2 3919 3919 ioc_tvbs 2 fiu+val; Flow C 0x33a3 seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 391a 391a fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 08 GP08 val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 391b 391b fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val ioc_fiubs 2 typ seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_latch 1 typ_a_adr 3c TR12:1c typ_b_adr 07 GP07 typ_frame 12 val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 08 GP08 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 391c 391c fiu_load_var 1 hold_var fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 07 GP07 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 391d 391d fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3921 fiu_load_mdr 1 hold_mdr fiu_mem_start 3 start-wr fiu_offs_lit 59 fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3921 0x3921 typ_a_adr 30 TR1b:10 typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1b typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 39 VR02:19 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 2 val_rand 9 PASS_A_HIGH 391e 391e fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 31 TR1b:11 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 31 VR1b:11 val_b_adr 30 VR1b:10 val_frame 1b 391f 391f fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 33 TR1b:13 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 22 VR11:02 val_frame 11 3920 3920 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3924 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3924 0x3924 typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 08 GP08 val_b_adr 07 GP07 3921 3921 fiu_len_fill_lit 4b zero-fill 0xb fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 54 fiu_op_sel 3 insert fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_load_wdr 0 typ_a_adr 32 TR1b:12 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 31 VR1b:11 val_b_adr 30 VR1b:10 val_frame 1b 3922 3922 fiu_len_fill_lit 3f sign-fill 0x3f fiu_mem_start 4 continue fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 typ_a_adr 34 TR1b:14 typ_alu_func 0 PASS_A typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR typ_rand c WRITE_OUTER_FRAME val_a_adr 01 GP01 val_alu_func 1e A_AND_B val_b_adr 22 VR11:02 val_frame 11 3923 3923 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3924 fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 seq_br_type 3 Unconditional Branch seq_branch_adr 3924 0x3924 typ_b_adr 03 GP03 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 08 GP08 val_b_adr 07 GP07 3924 3924 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_mem_start 4 continue fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 07 GP07 typ_b_adr 35 TR1b:15 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 35 VR1b:15 val_frame 1b 3925 3925 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 08 GP08 typ_b_adr 36 TR1b:16 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 36 VR1b:16 val_frame 1b 3926 3926 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 38 TR1b:18 typ_b_adr 37 TR1b:17 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 37 VR1b:17 val_frame 1b 3927 3927 fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_mar_cntl 6 INCREMENT_MAR val_a_adr 04 GP04 val_alu_func 1e A_AND_B val_b_adr 31 VR07:11 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 7 3928 3928 ioc_load_wdr 0 ; Flow C cc=True 0x393e seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 393e 0x393e typ_b_adr 39 TR1b:19 typ_frame 1b val_b_adr 39 VR1b:19 val_frame 1b 3929 3929 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 392a 392a fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 3d TR1b:1d typ_b_adr 04 GP04 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR val_b_adr 04 GP04 392b 392b fiu_mem_start 4 continue ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_cond_sel 38 TYP.D_BUS_BIT_35 (med_late) seq_latch 1 typ_b_adr 08 GP08 typ_mar_cntl 6 INCREMENT_MAR val_b_adr 3d VR1b:1d val_frame 1b 392c 392c ioc_load_wdr 0 ; Flow C cc=True 0x3940 seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 3940 0x3940 typ_b_adr 3e TR1b:1e typ_frame 1b val_b_adr 3e VR1b:1e val_frame 1b 392d 392d ioc_adrbs 1 val ; Flow C 0x3b17 ioc_fiubs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b17 0x3b17 typ_alu_func 1a PASS_B typ_b_adr 33 TR05:13 typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_alu_func 0 PASS_A 392e 392e fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x3937 fiu_load_var 1 hold_var fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 1 val seq_br_type 1 Branch True seq_branch_adr 3937 0x3937 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 34 TR07:14 typ_alu_func 1e A_AND_B typ_b_adr 07 GP07 typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS typ_frame 7 val_a_adr 08 GP08 392f 392f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_offs_lit 31 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 14 ZEROS 3930 3930 ioc_tvbs 3 fiu+fiu typ_a_adr 04 GP04 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3931 3931 ioc_adrbs 2 typ seq_int_reads 0 TYP VAL BUS seq_random 0e Load_control_top+? typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_csa_cntl 0 LOAD_CONTROL_TOP val_rand 2 DEC_LOOP_COUNTER 3932 3932 fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 3933 3933 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val typ_a_adr 01 GP01 typ_alu_func 7 INC_A typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 22 VR06:02 val_frame 6 3934 3934 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x32d7 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 20 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d7 0x32d7 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x0f) Discrete_Ref Float_Ref Access_Ref Task_Ref Subvector_Var Subarray_Var Heap_Access_Ref Record_Var Variant_Record_Var Vector_Var Matrix_Var Array_Var typ_a_adr 02 GP02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame f typ_mar_cntl e LOAD_MAR_CONTROL 3935 3935 ioc_load_wdr 0 ; Flow C cc=True 0x393d ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 393d 0x393d seq_cond_sel 67 REFRESH_MACRO_EVENT typ_a_adr 02 GP02 typ_alu_func 7 INC_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP 3936 3936 fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x3933 ioc_adrbs 2 typ seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3933 0x3933 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 01 GP01 typ_alu_func 0 PASS_A typ_mar_cntl e LOAD_MAR_CONTROL val_rand 2 DEC_LOOP_COUNTER 3937 3937 fiu_len_fill_lit 4f zero-fill 0xf; Flow R cc=False fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 70 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 3938 0x3938 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_random 04 Load_save_offset+? typ_a_adr 27 TR02:07 typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_b_adr 21 VR06:01 val_frame 6 3938 3938 fiu_mem_start 2 start-rd ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_int_reads 0 TYP VAL BUS seq_random 11 Load_current_instr+? typ_a_adr 04 GP04 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_frame 5 val_rand a PASS_B_HIGH 3939 3939 seq_int_reads 0 TYP VAL BUS seq_random 10 Load_break_mask+? val_b_adr 38 VR09:18 val_frame 9 393a 393a fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU val_a_adr 37 VR09:17 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 9 393b 393b ioc_load_wdr 0 typ_b_adr 04 GP04 val_b_adr 04 GP04 393c 393c fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 393d ; -------------------------------------------------------------------------------------- 393d ; Comes from: 393d ; 3935 C True from color 0x0b32 393d ; -------------------------------------------------------------------------------------- 393d 393d seq_br_type 3 Unconditional Branch; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 393e ; -------------------------------------------------------------------------------------- 393e ; Comes from: 393e ; 3928 C True from color 0x0b32 393e ; -------------------------------------------------------------------------------------- 393e 393e val_a_adr 04 GP04 val_alu_func 1d A_AND_NOT_B val_b_adr 2d VR1b:0d val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 1b 393f 393f seq_br_type a Unconditional Return; Flow R val_a_adr 04 GP04 val_alu_func 1b A_OR_B val_b_adr 29 VR05:09 val_c_adr 3b GP04 val_c_mux_sel 2 ALU val_frame 5 3940 ; -------------------------------------------------------------------------------------- 3940 ; Comes from: 3940 ; 392c C True from color 0x0b32 3940 ; -------------------------------------------------------------------------------------- 3940 3940 fiu_mem_start 3 start-wr ioc_adrbs 1 val ioc_fiubs 1 val typ_a_adr 33 TR05:13 typ_alu_func 0 PASS_A typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME val_alu_func 1a PASS_B val_b_adr 39 VR05:19 val_frame 5 val_rand 9 PASS_A_HIGH 3941 3941 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_offs_lit 30 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_load_wdr 0 typ_a_adr 07 GP07 typ_b_adr 06 GP06 val_b_adr 06 GP06 3942 3942 fiu_len_fill_lit 4f zero-fill 0xf fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 14 ZEROS typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 3b VR05:1b val_frame 5 val_rand 9 PASS_A_HIGH 3943 3943 ioc_tvbs 1 typ+fiu seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 25 VR09:05 val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 9 3944 3944 fiu_mem_start 3 start-wr ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 3945 3945 ioc_load_wdr 0 ; Flow R cc=False ioc_tvbs 1 typ+fiu seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3946 0x3946 typ_b_adr 04 GP04 typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3946 3946 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3947 3947 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_a_adr 27 TR02:07 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3948 3948 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return typ_b_adr 04 GP04 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 04 GP04 3949 ; -------------------------------------------------------------------------------------- 3949 ; Comes from: 3949 ; 0218 C from color MACRO_Action_Accept_Activation 3949 ; 2ee5 C from color 0x2edf 3949 ; 2ee6 C from color 0x2edf 3949 ; -------------------------------------------------------------------------------------- 3949 3949 fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x394a fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3952 0x3952 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 3a VR02:1a val_frame 2 394a 394a ioc_tvbs 2 fiu+val; Flow C 0x33a3 seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 seq_random 02 ? typ_a_adr 35 TR02:15 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 394b 394b fiu_mem_start 2 start-rd; Flow C 0x34f0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f0 0x34f0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 394c 394c seq_b_timing 1 Latch Condition; Flow J cc=True 0x394f seq_br_type 1 Branch True seq_branch_adr 394f 0x394f typ_a_adr 30 TR08:10 typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 8 394d 394d seq_br_type 5 Call True; Flow C cc=True 0x69b seq_branch_adr 069b 0x069b seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 04 GP04 typ_alu_func 1e A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 394e 394e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 394f 394f fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3950 3950 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3b18 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3b18 0x3b18 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3951 3951 seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 3952 3952 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 2 typ seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_a_adr 08 GP08 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3953 3953 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32d4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d4 0x32d4 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 31 VR02:11 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3954 3954 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x2f) Task_Ref typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame f typ_mar_cntl d LOAD_MAR_TYPE val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3955 3955 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3963 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3963 0x3963 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 14 ZEROS val_a_adr 08 GP08 val_alu_func 1e A_AND_B val_b_adr 30 VR02:10 val_frame 2 3956 3956 fiu_len_fill_lit 47 zero-fill 0x7; Flow J cc=True 0x395a fiu_offs_lit 24 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 395a 0x395a seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 34 TR07:14 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 7 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3957 3957 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 02 GP02 3958 3958 ioc_adrbs 2 typ ioc_tvbs 2 fiu+val typ_a_adr 02 GP02 typ_alu_func 6 A_MINUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_csa_cntl 1 START_POP_DOWN 3959 3959 ioc_fiubs 2 typ seq_en_micro 0 seq_random 0f Load_control_top+? typ_a_adr 02 GP02 typ_csa_cntl 7 FINISH_POP_DOWN 395a 395a fiu_mem_start 2 start-rd; Flow R cc=False ioc_adrbs 3 seq seq_b_timing 3 Late Condition, Hint False seq_br_type d Dispatch False seq_branch_adr 395b 0x395b seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_random 04 Load_save_offset+? typ_alu_func 1a PASS_B typ_b_adr 01 GP01 typ_c_adr 2e TOP + 1 typ_c_mux_sel 0 ALU typ_csa_cntl 2 PUSH_CSA typ_frame 1c typ_mar_cntl e LOAD_MAR_CONTROL val_alu_func 1a PASS_B val_b_adr 01 GP01 val_c_adr 2e TOP + 1 val_c_mux_sel 2 ALU 395b 395b fiu_len_fill_lit 3f sign-fill 0x3f fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 395c 395c fiu_fill_mode_src 0 ; Flow J cc=False 0x395e fiu_length_src 0 length_register fiu_load_mdr 1 hold_mdr fiu_mem_start a start_continue_if_false fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 395e 0x395e seq_cond_sel 65 CROSS_WORD_FIELD~ typ_mar_cntl 6 INCREMENT_MAR val_a_adr 10 TOP 395d 395d fiu_fill_mode_src 0 ; Flow J 0x3961 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3961 0x3961 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A 395e 395e fiu_fill_mode_src 0 ; Flow C cc=False 0x30ab fiu_length_src 0 length_register fiu_load_var 1 hold_var fiu_offset_src 0 offset_register fiu_op_sel 2 insert first fiu_tivi_src 1 tar_val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 30ab 0x30ab seq_cond_sel 6f MAR_WORD_EQUAL_ZERO~ 395f 395f fiu_fill_mode_src 0 fiu_length_src 0 length_register fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offset_src 0 offset_register fiu_op_sel 1 insert last fiu_tivi_src 9 type_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3d GP02 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 03 GP03 val_alu_func 0 PASS_A val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3960 3960 fiu_load_var 1 hold_var; Flow J 0x3961 fiu_mem_start 4 continue fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3961 0x3961 typ_b_adr 02 GP02 typ_mar_cntl 6 INCREMENT_MAR val_a_adr 02 GP02 3961 3961 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu typ_csa_cntl 3 POP_CSA 3962 3962 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3963 3963 seq_br_type 7 Unconditional Call; Flow C 0x3968 seq_branch_adr 3968 0x3968 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3964 3964 fiu_mem_start 2 start-rd; Flow C 0x34dc ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 34dc 0x34dc typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3965 3965 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3966 3966 fiu_mem_start 3 start-wr; Flow J 0x3967 ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 329a 0x329a typ_a_adr 30 TR08:10 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU typ_frame 8 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3967 3967 ioc_load_wdr 0 ; Flow J 0x6bd seq_br_type 3 Unconditional Branch seq_branch_adr 06bd 0x06bd typ_b_adr 02 GP02 val_b_adr 02 GP02 3968 ; -------------------------------------------------------------------------------------- 3968 ; Comes from: 3968 ; 3963 C from color 0x062d 3968 ; -------------------------------------------------------------------------------------- 3968 3968 fiu_mem_start 2 start-rd; Flow C 0x339b ioc_adrbs 3 seq seq_br_type 7 Unconditional Call seq_branch_adr 339b 0x339b seq_int_reads 5 RESOLVE RAM seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 3969 3969 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 396a 396a ioc_load_wdr 0 ; Flow J cc=True 0x3b1b ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3b1b 0x3b1b seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_frame 5 396b 396b fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 38 TR05:18 typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 396c 396c fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 4 continue fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 39 TR1b:19 typ_frame 1b typ_mar_cntl 6 INCREMENT_MAR 396d 396d fiu_len_fill_lit 5f zero-fill 0x1f fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_rand 1 INC_LOOP_COUNTER val_c_adr 3b GP04 val_c_source 0 FIU_BUS 396e 396e fiu_load_var 1 hold_var; Flow C 0x210 fiu_mem_start 3 start-wr fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 10 VAL.ALU_32_ZERO(late) typ_b_adr 16 CSA/VAL_BUS typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 04 GP04 396f 396f ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu 3970 3970 seq_br_type a Unconditional Return; Flow R 3971 ; -------------------------------------------------------------------------------------- 3971 ; Comes from: 3971 ; 0931 C from color 0x092f 3971 ; -------------------------------------------------------------------------------------- 3971 3971 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR05:01 val_frame 5 3972 3972 ioc_tvbs 2 fiu+val; Flow C 0x33a3 seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3973 3973 fiu_mem_start 2 start-rd; Flow C 0x34f0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f0 0x34f0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3974 3974 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3977 ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3977 0x3977 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3975 3975 <default> 3976 3976 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3978 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3978 0x3978 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 3977 3977 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 3978 3978 seq_br_type 7 Unconditional Call; Flow C 0x3b17 seq_branch_adr 3b17 0x3b17 3979 3979 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR07:0e val_frame 7 val_rand 9 PASS_A_HIGH 397a 397a fiu_load_tar 1 hold_tar; Flow C cc=True 0x32d4 fiu_tivi_src 8 type_var ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d4 0x32d4 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_b_adr 08 GP08 val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 397b 397b fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy typ_a_adr 39 TR1b:19 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1b val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 397c 397c ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_b_adr 01 GP01 typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 01 GP01 397d 397d seq_br_type 5 Call True; Flow C cc=True 0x69b seq_branch_adr 069b 0x069b seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 20 TR02:00 typ_frame 2 397e 397e seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 397f 397f fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 3e VR03:1e val_frame 3 3980 3980 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x34f0 fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator ioc_adrbs 1 val ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 34f0 0x34f0 seq_random 02 ? typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3981 3981 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x398a ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 398a 0x398a typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3982 3982 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 2 typ typ_a_adr 39 TR1b:19 typ_b_adr 08 GP08 typ_frame 1b 3983 3983 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x398a fiu_load_var 1 hold_var fiu_mem_start 8 start_wr_if_false fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 398a 0x398a seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3984 3984 ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_frame 1 3985 3985 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR07:0e val_frame 7 val_rand 9 PASS_A_HIGH 3986 3986 ioc_tvbs 1 typ+fiu; Flow C cc=True 0x32d4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32d4 0x32d4 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3987 3987 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3988 3988 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_load_wdr 0 ioc_tvbs 2 fiu+val typ_b_adr 16 CSA/VAL_BUS typ_frame 19 typ_rand 1 INC_LOOP_COUNTER 3989 3989 ioc_tvbs 2 fiu+val; Flow J 0x6b7 seq_br_type 3 Unconditional Branch seq_branch_adr 06b7 0x06b7 typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 398a 398a fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_int_reads 6 CONTROL TOP typ_a_adr 37 TR05:17 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 398b 398b fiu_mem_start 3 start-wr; Flow C cc=False 0x20d ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 398c 398c ioc_load_wdr 0 ; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_c_lit 2 typ_frame 1 val_b_adr 0f GP0f 398d ; -------------------------------------------------------------------------------------- 398d ; Comes from: 398d ; 022f C True from color MACRO_Action_Signal_Activated 398d ; 2eeb C from color 0x0000 398d ; 2eec C from color 0x0000 398d ; -------------------------------------------------------------------------------------- 398d 398d fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x39a2 ioc_adrbs 2 typ ioc_fiubs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 39a2 0x39a2 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_mar_cntl d LOAD_MAR_TYPE val_a_adr 09 GP09 398e 398e seq_br_type 0 Branch False; Flow J cc=False 0x399b seq_branch_adr 399b 0x399b seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 398f 398f fiu_load_tar 1 hold_tar; Flow J cc=False 0x3b1b fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3b1b 0x3b1b seq_cond_sel 07 VAL.ALU_32_CO(late) val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 2 3990 3990 ioc_load_wdr 0 ; Flow C cc=True 0x39bf ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 39bf 0x39bf seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 08 GP08 typ_b_adr 04 GP04 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 02 GP02 val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 5 3991 3991 fiu_mem_start 2 start-rd; Flow C 0x34f0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f0 0x34f0 seq_random 02 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3992 3992 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x399d ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 399d 0x399d typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3993 3993 seq_br_type 2 Push (branch address); Flow J 0x3994 seq_branch_adr 3995 0x3995 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_latch 1 val_a_adr 08 GP08 val_alu_func 1e A_AND_B val_b_adr 30 VR02:10 val_frame 2 3994 3994 fiu_len_fill_lit 44 zero-fill 0x4; Flow R cc=True ; Flow J cc=False 0x3996 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 8 Return True seq_branch_adr 3996 0x3996 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3995 3995 fiu_mem_start 2 start-rd; Flow R cc=True ; Flow J cc=False 0x62f ioc_adrbs 3 seq seq_b_timing 1 Latch Condition seq_br_type c Dispatch True seq_branch_adr 062f 0x062f seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 3996 3996 fiu_len_fill_lit 43 zero-fill 0x3; Flow J cc=True 0x3997 ; Flow C cc=#0x0 0x39a3 fiu_load_var 1 hold_var fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 39a3 0x39a3 seq_cond_sel 5a (VAL.ALU_A_LT_OR_LE_B(late)) nand (TYP.ALU_A_GT_OR_GE_B(late)) seq_en_micro 0 typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 2e TR11:0e typ_c_adr 3f GP00 typ_frame 11 val_a_adr 01 GP01 val_alu_func 5 DEC_A_MINUS_B val_b_adr 22 VR05:02 val_c_adr 3f GP00 val_frame 5 3997 3997 fiu_len_fill_lit 5f zero-fill 0x1f; Flow R cc=True fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type 8 Return True seq_branch_adr 3998 0x3998 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3998 3998 ioc_load_wdr 0 ; Flow C cc=False 0x32d4 ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 32d4 0x32d4 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 25 TR05:05 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_frame 5 3999 3999 fiu_mem_start 3 start-wr; Flow C 0x3b7e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b7e 0x3b7e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 399a 399a seq_br_type 3 Unconditional Branch; Flow J 0x3991 seq_branch_adr 3991 0x3991 399b 399b seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 399c 399c seq_br_type 1 Branch True; Flow J cc=True 0x398d seq_branch_adr 398d 0x398d seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 399d 399d fiu_mem_start 2 start-rd ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 39 TR05:19 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 5 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 399e 399e seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x39a1 seq_br_type 1 Branch True seq_branch_adr 39a1 0x39a1 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 04 GP04 typ_b_adr 08 GP08 399f 399f fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 39a0 39a0 ioc_load_wdr 0 typ_b_adr 03 GP03 typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 03 GP03 39a1 39a1 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 39a2 39a2 fiu_mem_start 2 start-rd; Flow C 0x210 ioc_adrbs 3 seq seq_br_type c Dispatch True seq_branch_adr 0210 0x0210 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_random 04 Load_save_offset+? typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL 39a3 ; -------------------------------------------------------------------------------------- 39a3 ; Comes from: 39a3 ; 3996 C #0x0 from color 0x03fa 39a3 ; -------------------------------------------------------------------------------------- 39a3 39a3 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 39a4 39a4 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 39a5 39a5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 39a6 39a6 fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=True ; Flow J cc=False 0x39a9 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 39a9 0x39a9 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 39a7 39a7 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ; Flow J cc=False 0x39b3 ioc_adrbs 1 val seq_br_type 8 Return True seq_branch_adr 39b3 0x39b3 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 39a8 39a8 fiu_mem_start 6 start_rd_if_false; Flow R cc=True ; Flow J cc=False 0x39b6 ioc_adrbs 1 val seq_br_type 8 Return True seq_branch_adr 39b6 0x39b6 seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 39a9 39a9 fiu_mem_start 8 start_wr_if_false; Flow J cc=True 0x39ae ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 39ae 0x39ae typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39aa 39aa ioc_load_wdr 0 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 39ab 39ab ioc_tvbs 2 fiu+val typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 39ac 39ac seq_br_type 7 Unconditional Call; Flow C 0x6b7 seq_branch_adr 06b7 0x06b7 39ad 39ad fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 39ae 39ae seq_br_type 7 Unconditional Call; Flow C 0x33a3 seq_branch_adr 33a3 0x33a3 seq_en_micro 0 39af 39af ioc_adrbs 3 seq ; Flow C 0x6b4 seq_br_type 7 Unconditional Call seq_branch_adr 06b4 0x06b4 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 39b0 39b0 fiu_mem_start 2 start-rd; Flow C 0x33c4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 33c4 0x33c4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39b1 39b1 seq_b_timing 1 Latch Condition; Flow C cc=True 0x33ec seq_br_type 5 Call True seq_branch_adr 33ec 0x33ec 39b2 39b2 seq_br_type 7 Unconditional Call; Flow C 0x329a seq_branch_adr 329a 0x329a typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 39b3 39b3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x39b9 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 39b9 0x39b9 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 39b4 39b4 ioc_load_wdr 0 ; Flow C 0x210 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A val_b_adr 01 GP01 39b5 39b5 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 39b6 39b6 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x39b9 fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 5 Call True seq_branch_adr 39b9 0x39b9 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_lit 2 typ_c_source 0 FIU_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 2 val_rand a PASS_B_HIGH 39b7 39b7 ioc_load_wdr 0 ; Flow J cc=True 0x39bc ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 39bc 0x39bc seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 01 GP01 val_rand 9 PASS_A_HIGH 39b8 39b8 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_random 04 Load_save_offset+? typ_mar_cntl e LOAD_MAR_CONTROL 39b9 ; -------------------------------------------------------------------------------------- 39b9 ; Comes from: 39b9 ; 39b3 C True from color 0x39a6 39b9 ; 39b6 C True from color 0x39a8 39b9 ; -------------------------------------------------------------------------------------- 39b9 39b9 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_latch 1 val_a_adr 08 GP08 val_alu_func 19 X_XOR_B val_b_adr 2d VR04:0d val_frame 4 39ba 39ba fiu_mem_start 7 start_wr_if_true; Flow R cc=True seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 39bb 0x39bb 39bb 39bb fiu_len_fill_lit 40 zero-fill 0x0; Flow R fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 20 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val seq_br_type a Unconditional Return val_b_adr 31 VR02:11 val_frame 2 39bc 39bc fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x39bd fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 069b 0x069b typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39bd 39bd ioc_load_wdr 0 ; Flow C 0x210 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 0 PASS_A 39be 39be ioc_tvbs 2 fiu+val; Flow J 0x6b7 seq_br_type 3 Unconditional Branch seq_branch_adr 06b7 0x06b7 typ_a_adr 30 TR05:10 typ_alu_func 1 A_PLUS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU typ_frame 5 39bf ; -------------------------------------------------------------------------------------- 39bf ; Comes from: 39bf ; 3990 C True from color 0x03fa 39bf ; -------------------------------------------------------------------------------------- 39bf 39bf seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 39c0 0x39c0 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 02 GP02 val_alu_func 6 A_MINUS_B val_b_adr 31 VR02:11 val_frame 2 39c0 39c0 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 39c1 39c1 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 39c2 39c2 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3c GP03 val_c_mux_sel 2 ALU 39c3 39c3 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x39ce seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 39ce 0x39ce seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 39c4 39c4 ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 39c5 0x39c5 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 03 GP03 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 24 VR05:04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 39c5 39c5 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 39c6 39c6 ioc_load_wdr 0 typ_b_adr 03 GP03 val_b_adr 03 GP03 39c7 39c7 fiu_mem_start 2 start-rd; Flow C 0x34de ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 34de 0x34de typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 2b TR06:0b typ_frame 6 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 39c8 39c8 seq_br_type 7 Unconditional Call; Flow C 0x6b4 seq_branch_adr 06b4 0x06b4 39c9 39c9 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x39d0 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 39d0 0x39d0 typ_a_adr 08 GP08 val_b_adr 39 VR02:19 val_frame 2 39ca 39ca fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 39cb 39cb fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 39cc 39cc fiu_len_fill_lit 44 zero-fill 0x4 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 3c GP03 val_c_source 0 FIU_BUS 39cd 39cd ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False ; Flow J cc=True 0x39c9 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 39c9 0x39c9 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 23 VR05:03 val_frame 5 39ce 39ce fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x39d0 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 39d0 0x39d0 typ_a_adr 08 GP08 val_b_adr 39 VR02:19 val_frame 2 39cf 39cf seq_br_type 3 Unconditional Branch; Flow J 0x39c0 seq_branch_adr 39c0 0x39c0 39d0 ; -------------------------------------------------------------------------------------- 39d0 ; Comes from: 39d0 ; 39c9 C from color 0x39bf 39d0 ; 39ce C from color 0x39bf 39d0 ; -------------------------------------------------------------------------------------- 39d0 39d0 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 39d1 39d1 fiu_mem_start 3 start-wr; Flow J 0x3b7e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b7e 0x3b7e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 39d2 39d2 fiu_mem_start 2 start-rd; Flow J cc=False 0x39d6 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 39d6 0x39d6 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_mar_cntl d LOAD_MAR_TYPE 39d3 39d3 <default> 39d4 39d4 fiu_load_tar 1 hold_tar; Flow J cc=True 0x39f5 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 39f5 0x39f5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 39d5 39d5 seq_br_type 3 Unconditional Branch; Flow J 0x39f1 seq_branch_adr 39f1 0x39f1 seq_en_micro 0 39d6 39d6 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39d7 39d7 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 24 VR05:04 val_frame 5 39d8 39d8 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x33a3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 39d9 39d9 fiu_mem_start 2 start-rd; Flow J cc=False 0x39e0 ioc_adrbs 2 typ seq_br_type 0 Branch False seq_branch_adr 39e0 0x39e0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_alu_func 1a PASS_B typ_b_adr 08 GP08 typ_mar_cntl d LOAD_MAR_TYPE 39da 39da seq_br_type 2 Push (branch address); Flow J 0x39db seq_branch_adr 39e2 0x39e2 39db 39db fiu_load_tar 1 hold_tar; Flow J cc=True 0x39f5 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 39f5 0x39f5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 39dc 39dc seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39dd 39dd seq_br_type 1 Branch True; Flow J cc=True 0x39f3 seq_branch_adr 39f3 0x39f3 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39de 39de fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_random 06 Pop_stack+? typ_a_adr 20 TR02:00 typ_frame 2 39df 39df ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 39e0 39e0 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 20 TR02:00 typ_frame 2 39e1 39e1 ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 39e2 39e2 fiu_len_fill_lit 41 zero-fill 0x1; Flow C cc=False 0x68d fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 068d 0x068d seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_a_adr 20 TR02:00 typ_b_adr 20 TR02:00 typ_frame 2 39e3 39e3 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 08 GP08 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 39e4 39e4 ioc_tvbs c mem+mem+csa+dummy; Flow C cc=False 0x68d seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 068d 0x068d seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER 39e5 39e5 ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 00 VAL.ALU_ZERO(late) typ_a_adr 34 TR02:14 typ_alu_func 1 A_PLUS_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 2 39e6 39e6 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR11:01 val_frame 11 39e7 39e7 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x33a3 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 39e8 39e8 fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 39e9 39e9 seq_br_type 2 Push (branch address); Flow J 0x39ea seq_branch_adr 39ec 0x39ec 39ea 39ea fiu_load_tar 1 hold_tar; Flow J cc=True 0x39f5 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 39f5 0x39f5 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 39eb 39eb seq_br_type 3 Unconditional Branch; Flow J 0x39f1 seq_branch_adr 39f1 0x39f1 seq_en_micro 0 39ec 39ec seq_br_type 1 Branch True; Flow J cc=True 0x39ee seq_branch_adr 39ee 0x39ee seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 37 TR02:17 typ_alu_func 1e A_AND_B typ_b_adr 20 TR02:00 typ_frame 2 39ed 39ed ioc_adrbs 2 typ ; Flow C 0x3ba5 ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3ba5 0x3ba5 seq_int_reads 6 CONTROL TOP typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 39ee 39ee fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 39ef 39ef fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_a_adr 35 TR12:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_frame 12 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_mux_sel 2 ALU 39f0 39f0 ioc_load_wdr 0 ; Flow C 0x68d seq_br_type 7 Unconditional Call seq_branch_adr 068d 0x068d typ_b_adr 05 GP05 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 05 GP05 39f1 39f1 fiu_tivi_src c mar_0xc; Flow C 0x34cd ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_rand a PASS_B_HIGH 39f2 39f2 seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 39f3 39f3 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 39f4 39f4 fiu_load_tar 1 hold_tar; Flow J 0x39f5 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 39f5 0x39f5 val_a_adr 30 VR02:10 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 2 39f5 39f5 ioc_load_wdr 0 ; Flow J cc=True 0x39f7 ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 39f7 0x39f7 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 06 GP06 val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_frame 5 39f6 39f6 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3b1a seq_br_type 9 Return False seq_branch_adr 3b1a 0x3b1a seq_cond_sel 00 VAL.ALU_ZERO(late) seq_random 02 ? val_a_adr 3e VR05:1e val_alu_func 19 X_XOR_B val_b_adr 06 GP06 val_frame 5 39f7 39f7 fiu_len_fill_lit 46 zero-fill 0x6 fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 39 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ typ_a_adr 2e TR02:0e typ_b_adr 08 GP08 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39f8 39f8 ioc_tvbs 2 fiu+val typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 39 GP06 typ_c_mux_sel 0 ALU 39f9 39f9 fiu_len_fill_lit 44 zero-fill 0x4 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS 39fa 39fa fiu_load_var 1 hold_var; Flow J cc=True 0x3a0b fiu_vmux_sel 1 fill value seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3a0b 0x3a0b seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 05 GP05 val_alu_func 19 X_XOR_B val_b_adr 2b VR05:0b val_frame 5 39fb 39fb seq_br_type 9 Return False; Flow R cc=False seq_branch_adr 39fc 0x39fc seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 35 TR08:15 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_frame 8 val_a_adr 23 VR05:03 val_alu_func 19 X_XOR_B val_b_adr 05 GP05 val_frame 5 39fc 39fc fiu_mem_start 2 start-rd; Flow C 0x34de ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34de 0x34de typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 30 VR11:10 val_frame 11 val_rand 9 PASS_A_HIGH 39fd 39fd fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 39fe 39fe fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 39ff 39ff fiu_tivi_src 1 tar_val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 31 GP0e val_c_source 0 FIU_BUS 3a00 3a00 fiu_load_var 1 hold_var; Flow J cc=False 0x3a02 fiu_mem_start 6 start_rd_if_false fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3a02 0x3a02 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_frame 5 val_rand 9 PASS_A_HIGH 3a01 3a01 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x3a0b seq_br_type 8 Return True seq_branch_adr 3a0b 0x3a0b seq_en_micro 0 3a02 3a02 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3a06 seq_br_type 1 Branch True seq_branch_adr 3a06 0x3a06 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 35 TR08:15 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 typ_frame 8 3a03 3a03 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3a04 0x3a04 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 3a04 3a04 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a05 3a05 ioc_load_wdr 0 ; Flow J 0x6b4 seq_br_type 3 Unconditional Branch seq_branch_adr 06b4 0x06b4 seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 3a06 3a06 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3a07 0x3a07 seq_cond_sel 19 TYP.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 06 GP06 typ_alu_func 19 X_XOR_B typ_b_adr 16 CSA/VAL_BUS 3a07 3a07 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3a0a seq_br_type 1 Branch True seq_branch_adr 3a0a 0x3a0a seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 3a08 3a08 fiu_mem_start 3 start-wr ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 21 TR01:01 typ_alu_func 1b A_OR_B typ_b_adr 0e GP0e typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a09 3a09 ioc_load_wdr 0 ; Flow J 0x6b4 seq_br_type 3 Unconditional Branch seq_branch_adr 06b4 0x06b4 seq_en_micro 0 typ_b_adr 0e GP0e val_b_adr 0e GP0e 3a0a 3a0a fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_vmux_sel 1 fill value ioc_adrbs 1 val seq_en_micro 0 typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 0f GP0f typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a0b 3a0b fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0e GP0e val_a_adr 09 GP09 val_b_adr 0e GP0e 3a0c 3a0c ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 3a0d 3a0d fiu_mem_start 3 start-wr; Flow C 0x3b7e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b7e 0x3b7e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a0e 3a0e fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 3a0f 3a0f fiu_load_tar 1 hold_tar; Flow J 0x39f5 fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 39f5 0x39f5 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU 3a10 3a10 seq_br_type 7 Unconditional Call; Flow C 0x33af seq_branch_adr 33af 0x33af 3a11 3a11 fiu_mem_start 2 start-rd; Flow J 0x3a12 ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3a11 0x3a11 seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a12 3a12 fiu_mem_start 4 continue seq_random 02 ? typ_mar_cntl 6 INCREMENT_MAR 3a13 3a13 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x3a4d fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3a4d 0x3a4d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_source 0 FIU_BUS val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3a14 3a14 fiu_load_var 1 hold_var; Flow J cc=True 0x3a43 fiu_mem_start 6 start_rd_if_false fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3a43 0x3a43 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 30 VR11:10 val_frame 11 val_rand 9 PASS_A_HIGH 3a15 3a15 seq_br_type 0 Branch False; Flow J cc=False 0x3a1e seq_branch_adr 3a1e 0x3a1e seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3a16 3a16 fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x3a23 fiu_offs_lit 22 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 3a23 0x3a23 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 34 TR08:14 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 8 val_a_adr 24 VR05:04 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_frame 5 3a17 3a17 seq_br_type 1 Branch True; Flow J cc=True 0x3a4f seq_branch_adr 3a4f 0x3a4f seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 2a VR05:0a val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_frame 5 3a18 3a18 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3a4f seq_br_type 1 Branch True seq_branch_adr 3a4f 0x3a4f seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 20 TR05:00 typ_frame 5 3a19 3a19 seq_br_type 1 Branch True; Flow J cc=True 0x3a37 seq_branch_adr 3a37 0x3a37 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 3a VR02:1a val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_frame 2 3a1a 3a1a seq_br_type 1 Branch True; Flow J cc=True 0x3a27 seq_branch_adr 3a27 0x3a27 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 23 VR05:03 val_alu_func 19 X_XOR_B val_b_adr 01 GP01 val_frame 5 3a1b 3a1b fiu_mem_start 2 start-rd; Flow J cc=True 0x3a22 ioc_adrbs 1 val seq_br_type 1 Branch True seq_branch_adr 3a22 0x3a22 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 32 TR02:12 typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 30 VR04:10 val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3a1c 3a1c fiu_len_fill_lit 46 zero-fill 0x6; Flow J 0x3a1d fiu_load_var 1 hold_var fiu_offs_lit 70 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 3a4f 0x3a4f typ_b_adr 16 CSA/VAL_BUS val_b_adr 16 CSA/VAL_BUS 3a1d 3a1d ioc_tvbs 1 typ+fiu; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS 3a1e 3a1e fiu_mem_start 11 start_tag_query ioc_adrbs 1 val seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 09 GP09 val_rand a PASS_B_HIGH 3a1f 3a1f ioc_fiubs 1 val ; Flow C 0x352b seq_br_type 7 Unconditional Call seq_branch_adr 352b 0x352b seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 2a VR05:0a val_frame 5 3a20 3a20 ioc_tvbs 8 typ+mem; Flow J cc=True 0x3a16 seq_br_type 1 Branch True seq_branch_adr 3a16 0x3a16 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 01 GP01 val_a_adr 2d VR05:0d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3a21 3a21 fiu_mem_start 2 start-rd; Flow J 0x34de ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 34de 0x34de typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 30 VR11:10 val_frame 11 val_rand 9 PASS_A_HIGH 3a22 3a22 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 seq_random 05 ? 3a23 3a23 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 38 TR07:18 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a24 3a24 fiu_len_fill_lit 73 zero-fill 0x33 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 48 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_a_adr 33 TR13:13 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 3a25 3a25 fiu_mem_start 3 start-wr; Flow C 0x210 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 21 TR07:01 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 3a26 3a26 ioc_load_wdr 0 ; Flow J 0x3a3f ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3a3f 0x3a3f typ_b_adr 03 GP03 3a27 3a27 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 7 val_rand a PASS_B_HIGH 3a28 3a28 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3a1b seq_br_type 1 Branch True seq_branch_adr 3a1b 0x3a1b seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) typ_a_adr 14 ZEROS typ_b_adr 16 CSA/VAL_BUS typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3a29 3a29 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a2a 3a2a ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3a2b 3a2b fiu_mem_start 3 start-wr; Flow J 0x3a2c seq_br_type 2 Push (branch address) seq_branch_adr 3a32 0x3a32 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 3a2c 3a2c ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 01 GP01 3a2d 3a2d fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=False 0x20d fiu_mem_start 5 start_rd_if_true fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 5 val_rand 9 PASS_A_HIGH 3a2e 3a2e fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3a2f 3a2f ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_random 06 Pop_stack+? val_b_adr 0f GP0f 3a30 3a30 seq_br_type 7 Unconditional Call; Flow C 0x6b4 seq_branch_adr 06b4 0x06b4 3a31 3a31 seq_br_type 3 Unconditional Branch; Flow J 0x3a4f seq_branch_adr 3a4f 0x3a4f 3a32 3a32 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3a33 3a33 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 20 TR08:00 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a34 3a34 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 30 TR02:10 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a35 3a35 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 21 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 16 CSA/VAL_BUS 3a36 3a36 ioc_load_wdr 0 ; Flow J 0x3a6e ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3a6e 0x3a6e val_c_adr 37 GP08 val_c_mux_sel 2 ALU 3a37 3a37 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x332e fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 2d TR08:0d typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a38 3a38 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x210 seq_br_type 0 Branch False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 32 TR13:12 typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 13 val_a_adr 3b VR13:1b val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 13 3a39 3a39 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3a41 seq_br_type 1 Branch True seq_branch_adr 3a41 0x3a41 seq_cond_sel 36 TYP.D_BUS_BIT_33 (med_late) seq_en_micro 0 typ_a_adr 21 TR07:01 typ_alu_func 1b A_OR_B typ_b_adr 03 GP03 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 7 val_a_adr 01 GP01 val_alu_func 1b A_OR_B val_b_adr 33 VR09:13 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 9 3a3a 3a3a fiu_mem_start 3 start-wr; Flow J 0x3a3b seq_br_type 2 Push (branch address) seq_branch_adr 0282 0x0282 seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 3a3b 3a3b ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 01 GP01 3a3c 3a3c fiu_len_fill_lit 4f zero-fill 0xf; Flow C cc=False 0x20d fiu_mem_start 5 start_rd_if_true fiu_offs_lit 50 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 4 Call False seq_branch_adr 020d 0x020d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 38 VR05:18 val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 5 val_rand 9 PASS_A_HIGH 3a3d 3a3d fiu_load_tar 1 hold_tar; Flow C 0x210 fiu_mem_start 7 start_wr_if_true fiu_tivi_src 8 type_var ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3a3e 3a3e ioc_load_wdr 0 ioc_tvbs 2 fiu+val seq_en_micro 0 seq_random 06 Pop_stack+? val_b_adr 0f GP0f 3a3f 3a3f seq_b_timing 1 Latch Condition; Flow C cc=False 0x6b4 seq_br_type 4 Call False seq_branch_adr 06b4 0x06b4 seq_en_micro 0 3a40 3a40 seq_br_type 3 Unconditional Branch; Flow J 0x3a43 seq_branch_adr 3a43 0x3a43 3a41 3a41 fiu_mem_start 3 start-wr seq_en_micro 0 typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 2 3a42 3a42 ioc_load_wdr 0 ; Flow J 0x3a3f seq_br_type 3 Unconditional Branch seq_branch_adr 3a3f 0x3a3f seq_en_micro 0 typ_b_adr 03 GP03 val_b_adr 01 GP01 3a43 3a43 fiu_mem_start 11 start_tag_query ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 6 CONTROL TOP typ_a_adr 20 TR00:00 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a44 3a44 seq_br_type 7 Unconditional Call; Flow C 0x352b seq_branch_adr 352b 0x352b seq_en_micro 0 3a45 3a45 ioc_tvbs 8 typ+mem; Flow J cc=True 0x3a49 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3a49 0x3a49 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 2d VR05:0d val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3a46 3a46 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3a47 3a47 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 3a48 3a48 fiu_mem_start 3 start-wr; Flow J 0x3b7e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b7e 0x3b7e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a49 3a49 seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 35 TR02:15 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a4a 3a4a seq_br_type 7 Unconditional Call; Flow C 0x33a3 seq_branch_adr 33a3 0x33a3 seq_en_micro 0 3a4b 3a4b ioc_adrbs 3 seq ; Flow C 0x6bd seq_br_type 7 Unconditional Call seq_branch_adr 06bd 0x06bd seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 3a4c 3a4c seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 3a4d 3a4d seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3a4e 3a4e seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 3a4f 0x3a4f seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3a4f 3a4f seq_en_micro 0 seq_random 06 Pop_stack+? 3a50 3a50 seq_b_timing 3 Late Condition, Hint False; Flow C 0x2ab4 seq_br_type 9 Return False seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT 3a51 ; -------------------------------------------------------------------------------------- 3a51 ; Comes from: 3a51 ; 0288 C from color 0x0000 3a51 ; 03fb C from color 0x03f9 3a51 ; -------------------------------------------------------------------------------------- 3a51 3a51 fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 3a52 3a52 fiu_load_tar 1 hold_tar; Flow C cc=False 0x3a69 fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 3a69 0x3a69 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 3a53 3a53 ioc_load_wdr 0 ; Flow J cc=True 0x3b1b ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3b1b 0x3b1b seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 val_a_adr 3e VR05:1e val_alu_func 1e A_AND_B val_b_adr 0f GP0f val_frame 5 3a54 3a54 fiu_mem_start 2 start-rd; Flow C 0x34dc ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34dc 0x34dc seq_random 02 ? typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 09 GP09 val_rand a PASS_B_HIGH 3a55 3a55 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a56 3a56 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 3a57 3a57 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 2c TR02:0c typ_alu_func 18 NOT_A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3a58 3a58 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3a5a seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3a5a 0x3a5a seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS 3a59 3a59 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x3a65 seq_br_type 8 Return True seq_branch_adr 3a65 0x3a65 seq_en_micro 0 3a5a 3a5a ioc_tvbs 1 typ+fiu; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 3a5b 0x3a5b seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 val_a_adr 24 VR05:04 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3a5b 3a5b fiu_mem_start 3 start-wr; Flow C 0x210 ioc_adrbs 1 val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 2a TYP.CLASS_B_EQ_LIT (med_late) seq_en_micro 0 typ_b_adr 0f GP0f typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a5c 3a5c ioc_load_wdr 0 ; Flow C 0x6b4 seq_br_type 7 Unconditional Call seq_branch_adr 06b4 0x06b4 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3a5d 3a5d fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3a5e 3a5e ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 3a5f 3a5f fiu_mem_start 3 start-wr; Flow C 0x3b7e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b7e 0x3b7e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a60 3a60 fiu_mem_start 2 start-rd ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 09 GP09 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3a61 3a61 fiu_mem_start 4 continue typ_mar_cntl 6 INCREMENT_MAR 3a62 3a62 fiu_len_fill_lit 44 zero-fill 0x4 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3a63 3a63 ioc_tvbs c mem+mem+csa+dummy; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3a64 0x3a64 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_frame 2 val_a_adr 0f GP0f val_alu_func 19 X_XOR_B val_b_adr 23 VR05:03 val_frame 5 3a64 3a64 seq_b_timing 1 Latch Condition; Flow R cc=True ; Flow J cc=False 0x3a5d seq_br_type 8 Return True seq_branch_adr 3a5d 0x3a5d 3a65 3a65 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3a66 3a66 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu typ_b_adr 32 TR02:12 typ_frame 2 3a67 3a67 fiu_mem_start 3 start-wr; Flow C 0x3b7e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 3b7e 0x3b7e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a68 3a68 seq_br_type 3 Unconditional Branch; Flow J 0x3a54 seq_branch_adr 3a54 0x3a54 3a69 ; -------------------------------------------------------------------------------------- 3a69 ; Comes from: 3a69 ; 3a52 C False from color 0x03fa 3a69 ; -------------------------------------------------------------------------------------- 3a69 3a69 ioc_adrbs 2 typ ; Flow C 0x34cd seq_br_type 7 Unconditional Call seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 08 GP08 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3a6a 3a6a seq_br_type 4 Call False; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3a6b 3a6b fiu_mem_start 2 start-rd; Flow C 0x332e ioc_adrbs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_a_adr 08 GP08 typ_alu_func 0 PASS_A typ_mar_cntl d LOAD_MAR_TYPE 3a6c 3a6c fiu_load_tar 1 hold_tar; Flow R fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type a Unconditional Return val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 3a6d 3a6d ioc_fiubs 1 val ; Flow J 0x3a6f seq_br_type 3 Unconditional Branch seq_branch_adr 3a6f 0x3a6f typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 3a6e 3a6e ioc_fiubs 1 val ; Flow C 0x33af seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 3a6f 3a6f ioc_adrbs 1 val ; Flow J 0x3a70 seq_br_type 2 Push (branch address) seq_branch_adr 3a6d 0x3a6d typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 3a70 3a70 ioc_fiubs 1 val ; Flow J 0x3a75 seq_br_type 3 Unconditional Branch seq_branch_adr 3a75 0x3a75 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 29 VR05:09 val_alu_func 1a PASS_B val_b_adr 08 GP08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3a71 3a71 ioc_fiubs 1 val ; Flow J 0x3a73 seq_br_type 3 Unconditional Branch seq_branch_adr 3a73 0x3a73 typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 3a72 3a72 ioc_fiubs 1 val ; Flow C 0x33af seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af typ_c_adr 39 GP06 typ_c_source 0 FIU_BUS val_a_adr 09 GP09 3a73 3a73 ioc_adrbs 1 val ; Flow J 0x3a74 seq_br_type 2 Push (branch address) seq_branch_adr 3a72 0x3a72 typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU val_frame 4 val_rand a PASS_B_HIGH 3a74 3a74 ioc_fiubs 1 val ; Flow J 0x3a75 seq_br_type 3 Unconditional Branch seq_branch_adr 3a75 0x3a75 seq_cond_sel 16 VAL.TRUE(early) seq_latch 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS val_a_adr 23 VR07:03 val_alu_func 1a PASS_B val_b_adr 08 GP08 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 7 3a75 3a75 fiu_mem_start 5 start_rd_if_true; Flow C cc=True 0x34f0 ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 5 Call True seq_branch_adr 34f0 0x34f0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS val_a_adr 14 ZEROS 3a76 3a76 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3add ioc_adrbs 1 val seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3add 0x3add typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3a77 3a77 fiu_mem_start 4 continue; Flow C cc=False 0x3a9e ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 3a9e 0x3a9e seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR 3a78 3a78 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x210 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3a79 3a79 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x3add fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3add 0x3add seq_cond_sel 00 VAL.ALU_ZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 2a VR05:0a val_frame 5 3a7a 3a7a ioc_fiubs 0 fiu ; Flow J cc=True 0x3adf seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3adf 0x3adf seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 01 GP01 typ_c_adr 3e GP01 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3a7b 3a7b fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3af4 fiu_load_mdr 1 hold_mdr fiu_mem_start 6 start_rd_if_false fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 1 Branch True seq_branch_adr 3af4 0x3af4 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_a_adr 20 TR08:00 typ_b_adr 01 GP01 typ_frame 8 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 30 VR04:10 val_frame 4 val_rand 9 PASS_A_HIGH 3a7c 3a7c fiu_len_fill_lit 40 zero-fill 0x0; Flow J cc=True 0x3adc fiu_load_var 1 hold_var fiu_offs_lit 77 fiu_op_sel 3 insert fiu_tivi_src 1 tar_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3adc 0x3adc seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 9 typ_rand 1 INC_LOOP_COUNTER val_a_adr 38 VR08:18 val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_frame 8 3a7d 3a7d fiu_mem_start 2 start-rd; Flow C cc=True 0x3b09 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3b09 0x3b09 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 04 GP04 val_rand 9 PASS_A_HIGH 3a7e 3a7e fiu_mem_start 2 start-rd; Flow C cc=True 0x3b09 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3b09 0x3b09 seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 14 ZEROS typ_alu_func 19 X_XOR_B typ_b_adr 32 TR02:12 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2d VR04:0d val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_frame 4 3a7f 3a7f fiu_mem_start 2 start-rd; Flow J cc=False 0x3a8c ioc_adrbs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3a8c 0x3a8c seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 24 VR05:04 val_frame 5 3a80 3a80 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x332e fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e seq_en_micro 0 typ_a_adr 03 GP03 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3a81 3a81 fiu_len_fill_lit 40 zero-fill 0x0; Flow C 0x210 fiu_offs_lit 12 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_alu_func 1a PASS_B val_b_adr 09 GP09 val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3a82 3a82 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=False 0x3ac9 fiu_mem_start 2 start-rd fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3ac9 0x3ac9 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 1 INC_LOOP_COUNTER val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 01 GP01 val_c_adr 3c GP03 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 3a83 3a83 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3adb seq_br_type 5 Call True seq_branch_adr 3adb 0x3adb seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_en_micro 0 typ_b_adr 01 GP01 3a84 3a84 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3a87 seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3a87 0x3a87 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_lit 2 typ_c_mux_sel 0 ALU typ_frame 1f typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3a85 3a85 fiu_mem_start 3 start-wr seq_en_micro 0 typ_a_adr 35 TR02:15 typ_alu_func 18 NOT_A_AND_B typ_b_adr 0f GP0f typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 3a86 3a86 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3a87 3a87 seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3ac8 seq_br_type 5 Call True seq_branch_adr 3ac8 0x3ac8 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 3a88 3a88 fiu_len_fill_lit 44 zero-fill 0x4; Flow C 0x33a3 fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 33a3 0x33a3 seq_en_micro 0 seq_random 02 ? typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3a89 3a89 fiu_load_var 1 hold_var; Flow J cc=False 0x3aa1 fiu_tivi_src 2 tar_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 0 Branch False seq_branch_adr 3aa1 0x3aa1 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS val_a_adr 03 GP03 3a8a 3a8a fiu_mem_start 2 start-rd; Flow C 0x33c4 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 33c4 0x33c4 typ_a_adr 3a TR09:1a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3a8b 3a8b fiu_len_fill_lit 44 zero-fill 0x4; Flow J 0x3aa1 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3aa1 0x3aa1 typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3a8c 3a8c seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x3a80 seq_br_type 0 Branch False seq_branch_adr 3a80 0x3a80 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 27 VR05:07 val_frame 5 3a8d 3a8d fiu_mem_start 2 start-rd fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 3a GP05 val_c_source 0 FIU_BUS val_frame 4 val_rand a PASS_B_HIGH 3a8e 3a8e ioc_fiubs 1 val ; Flow C 0x3b09 seq_br_type 7 Unconditional Call seq_branch_adr 3b09 0x3b09 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS val_a_adr 05 GP05 3a8f 3a8f fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=True 0x3aee fiu_load_var 1 hold_var fiu_mem_start 6 start_rd_if_false fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ ioc_tvbs c mem+mem+csa+dummy seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3aee 0x3aee seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_a_adr 05 GP05 typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand a PASS_B_HIGH 3a90 3a90 ioc_fiubs 0 fiu seq_en_micro 0 val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3a91 3a91 fiu_len_fill_lit 53 zero-fill 0x13; Flow J cc=False 0x3a98 fiu_load_var 1 hold_var fiu_offs_lit 25 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 0 Branch False seq_branch_adr 3a98 0x3a98 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3a92 3a92 ioc_fiubs 2 typ ; Flow J cc=True 0x3a80 ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3a80 0x3a80 seq_cond_sel 08 VAL.ALU_CARRY(late) seq_en_micro 0 typ_a_adr 05 GP05 val_a_adr 04 GP04 val_alu_func 5 DEC_A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_source 0 FIU_BUS 3a93 3a93 fiu_len_fill_lit 5f zero-fill 0x1f; Flow C cc=True 0x3b09 fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3b09 0x3b09 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_a_adr 05 GP05 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 04 GP04 val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand a PASS_B_HIGH 3a94 3a94 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=False 0x3a80 seq_br_type 0 Branch False seq_branch_adr 3a80 0x3a80 seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 val_a_adr 01 GP01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 3a95 3a95 ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3a80 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3a80 0x3a80 seq_cond_sel 28 TYP.OF_KIND_MATCH(0x32) Module_Key Deletion_Key Interface_Key seq_en_micro 0 typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 12 3a96 3a96 fiu_mem_start 2 start-rd; Flow C cc=True 0x3b09 ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 3b09 0x3b09 seq_cond_sel 01 VAL.ALU_NONZERO(late) seq_en_micro 0 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_rand 9 PASS_A_HIGH 3a97 3a97 seq_br_type 3 Unconditional Branch; Flow J 0x3a80 seq_branch_adr 3a80 0x3a80 seq_en_micro 0 3a98 3a98 ioc_fiubs 1 val seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3a GP05 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 05 GP05 3a99 3a99 seq_br_type 1 Branch True; Flow J cc=True 0x3a80 seq_branch_adr 3a80 0x3a80 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 04 GP04 typ_alu_func 19 X_XOR_B typ_b_adr 05 GP05 3a9a 3a9a seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_en_micro 0 3a9b 3a9b ioc_fiubs 1 val ; Flow R cc=True seq_br_type 8 Return True seq_branch_adr 3a9c 0x3a9c seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME val_a_adr 05 GP05 3a9c 3a9c ioc_adrbs 1 val ; Flow J 0x3a9d seq_br_type 2 Push (branch address) seq_branch_adr 3a76 0x3a76 seq_cond_sel 16 VAL.TRUE(early) seq_en_micro 0 seq_latch 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3a9d 3a9d fiu_mem_start 5 start_rd_if_true; Flow R cc=False ; Flow J cc=True 0x34f0 ioc_tvbs 5 seq+seq seq_br_type 9 Return False seq_branch_adr 34f0 0x34f0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 06 GP06 typ_b_adr 16 CSA/VAL_BUS 3a9e ; -------------------------------------------------------------------------------------- 3a9e ; Comes from: 3a9e ; 3a77 C False from color 0x0000 3a9e ; -------------------------------------------------------------------------------------- 3a9e 3a9e seq_br_type 7 Unconditional Call; Flow C 0x33a3 seq_branch_adr 33a3 0x33a3 seq_en_micro 0 3a9f 3a9f fiu_mem_start 5 start_rd_if_true ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 4 val_rand a PASS_B_HIGH 3aa0 3aa0 fiu_mem_start 4 continue; Flow R seq_br_type a Unconditional Return typ_mar_cntl 6 INCREMENT_MAR 3aa1 3aa1 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_tar 1 hold_tar fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator ioc_adrbs 1 val typ_a_adr 3a TR09:1a typ_alu_func 0 PASS_A typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3b VR05:1b val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 5 val_rand a PASS_B_HIGH 3aa2 3aa2 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu fiu_vmux_sel 1 fill value ioc_fiubs 2 typ typ_a_adr 20 TR02:00 typ_alu_func 1e A_AND_B typ_b_adr 03 GP03 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3aa3 3aa3 fiu_mem_start 3 start-wr; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU val_a_adr 2a VR12:0a val_alu_func 1b A_OR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3d GP02 val_c_mux_sel 2 ALU val_frame 12 3aa4 3aa4 ioc_load_wdr 0 typ_b_adr 02 GP02 typ_c_lit 1 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 02 GP02 3aa5 3aa5 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=True 0x3aa7 fiu_load_var 1 hold_var fiu_rdata_src 0 rotator ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 1 Branch True seq_branch_adr 3aa7 0x3aa7 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3aa6 3aa6 fiu_len_fill_lit 3f sign-fill 0x3f fiu_rdata_src 0 rotator ioc_fiubs 0 fiu typ_a_adr 20 TR02:00 typ_alu_func 6 A_MINUS_B typ_b_adr 34 TR02:14 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3aa7 3aa7 fiu_len_fill_lit 44 zero-fill 0x4; Flow J cc=True 0x3aa8 ; Flow J cc=#0x0 0x3aa8 fiu_load_tar 1 hold_tar fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var ioc_fiubs 1 val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3aa8 0x3aa8 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_a_adr 29 TR02:09 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS 3aa8 3aa8 ioc_adrbs 1 val ; Flow J 0x3afb seq_br_type 3 Unconditional Branch seq_branch_adr 3afb 0x3afb typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 3aa9 3aa9 seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 3aaa 3aaa seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 3aab 3aab seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 3aac 3aac seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 3aad 3aad seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 3aae 3aae seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 3aaf 3aaf fiu_mem_start 2 start-rd; Flow J 0x3aff ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3aff 0x3aff typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 7 val_rand a PASS_B_HIGH 3ab0 3ab0 seq_br_type 3 Unconditional Branch; Flow J 0x3b02 seq_branch_adr 3b02 0x3b02 3ab1 3ab1 seq_br_type 3 Unconditional Branch; Flow J 0x3b01 seq_branch_adr 3b01 0x3b01 3ab2 3ab2 seq_br_type 3 Unconditional Branch; Flow J 0x3b02 seq_branch_adr 3b02 0x3b02 3ab3 3ab3 ioc_adrbs 1 val ; Flow J 0x3afd seq_br_type 3 Unconditional Branch seq_branch_adr 3afd 0x3afd typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 3ab4 3ab4 ioc_tvbs 2 fiu+val; Flow J 0x3b06 seq_br_type 3 Unconditional Branch seq_branch_adr 3b06 0x3b06 typ_a_adr 20 TR02:00 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3ab5 3ab5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3ab6 3ab6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3ab7 3ab7 seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 3ab8 3ab8 ioc_adrbs 1 val ; Flow J 0x3afd seq_br_type 3 Unconditional Branch seq_branch_adr 3afd 0x3afd typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 3ab9 3ab9 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3aba 3aba seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3abb 3abb seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 3abc 3abc seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3abd 3abd seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3abe 3abe seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3abf 3abf seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3ac0 3ac0 seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 3ac1 3ac1 seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 3ac2 3ac2 ioc_adrbs 1 val ; Flow J 0x3afd seq_br_type 3 Unconditional Branch seq_branch_adr 3afd 0x3afd typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 0 PASS_A 3ac3 3ac3 seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 3ac4 3ac4 fiu_mem_start 2 start-rd; Flow J 0x3aff ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3aff 0x3aff typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR07:0e val_alu_func 0 PASS_A val_b_adr 01 GP01 val_frame 7 val_rand a PASS_B_HIGH 3ac5 3ac5 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3ac6 3ac6 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3ac7 3ac7 seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 3ac8 3ac8 seq_b_timing 3 Late Condition, Hint False; Flow R cc=False ; Flow J cc=True 0x3add seq_br_type 9 Return False seq_branch_adr 3add 0x3add seq_cond_sel 18 TYP.ALU_ZERO(late) typ_a_adr 31 TR13:11 typ_alu_func 1d A_AND_NOT_B typ_b_adr 01 GP01 typ_frame 13 3ac9 3ac9 val_c_adr 3e GP01 3aca 3aca ioc_tvbs c mem+mem+csa+dummy; Flow J cc=True 0x3ae8 seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3ae8 0x3ae8 seq_cond_sel 39 TYP.D_BUS_BIT_36 (med_late) typ_b_adr 16 CSA/VAL_BUS typ_c_lit 2 typ_frame 1f typ_rand 1 INC_LOOP_COUNTER 3acb 3acb seq_b_timing 3 Late Condition, Hint False; Flow C cc=True 0x3ac8 seq_br_type 5 Call True seq_branch_adr 3ac8 0x3ac8 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 39 VR02:19 val_frame 2 3acc 3acc fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val typ_a_adr 23 TR01:03 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 1 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3acd 3acd ioc_fiubs 0 fiu ioc_load_wdr 0 typ_b_adr 01 GP01 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS val_b_adr 01 GP01 val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3ace 3ace seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3ad3 seq_br_type 1 Branch True seq_branch_adr 3ad3 0x3ad3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 2a TR02:0a typ_frame 2 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 28 VR05:08 val_frame 5 3acf 3acf seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3ad3 seq_br_type 1 Branch True seq_branch_adr 3ad3 0x3ad3 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 02 GP02 typ_alu_func 19 X_XOR_B typ_b_adr 32 TR11:12 typ_frame 11 val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 20 VR11:00 val_frame 11 3ad0 3ad0 seq_br_type 7 Unconditional Call; Flow C 0x6cf seq_branch_adr 06cf 0x06cf 3ad1 3ad1 ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 36 GP09 val_c_source 0 FIU_BUS 3ad2 3ad2 ioc_fiubs 2 typ ; Flow J 0x3a75 seq_br_type 3 Unconditional Branch seq_branch_adr 3a75 0x3a75 typ_a_adr 06 GP06 val_c_adr 3e GP01 val_c_source 0 FIU_BUS 3ad3 3ad3 seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 3ad4 3ad4 ioc_adrbs 2 typ ; Flow J cc=True 0x3ad2 ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3ad2 0x3ad2 seq_cond_sel 01 VAL.ALU_NONZERO(late) typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 02 GP02 val_alu_func 19 X_XOR_B val_b_adr 26 VR05:06 val_c_adr 36 GP09 val_c_source 0 FIU_BUS val_frame 5 3ad5 3ad5 seq_br_type 7 Unconditional Call; Flow C 0x34f0 seq_branch_adr 34f0 0x34f0 3ad6 3ad6 fiu_mem_start 5 start_rd_if_true; Flow J cc=False 0x3add ioc_adrbs 2 typ seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3add 0x3add typ_a_adr 06 GP06 typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B 3ad7 3ad7 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 14 ZEROS 3ad8 3ad8 fiu_len_fill_lit 40 zero-fill 0x0 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 22 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy 3ad9 3ad9 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_tar 1 hold_tar fiu_mem_start 3 start-wr fiu_offs_lit 15 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ typ_a_adr 31 TR02:11 typ_frame 2 3ada 3ada ioc_load_wdr 0 ; Flow J 0x3ad2 ioc_tvbs 3 fiu+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 3ad2 0x3ad2 3adb 3adb seq_b_timing 3 Late Condition, Hint False; Flow R cc=True ; Flow J cc=False 0x3add seq_br_type 8 Return True seq_branch_adr 3add 0x3add seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 03 GP03 val_alu_func 19 X_XOR_B val_b_adr 24 VR08:04 val_frame 8 3adc 3adc fiu_mem_start 3 start-wr; Flow C 0x332e ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 332e 0x332e typ_b_adr 05 GP05 3add 3add seq_br_type 1 Branch True; Flow J cc=True 0x3b16 seq_branch_adr 3b16 0x3b16 seq_cond_sel 01 VAL.ALU_NONZERO(late) val_a_adr 14 ZEROS val_alu_func 19 X_XOR_B val_b_adr 08 GP08 3ade 3ade seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d 3adf 3adf seq_br_type 1 Branch True; Flow J cc=True 0x3ae8 seq_branch_adr 3ae8 0x3ae8 seq_cond_sel 19 TYP.ALU_NONZERO(late) typ_a_adr 01 GP01 typ_alu_func 1e A_AND_B typ_b_adr 34 TR13:14 typ_frame 13 3ae0 3ae0 fiu_mem_start 2 start-rd; Flow C 0x332f ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 332f 0x332f seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 11 val_rand a PASS_B_HIGH 3ae1 3ae1 fiu_tivi_src 1 tar_val; Flow C 0x210 ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 3ae2 3ae2 ioc_tvbs 5 seq+seq; Flow J cc=True 0x3ae8 seq_br_type 1 Branch True seq_branch_adr 3ae8 0x3ae8 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_b_adr 16 CSA/VAL_BUS 3ae3 3ae3 fiu_mem_start 2 start-rd; Flow J 0x3ae4 ioc_adrbs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3a6d 0x3a6d seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 3c VR13:1c val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 13 val_rand a PASS_B_HIGH 3ae4 3ae4 seq_en_micro 0 typ_c_adr 30 GP0f typ_c_source 0 FIU_BUS 3ae5 3ae5 fiu_len_fill_lit 4f zero-fill 0xf; Flow C 0x210 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_c_adr 31 GP0e typ_c_source 0 FIU_BUS 3ae6 3ae6 seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 0f GP0f typ_alu_func 19 X_XOR_B typ_b_adr 0e GP0e typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU 3ae7 3ae7 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3a7b seq_br_type 1 Branch True seq_branch_adr 3a7b 0x3a7b seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1e A_AND_B typ_b_adr 39 TR13:19 typ_frame 13 3ae8 3ae8 fiu_len_fill_lit 41 zero-fill 0x1 fiu_offs_lit 13 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_b_adr 01 GP01 3ae9 3ae9 fiu_mem_start 2 start-rd; Flow J cc=True 0x3aea ; Flow J cc=#0x0 0x3aea ioc_adrbs 1 val seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3aea 0x3aea seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR11:0f val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 11 val_rand a PASS_B_HIGH 3aea 3aea seq_br_type 3 Unconditional Branch; Flow J 0x3af4 seq_branch_adr 3af4 0x3af4 3aeb 3aeb seq_br_type 3 Unconditional Branch; Flow J 0x3af4 seq_branch_adr 3af4 0x3af4 3aec 3aec seq_br_type 3 Unconditional Branch; Flow J 0x3af7 seq_branch_adr 3af7 0x3af7 3aed 3aed seq_br_type 3 Unconditional Branch; Flow J 0x3af9 seq_branch_adr 3af9 0x3af9 3aee 3aee fiu_mem_start 5 start_rd_if_true; Flow J cc=True 0x3af1 ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 1 Branch True seq_branch_adr 3af1 0x3af1 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 0f GP0f typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 05 GP05 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3aef 3aef fiu_mem_start 6 start_rd_if_false; Flow J cc=False 0x3a90 ioc_adrbs 1 val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3a90 0x3a90 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 typ_mar_cntl c LOAD_MAR_QUEUE val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 05 GP05 val_rand a PASS_B_HIGH 3af0 3af0 seq_br_type 3 Unconditional Branch; Flow J 0x3af3 seq_branch_adr 3af3 0x3af3 seq_en_micro 0 typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 20 TR02:00 typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3af1 3af1 fiu_mem_start 7 start_wr_if_true; Flow C 0x210 ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3af2 3af2 ioc_load_wdr 0 seq_en_micro 0 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3af3 3af3 fiu_len_fill_lit 5f zero-fill 0x1f; Flow J 0x3af5 fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3af5 0x3af5 seq_en_micro 0 val_a_adr 05 GP05 val_b_adr 39 VR02:19 val_frame 2 3af4 3af4 fiu_len_fill_lit 5f zero-fill 0x1f fiu_load_var 1 hold_var fiu_offs_lit 60 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 5 fiu_val fiu_vmux_sel 3 FIU BUS ioc_fiubs 1 val val_a_adr 09 GP09 val_b_adr 39 VR02:19 val_frame 2 3af5 3af5 ioc_load_wdr 0 ioc_tvbs 1 typ+fiu 3af6 3af6 fiu_mem_start 3 start-wr; Flow J 0x3b7e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b7e 0x3b7e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3af7 3af7 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 3af8 3af8 fiu_mem_start 3 start-wr; Flow J 0x3b8d ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b8d 0x3b8d seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3af9 3af9 ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy 3afa 3afa fiu_mem_start 3 start-wr; Flow J 0x3b7e ioc_adrbs 2 typ ioc_tvbs 5 seq+seq seq_br_type 3 Unconditional Branch seq_branch_adr 3b7e 0x3b7e seq_int_reads 6 CONTROL TOP typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3afb 3afb seq_br_type 7 Unconditional Call; Flow C 0x6cf seq_branch_adr 06cf 0x06cf 3afc 3afc seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 3afd 3afd seq_br_type 7 Unconditional Call; Flow C 0x5a7 seq_branch_adr 05a7 0x05a7 3afe 3afe seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 3aff 3aff seq_br_type 2 Push (branch address); Flow J 0x3b00 seq_branch_adr 3b06 0x3b06 3b00 3b00 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J 0x3a51 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_br_type 3 Unconditional Branch seq_branch_adr 3a51 0x3a51 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 19 typ_rand 1 INC_LOOP_COUNTER val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 36 GP09 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3b01 3b01 ioc_adrbs 3 seq ; Flow C 0x5a7 seq_br_type 7 Unconditional Call seq_branch_adr 05a7 0x05a7 seq_int_reads 6 CONTROL TOP seq_random 13 ? typ_mar_cntl e LOAD_MAR_CONTROL 3b02 3b02 seq_br_type 7 Unconditional Call; Flow C 0x662 seq_branch_adr 0662 0x0662 3b03 3b03 seq_b_timing 1 Latch Condition; Flow J cc=True 0x3b05 seq_br_type 1 Branch True seq_branch_adr 3b05 0x3b05 typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 09 GP09 val_alu_func 0 PASS_A val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3b04 3b04 seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3b05 3b05 seq_br_type 3 Unconditional Branch; Flow J 0x3b06 seq_branch_adr 3b06 0x3b06 typ_alu_func 1b A_OR_B typ_b_adr 22 TR01:02 typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_frame 1 val_a_adr 08 GP08 val_alu_func 0 PASS_A val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3b06 3b06 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_var 1 hold_var fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_int_reads 5 RESOLVE RAM typ_alu_func 0 PASS_A typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_rand c WRITE_OUTER_FRAME 3b07 3b07 fiu_mem_start 3 start-wr ioc_adrbs 1 val typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 01 GP01 val_alu_func 1a PASS_B val_b_adr 2d VR07:0d val_frame 7 val_rand 9 PASS_A_HIGH 3b08 3b08 ioc_load_wdr 0 ; Flow J 0x62f ioc_tvbs 1 typ+fiu seq_br_type 3 Unconditional Branch seq_branch_adr 062f 0x062f typ_alu_func 1a PASS_B typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3b09 ; -------------------------------------------------------------------------------------- 3b09 ; Comes from: 3b09 ; 3a7d C True from color 0x0000 3b09 ; 3a7e C True from color 0x0000 3b09 ; 3a8e C from color 0x0000 3b09 ; 3a93 C True from color 0x0000 3b09 ; 3a96 C True from color 0x0000 3b09 ; -------------------------------------------------------------------------------------- 3b09 3b09 seq_br_type 8 Return True; Flow R cc=True seq_branch_adr 3b0a 0x3b0a seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3b0a 3b0a seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3b0b 3b0b seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 seq_random 06 Pop_stack+? 3b0c 3b0c seq_br_type a Unconditional Return; Flow R seq_en_micro 0 3b0d 3b0d fiu_mem_start 2 start-rd; Flow C 0x34f0 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 34f0 0x34f0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3b0e 3b0e fiu_len_fill_lit 3f sign-fill 0x3f; Flow R cc=False fiu_load_var 1 hold_var fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_b_timing 1 Latch Condition seq_br_type 9 Return False seq_branch_adr 3b0f 0x3b0f seq_int_reads 6 CONTROL TOP typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 09 GP09 val_frame 4 val_rand a PASS_B_HIGH 3b0f 3b0f ioc_tvbs 1 typ+fiu; Flow R cc=True seq_b_timing 3 Late Condition, Hint False seq_br_type 8 Return True seq_branch_adr 3b10 0x3b10 seq_cond_sel 10 VAL.ALU_32_ZERO(late) val_a_adr 09 GP09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 3b10 3b10 fiu_len_fill_lit 44 zero-fill 0x4 fiu_load_var 1 hold_var fiu_offs_lit 15 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 37 TYP.D_BUS_BIT_34 (med_late) seq_latch 1 typ_a_adr 32 TR09:12 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3b GP04 typ_c_mux_sel 0 ALU typ_frame 9 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3b GP04 val_c_mux_sel 2 ALU 3b11 3b11 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x3b14 seq_br_type 1 Branch True seq_branch_adr 3b14 0x3b14 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 23 VR07:03 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 7 3b12 3b12 ioc_tvbs 1 typ+fiu; Flow J cc=True 0x3b14 seq_br_type 1 Branch True seq_branch_adr 3b14 0x3b14 seq_cond_sel 00 VAL.ALU_ZERO(late) val_a_adr 29 VR05:09 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_frame 5 3b13 3b13 seq_b_timing 1 Latch Condition; Flow C 0x210 seq_br_type 8 Return True seq_branch_adr 0210 0x0210 3b14 3b14 fiu_mem_start 3 start-wr 3b15 3b15 ioc_load_wdr 0 ; Flow J 0x6b4 seq_br_type 3 Unconditional Branch seq_branch_adr 06b4 0x06b4 typ_b_adr 04 GP04 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_b_adr 04 GP04 3b16 3b16 seq_br_type 7 Unconditional Call; Flow C 0x69b seq_branch_adr 069b 0x069b seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 1d A_AND_NOT_B typ_b_adr 2c TR02:0c typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 3b17 ; -------------------------------------------------------------------------------------- 3b17 ; Comes from: 3b17 ; 392d C from color 0x0b32 3b17 ; 3978 C from color 0x0913 3b17 ; -------------------------------------------------------------------------------------- 3b17 3b17 fiu_mem_start 2 start-rd; Flow C 0x34dc fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 34dc 0x34dc typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 39 VR02:19 val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 2 val_rand a PASS_B_HIGH 3b18 3b18 fiu_mem_start 2 start-rd; Flow C 0x33c4 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 3 fiu+fiu seq_br_type 7 Unconditional Call seq_branch_adr 33c4 0x33c4 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2e VR04:0e val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 3b19 3b19 seq_b_timing 1 Latch Condition; Flow R cc=False ; Flow J cc=True 0x33ec seq_br_type 9 Return False seq_branch_adr 33ec 0x33ec 3b1a 3b1a seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 3b1b 3b1b seq_br_type 7 Unconditional Call; Flow C 0x210 seq_branch_adr 0210 0x0210 seq_en_micro 0 3b1c ; -------------------------------------------------------------------------------------- 3b1c ; 0x00ad Action InMicrocode,Package,Field_Execute_Dynamic 3b1c ; -------------------------------------------------------------------------------------- 3b1c MACRO_Action_InMicrocode,Package,Field_Execute_Dynamic: 3b1c 3b1c dispatch_brk_class 0 ; Flow J 0x3b1d dispatch_csa_valid 3 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3b1c seq_br_type 2 Push (branch address) seq_branch_adr 3b22 0x3b22 typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3b1d 3b1d ioc_fiubs 1 val ; Flow J 0x3b1f seq_br_type 3 Unconditional Branch seq_branch_adr 3b1f 0x3b1f typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3b1e ; -------------------------------------------------------------------------------------- 3b1e ; 0x1700-0x17ff Execute Task,Entry_Call,fieldnum 3b1e ; -------------------------------------------------------------------------------------- 3b1e MACRO_Execute_Task,Entry_Call,fieldnum: 3b1e 3b1e dispatch_brk_class 5 ; Flow J 0x3b1f dispatch_csa_valid 2 dispatch_ibuff_fill 1 dispatch_uadr 3b1e ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b23 0x3b23 typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3b1f 3b1f ioc_fiubs 1 val ; Flow C 0x33af seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b20 3b20 fiu_mem_start 2 start-rd; Flow C 0x3b71 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b21 3b21 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32dc fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32dc 0x32dc seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3b22 3b22 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3b24 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b24 0x3b24 typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b23 3b23 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b24 3b24 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3b25 3b25 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_alu_func 1a PASS_B val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b26 3b26 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3b27 3b27 ioc_tvbs 3 fiu+fiu typ_a_adr 14 ZEROS typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b28 3b28 fiu_mem_start 2 start-rd; Flow J 0x371c ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 371c 0x371c typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b29 3b29 <halt> ; Flow R 3b2a ; -------------------------------------------------------------------------------------- 3b2a ; 0x00aa QQUnknown InMicrocode 3b2a ; -------------------------------------------------------------------------------------- 3b2a MACRO_3b2a_QQUnknown_InMicrocode: 3b2a 3b2a dispatch_brk_class 0 ; Flow J 0x3b2b dispatch_csa_valid 4 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3b2a seq_br_type 2 Push (branch address) seq_branch_adr 3b30 0x3b30 typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3b2b 3b2b ioc_fiubs 1 val ; Flow J 0x3b2d seq_br_type 3 Unconditional Branch seq_branch_adr 3b2d 0x3b2d typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b2c ; -------------------------------------------------------------------------------------- 3b2c ; 0x1400-0x14ff Execute Task,Family_Call,fieldnum 3b2c ; -------------------------------------------------------------------------------------- 3b2c MACRO_Execute_Task,Family_Call,fieldnum: 3b2c 3b2c dispatch_brk_class 5 ; Flow J 0x3b2d dispatch_csa_valid 3 dispatch_ibuff_fill 1 dispatch_uadr 3b2c ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b31 0x3b31 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b2d 3b2d ioc_fiubs 1 val ; Flow C 0x33af seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3b2e 3b2e fiu_mem_start 2 start-rd; Flow C 0x3b71 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b2f 3b2f fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32dc fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32dc 0x32dc seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3b30 3b30 fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3b32 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b32 0x3b32 typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b31 3b31 fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b32 3b32 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 1 INC_LOOP_COUNTER 3b33 3b33 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b34 3b34 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3b35 3b35 ioc_tvbs 3 fiu+fiu typ_a_adr 22 TR01:02 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b36 3b36 fiu_mem_start 2 start-rd; Flow J 0x371c ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 371c 0x371c typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3b37 3b37 <halt> ; Flow R 3b38 ; -------------------------------------------------------------------------------------- 3b38 ; 0x00ab QQUnknown InMicrocode 3b38 ; -------------------------------------------------------------------------------------- 3b38 MACRO_3b38_QQUnknown_InMicrocode: 3b38 3b38 dispatch_brk_class 0 ; Flow J 0x3b39 dispatch_csa_valid 4 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3b38 seq_br_type 2 Push (branch address) seq_branch_adr 3b3e 0x3b3e typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3b39 3b39 ioc_fiubs 1 val ; Flow J 0x3b3b seq_br_type 3 Unconditional Branch seq_branch_adr 3b3b 0x3b3b typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b3a ; -------------------------------------------------------------------------------------- 3b3a ; 0x1500-0x15ff Execute Task,Timed_Call,fieldnum 3b3a ; -------------------------------------------------------------------------------------- 3b3a MACRO_Execute_Task,Timed_Call,fieldnum: 3b3a 3b3a dispatch_brk_class 5 ; Flow J 0x3b3b dispatch_csa_valid 3 dispatch_ibuff_fill 1 dispatch_uadr 3b3a ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b3f 0x3b3f typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b3b 3b3b ioc_fiubs 1 val ; Flow C 0x33af seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af typ_a_adr 1e TOP - 2 typ_b_adr 1f TOP - 1 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3b3c 3b3c fiu_mem_start 2 start-rd; Flow C 0x3b71 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b3d 3b3d fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32dc fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32dc 0x32dc seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3b3e 3b3e fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3b40 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b40 0x3b40 typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b3f 3b3f fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b40 3b40 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 1 INC_LOOP_COUNTER 3b41 3b41 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b42 3b42 ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3b43 3b43 ioc_tvbs 3 fiu+fiu typ_a_adr 35 TR02:15 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b44 3b44 fiu_mem_start 2 start-rd; Flow J 0x371b ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 371b 0x371b typ_a_adr 04 GP04 typ_c_adr 38 GP07 typ_c_source 0 FIU_BUS typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b45 3b45 <halt> ; Flow R 3b46 ; -------------------------------------------------------------------------------------- 3b46 ; 0x00a8 QQUnknown InMicrocode 3b46 ; -------------------------------------------------------------------------------------- 3b46 MACRO_3b46_QQUnknown_InMicrocode: 3b46 3b46 dispatch_brk_class 0 ; Flow J 0x3b47 dispatch_csa_valid 5 dispatch_ibuff_fill 1 dispatch_ignore 1 dispatch_uadr 3b46 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b4d 0x3b4d typ_a_adr 10 TOP typ_c_adr 3a GP05 typ_c_source 0 FIU_BUS typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP 3b47 3b47 ioc_fiubs 1 val ; Flow J 0x3b49 seq_br_type 3 Unconditional Branch seq_branch_adr 3b49 0x3b49 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 36 GP09 val_c_source 0 FIU_BUS 3b48 ; -------------------------------------------------------------------------------------- 3b48 ; 0x1200-0x12ff Execute Task,Family_Timed,fieldnum 3b48 ; -------------------------------------------------------------------------------------- 3b48 MACRO_Execute_Task,Family_Timed,fieldnum: 3b48 3b48 dispatch_brk_class 5 ; Flow J 0x3b49 dispatch_csa_valid 4 dispatch_ibuff_fill 1 dispatch_uadr 3b48 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b4f 0x3b4f typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 36 GP09 val_c_source 0 FIU_BUS 3b49 3b49 ioc_fiubs 1 val typ_a_adr 1f TOP - 1 typ_b_adr 1e TOP - 2 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 1d TOP - 3 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3b4a 3b4a ioc_fiubs 1 val ; Flow C 0x33af seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af typ_b_adr 1d TOP - 3 typ_c_adr 3b GP04 typ_c_source 0 FIU_BUS typ_rand a PASS_B_HIGH val_a_adr 1e TOP - 2 val_alu_func 1a PASS_B val_b_adr 10 TOP val_c_adr 3d GP02 val_c_mux_sel 2 ALU 3b4b 3b4b fiu_mem_start 2 start-rd; Flow C 0x3b71 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b4c 3b4c fiu_len_fill_lit 47 zero-fill 0x7; Flow R fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type a Unconditional Return seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 1 A_PLUS_B val_b_adr 21 VR05:01 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_frame 5 3b4d 3b4d fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dc 0x32dc seq_cond_sel 08 VAL.ALU_CARRY(late) typ_a_adr 05 GP05 val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 3b4e 3b4e fiu_len_fill_lit 43 zero-fill 0x3; Flow J 0x3b51 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val seq_br_type 3 Unconditional Branch seq_branch_adr 3b51 0x3b51 typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b4f 3b4f fiu_len_fill_lit 47 zero-fill 0x7; Flow C cc=True 0x32dc fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 32dc 0x32dc seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 1 CURRENT MACRO INSTRUCTION val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_frame 5 3b50 3b50 fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 3c VR02:1c val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b51 3b51 fiu_mem_start 3 start-wr ioc_adrbs 2 typ ioc_fiubs 2 typ typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 39 GP06 val_c_source 0 FIU_BUS 3b52 3b52 fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_fiubs 1 val ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3b53 3b53 ioc_tvbs 3 fiu+fiu typ_a_adr 29 TR07:09 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b54 3b54 fiu_mem_start 2 start-rd; Flow J 0x371b ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 371b 0x371b typ_a_adr 03 GP03 typ_alu_func 1a PASS_B typ_b_adr 04 GP04 typ_c_adr 38 GP07 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3b55 3b55 <halt> ; Flow R 3b56 ; -------------------------------------------------------------------------------------- 3b56 ; 0x00ac QQUnknown InMicrocode 3b56 ; -------------------------------------------------------------------------------------- 3b56 MACRO_3b56_QQUnknown_InMicrocode: 3b56 3b56 dispatch_brk_class 0 ; Flow J 0x3b57 dispatch_csa_valid 3 dispatch_ignore 1 dispatch_uadr 3b56 seq_br_type 2 Push (branch address) seq_branch_adr 3b5c 0x3b5c typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3b57 3b57 ioc_fiubs 1 val ; Flow J 0x3b59 seq_br_type 3 Unconditional Branch seq_branch_adr 3b59 0x3b59 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b58 ; -------------------------------------------------------------------------------------- 3b58 ; 0x1600-0x16ff Execute Task,Conditional_Call,fieldnum 3b58 ; -------------------------------------------------------------------------------------- 3b58 MACRO_Execute_Task,Conditional_Call,fieldnum: 3b58 3b58 dispatch_brk_class 5 ; Flow J 0x3b59 dispatch_csa_valid 2 dispatch_uadr 3b58 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b5d 0x3b5d typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b59 3b59 ioc_fiubs 1 val ; Flow C 0x33af seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af typ_a_adr 1f TOP - 1 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 1f TOP - 1 val_c_adr 3c GP03 val_c_source 0 FIU_BUS 3b5a 3b5a fiu_mem_start 2 start-rd; Flow C 0x3b71 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b5b 3b5b fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32dc fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32dc 0x32dc seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3b5c 3b5c fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3b5e fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b5e 0x3b5e typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b5d 3b5d fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b5e 3b5e fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 3b5f 3b5f fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b60 3b60 ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3b61 3b61 ioc_tvbs 3 fiu+fiu typ_a_adr 23 TR01:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 1 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b62 3b62 fiu_mem_start 2 start-rd; Flow J 0x371b ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 371b 0x371b typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b63 3b63 <halt> ; Flow R 3b64 ; -------------------------------------------------------------------------------------- 3b64 ; 0x00a9 QQUnknown InMicrocode 3b64 ; -------------------------------------------------------------------------------------- 3b64 MACRO_3b64_QQUnknown_InMicrocode: 3b64 3b64 dispatch_brk_class 0 ; Flow J 0x3b65 dispatch_csa_valid 4 dispatch_ignore 1 dispatch_uadr 3b64 seq_br_type 2 Push (branch address) seq_branch_adr 3b6a 0x3b6a typ_a_adr 10 TOP typ_csa_cntl 3 POP_CSA typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_alu_func 0 PASS_A val_c_adr 3a GP05 val_c_mux_sel 2 ALU 3b65 3b65 ioc_fiubs 1 val ; Flow J 0x3b67 seq_br_type 3 Unconditional Branch seq_branch_adr 3b67 0x3b67 typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b66 ; -------------------------------------------------------------------------------------- 3b66 ; 0x1300-0x13ff Execute Task,Family_Cond,fieldnum 3b66 ; -------------------------------------------------------------------------------------- 3b66 MACRO_Execute_Task,Family_Cond,fieldnum: 3b66 3b66 dispatch_brk_class 5 ; Flow J 0x3b67 dispatch_csa_valid 3 dispatch_uadr 3b66 ioc_fiubs 1 val seq_br_type 2 Push (branch address) seq_branch_adr 3b6b 0x3b6b typ_a_adr 10 TOP typ_c_adr 3f GP00 typ_c_source 0 FIU_BUS typ_frame 18 typ_rand b CARRY IN = Q BIT FROM VAL val_a_adr 10 TOP val_c_adr 3d GP02 val_c_source 0 FIU_BUS 3b67 3b67 ioc_fiubs 1 val ; Flow C 0x33af seq_br_type 7 Unconditional Call seq_branch_adr 33af 0x33af typ_a_adr 1e TOP - 2 typ_b_adr 1f TOP - 1 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_rand 8 SPARE_0x08 val_a_adr 1f TOP - 1 val_alu_func 1a PASS_B val_b_adr 1e TOP - 2 val_c_adr 3c GP03 val_c_mux_sel 2 ALU 3b68 3b68 fiu_mem_start 2 start-rd; Flow C 0x3b71 ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 3b71 0x3b71 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b69 3b69 fiu_len_fill_lit 47 zero-fill 0x7; Flow R cc=False ; Flow J cc=True 0x32dc fiu_load_tar 1 hold_tar fiu_offs_lit 08 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 6 fiu_fiu ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 32dc 0x32dc seq_cond_sel 08 VAL.ALU_CARRY(late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_a_adr 03 GP03 val_alu_func 5 DEC_A_MINUS_B val_b_adr 36 VR05:16 val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS val_frame 5 3b6a 3b6a fiu_len_fill_lit 47 zero-fill 0x7; Flow J 0x3b6c fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3b6c 0x3b6c typ_a_adr 01 GP01 val_b_adr 05 GP05 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b6b 3b6b fiu_len_fill_lit 47 zero-fill 0x7 fiu_load_tar 1 hold_tar fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_fiubs 2 typ ioc_tvbs 5 seq+seq seq_int_reads 1 CURRENT MACRO INSTRUCTION typ_a_adr 01 GP01 val_c_adr 39 GP06 val_c_source 0 FIU_BUS val_rand 1 INC_LOOP_COUNTER 3b6c 3b6c fiu_len_fill_lit 43 zero-fill 0x3 fiu_load_tar 1 hold_tar fiu_offs_lit 1c fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_tvbs 2 fiu+val typ_a_adr 2d TR02:0d typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR02:04 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 02 GP02 val_alu_func 0 PASS_A val_b_adr 20 VR02:00 val_c_adr 1b VR02:04 val_c_mux_sel 2 ALU val_frame 2 val_rand 1 INC_LOOP_COUNTER 3b6d 3b6d fiu_len_fill_lit 78 zero-fill 0x38 fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 1 val typ_a_adr 01 GP01 typ_alu_func 1a PASS_B typ_b_adr 20 TR07:00 typ_frame 7 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 17 LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 3c VR02:1c val_c_adr 37 GP08 val_c_mux_sel 2 ALU val_frame 2 3b6e 3b6e ioc_load_wdr 0 typ_b_adr 24 TR02:04 typ_frame 2 val_alu_func 1a PASS_B val_b_adr 02 GP02 val_c_adr 36 GP09 val_c_mux_sel 2 ALU 3b6f 3b6f ioc_tvbs 3 fiu+fiu typ_a_adr 23 TR07:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 37 GP08 typ_c_mux_sel 0 ALU typ_frame 7 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 06 GP06 val_alu_func 6 A_MINUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 39 GP06 val_c_mux_sel 2 ALU val_rand 9 PASS_A_HIGH 3b70 3b70 fiu_mem_start 2 start-rd; Flow J 0x371b ioc_adrbs 1 val ioc_fiubs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 371b 0x371b typ_a_adr 03 GP03 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 38 GP07 val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3b71 ; -------------------------------------------------------------------------------------- 3b71 ; Comes from: 3b71 ; 3b4b C from color MACRO_3b46_QQUnknown_InMicrocode 3b71 ; -------------------------------------------------------------------------------------- 3b71 3b71 ioc_tvbs 5 seq+seq; Flow J cc=False 0x3b76 seq_br_type 0 Branch False seq_branch_adr 3b76 0x3b76 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_int_reads 6 CONTROL TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3d GP02 typ_c_mux_sel 0 ALU 3b72 3b72 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=True 0x3b78 fiu_load_var 1 hold_var fiu_offs_lit 1a fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 1 Branch True seq_branch_adr 3b78 0x3b78 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3b73 3b73 seq_br_type 7 Unconditional Call; Flow C 0x34cd seq_branch_adr 34cd 0x34cd seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3b74 3b74 seq_br_type 1 Branch True; Flow J cc=True 0x3b7c seq_branch_adr 3b7c 0x3b7c seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 3b75 3b75 seq_br_type 3 Unconditional Branch; Flow J 0x32d5 seq_branch_adr 32d5 0x32d5 3b76 3b76 fiu_mem_start 3 start-wr ioc_tvbs c mem+mem+csa+dummy typ_b_adr 16 CSA/VAL_BUS typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3e GP01 val_c_mux_sel 2 ALU 3b77 3b77 ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0x3b79 seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3b79 0x3b79 seq_cond_sel 35 TYP.D_BUS_BIT_32 (med_late) typ_alu_func 1a PASS_B typ_b_adr 20 TR02:00 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_alu_func 13 ONES val_b_adr 01 GP01 val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU 3b78 3b78 ioc_tvbs 1 typ+fiu; Flow R cc=False seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 3b79 0x3b79 seq_cond_sel 59 (VAL.ALU_NONZERO(late)) nand (TYP.ALU_NONZERO(late)) typ_a_adr 21 TR01:01 typ_alu_func 1d A_AND_NOT_B typ_b_adr 01 GP01 typ_frame 1 typ_rand 1 INC_LOOP_COUNTER val_a_adr 21 VR05:01 val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS val_c_adr 28 LOOP_COUNTER val_c_mux_sel 2 ALU val_frame 5 3b79 3b79 fiu_mem_start 8 start_wr_if_false; Flow C cc=True 0x32d5 seq_b_timing 0 Early Condition seq_br_type 5 Call True seq_branch_adr 32d5 0x32d5 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 37 TR02:17 typ_alu_func 1b A_OR_B typ_b_adr 01 GP01 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 02 GP02 val_c_adr 3f GP00 val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3b7a 3b7a ioc_load_wdr 0 typ_b_adr 01 GP01 val_b_adr 01 GP01 3b7b 3b7b fiu_mem_start 3 start-wr; Flow C 0x3b7e ioc_adrbs 2 typ ioc_load_wdr 0 seq_br_type 7 Unconditional Call seq_branch_adr 3b7e 0x3b7e typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 02 GP02 typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3b7c 3b7c fiu_mem_start 2 start-rd; Flow J 0x3b71 ioc_adrbs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3b71 0x3b71 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 02 GP02 val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_frame 4 val_rand 9 PASS_A_HIGH 3b7d ; -------------------------------------------------------------------------------------- 3b7d ; Comes from: 3b7d ; 3bc3 C from color 0x3bbf 3b7d ; -------------------------------------------------------------------------------------- 3b7d 3b7d seq_br_type a Unconditional Return; Flow R seq_en_micro 0 3b7e ; -------------------------------------------------------------------------------------- 3b7e ; Comes from: 3b7e ; 0625 C from color 0x05fb 3b7e ; 3906 C from color 0x38e7 3b7e ; 3999 C from color 0x03fa 3b7e ; 3a5f C from color 0x3a5c 3b7e ; 3a67 C from color 0x03fa 3b7e ; -------------------------------------------------------------------------------------- 3b7e 3b7e fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 13 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR05:01 val_frame 5 3b7f 3b7f fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 3b80 3b80 fiu_tivi_src c mar_0xc; Flow J 0x3b81 ioc_fiubs 0 fiu ioc_load_wdr 0 seq_br_type 2 Push (branch address) seq_branch_adr 068f 0x068f seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_b_adr 30 TR03:10 typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 3 typ_rand c WRITE_OUTER_FRAME 3b81 3b81 ioc_fiubs 2 typ ; Flow J 0x7b6 seq_br_type 3 Unconditional Branch seq_branch_adr 07b6 0x07b6 seq_en_micro 0 typ_a_adr 21 TR02:01 typ_c_adr 1e TR02:01 typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3b82 ; -------------------------------------------------------------------------------------- 3b82 ; Comes from: 3b82 ; 05ab C from color 0x05a7 3b82 ; 06d3 C from color 0x06d2 3b82 ; -------------------------------------------------------------------------------------- 3b82 3b82 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_offs_lit 13 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val seq_en_micro 0 typ_b_adr 20 TR02:00 typ_frame 2 val_a_adr 21 VR05:01 val_frame 5 3b83 3b83 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_rdata_src 0 rotator ioc_fiubs 0 fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 1f TOP - 0x0 typ_c_source 0 FIU_BUS typ_frame 2 3b84 3b84 fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 typ_b_adr 30 TR03:10 typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 3 typ_rand c WRITE_OUTER_FRAME 3b85 3b85 ioc_fiubs 2 typ ; Flow R seq_br_type a Unconditional Return seq_en_micro 0 typ_a_adr 21 TR02:01 typ_c_adr 1e TR02:01 typ_frame 2 typ_rand c WRITE_OUTER_FRAME 3b86 3b86 fiu_len_fill_lit 41 zero-fill 0x1 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 3 start-wr fiu_offs_lit 13 fiu_op_sel 3 insert seq_en_micro 0 3b87 3b87 ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3b88 3b88 fiu_mem_start 5 start_rd_if_true; Flow C 0x210 fiu_tivi_src c mar_0xc ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 3b89 3b89 fiu_len_fill_lit 3f sign-fill 0x3f fiu_load_mdr 1 hold_mdr fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_fiubs 2 typ seq_en_micro 0 typ_a_adr 30 TR03:10 typ_frame 3 3b8a 3b8a fiu_len_fill_lit 5f zero-fill 0x1f; Flow C 0x210 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 7 start_wr_if_true fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 3b8b 3b8b ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 3b8c 3b8c fiu_mem_start 2 start-rd; Flow R fiu_tivi_src c mar_0xc ioc_adrbs 3 seq ioc_fiubs 0 fiu seq_br_type e Unconditional Dispatch seq_en_micro 0 seq_random 04 Load_save_offset+? typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand c WRITE_OUTER_FRAME 3b8d ; -------------------------------------------------------------------------------------- 3b8d ; Comes from: 3b8d ; 390a C from color 0x38e7 3b8d ; -------------------------------------------------------------------------------------- 3b8d 3b8d fiu_len_fill_lit 49 zero-fill 0x9; Flow C cc=True 0x211 fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs 5 seq+seq seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 0211 0x0211 seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_a_adr 31 TR03:11 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 3 val_a_adr 20 VR02:00 val_alu_func 0 PASS_A val_c_adr 30 GP0f val_frame 2 3b8e ; -------------------------------------------------------------------------------------- 3b8e ; Comes from: 3b8e ; 3ba0 C from color 0x0bab 3b8e ; -------------------------------------------------------------------------------------- 3b8e 3b8e fiu_len_fill_lit 78 zero-fill 0x38; Flow C 0x210 fiu_load_var 1 hold_var fiu_mem_start 11 start_tag_query fiu_offs_lit 40 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 4 fiu_var fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0f GP0f val_alu_func 0 PASS_A 3b8f 3b8f ioc_tvbs 1 typ+fiu; Flow C 0x3524 seq_br_type 7 Unconditional Call seq_branch_adr 3524 0x3524 seq_cond_sel 6a PAGE_CROSSING~ seq_en_micro 0 typ_a_adr 20 TR02:00 typ_alu_func 0 PASS_A typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 22 VR04:02 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_frame 4 3b90 3b90 fiu_len_fill_lit 3f sign-fill 0x3f; Flow J cc=False 0x3b93 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src 1 tar_val ioc_adrbs 1 val ioc_tvbs 8 typ+mem seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3b93 0x3b93 seq_cond_sel 27 TYP.PREVIOUS (early) seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 1d A_AND_NOT_B typ_b_adr 3c TR09:1c typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 9 typ_mar_cntl b LOAD_MAR_DATA val_a_adr 0e GP0e val_alu_func 0 PASS_A 3b91 3b91 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x3b95 fiu_offs_lit 78 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 3 fiu+fiu seq_br_type 0 Branch False seq_branch_adr 3b95 0x3b95 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_a_adr 3d VR02:1d val_alu_func 1d A_AND_NOT_B val_b_adr 16 CSA/VAL_BUS val_frame 2 3b92 3b92 ioc_tvbs 5 seq+seq; Flow J cc=True 0x3b93 ; Flow J cc=#0x0 0x3b94 seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3b94 0x3b94 seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_int_reads 6 CONTROL TOP typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT 3b93 3b93 seq_br_type 3 Unconditional Branch; Flow J 0x3b95 seq_branch_adr 3b95 0x3b95 seq_en_micro 0 3b94 3b94 seq_br_type 7 Unconditional Call; Flow C 0x20d seq_branch_adr 020d 0x020d seq_en_micro 0 3b95 3b95 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 3b96 3b96 seq_br_type a Unconditional Return; Flow R seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 3b97 3b97 seq_b_timing 3 Late Condition, Hint False; Flow C 0x210 seq_br_type 5 Call True seq_branch_adr 0210 0x0210 seq_cond_sel 18 TYP.ALU_ZERO(late) seq_en_micro 0 typ_a_adr 31 TR03:11 typ_alu_func 19 X_XOR_B typ_b_adr 0f GP0f typ_frame 3 3b98 3b98 fiu_len_fill_lit 5a zero-fill 0x1a; Flow J 0x3b99 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 23 fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_tvbs c mem+mem+csa+dummy seq_br_type 2 Push (branch address) seq_branch_adr 068d 0x068d seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_latch 1 typ_a_adr 0e GP0e typ_alu_func 1b A_OR_B typ_b_adr 24 TR12:04 typ_c_adr 31 GP0e typ_c_mux_sel 0 ALU typ_frame 12 val_a_adr 2a VR04:0a val_alu_func 1 A_PLUS_B val_b_adr 33 VR04:13 val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3b99 3b99 fiu_len_fill_lit 00 sign-fill 0x0; Flow J 0x3b9a fiu_load_var 1 hold_var fiu_offs_lit 20 fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 2 Push (branch address) seq_branch_adr 07b6 0x07b6 seq_en_micro 0 typ_a_adr 0f GP0f typ_alu_func 1a PASS_B typ_b_adr 21 TR02:01 typ_c_adr 1e TR02:01 typ_c_mux_sel 0 ALU typ_frame 2 typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 31 VR02:11 val_alu_func 1 A_PLUS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_frame 2 3b9a 3b9a fiu_len_fill_lit 5a zero-fill 0x1a; Flow J cc=True 0x3b9b ; Flow J cc=#0x0 0x3b9c fiu_load_tar 1 hold_tar fiu_mem_start 8 start_wr_if_false fiu_offs_lit 23 fiu_op_sel 3 insert fiu_rdata_src 0 rotator fiu_tivi_src a type_fiu ioc_fiubs 1 val ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type b Case False seq_branch_adr 3b9c 0x3b9c seq_cond_sel 56 SEQ.LATCHED_COND seq_en_micro 0 typ_a_adr 0e GP0e typ_alu_func 0 PASS_A typ_c_adr 1f TOP - 0x0 typ_c_mux_sel 0 ALU typ_frame 2 val_a_adr 0d GP0d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 33 GP0c val_c_mux_sel 2 ALU 3b9b 3b9b ioc_load_wdr 0 ; Flow R cc=False ; Flow J cc=True 0xbab ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 9 Return False seq_branch_adr 0bab 0x0bab seq_cond_sel 22 TYP.ALU_LT_ZERO(late) seq_en_micro 0 typ_a_adr 34 TR0d:14 typ_alu_func 3 LEFT_I_A typ_frame d val_b_adr 0c GP0c 3b9c 3b9c seq_b_timing 1 Latch Condition; Flow J cc=True 0x3b9c seq_br_type 1 Branch True seq_branch_adr 3b9c 0x3b9c seq_cond_sel 17 VAL.FALSE(early) seq_en_micro 0 seq_latch 1 seq_random 06 Pop_stack+? 3b9d 3b9d seq_br_type 7 Unconditional Call; Flow C 0x7b6 seq_branch_adr 07b6 0x07b6 seq_en_micro 0 3b9e 3b9e fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x36c1 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 36c1 0x36c1 seq_en_micro 0 seq_int_reads 6 CONTROL TOP val_a_adr 23 VR04:03 val_alu_func 0 PASS_A val_c_adr 1c VR04:03 val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3b9f 3b9f seq_br_type 7 Unconditional Call; Flow C 0x68d seq_branch_adr 068d 0x068d seq_en_micro 0 3ba0 3ba0 fiu_len_fill_lit 49 zero-fill 0x9; Flow C 0x3b8e fiu_load_var 1 hold_var fiu_offs_lit 16 fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var fiu_vmux_sel 1 fill value ioc_load_wdr 0 ioc_tvbs 1 typ+fiu seq_br_type 7 Unconditional Call seq_branch_adr 3b8e 0x3b8e seq_en_micro 0 typ_a_adr 31 TR03:11 typ_alu_func 0 PASS_A typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_frame 3 val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3ba1 3ba1 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val ioc_tvbs 5 seq+seq seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_int_reads 6 CONTROL TOP seq_latch 1 typ_a_adr 10 TOP typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_lit 1 typ_c_mux_sel 0 ALU typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand b CARRY IN = Q BIT FROM VAL val_alu_func 1a PASS_B val_b_adr 10 TOP 3ba2 3ba2 fiu_len_fill_lit 4c zero-fill 0xc; Flow J cc=False 0x3ba4 fiu_load_var 1 hold_var fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_tvbs 8 typ+mem seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3ba4 0x3ba4 seq_en_micro 0 typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_mux_sel 2 ALU 3ba3 3ba3 fiu_mem_start 3 start-wr; Flow J cc=False 0x3ba0 fiu_tivi_src 4 fiu_var ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_b_timing 3 Late Condition, Hint False seq_br_type 0 Branch False seq_branch_adr 3ba0 0x3ba0 seq_cond_sel 58 (VAL.ALU_ZERO(late)) nand (TYP.ALU_ZERO(late)) seq_en_micro 0 typ_a_adr 34 TR06:14 typ_alu_func 1d A_AND_NOT_B typ_b_adr 16 CSA/VAL_BUS typ_frame 6 val_alu_func 1e A_AND_B val_b_adr 3d VR02:1d val_frame 2 3ba4 3ba4 fiu_mem_start 2 start-rd; Flow R ioc_adrbs 3 seq seq_br_type e Unconditional Dispatch seq_cond_sel 68 CONTROL_ADDRESS_OUT_OF_RANGE seq_en_micro 0 seq_random 04 Load_save_offset+? typ_csa_cntl 3 POP_CSA typ_mar_cntl e LOAD_MAR_CONTROL 3ba5 ; -------------------------------------------------------------------------------------- 3ba5 ; Comes from: 3ba5 ; 0410 C from color 0x0410 3ba5 ; 0627 C from color 0x0627 3ba5 ; 0687 C from color 0x0687 3ba5 ; 07eb C from color 0x07e8 3ba5 ; 38fe C from color 0x38e7 3ba5 ; 3914 C from color 0x3914 3ba5 ; -------------------------------------------------------------------------------------- 3ba5 3ba5 fiu_tivi_src c mar_0xc; Flow R cc=False fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 1 typ+fiu seq_br_type 9 Return False seq_branch_adr 3ba6 0x3ba6 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 14 ZEROS typ_b_adr 30 TR03:10 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 3 val_a_adr 14 ZEROS val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_rand a PASS_B_HIGH 3ba6 3ba6 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 1b TR0d:04 typ_c_mux_sel 0 ALU typ_frame d val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 1b VR0d:04 val_c_mux_sel 2 ALU val_frame d 3ba7 3ba7 fiu_mem_start 5 start_rd_if_true; Flow C 0x3bb0 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3bb0 0x3bb0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 30 TR03:10 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 2f VR11:0f val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 11 3ba8 3ba8 seq_br_type 3 Unconditional Branch; Flow J 0x3ba7 seq_branch_adr 3ba7 0x3ba7 seq_en_micro 0 typ_b_adr 0b GP0b typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT 3ba9 3ba9 fiu_len_fill_lit 75 zero-fill 0x35; Flow C 0xd5a fiu_len_fill_reg_ctl 1 len=literal, fill=literal fiu_load_oreg 1 hold_oreg fiu_mem_start 2 start-rd fiu_oreg_src 0 rotator output ioc_adrbs 1 val seq_br_type 7 Unconditional Call seq_branch_adr 0d5a 0x0d5a seq_cond_sel 17 VAL.FALSE(early) seq_latch 1 typ_b_adr 10 TOP typ_c_lit 1 typ_frame 4 typ_mar_cntl b LOAD_MAR_DATA typ_rand 1 INC_LOOP_COUNTER val_alu_func 1a PASS_B val_b_adr 10 TOP 3baa 3baa fiu_len_fill_lit 4c zero-fill 0xc; Flow J 0x3bab fiu_offs_lit 33 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu seq_br_type 2 Push (branch address) seq_branch_adr 3ba4 0x3ba4 seq_en_micro 0 typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU val_c_adr 32 GP0d val_c_source 0 FIU_BUS 3bab 3bab fiu_mem_start 5 start_rd_if_true; Flow C 0x3bb0 fiu_tivi_src 4 fiu_var ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs 2 fiu+val seq_br_type 7 Unconditional Call seq_branch_adr 3bb0 0x3bb0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 31 TR03:11 typ_alu_func 1a PASS_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 2f VR11:0f val_alu_func 13 ONES val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 11 3bac 3bac seq_br_type 3 Unconditional Branch; Flow J 0x3bab seq_branch_adr 3bab 0x3bab seq_en_micro 0 typ_b_adr 0b GP0b typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT 3bad 3bad ioc_load_wdr 0 ; Flow C 0x2ab4 seq_b_timing 3 Late Condition, Hint False seq_br_type 5 Call True seq_branch_adr 2ab4 0x2ab4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 typ_b_adr 0b GP0b val_b_adr 0b GP0b 3bae 3bae fiu_mem_start 5 start_rd_if_true; Flow J 0x3bb0 ioc_adrbs 2 typ seq_br_type 3 Unconditional Branch seq_branch_adr 3bb0 0x3bb0 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 0b GP0b typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT 3baf 3baf fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_mem_start 5 start_rd_if_true fiu_rdata_src 0 rotator fiu_tivi_src 8 type_var ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 23 TR11:03 typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_source 0 FIU_BUS typ_frame 11 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 34 GP0b val_c_mux_sel 2 ALU 3bb0 ; -------------------------------------------------------------------------------------- 3bb0 ; Comes from: 3bb0 ; 3ba7 C from color 0x0000 3bb0 ; 3bab C from color 0x3ba9 3bb0 ; -------------------------------------------------------------------------------------- 3bb0 3bb0 seq_b_timing 1 Latch Condition; Flow J cc=False 0x3bb8 seq_br_type 0 Branch False seq_branch_adr 3bb8 0x3bb8 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 seq_latch 1 val_a_adr 33 VR04:13 val_alu_func 1e A_AND_B val_b_adr 0c GP0c val_c_adr 33 GP0c val_c_mux_sel 2 ALU val_frame 4 3bb1 3bb1 fiu_len_fill_lit 3f sign-fill 0x3f; Flow C 0x210 fiu_load_mdr 1 hold_mdr fiu_mem_start 2 start-rd fiu_offs_lit 40 fiu_rdata_src 0 rotator fiu_tivi_src 2 tar_fiu ioc_adrbs 2 typ ioc_fiubs 1 val ioc_tvbs c mem+mem+csa+dummy seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 1a PASS_B typ_b_adr 20 TR00:00 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 14 ZEROS val_alu_func 1a PASS_B val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_c_mux_sel 2 ALU 3bb2 3bb2 fiu_mem_start 4 continue; Flow J cc=True 0x3bad fiu_tivi_src c mar_0xc ioc_fiubs 0 fiu ioc_load_wdr 0 seq_b_timing 1 Latch Condition seq_br_type 1 Branch True seq_branch_adr 3bad 0x3bad seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_latch 1 typ_b_adr 0d GP0d typ_mar_cntl 6 INCREMENT_MAR val_a_adr 0d GP0d val_alu_func 19 X_XOR_B val_b_adr 0f GP0f val_c_adr 30 GP0f val_c_source 0 FIU_BUS 3bb3 3bb3 fiu_len_fill_lit 41 zero-fill 0x1; Flow J cc=False 0x3baf fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_offs_lit 13 fiu_op_sel 3 insert fiu_tivi_src 9 type_val ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 0 Branch False seq_branch_adr 3baf 0x3baf seq_cond_sel 60 FIU.MEM_EXCEPTION~ seq_en_micro 0 seq_latch 1 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_c_adr 32 GP0d typ_c_mux_sel 0 ALU 3bb4 3bb4 fiu_len_fill_lit 43 zero-fill 0x3; Flow C 0x210 fiu_mem_start 3 start-wr fiu_offs_lit 1c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 1 val ioc_fiubs 0 fiu ioc_tvbs c mem+mem+csa+dummy seq_b_timing 1 Latch Condition seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_en_micro 0 typ_a_adr 0b GP0b typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 34 GP0b typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0f GP0f val_alu_func 1a PASS_B val_b_adr 2e VR04:0e val_c_adr 30 GP0f val_c_source 0 FIU_BUS val_frame 4 val_rand 9 PASS_A_HIGH 3bb5 3bb5 fiu_load_oreg 1 hold_oreg ioc_load_wdr 0 ioc_tvbs 3 fiu+fiu seq_en_micro 0 typ_c_adr 32 GP0d val_a_adr 0f GP0f val_alu_func 1 A_PLUS_B val_b_adr 3f VR02:1f val_c_adr 30 GP0f val_c_mux_sel 2 ALU val_frame 2 3bb6 3bb6 ioc_fiubs 1 val ; Flow C 0x6b7 seq_br_type 7 Unconditional Call seq_branch_adr 06b7 0x06b7 seq_en_micro 0 typ_c_adr 28 LOOP_COUNTER typ_c_source 0 FIU_BUS val_a_adr 0f GP0f 3bb7 3bb7 fiu_mem_start 7 start_wr_if_true; Flow R cc=False ; Flow J cc=True 0x3bad ioc_adrbs 2 typ seq_br_type 9 Return False seq_branch_adr 3bad 0x3bad seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 typ_a_adr 3f TR02:1f typ_alu_func 0 PASS_A typ_b_adr 0d GP0d typ_frame 2 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 0c GP0c val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3bb8 3bb8 fiu_load_tar 1 hold_tar; Flow J 0x3b7d fiu_load_var 1 hold_var fiu_tivi_src 9 type_val seq_br_type 3 Unconditional Branch seq_branch_adr 3b7d 0x3b7d seq_cond_sel 64 OFFSET_REGISTER_???? seq_en_micro 0 seq_latch 1 seq_random 06 Pop_stack+? typ_b_adr 24 TR0d:04 typ_frame d val_b_adr 24 VR0d:04 val_frame d 3bb9 3bb9 fiu_mem_start 11 start_tag_query; Flow C 0x3bbd fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3bbd 0x3bbd seq_en_micro 0 typ_a_adr 31 TR03:11 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_a_adr 33 VR04:13 val_alu_func 0 PASS_A val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_frame 4 val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3bba 3bba ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0e TR03:11 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3bbb 3bbb fiu_mem_start 11 start_tag_query; Flow C 0x3bbd fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_br_type 7 Unconditional Call seq_branch_adr 3bbd 0x3bbd seq_en_micro 0 typ_a_adr 30 TR03:10 typ_c_adr 32 GP0d typ_c_source 0 FIU_BUS typ_frame 3 typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 6 CHECK_CLASS_A_??_B val_c_adr 32 GP0d val_c_mux_sel 2 ALU val_c_source 0 FIU_BUS val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3bbc 3bbc ioc_tvbs c mem+mem+csa+dummy; Flow R seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 16 CSA/VAL_BUS typ_c_adr 0f TR03:10 typ_c_mux_sel 0 ALU typ_frame 3 typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3bbd ; -------------------------------------------------------------------------------------- 3bbd ; Comes from: 3bbd ; 3bb9 C from color 0x36d0 3bbd ; 3bbb C from color 0x36d3 3bbd ; -------------------------------------------------------------------------------------- 3bbd 3bbd fiu_tivi_src c mar_0xc ioc_tvbs 1 typ+fiu seq_cond_sel 10 VAL.ALU_32_ZERO(late) seq_en_micro 0 seq_latch 1 val_a_adr 0d GP0d val_alu_func 19 X_XOR_B val_b_adr 16 CSA/VAL_BUS 3bbe 3bbe fiu_mem_start d start_physical_rd; Flow C 0x210 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_frame 4 val_rand a PASS_B_HIGH 3bbf 3bbf ioc_fiubs 1 val ; Flow R cc=True seq_b_timing 1 Latch Condition seq_br_type 8 Return True seq_branch_adr 3bc0 0x3bc0 seq_en_micro 0 val_a_adr 0d GP0d val_c_adr 31 GP0e val_c_mux_sel 2 ALU val_rand 4 SPLIT_C_SOURCE (C_SRC HI, NON-C_SRC LO) 3bc0 3bc0 fiu_mem_start 11 start_tag_query fiu_tivi_src c mar_0xc ioc_adrbs 2 typ ioc_fiubs 0 fiu ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_cond_sel 31 TYP.PRIVACY_NAMES_EQ (med_late) seq_en_micro 0 seq_latch 1 typ_a_adr 0d GP0d typ_b_adr 16 CSA/VAL_BUS typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_c_adr 32 GP0d val_c_source 0 FIU_BUS 3bc1 3bc1 seq_b_timing 3 Late Condition, Hint False; Flow J cc=False 0x3bc4 seq_br_type 0 Branch False seq_branch_adr 3bc4 0x3bc4 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 val_a_adr 2a VR04:0a val_alu_func 6 A_MINUS_B val_b_adr 0e GP0e val_c_adr 15 VR04:0a val_c_mux_sel 2 ALU val_frame 4 3bc2 3bc2 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 seq_en_micro 0 3bc3 3bc3 fiu_mem_start 11 start_tag_query; Flow C 0x3b7d seq_br_type 7 Unconditional Call seq_branch_adr 3b7d 0x3b7d seq_en_micro 0 3bc4 3bc4 fiu_mem_start d start_physical_rd; Flow C 0x210 fiu_tivi_src 3 tar_frame ioc_adrbs 1 val ioc_tvbs 1 typ+fiu seq_br_type 4 Call False seq_branch_adr 0210 0x0210 seq_cond_sel 6b CACHE_MISS~ seq_en_micro 0 typ_c_adr 30 GP0f typ_mar_cntl e LOAD_MAR_CONTROL val_a_adr 2f VR04:0f val_alu_func 0 PASS_A val_b_adr 16 CSA/VAL_BUS val_c_adr 30 GP0f val_frame 4 val_rand a PASS_B_HIGH 3bc5 3bc5 seq_b_timing 1 Latch Condition; Flow J cc=True 0x3bc0 seq_br_type 1 Branch True seq_branch_adr 3bc0 0x3bc0 seq_en_micro 0 val_c_adr 31 GP0e val_c_mux_sel 2 ALU 3bc6 3bc6 fiu_mem_start e start_physical_wr ioc_adrbs 1 val ioc_tvbs c mem+mem+csa+dummy seq_en_micro 0 seq_random 06 Pop_stack+? typ_a_adr 0f GP0f typ_alu_func 0 PASS_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 30 GP0f typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 5 CHECK_CLASS_B_LIT val_a_adr 0d GP0d val_alu_func 0 PASS_A 3bc7 3bc7 ioc_load_wdr 0 ; Flow R seq_br_type a Unconditional Return seq_cond_sel 45 SEQ.saved_latched_cond seq_en_micro 0 seq_latch 1 typ_b_adr 0f GP0f val_b_adr 0f GP0f 3bc8 3bc8 fiu_len_fill_lit 58 zero-fill 0x18; Flow J cc=True 0x3bca fiu_offs_lit 60 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu ioc_tvbs 5 seq+seq seq_br_type 1 Branch True seq_branch_adr 3bca 0x3bca seq_cond_sel 00 VAL.ALU_ZERO(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 6a ? typ_a_adr 26 TR05:06 typ_alu_func 1e A_AND_B typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3f GP00 typ_c_mux_sel 0 ALU typ_csa_cntl 3 POP_CSA typ_frame 5 val_a_adr 2a VR05:0a val_alu_func 1e A_AND_B val_b_adr 16 CSA/VAL_BUS val_c_adr 3f GP00 val_c_source 0 FIU_BUS val_frame 5 3bc9 3bc9 seq_en_micro 0 seq_lex_adr 3 seq_random 6a ? 3bca 3bca fiu_len_fill_lit 78 zero-fill 0x38; Flow C 0x32f5 fiu_load_tar 1 hold_tar fiu_load_var 1 hold_var fiu_mem_start 2 start-rd fiu_rdata_src 0 rotator fiu_tivi_src 9 type_val fiu_vmux_sel 1 fill value ioc_adrbs 3 seq ioc_fiubs 1 val ioc_tvbs 5 seq+seq seq_br_type 4 Call False seq_branch_adr 32f5 0x32f5 seq_cond_sel 02 VAL.ALU_A_LT_OR_LE_B(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_random 15 ? typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 23 TR05:03 typ_c_adr 3e GP01 typ_c_mux_sel 0 ALU typ_frame 5 typ_mar_cntl 9 LOAD_MAR_CODE val_alu_func 5 DEC_A_MINUS_B val_b_adr 20 VR09:00 val_frame 9 3bcb 3bcb fiu_len_fill_lit 78 zero-fill 0x38; Flow J cc=True 0x3bcc ; Flow C cc=#0x0 0x3bd9 fiu_load_oreg 1 hold_oreg fiu_offs_lit 40 fiu_op_sel 3 insert fiu_oreg_src 0 rotator output fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_adrbs 2 typ ioc_fiubs 0 fiu seq_b_timing 3 Late Condition, Hint False seq_br_type b Case False seq_branch_adr 3bd9 0x3bd9 seq_cond_sel 20 TYP.ALU_CARRY(late) seq_en_micro 0 seq_int_reads 6 CONTROL TOP seq_lex_adr 1 seq_random 6a ? typ_a_adr 01 GP01 typ_alu_func 5 DEC_A_MINUS_B typ_b_adr 31 TR02:11 typ_c_adr 3c GP03 typ_c_source 0 FIU_BUS typ_frame 2 3bcc 3bcc fiu_len_fill_lit 4a zero-fill 0xa; Flow J cc=True 0x3bd2 fiu_offs_lit 3c fiu_rdata_src 0 rotator fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu seq_br_type 1 Branch True seq_branch_adr 3bd2 0x3bd2 seq_cond_sel 1a TYP.ALU_A_GT_OR_GE_B(late) typ_a_adr 01 GP01 typ_alu_func 6 A_MINUS_B typ_b_adr 32 TR02:12 typ_c_adr 3d GP02 typ_c_source 0 FIU_BUS typ_frame 2 3bcd 3bcd fiu_mem_start 2 start-rd ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL 3bce 3bce typ_a_adr 01 GP01 typ_alu_func 10 NOT_A typ_c_adr 28 LOOP_COUNTER typ_c_mux_sel 0 ALU 3bcf 3bcf fiu_mem_start 6 start_rd_if_false; Flow J cc=True 0x3bd1 ioc_adrbs 2 typ ioc_load_wdr 0 ioc_tvbs c mem+mem+csa+dummy seq_b_timing 0 Early Condition seq_br_type 1 Branch True seq_branch_adr 3bd1 0x3bd1 seq_cond_sel 1c TYP.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 1c DEC_A typ_b_adr 16 CSA/VAL_BUS typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP val_b_adr 16 CSA/VAL_BUS 3bd0 3bd0 seq_br_type 3 Unconditional Branch; Flow J 0x3bcf seq_branch_adr 3bcf 0x3bcf seq_en_micro 0 typ_c_adr 2b BOT - 1 typ_csa_cntl 4 DEC_CSA_BOTTOM typ_rand d SET_PASS_PRIVACY_BIT val_c_adr 2b BOT - 1 3bd1 3bd1 fiu_mem_start 2 start-rd; Flow J 0x3bd6 ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3bd6 0x3bd6 seq_en_micro 0 seq_random 15 ? typ_c_adr 2b BOT - 1 typ_csa_cntl 4 DEC_CSA_BOTTOM typ_mar_cntl 9 LOAD_MAR_CODE val_c_adr 2b BOT - 1 3bd2 3bd2 fiu_len_fill_lit 46 zero-fill 0x6 fiu_offs_lit 79 fiu_rdata_src 0 rotator fiu_tivi_src c mar_0xc fiu_vmux_sel 1 fill value ioc_fiubs 0 fiu typ_a_adr 03 GP03 typ_alu_func 6 A_MINUS_B typ_b_adr 02 GP02 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU val_c_adr 28 LOOP_COUNTER val_c_source 0 FIU_BUS 3bd3 3bd3 fiu_mem_start 3 start-wr ioc_adrbs 2 typ typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_csa_cntl 5 INC_CSA_BOTTOM typ_mar_cntl e LOAD_MAR_CONTROL typ_rand 0 NO_OP 3bd4 3bd4 ioc_load_wdr 0 ; Flow J cc=False 0x3bd3 seq_b_timing 0 Early Condition seq_br_type 0 Branch False seq_branch_adr 3bd3 0x3bd3 seq_cond_sel 04 VAL.LOOP_COUNTER_ZERO(early) typ_a_adr 03 GP03 typ_alu_func 7 INC_A typ_b_adr 14 BOT - 1 typ_c_adr 3c GP03 typ_c_mux_sel 0 ALU typ_rand 0 NO_OP val_b_adr 14 BOT - 1 val_rand 2 DEC_LOOP_COUNTER 3bd5 3bd5 fiu_mem_start 2 start-rd; Flow J 0x3bd6 ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3bd6 0x3bd6 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 3bd6 3bd6 seq_b_timing 3 Late Condition, Hint False; Flow J cc=True 0x3bd7 ; Flow C cc=#0x0 0x3bd9 seq_br_type b Case False seq_branch_adr 3bd9 0x3bd9 seq_cond_sel 67 REFRESH_MACRO_EVENT seq_en_micro 0 3bd7 3bd7 seq_br_type 7 Unconditional Call; Flow C 0x2ab4 seq_branch_adr 2ab4 0x2ab4 3bd8 3bd8 fiu_mem_start 2 start-rd; Flow J 0x3bd6 ioc_adrbs 3 seq ioc_fiubs 1 val seq_br_type 3 Unconditional Branch seq_branch_adr 3bd6 0x3bd6 seq_random 15 ? typ_mar_cntl 9 LOAD_MAR_CODE 3bd9 ; -------------------------------------------------------------------------------------- 3bd9 ; Comes from: 3bd9 ; 3bcb C #0x0 from color 0x3bcb 3bd9 ; 3bd6 C #0x0 from color 0x3bcb 3bd9 ; -------------------------------------------------------------------------------------- 3bd9 3bd9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdfb seq_br_type 3 Unconditional Branch seq_branch_adr 0dfb 0x0dfb seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bda 3bda ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe06 seq_br_type 3 Unconditional Branch seq_branch_adr 0e06 0x0e06 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bdb 3bdb ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe09 seq_br_type 3 Unconditional Branch seq_branch_adr 0e09 0x0e09 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bdc 3bdc ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd6b seq_br_type 3 Unconditional Branch seq_branch_adr 0d6b 0x0d6b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bdd 3bdd ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe7b seq_br_type 3 Unconditional Branch seq_branch_adr 0e7b 0x0e7b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bde 3bde ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe17 seq_br_type 3 Unconditional Branch seq_branch_adr 0e17 0x0e17 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bdf 3bdf ioc_tvbs c mem+mem+csa+dummy; Flow J 0xf0c seq_br_type 3 Unconditional Branch seq_branch_adr 0f0c 0x0f0c seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be0 3be0 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd8f seq_br_type 3 Unconditional Branch seq_branch_adr 0d8f 0x0d8f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be1 3be1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe1b seq_br_type 3 Unconditional Branch seq_branch_adr 0e1b 0x0e1b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be2 3be2 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe26 seq_br_type 3 Unconditional Branch seq_branch_adr 0e26 0x0e26 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be3 3be3 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe29 seq_br_type 3 Unconditional Branch seq_branch_adr 0e29 0x0e29 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be4 3be4 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe2b seq_br_type 3 Unconditional Branch seq_branch_adr 0e2b 0x0e2b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be5 3be5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe42 seq_br_type 3 Unconditional Branch seq_branch_adr 0e42 0x0e42 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be6 3be6 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe50 seq_br_type 3 Unconditional Branch seq_branch_adr 0e50 0x0e50 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be7 3be7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe82 seq_br_type 3 Unconditional Branch seq_branch_adr 0e82 0x0e82 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be8 3be8 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe5e seq_br_type 3 Unconditional Branch seq_branch_adr 0e5e 0x0e5e seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3be9 3be9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe63 seq_br_type 3 Unconditional Branch seq_branch_adr 0e63 0x0e63 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bea 3bea ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe68 seq_br_type 3 Unconditional Branch seq_branch_adr 0e68 0x0e68 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3beb 3beb ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe8a seq_br_type 3 Unconditional Branch seq_branch_adr 0e8a 0x0e8a seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bec 3bec ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe6a seq_br_type 3 Unconditional Branch seq_branch_adr 0e6a 0x0e6a seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bed 3bed ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe6e seq_br_type 3 Unconditional Branch seq_branch_adr 0e6e 0x0e6e seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bee 3bee ioc_tvbs c mem+mem+csa+dummy; Flow J 0x883 seq_br_type 3 Unconditional Branch seq_branch_adr 0883 0x0883 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bef 3bef ioc_tvbs c mem+mem+csa+dummy; Flow J 0xef7 seq_br_type 3 Unconditional Branch seq_branch_adr 0ef7 0x0ef7 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf0 3bf0 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xf17 seq_br_type 3 Unconditional Branch seq_branch_adr 0f17 0x0f17 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf1 3bf1 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xf1a seq_br_type 3 Unconditional Branch seq_branch_adr 0f1a 0x0f1a seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf2 3bf2 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xefc seq_br_type 3 Unconditional Branch seq_branch_adr 0efc 0x0efc seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf3 3bf3 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xefd seq_br_type 3 Unconditional Branch seq_branch_adr 0efd 0x0efd seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf4 3bf4 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xf00 seq_br_type 3 Unconditional Branch seq_branch_adr 0f00 0x0f00 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf5 3bf5 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xece seq_br_type 3 Unconditional Branch seq_branch_adr 0ece 0x0ece seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf6 3bf6 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x799 seq_br_type 3 Unconditional Branch seq_branch_adr 0799 0x0799 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf7 3bf7 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3689 seq_br_type 3 Unconditional Branch seq_branch_adr 3689 0x3689 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf8 3bf8 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xf07 seq_br_type 3 Unconditional Branch seq_branch_adr 0f07 0x0f07 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bf9 3bf9 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d26 seq_br_type 3 Unconditional Branch seq_branch_adr 2d26 0x2d26 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfa 3bfa ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d49 seq_br_type 3 Unconditional Branch seq_branch_adr 2d49 0x2d49 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfb 3bfb ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d2d seq_br_type 3 Unconditional Branch seq_branch_adr 2d2d 0x2d2d seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfc 3bfc ioc_tvbs c mem+mem+csa+dummy; Flow J 0x345 seq_br_type 3 Unconditional Branch seq_branch_adr 0345 0x0345 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfd 3bfd ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe11 seq_br_type 3 Unconditional Branch seq_branch_adr 0e11 0x0e11 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bfe 3bfe ioc_tvbs c mem+mem+csa+dummy; Flow J 0xf12 seq_br_type 3 Unconditional Branch seq_branch_adr 0f12 0x0f12 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3bff 3bff ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd95 seq_br_type 3 Unconditional Branch seq_branch_adr 0d95 0x0d95 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c00 3c00 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdf3 seq_br_type 3 Unconditional Branch seq_branch_adr 0df3 0x0df3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c01 3c01 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xda5 seq_br_type 3 Unconditional Branch seq_branch_adr 0da5 0x0da5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c02 3c02 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xeb6 seq_br_type 3 Unconditional Branch seq_branch_adr 0eb6 0x0eb6 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c03 3c03 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xec7 seq_br_type 3 Unconditional Branch seq_branch_adr 0ec7 0x0ec7 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c04 3c04 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe84 seq_br_type 3 Unconditional Branch seq_branch_adr 0e84 0x0e84 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c05 3c05 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xf0b seq_br_type 3 Unconditional Branch seq_branch_adr 0f0b 0x0f0b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c06 3c06 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x334 seq_br_type 3 Unconditional Branch seq_branch_adr 0334 0x0334 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c07 3c07 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe70 seq_br_type 3 Unconditional Branch seq_branch_adr 0e70 0x0e70 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c08 3c08 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe0b seq_br_type 3 Unconditional Branch seq_branch_adr 0e0b 0x0e0b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c09 3c09 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x87b seq_br_type 3 Unconditional Branch seq_branch_adr 087b 0x087b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0a 3c0a ioc_tvbs c mem+mem+csa+dummy; Flow J 0x903 seq_br_type 3 Unconditional Branch seq_branch_adr 0903 0x0903 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0b 3c0b ioc_tvbs c mem+mem+csa+dummy; Flow J 0x905 seq_br_type 3 Unconditional Branch seq_branch_adr 0905 0x0905 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0c 3c0c ioc_tvbs c mem+mem+csa+dummy; Flow J 0xb38 seq_br_type 3 Unconditional Branch seq_branch_adr 0b38 0x0b38 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0d 3c0d ioc_tvbs c mem+mem+csa+dummy; Flow J 0x913 seq_br_type 3 Unconditional Branch seq_branch_adr 0913 0x0913 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0e 3c0e ioc_tvbs c mem+mem+csa+dummy; Flow J 0x917 seq_br_type 3 Unconditional Branch seq_branch_adr 0917 0x0917 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c0f 3c0f ioc_tvbs c mem+mem+csa+dummy; Flow J 0xf09 seq_br_type 3 Unconditional Branch seq_branch_adr 0f09 0x0f09 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c10 3c10 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3698 seq_br_type 3 Unconditional Branch seq_branch_adr 3698 0x3698 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c11 3c11 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d29 seq_br_type 3 Unconditional Branch seq_branch_adr 2d29 0x2d29 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c12 3c12 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe81 seq_br_type 3 Unconditional Branch seq_branch_adr 0e81 0x0e81 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c13 3c13 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xea1 seq_br_type 3 Unconditional Branch seq_branch_adr 0ea1 0x0ea1 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c14 3c14 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xeb0 seq_br_type 3 Unconditional Branch seq_branch_adr 0eb0 0x0eb0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c15 3c15 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x919 seq_br_type 3 Unconditional Branch seq_branch_adr 0919 0x0919 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c16 3c16 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x977 seq_br_type 3 Unconditional Branch seq_branch_adr 0977 0x0977 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c17 3c17 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d2a seq_br_type 3 Unconditional Branch seq_branch_adr 2d2a 0x2d2a seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c18 3c18 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xea9 seq_br_type 3 Unconditional Branch seq_branch_adr 0ea9 0x0ea9 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c19 3c19 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2def seq_br_type 3 Unconditional Branch seq_branch_adr 2def 0x2def seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1a 3c1a ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d38 seq_br_type 3 Unconditional Branch seq_branch_adr 2d38 0x2d38 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1b 3c1b ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d40 seq_br_type 3 Unconditional Branch seq_branch_adr 2d40 0x2d40 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1c 3c1c ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d43 seq_br_type 3 Unconditional Branch seq_branch_adr 2d43 0x2d43 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1d 3c1d ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3606 seq_br_type 3 Unconditional Branch seq_branch_adr 3606 0x3606 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1e 3c1e ioc_tvbs c mem+mem+csa+dummy; Flow J 0x360b seq_br_type 3 Unconditional Branch seq_branch_adr 360b 0x360b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c1f 3c1f ioc_tvbs c mem+mem+csa+dummy; Flow J 0xb70 seq_br_type 3 Unconditional Branch seq_branch_adr 0b70 0x0b70 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c20 3c20 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3600 seq_br_type 3 Unconditional Branch seq_branch_adr 3600 0x3600 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c21 3c21 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d33 seq_br_type 3 Unconditional Branch seq_branch_adr 2d33 0x2d33 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c22 3c22 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d35 seq_br_type 3 Unconditional Branch seq_branch_adr 2d35 0x2d35 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c23 3c23 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3ba1 seq_br_type 3 Unconditional Branch seq_branch_adr 3ba1 0x3ba1 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c24 3c24 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x3ba9 seq_br_type 3 Unconditional Branch seq_branch_adr 3ba9 0x3ba9 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c25 3c25 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x95c seq_br_type 3 Unconditional Branch seq_branch_adr 095c 0x095c seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c26 3c26 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xb31 seq_br_type 3 Unconditional Branch seq_branch_adr 0b31 0x0b31 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c27 3c27 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d2b seq_br_type 3 Unconditional Branch seq_branch_adr 2d2b 0x2d2b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c28 3c28 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35dc seq_br_type 3 Unconditional Branch seq_branch_adr 35dc 0x35dc seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c29 3c29 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35e4 seq_br_type 3 Unconditional Branch seq_branch_adr 35e4 0x35e4 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c2a 3c2a ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35ed seq_br_type 3 Unconditional Branch seq_branch_adr 35ed 0x35ed seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c2b 3c2b ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35e1 seq_br_type 3 Unconditional Branch seq_branch_adr 35e1 0x35e1 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c2c 3c2c ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d30 seq_br_type 3 Unconditional Branch seq_branch_adr 2d30 0x2d30 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c2d 3c2d ioc_tvbs c mem+mem+csa+dummy; Flow J 0xd7f seq_br_type 3 Unconditional Branch seq_branch_adr 0d7f 0x0d7f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c2e 3c2e ioc_tvbs c mem+mem+csa+dummy; Flow J 0xeff seq_br_type 3 Unconditional Branch seq_branch_adr 0eff 0x0eff seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c2f 3c2f ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2c11 seq_br_type 3 Unconditional Branch seq_branch_adr 2c11 0x2c11 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c30 3c30 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xeb3 seq_br_type 3 Unconditional Branch seq_branch_adr 0eb3 0x0eb3 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c31 3c31 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x360f seq_br_type 3 Unconditional Branch seq_branch_adr 360f 0x360f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c32 3c32 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x35f7 seq_br_type 3 Unconditional Branch seq_branch_adr 35f7 0x35f7 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c33 3c33 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x767 seq_br_type 3 Unconditional Branch seq_branch_adr 0767 0x0767 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c34 3c34 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x776 seq_br_type 3 Unconditional Branch seq_branch_adr 0776 0x0776 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c35 3c35 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x774 seq_br_type 3 Unconditional Branch seq_branch_adr 0774 0x0774 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c36 3c36 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x784 seq_br_type 3 Unconditional Branch seq_branch_adr 0784 0x0784 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c37 3c37 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x775 seq_br_type 3 Unconditional Branch seq_branch_adr 0775 0x0775 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c38 3c38 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xb95 seq_br_type 3 Unconditional Branch seq_branch_adr 0b95 0x0b95 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c39 3c39 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xf05 seq_br_type 3 Unconditional Branch seq_branch_adr 0f05 0x0f05 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c3a 3c3a ioc_tvbs c mem+mem+csa+dummy; Flow J 0x34f seq_br_type 3 Unconditional Branch seq_branch_adr 034f 0x034f seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c3b 3c3b ioc_tvbs c mem+mem+csa+dummy; Flow J 0x36a seq_br_type 3 Unconditional Branch seq_branch_adr 036a 0x036a seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c3c 3c3c ioc_tvbs c mem+mem+csa+dummy; Flow J 0x36c seq_br_type 3 Unconditional Branch seq_branch_adr 036c 0x036c seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c3d 3c3d ioc_tvbs c mem+mem+csa+dummy; Flow J 0x377 seq_br_type 3 Unconditional Branch seq_branch_adr 0377 0x0377 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c3e 3c3e ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d51 seq_br_type 3 Unconditional Branch seq_branch_adr 2d51 0x2d51 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c3f 3c3f ioc_tvbs c mem+mem+csa+dummy; Flow J 0x349 seq_br_type 3 Unconditional Branch seq_branch_adr 0349 0x0349 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c40 3c40 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x794 seq_br_type 3 Unconditional Branch seq_branch_adr 0794 0x0794 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c41 3c41 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xf14 seq_br_type 3 Unconditional Branch seq_branch_adr 0f14 0x0f14 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c42 3c42 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xecc seq_br_type 3 Unconditional Branch seq_branch_adr 0ecc 0x0ecc seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c43 3c43 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2d0e seq_br_type 3 Unconditional Branch seq_branch_adr 2d0e 0x2d0e seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c44 3c44 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xf06 seq_br_type 3 Unconditional Branch seq_branch_adr 0f06 0x0f06 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c45 3c45 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xf1b seq_br_type 3 Unconditional Branch seq_branch_adr 0f1b 0x0f1b seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c46 3c46 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xf1d seq_br_type 3 Unconditional Branch seq_branch_adr 0f1d 0x0f1d seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c47 3c47 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xdd0 seq_br_type 3 Unconditional Branch seq_branch_adr 0dd0 0x0dd0 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c48 3c48 ioc_tvbs c mem+mem+csa+dummy; Flow J 0x2e04 seq_br_type 3 Unconditional Branch seq_branch_adr 2e04 0x2e04 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c49 3c49 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xde4 seq_br_type 3 Unconditional Branch seq_branch_adr 0de4 0x0de4 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c4a 3c4a ioc_tvbs c mem+mem+csa+dummy; Flow C 0x32f5 seq_br_type 3 Unconditional Branch seq_branch_adr 32f5 0x32f5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c4b 3c4b ioc_tvbs c mem+mem+csa+dummy; Flow C 0x32f5 seq_br_type 3 Unconditional Branch seq_branch_adr 32f5 0x32f5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c4c 3c4c ioc_tvbs c mem+mem+csa+dummy; Flow C 0x32f5 seq_br_type 3 Unconditional Branch seq_branch_adr 32f5 0x32f5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c4d 3c4d ioc_tvbs c mem+mem+csa+dummy; Flow C 0x32f5 seq_br_type 3 Unconditional Branch seq_branch_adr 32f5 0x32f5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c4e 3c4e ioc_tvbs c mem+mem+csa+dummy; Flow C 0x32f5 seq_br_type 3 Unconditional Branch seq_branch_adr 32f5 0x32f5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c4f 3c4f ioc_tvbs c mem+mem+csa+dummy; Flow C 0x32f5 seq_br_type 3 Unconditional Branch seq_branch_adr 32f5 0x32f5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c50 3c50 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x32f5 seq_br_type 3 Unconditional Branch seq_branch_adr 32f5 0x32f5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c51 3c51 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x32f5 seq_br_type 3 Unconditional Branch seq_branch_adr 32f5 0x32f5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c52 3c52 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x32f5 seq_br_type 3 Unconditional Branch seq_branch_adr 32f5 0x32f5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c53 3c53 ioc_tvbs c mem+mem+csa+dummy; Flow J 0xe88 seq_br_type 3 Unconditional Branch seq_branch_adr 0e88 0x0e88 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c54 3c54 ioc_tvbs c mem+mem+csa+dummy; Flow C 0x32f5 seq_br_type 3 Unconditional Branch seq_branch_adr 32f5 0x32f5 seq_int_reads 0 TYP VAL BUS seq_lex_adr 2 seq_random 1e Load_ibuff+? 3c55 3c55 <default>
PyReveng3/R1000.Disassembly disass_ucode.py /tmp/_aa_r1k_dfs/r1k_dfs/5e/5e103225d.tmp.0.28179 /tmp/_aa_r1k_dfs/r1k_dfs/5e/5e103225d.tmp.1.28180
FN /tmp/_aa_r1k_dfs/r1k_dfs/5e/5e103225d.tmp.0.28179
CX <__main__.R1kUcode object at 0x2ba15ce247d0> CX.M <word_mem 0x100-0x3c56, @14 bits, 0 attr>
Case table at 0x0000 lacks width <leaf 0x735-0x736 R1KUCODE>
? None <leaf 0x0-0x1 R1KUCODE>
Case table at 0x0bb2 lacks width <leaf 0xbae-0xbaf R1KUCODE>
Case table at 0x0bff lacks width <leaf 0xbfe-0xbff R1KUCODE>
Case table at 0x0bcd lacks width <leaf 0xbcc-0xbcd R1KUCODE>
Case table at 0x081f lacks width <leaf 0x81d-0x81e R1KUCODE>
Case table at 0x0830 lacks width <leaf 0x82f-0x830 R1KUCODE>
Case table at 0x2d97 lacks width <leaf 0x149-0x14a R1KUCODE>
Case table at 0x34d2 lacks width <leaf 0x34d1-0x34d2 R1KUCODE>
Case table at 0x2d87 lacks width <leaf 0x2d86-0x2d87 R1KUCODE>
Case table at 0x06a3 lacks width <leaf 0x69e-0x69f R1KUCODE>
Case table at 0x39a3 lacks width <leaf 0x3996-0x3997 R1KUCODE>
Case table at 0x3382 lacks width <leaf 0x337c-0x337d R1KUCODE>
Case table at 0x337e lacks width <leaf 0x337d-0x337e R1KUCODE>
Case table at 0x0260 lacks width <leaf 0x24f-0x250 R1KUCODE>
Case table at 0x338f lacks width <leaf 0x338e-0x338f R1KUCODE>
Case table at 0x02c7 lacks width <leaf 0x2c1-0x2c2 R1KUCODE>
Case table at 0x02c7 lacks width <leaf 0x2c5-0x2c6 R1KUCODE>
Case table at 0x3aea lacks width <leaf 0x3ae9-0x3aea R1KUCODE>
Case table at 0x3753 lacks width <leaf 0x3747-0x3748 R1KUCODE>
Case table at 0x22fd lacks width <leaf 0x22fa-0x22fb R1KUCODE>
Case table at 0x0396 lacks width <leaf 0x38e-0x38f R1KUCODE>
Case table at 0x03c0 lacks width <leaf 0x3b9-0x3ba R1KUCODE>
Case table at 0x03f8 lacks width <leaf 0x3f6-0x3f7 R1KUCODE>
Case table at 0x04af lacks width <leaf 0x4ae-0x4af R1KUCODE>
Case table at 0x04b8 lacks width <leaf 0x4b3-0x4b4 R1KUCODE>
Case table at 0x3539 lacks width <leaf 0x3533-0x3534 R1KUCODE>
Case table at 0x3539 lacks width <leaf 0x3535-0x3536 R1KUCODE>
Case table at 0x3539 lacks width <leaf 0x3544-0x3545 R1KUCODE>
Case table at 0x0516 lacks width <leaf 0x514-0x515 R1KUCODE>
Case table at 0x04f5 lacks width <leaf 0x4f0-0x4f1 R1KUCODE>
Case table at 0x0552 lacks width <leaf 0x551-0x552 R1KUCODE>
Case table at 0x063c lacks width <leaf 0x635-0x636 R1KUCODE>
Case table at 0x063c lacks width <leaf 0x63b-0x63c R1KUCODE>
Case table at 0x06a3 lacks width <leaf 0x697-0x698 R1KUCODE>
Case table at 0x0802 lacks width <leaf 0x801-0x802 R1KUCODE>
Case table at 0x334b lacks width <leaf 0x3343-0x3344 R1KUCODE>
Case table at 0x334b lacks width <leaf 0x3344-0x3345 R1KUCODE>
Case table at 0x334b lacks width <leaf 0x3347-0x3348 R1KUCODE>
Case table at 0x334b lacks width <leaf 0x334a-0x334b R1KUCODE>
Case table at 0x335a lacks width <leaf 0x3359-0x335a R1KUCODE>
Case table at 0x335a lacks width <leaf 0x3357-0x3358 R1KUCODE>
Case table at 0x335a lacks width <leaf 0x3354-0x3355 R1KUCODE>
Case table at 0x335a lacks width <leaf 0x3355-0x3356 R1KUCODE>
Case table at 0x0983 lacks width <leaf 0x982-0x983 R1KUCODE>
Case table at 0x0993 lacks width <leaf 0x992-0x993 R1KUCODE>
Case table at 0x09a5 lacks width <leaf 0x9a4-0x9a5 R1KUCODE>
Case table at 0x09b5 lacks width <leaf 0x9b4-0x9b5 R1KUCODE>
Case table at 0x0a29 lacks width <leaf 0xa28-0xa29 R1KUCODE>
Case table at 0x0a3b lacks width <leaf 0xa3a-0xa3b R1KUCODE>
Case table at 0x0a52 lacks width <leaf 0xa4f-0xa50 R1KUCODE>
Case table at 0x0a63 lacks width <leaf 0xa50-0xa51 R1KUCODE>
Case table at 0x0a73 lacks width <leaf 0xa72-0xa73 R1KUCODE>
Case table at 0x0a63 lacks width <leaf 0xa62-0xa63 R1KUCODE>
Case table at 0x0a87 lacks width <leaf 0xa86-0xa87 R1KUCODE>
Case table at 0x0a9b lacks width <leaf 0xa9a-0xa9b R1KUCODE>
Case table at 0x1d79 lacks width <leaf 0x1d78-0x1d79 R1KUCODE>
Case table at 0x0abb lacks width <leaf 0xab9-0xaba R1KUCODE>
Case table at 0x0c69 lacks width <leaf 0xc68-0xc69 R1KUCODE>
Case table at 0x0ccd lacks width <leaf 0xccc-0xccd R1KUCODE>
Case table at 0x0e01 lacks width <leaf 0xe00-0xe01 R1KUCODE>
Case table at 0x0e3b lacks width <leaf 0xe39-0xe3a R1KUCODE>
Case table at 0x0e3d lacks width <leaf 0xe3b-0xe3c R1KUCODE>
Case table at 0x0e47 lacks width <leaf 0xe46-0xe47 R1KUCODE>
Case table at 0x0e8e lacks width <leaf 0xe8c-0xe8d R1KUCODE>
Case table at 0x0ee2 lacks width <leaf 0xee1-0xee2 R1KUCODE>
Case table at 0x0f40 lacks width <leaf 0xf22-0xf23 R1KUCODE>
Case table at 0x0f26 lacks width <leaf 0xf23-0xf24 R1KUCODE>
Case table at 0x0f2d lacks width <leaf 0xf2c-0xf2d R1KUCODE>
Case table at 0x0ffc lacks width <leaf 0xffb-0xffc R1KUCODE>
Case table at 0x0ff4 lacks width <leaf 0xff2-0xff3 R1KUCODE>
Case table at 0x365d lacks width <leaf 0x365c-0x365d R1KUCODE>
Case table at 0x1032 lacks width <leaf 0x1019-0x101a R1KUCODE>
Case table at 0x1085 lacks width <leaf 0x1083-0x1084 R1KUCODE>
Case table at 0x105f lacks width <leaf 0x105d-0x105e R1KUCODE>
Case table at 0x1056 lacks width <leaf 0x105f-0x1060 R1KUCODE>
Case table at 0x1056 lacks width <leaf 0x1055-0x1056 R1KUCODE>
Case table at 0x104d lacks width <leaf 0x104c-0x104d R1KUCODE>
Case table at 0x1056 lacks width <leaf 0x104d-0x104e R1KUCODE>
Case table at 0x10e8 lacks width <leaf 0x10d9-0x10da R1KUCODE>
Case table at 0x10e8 lacks width <leaf 0x10dd-0x10de R1KUCODE>
Case table at 0x1105 lacks width <leaf 0x1103-0x1104 R1KUCODE>
Case table at 0x10e8 lacks width <leaf 0x10e1-0x10e2 R1KUCODE>
Case table at 0x10e8 lacks width <leaf 0x10e5-0x10e6 R1KUCODE>
Case table at 0x113f lacks width <leaf 0x1131-0x1132 R1KUCODE>
Case table at 0x113f lacks width <leaf 0x1135-0x1136 R1KUCODE>
Case table at 0x113f lacks width <leaf 0x1139-0x113a R1KUCODE>
Case table at 0x113f lacks width <leaf 0x113d-0x113e R1KUCODE>
Case table at 0x119b lacks width <leaf 0x1193-0x1194 R1KUCODE>
Case table at 0x11ca lacks width <leaf 0x11a3-0x11a4 R1KUCODE>
Case table at 0x1223 lacks width <leaf 0x1215-0x1216 R1KUCODE>
Case table at 0x1223 lacks width <leaf 0x1219-0x121a R1KUCODE>
Case table at 0x1223 lacks width <leaf 0x121d-0x121e R1KUCODE>
Case table at 0x1223 lacks width <leaf 0x1221-0x1222 R1KUCODE>
Case table at 0x1281 lacks width <leaf 0x1273-0x1274 R1KUCODE>
Case table at 0x1281 lacks width <leaf 0x1277-0x1278 R1KUCODE>
Case table at 0x1281 lacks width <leaf 0x127b-0x127c R1KUCODE>
Case table at 0x1281 lacks width <leaf 0x127f-0x1280 R1KUCODE>
Case table at 0x16b6 lacks width <leaf 0x16b5-0x16b6 R1KUCODE>
Case table at 0x16bc lacks width <leaf 0x16bb-0x16bc R1KUCODE>
Case table at 0x16c2 lacks width <leaf 0x16c1-0x16c2 R1KUCODE>
Case table at 0x194d lacks width <leaf 0x1941-0x1942 R1KUCODE>
Case table at 0x1d58 lacks width <leaf 0x1d3c-0x1d3d R1KUCODE>
Case table at 0x1cd5 lacks width <leaf 0x1cd4-0x1cd5 R1KUCODE>
Case table at 0x1ef1 lacks width <leaf 0x1ef0-0x1ef1 R1KUCODE>
Case table at 0x1f96 lacks width <leaf 0x1f90-0x1f91 R1KUCODE>
Case table at 0x20d8 lacks width <leaf 0x2041-0x2042 R1KUCODE>
Case table at 0x209f lacks width <leaf 0x209d-0x209e R1KUCODE>
Case table at 0x209f lacks width <leaf 0x20ce-0x20cf R1KUCODE>
Case table at 0x209f lacks width <leaf 0x20d1-0x20d2 R1KUCODE>
Case table at 0x209f lacks width <leaf 0x20d6-0x20d7 R1KUCODE>
Case table at 0x20d8 lacks width <leaf 0x20fd-0x20fe R1KUCODE>
Case table at 0x20d8 lacks width <leaf 0x2146-0x2147 R1KUCODE>
Case table at 0x20d8 lacks width <leaf 0x214b-0x214c R1KUCODE>
Case table at 0x20d8 lacks width <leaf 0x2150-0x2151 R1KUCODE>
Case table at 0x21f9 lacks width <leaf 0x21f4-0x21f5 R1KUCODE>
Case table at 0x2223 lacks width <leaf 0x221d-0x221e R1KUCODE>
Case table at 0x2240 lacks width <leaf 0x223f-0x2240 R1KUCODE>
Case table at 0x2340 lacks width <leaf 0x233f-0x2340 R1KUCODE>
Case table at 0x2585 lacks width <leaf 0x2640-0x2641 R1KUCODE>
Case table at 0x2585 lacks width <leaf 0x2582-0x2583 R1KUCODE>
Case table at 0x2585 lacks width <leaf 0x25d7-0x25d8 R1KUCODE>
Case table at 0x25e3 lacks width <leaf 0x25dd-0x25de R1KUCODE>
Case table at 0x26a8 lacks width <leaf 0x2697-0x2698 R1KUCODE>
Case table at 0x26a8 lacks width <leaf 0x26e4-0x26e5 R1KUCODE>
Case table at 0x26ef lacks width <leaf 0x26ec-0x26ed R1KUCODE>
Case table at 0x2709 lacks width <leaf 0x2705-0x2706 R1KUCODE>
Case table at 0x2714 lacks width <leaf 0x2711-0x2712 R1KUCODE>
Case table at 0x2709 lacks width <leaf 0x2727-0x2728 R1KUCODE>
Case table at 0x27e4 lacks width <leaf 0x27e3-0x27e4 R1KUCODE>
Case table at 0x27e4 lacks width <leaf 0x27ea-0x27eb R1KUCODE>
Case table at 0x280f lacks width <leaf 0x280e-0x280f R1KUCODE>
Case table at 0x2813 lacks width <leaf 0x2812-0x2813 R1KUCODE>
Case table at 0x2b35 lacks width <leaf 0x2b2a-0x2b2b R1KUCODE>
Case table at 0x2b4a lacks width <leaf 0x2b47-0x2b48 R1KUCODE>
Case table at 0x2ba0 lacks width <leaf 0x2b9e-0x2b9f R1KUCODE>
Case table at 0x2c7f lacks width <leaf 0x2c7d-0x2c7e R1KUCODE>
Case table at 0x2c90 lacks width <leaf 0x2c8e-0x2c8f R1KUCODE>
Case table at 0x2e4b lacks width <leaf 0x2e46-0x2e47 R1KUCODE>
Case table at 0x2e70 lacks width <leaf 0x2e6f-0x2e70 R1KUCODE>
Case table at 0x2e8b lacks width <leaf 0x2e89-0x2e8a R1KUCODE>
Case table at 0x2edf lacks width <leaf 0x2ede-0x2edf R1KUCODE>
Case table at 0x2f1b lacks width <leaf 0x2f19-0x2f1a R1KUCODE>
Case table at 0x2fa2 lacks width <leaf 0x2f9c-0x2f9d R1KUCODE>
Case table at 0x2fa2 lacks width <leaf 0x2fa0-0x2fa1 R1KUCODE>
Case table at 0x3793 lacks width <leaf 0x3766-0x3767 R1KUCODE>
Case table at 0x308d lacks width <leaf 0x308c-0x308d R1KUCODE>
Case table at 0x308d lacks width <leaf 0x308d-0x308e R1KUCODE>
Case table at 0x308d lacks width <leaf 0x308e-0x308f R1KUCODE>
Case table at 0x308d lacks width <leaf 0x308f-0x3090 R1KUCODE>
Case table at 0x308d lacks width <leaf 0x3090-0x3091 R1KUCODE>
Case table at 0x308d lacks width <leaf 0x3091-0x3092 R1KUCODE>
Case table at 0x308d lacks width <leaf 0x3092-0x3093 R1KUCODE>
Case table at 0x308d lacks width <leaf 0x3093-0x3094 R1KUCODE>
Case table at 0x308d lacks width <leaf 0x3094-0x3095 R1KUCODE>
Case table at 0x308d lacks width <leaf 0x3095-0x3096 R1KUCODE>
Case table at 0x308d lacks width <leaf 0x3096-0x3097 R1KUCODE>
Case table at 0x308d lacks width <leaf 0x3097-0x3098 R1KUCODE>
Case table at 0x308d lacks width <leaf 0x3098-0x3099 R1KUCODE>
Case table at 0x308d lacks width <leaf 0x3099-0x309a R1KUCODE>
Case table at 0x308d lacks width <leaf 0x309a-0x309b R1KUCODE>
Case table at 0x308d lacks width <leaf 0x309b-0x309c R1KUCODE>
Case table at 0x308d lacks width <leaf 0x309c-0x309d R1KUCODE>
Case table at 0x31ba lacks width <leaf 0x31b3-0x31b4 R1KUCODE>
Case table at 0x36d0 lacks width <leaf 0x36cb-0x36cc R1KUCODE>
Case table at 0x3725 lacks width <leaf 0x3720-0x3721 R1KUCODE>
Case table at 0x0000 lacks width <leaf 0x3752-0x3753 R1KUCODE>
Case table at 0x379b lacks width <leaf 0x3771-0x3772 R1KUCODE>
Case table at 0x3819 lacks width <leaf 0x3818-0x3819 R1KUCODE>
Case table at 0x3831 lacks width <leaf 0x382a-0x382b R1KUCODE>
Case table at 0x3861 lacks width <leaf 0x3859-0x385a R1KUCODE>
Case table at 0x3877 lacks width <leaf 0x385a-0x385b R1KUCODE>
Case table at 0x38ab lacks width <leaf 0x38a5-0x38a6 R1KUCODE>
Case table at 0x38ab lacks width <leaf 0x38a9-0x38aa R1KUCODE>
Case table at 0x38fa lacks width <leaf 0x38f9-0x38fa R1KUCODE>
Case table at 0x3aa8 lacks width <leaf 0x3aa7-0x3aa8 R1KUCODE>
Case table at 0x3b94 lacks width <leaf 0x3b92-0x3b93 R1KUCODE>
Case table at 0x3b9c lacks width <leaf 0x3b9a-0x3b9b R1KUCODE>
Case table at 0x3bd9 lacks width <leaf 0x3bcb-0x3bcc R1KUCODE>
Case table at 0x3bd9 lacks width <leaf 0x3bd6-0x3bd7 R1KUCODE>
? None <leaf 0x3c60-0x3c61 R1KUCODE>
fiu_len_fill_reg_ctl 1 {3}
fiu_load_mdr 1 {0}
fiu_load_oreg 1 {0}
fiu_mem_start 1 {2}
fiu_oreg_src 1 {1}
ioc_adrbs 1 {3}
seq_lex_adr 1 {0}
typ_mar_cntl 1 {14}
typ_priv_check 1 {7}
Stranger in color <Color 15 0x117-0x73c #2> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 24 0x120-0x83e #40> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 25 0x127-0x2aee #133> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 42 0x138-0x2aba #45> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 48 0x148-0x3c43 #100> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 65 0x160-0x2a94 #13> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 79 0x180-0xf1e #4> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 181 0x200-0x3c10 #47> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 182 0x201-0x20b #2> <Stretch 202 259> <Color 183 0x202-0x20c #2>
Stranger in color <Color 183 0x202-0x20c #2> <Stretch 203 260> <Color 184 0x203-0xf04 #25>
Stranger in color <Color 184 0x203-0xf04 #25> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 185 0x204-0x20e #2> <Stretch 205 262> <Color 186 0x205-0x20f #2>
Stranger in color <Color 186 0x205-0x20f #2> <Stretch 206 263> <Color 187 0x206-0x210 #2>
Stranger in color <Color 187 0x206-0x210 #2> <Stretch 207 264> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 188 0x208-0x212 #2> <Stretch 209 266> <Color 189 0x209-0x213 #2>
Stranger in color <Color 189 0x209-0x213 #2> <Stretch 20a 267> <Color 181 0x200-0x3c10 #47>
Stranger in color <Color 190 0x214-0x338b #50> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 201 0x2c2-0x2e0 #7> <Stretch 2c7 456> <Color 202 0x2c7-0x2cc #4>
Stranger in color <Color 202 0x2c7-0x2cc #4> <Stretch 2c9 458> <Color 203 0x2c9-0x38ad #12>
Stranger in color <Color 203 0x2c9-0x38ad #12> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 204 0x2ca-0x2d5 #6> <Stretch 2cb 460> <Color 202 0x2c7-0x2cc #4>
Stranger in color <Color 205 0x2d6-0x2df #9> <Stretch 2de 479> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 215 0x331-0x3c06 #5> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 224 0x345-0x3bfc #3> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 225 0x349-0x3c3f #3> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 226 0x377-0x3c3d #10> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 230 0x397-0x3a1 #8> <Stretch 398 665> <Color 231 0x398-0x3c3 #16>
Stranger in color <Color 231 0x398-0x3c3 #16> <Stretch 39b 668> <Color 230 0x397-0x3a1 #8>
Stranger in color <Color 235 0x3c1-0x3ca #8> <Stretch 3c2 707> <Color 231 0x398-0x3c3 #16>
Stranger in color <Color 238 0x3f0-0x407 #17> <Stretch 3f7 760> <Color 239 0x3f7-0x3f7 #1>
Stranger in color <Color 241 0x3f9-0x3fc #3> <Stretch 3fa 763> <Color 242 0x3fa-0x3b1b #50>
Stranger in color <Color 242 0x3fa-0x3b1b #50> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 252 0x4b0-0x4d4 #24> <Stretch 4b2 947> <Color 253 0x4b2-0x4b2 #1>
Stranger in color <Color 266 0x4fa-0x50a #13> <Stretch 4fd 1022> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 270 0x525-0x52b #4> <Stretch 526 1063> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 292 0x573-0x598 #18> <Stretch 576 1143> <Color 293 0x576-0x577 #2>
Stranger in color <Color 302 0x5a7-0x36fc #92> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 311 0x5db-0x367f #17> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 317 0x5fb-0x626 #15> <Stretch 614 1301> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 321 0x62d-0x3967 #25> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 327 0x66a-0x68c #28> <Stretch 683 1412> <Color 328 0x683-0x683 #1>
Stranger in color <Color 337 0x6b7-0x39be #57> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 340 0x6ce-0x6e5 #10> <Stretch 6d2 1491> <Color 341 0x6d2-0x6fb #26>
Stranger in color <Color 341 0x6d2-0x6fb #26> <Stretch 6d8 1497> <Color 342 0x6d8-0x6da #3>
Stranger in color <Color 353 0x767-0x3c36 #45> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 355 0x794-0x3c40 #6> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 356 0x799-0x3bf6 #8> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 362 0x7b5-0x3b81 #6> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 363 0x7b9-0x7e7 #18> <Stretch 7c0 1729> <Color 364 0x7c0-0x7c0 #1>
Stranger in color <Color 374 0x820-0x870 #47> <Stretch 821 1826> <Color 375 0x821-0x87a #11>
Stranger in color <Color 375 0x821-0x87a #11> <Stretch 822 1827> <Color 374 0x820-0x870 #47>
Stranger in color <Color 379 0x903-0x3c0a #3> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 380 0x905-0x3c0b #7> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 381 0x90b-0x912 #7> <Stretch 90d 2062> <Color 382 0x90d-0x90d #1>
Stranger in color <Color 383 0x913-0x3c0d #19> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 384 0x917-0x3c0e #2> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 388 0x921-0x339a #90> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 395 0x950-0x3c25 #32> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 400 0x980-0x3194 #5> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 403 0x98b-0x1f7b #213> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 404 0x98c-0x1304 #2> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 407 0x990-0x3193 #6> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 409 0x995-0x30fd #3> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 410 0x998-0x136c #4> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 411 0x99b-0x1f06 #2> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 412 0x99c-0x12f8 #2> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 416 0x9a2-0x2fcc #5> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 421 0x9aa-0x22f2 #60> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 422 0x9ab-0x186c #37> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 423 0x9ac-0x1497 #50> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 424 0x9ad-0x1823 #6> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 425 0x9ae-0x177c #11> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 428 0x9b2-0x2fd0 #5> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 436 0x9c9-0xae5 #7> <Stretch 9ca 2251> <Color 437 0x9ca-0x9ca #1>
Stranger in color <Color 439 0x9cc-0x9f6 #39> <Stretch 9e1 2274> <Color 440 0x9e1-0x9e4 #4>
Stranger in color <Color 462 0xa26-0x302b #19> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 464 0xa2b-0x292d #12> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 467 0xa2f-0x1ae5 #78> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 468 0xa31-0x1840 #21> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 469 0xa32-0x17da #15> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 470 0xa33-0x1b43 #20> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 471 0xa35-0xc4f #17> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 479 0xa50-0x301d #31> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 484 0xa57-0xa5c #2> <Stretch a58 2393> <Color 485 0xa58-0xa5d #2>
Stranger in color <Color 485 0xa58-0xa5d #2> <Stretch a59 2394> <Color 486 0xa59-0xa5e #2>
Stranger in color <Color 486 0xa59-0xa5e #2> <Stretch a5a 2395> <Color 479 0xa50-0x301d #31>
Stranger in color <Color 491 0xa75-0x2929 #15> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 492 0xa76-0xa82 #6> <Stretch a78 2425> <Color 493 0xa78-0x1be2 #14>
Stranger in color <Color 493 0xa78-0x1be2 #14> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 494 0xa7a-0x14e2 #4> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
Stranger in color <Color 495 0xa7c-0x17e3 #5> <Stretch b0f 2576> <Color 0 0x0-0x3c46 #3914>
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PFX /tmp/_aa_r1k_dfs/r1k_dfs/5e/5e103225d.tmp