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Length: 3343 (0xd0f)
Types: EM, TextFile
Names: »FIU_MM_CSA2_TESTS.EM«
└─⟦24d56d853⟧ Bits:30000744 8mm tape, Rational 1000, DFS, D_12_6_5 SEQ293
└─⟦this⟧ »FIU_MM_CSA2_TESTS.EM«
└─⟦9031b0687⟧ Bits:30000407 8mm tape, Rational 1000, DFS, D_12_7_3
└─⟦this⟧ »FIU_MM_CSA2_TESTS.EM«
[xeq fiu clear_exceptions]
[xeq fiu step_fiu 9 3 0]
[set experiment_result [xeq fiu read_mdr 0]]
[ne,[and,00f0000000000000,[arg 1,[var experiment_result]]],0]
[FAIL_MESSAGE conditional_memory_start_test_4]
[set num_fails [add,[var num_fails],1]]
[write [ASCII,7]]
[NAME_MESSAGE load_pareg 0ff 0]
[NAME_MESSAGE load_cond_mem_ucode]
[NAME_MESSAGE clear_exceptions]
[NAME_MESSAGE step_fiu 9 3 0]
[NAME_MESSAGE read_mdr 0]
[write mdr should be : XX0XXXXXXXXXXXXX][write]
[else]
[PASS_MESSAGE conditional_memory_start_test_4]
[end]
[xeq fiu clear_exceptions]
[xeq fiu step_fiu 0c 3 0]
[set experiment_result [xeq fiu read_mdr 0]]
[ne,[and,00f0000000000000,[arg 1,[var experiment_result]]],40000000000000]
[FAIL_MESSAGE conditional_memory_start_test_5]
[set num_fails [add,[var num_fails],1]]
[write [ASCII,7]]
[NAME_MESSAGE load_pareg 0ff 0]
[NAME_MESSAGE load_cond_mem_ucode]
[NAME_MESSAGE clear_exceptions]
[NAME_MESSAGE step_fiu C 3 0]
[NAME_MESSAGE read_mdr 0]
[write mdr should be : XX4XXXXXXXXXXXXX][write]
[else]
[PASS_MESSAGE conditional_memory_start_test_5]
[end]
[xeq fiu load_simple_mem_test]
[xeq fiu load_mar_state_bits 7]
[xeq fiu load_dreg 6,6,0]
[xeq fiu load_mar 4,0,1F,0]
[xeq fiu step_fiu 2,4,0]
[set experiment_result [xeq fiu read_inc_mcyc]]
[eq,[arg 1,[var experiment_result]],true]
[FAIL_MESSAGE incomplete_memory_cycle_test_1]
[set num_fails [add,[var num_fails],1]]
[write [ASCII,7]]
[NAME_MESSAGE load_simple_mem_test]
[NAME_MESSAGE load_mar_state_bits 7]
[NAME_MESSAGE load_dreg 6,6,0]
[NAME_MESSAGE load_mar 4,0,1F,0]
[NAME_MESSAGE step_fiu 2 4 0]
[NAME_MESSAGE read_inc_mcyc]
[write result should be: false][write]
[else]
[PASS_MESSAGE incomplete_memory_cycle_test_1]
[end]
[xeq fiu load_mar_state_bits 7]
[xeq fiu load_dreg 6,6,0]
[xeq fiu load_mar 4,0,1F,0]
[xeq fiu step_fiu 3,3,0]
[set experiment_result [xeq fiu read_inc_mcyc]]
[eq,[arg 1,[var experiment_result]],false]
[eq,[var BENCH_MODE],true]
[FAIL_MESSAGE incomplete_memory_cycle_test_2]
[set num_fails [add,[var num_fails],1]]
[write [ASCII,7]]
[write ****** CHECK THAT ECO WIRE FROM F45-10 TO N47-13 IS CORRECT ******]
[write [ASCII,7]]
[NAME_MESSAGE load_simple_mem_test]
[NAME_MESSAGE load_mar_state_bits 7]
[NAME_MESSAGE load_dreg 6,6,0]
[NAME_MESSAGE load_mar 4,0,1F,0]
[NAME_MESSAGE step_fiu 3 3 0]
[NAME_MESSAGE read_inc_mcyc]
[write result should be: true][write]
[else]
[end]
[else]
[PASS_MESSAGE incomplete_memory_cycle_test_2]
[end]
[xeq fiu load_mar_state_bits 7]
[xeq fiu load_dreg 6,6,0]
[xeq fiu load_mar 4,0,1E,0]
[xeq fiu step_fiu 3,3,0]
[set experiment_result [xeq fiu read_inc_mcyc]]
[eq,[arg 1,[var experiment_result]],true]
[FAIL_MESSAGE incomplete_memory_cycle_test_3]
[set num_fails [add,[var num_fails],1]]
[write [ASCII,7]]
[NAME_MESSAGE load_simple_mem_test]
[NAME_MESSAGE load_mar_state_bits 7]
[NAME_MESSAGE load_dreg 6,6,0]
[NAME_MESSAGE load_mar 4,0,1E,0]
[NAME_MESSAGE step_fiu 3 3 0]
[NAME_MESSAGE read_inc_mcyc]
[write result should be: false][write]
[else]
[PASS_MESSAGE incomplete_memory_cycle_test_3]
[end]